A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.
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11. A memory array comprising:
a first static random access memory (sram) cell area on a substrate; and
a second sram cell area on the substrate, the first sram cell area adjoining the second sram cell area at a boundary, a fin active area being in each of the first sram cell area and the second sram cell area and extending across the boundary, the fin active area being (i) a component of a first isolation transistor in the first sram cell area, (ii) a component of a first operational transistor in the first sram cell area, (iii) a component of a second isolation transistor in the second sram cell area, and (iv) a component of a second operational transistor in the second sram cell area.
16. A method comprising:
forming a fin active area on a substrate, the fin active area extending across a boundary of a first static random access memory (sram) cell area into a second sram cell area;
forming a first gate structure over the fin active area in the first sram cell area proximate the boundary and a second gate structure over the fin active area in the second sram cell area proximate the boundary;
forming a dielectric layer over the fin active area, the first gate structure, and the second gate structure; and
forming a first contact through the dielectric layer to a source/drain region of the fin active area in the first sram cell area and a second contact through the dielectric layer to a source/drain region of the fin active area in the second sram cell area, the first contact being on an opposite side of the first gate structure from the boundary, the second contact being on an opposite side of the second gate structure from the boundary, no contact being formed to a region of the fin active area at the boundary between the first gate structure and the second gate structure.
0. 31. A memory cell comprising:
a first pull-up transistor and a first pull-down transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node;
a second pull-up transistor and a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node;
a first pass-gate transistor electrically coupled to the first node;
a second pass-gate transistor electrically coupled to the second node;
a first isolation transistor electrically coupled to the first node; and
a second isolation transistor electrically coupled to the second node, wherein the first isolation transistor is configured to have a source and a gate coupled to the first node, and the second isolation transistor is configured to have a source and a gate coupled to the second node.
0. 21. A memory array comprising:
a first active area, a second active area, a third active area, and a fourth active area each traversing a first memory cell area and a second memory cell area, the first memory cell area being adjacent to the second memory cell area;
wherein in the first memory cell area:
the first active area is a component of a first pull-down transistor,
the second active area is a component of a first pull-up transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node,
the third active area is a component of a first isolation transistor and a second pull-up transistor, and
the fourth active area is a component of a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node;
wherein in the second memory cell area:
the first active area is a component of a third pull-down transistor,
the second active area is a component of a third pull-up transistor, a drain of the third pull-up transistor being electrically coupled to a drain of the third pull-down transistor at a third node,
the third active area is a component of a second isolation transistor and a fourth pull-up transistor, and
the fourth active area is a component of a fourth pull-down transistor, a drain of the fourth pull-up transistor being electrically coupled to a drain of the fourth pull-down transistor at a fourth node, a gate of the fourth pull-up transistor and a gate of the fourth pull-down transistor being electrically coupled to the third node, a gate of the third pull-up transistor and a gate of the third pull-down transistor being electrically coupled to the fourth node; and
wherein the first isolation transistor and the second isolation transistor have a shared source/drain region at a boundary between the first memory cell area and the second memory cell area.
1. A memory array comprising:
a first active area, a second active area, a third active area, and a fourth active area each traversing a first memory cell area and a second memory cell area, the first memory cell area being adjacent to the second memory cell area;
wherein in the first memory cell area:
the first active area is a component of a first pull-down transistor,
the second active area is a component of a first pull-up transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node,
the third active area is a component of a first isolation transistor and a second pull-up transistor, and
the fourth active area is a component of a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node;
wherein in the second memory cell area:
the first active area is a component of a third pull-down transistor,
the second active area is a component of a third pull-up transistor, a drain of the third pull-up transistor being electrically coupled to a drain of the third pull-down transistor at a third node,
the third active area is a component of a second isolation transistor and a fourth pull-up transistor, and
the fourth active area is a component of a fourth pull-down transistor, a drain of the fourth pull-up transistor being electrically coupled to a drain of the fourth pull-down transistor at a fourth node, a gate of the fourth pull-up transistor and a gate of the fourth pull-down transistor being electrically coupled to the third node, a gate of the third pull-up transistor and a gate of the third pull-down transistor being electrically coupled to the fourth node; and
wherein the first isolation transistor and the second isolation transistor have a shared source/drain region at a boundary between the first memory cell area and the second memory cell area, the shared source/drain region not having a contact directly coupled thereto.
2. The memory array of
in the first memory cell area:
the first active area is a component of a first pass-gate transistor, and
the fourth active area is a component of a second pass-gate transistor, and in the second memory cell area:
the first active area is a component of a third pass-gate transistor, and
the fourth active area is a component of a fourth pass-gate transistor.
3. The memory array of
wherein in the first memory cell area:
the fifth active area is a further component of the first pull-down transistor, and
the sixth active area is a further component of the second pull-down transistor, and
wherein in the second memory cell area:
the fifth active area is a further component of the third pull-down transistor, and
the sixth active area is a further component of the fourth pull-down transistor.
4. The memory array of
5. The memory array of
6. The memory array of
7. The memory array of
8. The memory array of
9. The memory array of
wherein in the first memory cell area:
the first active area is a component of a first pass-gate transistor,
the fourth active area is a component of a second pass-gate transistor,
the fifth active area is a component of a third pass-gate transistor, and
the sixth active area is a component of a fourth pass-gate transistor, and
wherein in the second memory cell area:
the first active area is a component of a fifth pass-gate transistor,
the fourth active area is a component of a sixth pass-gate transistor,
the fifth active area is a component of a seventh pass-gate transistor, and
the sixth active area is a component of a eighth pass-gate transistor.
10. The memory array of
wherein in the first memory cell area:
the fifth active area is a component of a first read pass-gate transistor and a first read pull-down transistor, and
wherein in the second memory cell area:
the fifth active area is a component of a second read pass-gate transistor and a second read pull-down transistor.
12. The memory array of
a first pull-down transistor,
a first pull-up transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node, the first pull-up transistor in the first sram cell area being the first operational transistor, and the first pull-up transistor in the second sram cell area being the second operational transistor,
a second pull-up transistor, and
a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node.
13. The memory array of
14. The memory array of
15. The memory array of
17. The method of
forming a first metallization layer over the substrate; and
forming a second metallization layer over the first metallization layer, one of the first metallization layer or the second metallization layer comprising a bit line trace traversing the first sram cell area and the second sram cell area, the other of the first metallization layer or the second metallization layer comprising a first word line trace extending across the first sram cell area at a direction that intersects the bit line trace and a second word line trace extending across the second sram cell area at a direction that intersects the bit line trace.
18. The method of
19. The method of
20. The method of
0. 22. The memory array of claim 21, wherein:
in the first memory cell area:
the first active area is a component of a first pass-gate transistor, and
the fourth active area is a component of a second pass-gate transistor, and
in the second memory cell area:
the first active area is a component of a third pass-gate transistor, and
the fourth active area is a component of a fourth pass-gate transistor.
0. 23. The memory array of claim 21 further comprising a fifth active area and a sixth active area each traversing the first memory cell area and the second memory cell area,
wherein in the first memory cell area:
the fifth active area is a further component of the first pull-down transistor, and
the sixth active area is a further component of the second pull-down transistor, and
wherein in the second memory cell area:
the fifth active area is a further component of the third pull-down transistor, and
the sixth active area is a further component of the fourth pull-down transistor.
0. 24. The memory array of claim 21, wherein each of the first active area, the second active area, the third active area, and the fourth active area comprises a fin active area.
0. 25. The memory array of claim 21 further comprising a first metallization layer over the active areas and a second metallization layer over the first metallization layer, one of the first metallization layer or the second metallization layer comprising a bit line trace traversing the first memory cell area and the second memory cell area, the other of the first metallization layer or the second metallization layer comprising a first word line trace extending across the first memory cell area at a direction that intersects the bit line trace and a second word line trace extending across the second memory cell area at a direction that intersects the bit line trace.
0. 26. The memory array of claim 25, wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first memory cell area and the second memory cell area, and the other of the first metallization layer or the second metallization layer further comprises a first ground trace extending across the first memory cell area at a direction that intersects the bit line trace and a second ground trace extending across the second memory cell area at a direction that intersects the bit line trace.
0. 27. The memory array of claim 25, wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first memory cell area and the second memory cell area, and further comprises a ground trace traversing the first memory cell area and the second memory cell area.
0. 28. The memory array of claim 25, wherein the one of the first metallization layer or the second metallization layer further comprises (i) a power trace traversing the first memory cell area and the second memory cell area, (ii) a first ground trace traversing the first memory cell area and the second memory cell area, and (iii) a second ground trace traversing the first memory cell area and the second memory cell area, and the other of the first metallization layer or the second metallization layer further comprises a ground mesh trace, a first via electrically coupling the ground mesh trace to the first ground trace, and a second via electrically coupling the ground mesh trace to the second ground trace.
0. 29. The memory array of claim 21, further comprising a fifth active area and a sixth active area each traversing the first memory cell area and the second memory cell area,
wherein in the first memory cell area:
the first active area is a component of a first pass-gate transistor,
the fourth active area is a component of a second pass-gate transistor,
the fifth active area is a component of a third pass-gate transistor, and
the sixth active area is a component of a fourth pass-gate transistor, and
wherein in the second memory cell area:
the first active area is a component of a fifth pass-gate transistor,
the fourth active area is a component of a sixth pass-gate transistor,
the fifth active area is a component of a seventh pass-gate transistor, and
the sixth active area is a component of a eighth pass-gate transistor.
0. 30. The memory array of claim 21, further comprising a fifth active area traversing the first memory cell area and the second memory cell area,
wherein in the first memory cell area:
the fifth active area is a component of a first read pass-gate transistor and a first read pull-down transistor, and
wherein in the second memory cell area:
the fifth active area is a component of a second read pass-gate transistor and a second read pull-down transistor.
0. 32. The memory cell of claim 31, wherein a drain of the first isolation transistor is floating.
0. 33. The memory cell of claim 32, wherein a bit line (BL) or power voltage (VDD) is formed over the drain of the first isolation transistor.
0. 34. The memory cell of claim 32, wherein the drain of the first isolation transistor is sandwiched between a bit line (BL) and a power voltage (VDD).
0. 35. The memory cell of claim 31, wherein a drain of the second isolation transistor is floating.
0. 36. The memory cell of claim 35, wherein a complementary bit line (BLB) or a power voltage (VDD) is formed over the drain of the second isolation transistor.
0. 37. The memory cell of claim 35, wherein the drain of the second isolation transistor is sandwiched between a complementary bit line (BLB) and a power voltage (VDD).
0. 38. The memory cell of claim 31, wherein a word line (WL) is formed over the first and second isolation transistors.
0. 39. The memory cell of claim 31, wherein a drain of the first isolation transistor is formed at a first side of a word line (WL), a drain of the second isolation transistor is formed at a second side of the WL.
0. 40. The memory cell of claim 31, wherein a first word line (AWL) or a second word line (BWL) is formed over a drain of the first isolation transistor.
0. 41. The memory cell of claim 31, wherein a first word line (AWL) or a second word line (BWL) is formed over a drain of the second isolation transistor.
0. 42. The memory cell of claim 31, wherein a write word line (WWL) or a read word line (RWL) is formed over a drain of the first isolation transistor.
0. 43. The memory cell of claim 31, wherein a write word line (WWL) or a read word line (RWL) is formed over a drain of the second isolation transistor.
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This application is a reissue application of U.S. Pat. No. 8,879,305.
This application is a continuation of U.S. patent application Ser. No. 13/328,685, filed on Dec. 16, 2011, entitled “Memory Cell,” now U.S. Pat. No. 8,625,334, which application is hereby incorporated herein by reference in its entirety.
Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Each row of the SRAM cells is connected to a word line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit line (or a pair of complementary bit lines), which is used for writing a bit into, or reading a bit from, the SRAM cell.
Recent advances in finFET transistor technology have made advanced SRAM cells using finFET transistors possible. In contrast to the prior planar MOS transistor, which has a channel formed at the surface of a semiconductor substrate, a finFET has a three dimensional channel region. In the finFET, the channel for the transistor is formed on the sides, and sometimes also the top, of a “fin” of semiconductor material. The gate, typically a polysilicon or metal gate, extends over the fin and a gate dielectric is disposed between the gate and the fin. The three-dimensional shape of the finFET channel region allows for an increased gate width without increased silicon area even as the overall scale of the devices is reduced with semiconductor process scaling, and in conjunction with a reduced gate length, providing a reasonable channel width characteristic at a low silicon area cost.
For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.
Embodiments will be described with respect to a specific context, namely a memory cell, such as a static random access memory (SRAM) cell. Other embodiments may also be applied, however, to other circuits and layouts of circuits where a greater uniformity of the layout is desired. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
The drains of pull-up transistors PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a data latch. The gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2, and the gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1. Sources of the pull-up transistors PU1 and PU2 are coupled to power voltage Vdd, and the sources of the pull-down transistors PD1 and PD2 are coupled to a ground voltage Vss.
Storage node N1 of the data latch is coupled to bit line BL through pass-gate transistor PG1, and storage node N2 is coupled to complementary bit line BLB through pass-gate transistor PG2. Storage nodes N1 and N2 are complementary nodes that are often at opposite logic levels (logic high or logic low). Gates of pass-gate transistors PG1 and PG2 are coupled to a word line WL. The source and gate of the isolation transistor IS1 are coupled together and to the storage node N1, and the source and gate of the isolation transistor IS2 are coupled together and to the storage node N2. Drains of the isolation transistors IS1 and IS2 are depicted as floating, but may be coupled to respective isolation transistors in adjacent cells, as will be discussed.
The dashed lines that intersect the cell indicate boundaries between a p-type well in the substrate and an n-type well in the substrate in which respective active areas are formed. The active area of transistors PG1 and PD1 is formed in a p-type well, as these transistors are n-type transistors. The two active areas of transistors IS1, PU1, PU2, and IS2 are formed in an n-type well, as these transistors are p-type transistors. The active area of transistors PD2 and PG2 is formed in a p-type well, as these transistors are n-type transistors. As person having ordinary skill in the art will readily understand that source/drain regions of the active areas of the transistors are generally doped an opposite dopant type from that of the well. For example, a source/drain region is generally p-type doped when the well in which the active area is formed is an n-type well.
A single gate pattern is used as the gates of transistors PD1, PU1, and IS2, and another single gate pattern is used as the gates of transistors PD2, PU2, and IS1. In this manner, each single gate pattern electrically couples the gates of the respective three transistors. A gate pattern for pass-gate transistor PG1 extends beyond a cell boundary so that the gate pattern can be shared by an adjacent bit cell, as does a gate pattern for pass-gate transistor PG2.
Various contacts couple components in the bit cell. A word line contact WL is coupled to the gate of pass-gate transistor PG1, and another word line contact WL is coupled to the gate of pass-gate transistor PG2. A bit line contact BL is coupled to the drain of pass-gate transistor PG1, and an complementary bit line contact BLB is coupled to the drain of pass-gate transistor PG2. A power contact Vdd is coupled to the source of pull-up transistor PU1, and another power contact Vdd is coupled to the source of pull-up transistor PU2. A ground contact Vss is coupled to the source of pull-down transistor PD1, and another ground contact Vss is coupled to the source of pull-down transistor PD2. A node contact N1 couples together the sources of transistors PG1 and IS1 and the drains of transistors PD1 and PU1, and a node contact N2 couples together the sources of transistors PG2 and IS2 and the drains of transistors PD2 and PU2. A butted contact BC1 couples the source of isolation transistor IS1 to the gate of the isolation transistor IS1, and a butted contact BC2 couples the source of isolation transistor IS2 to the gate of the isolation transistor IS2.
Each active area in a bit cell extends through multiple bit cells in a column. In an embodiment, each active area in a bit cell extends through all of the bit cells in a column. In other embodiments, each active area extends through less than all of the bit cells in the column. In
In operation, the bit cells in
The isolation transistors IS1 and IS2 may have a negligible effect on the operation of the bit cell. When the node to which the source and gate of the isolation transistor IS1 or IS2 is coupled is at a high voltage, e.g., a logic high, the voltage at the gate of the isolation transistor IS1 or IS2 is also high, and the isolation transistor IS1 or IS2 will be in an “off” state. When the node is at a low voltage, e.g., a logic low, the voltage at the gate will also be low, and the isolation transistor IS1 or IS2 will be in an “on” state. However, because the voltage at the source is also low, such as coupled to ground, no current will flow away from the node through the isolation transistor IS1 or IS2. In some instances, a small amount of leakage may flow through the isolation transistor IS1 or IS2 when the voltage at the node is switched, e.g., from low to high and vice versa. With fast switching times and/or low voltages, the leakage current can be very small and negligible.
By having the bit cells in the configuration in
The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a data latch. The gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2, and the gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1. Sources of the pull-up transistors PU1 and PU2 are coupled to power voltage Vdd, and the sources of the pull-down transistors PD1 and PD2 are coupled to a ground voltage Vss.
Storage node N1 of the data latch is coupled to a first bit line ABL through pass-gate transistor PG1 and to a second bit line BBL through pass-gate transistor PG3, and storage node N2 is coupled to a complementary first bit line ABLB through pass-gate transistor PG2 and to a complementary second bit line BBLB through pass-gate transistor PG4. Storage nodes N1 and N2 are complementary nodes that are often at opposite logic levels (logic high or logic low). Gates of pass-gate transistors PG1 and PG2 are coupled to a first word line AWL, and gates of pass-gate transistors PG3 and PG4 are coupled to a second word line BWL. The source and gate of the isolation transistor IS1 are coupled together and to the storage node N1, and the source and gate of the isolation transistor IS2 are coupled together and to the storage node N2. Drains of the isolation transistors IS1 and IS2 are depicted as floating, but may be coupled to respective isolation transistors in adjacent cells, as will be discussed.
The dashed lines that intersect the cell indicate boundaries between a p-type well in the substrate and an n-type well in the substrate in which respective active areas are formed. The four active areas of transistors PG1, PG3, and PD1 are formed in a p-type well, as these transistors are n-type transistors. The two active areas of transistors IS1, PU1, PU2, and IS2 are formed in an n-type well, as these transistors are p-type transistors. The four active areas of transistors PG2, PG4, and PD2 are formed in a p-type well, as these transistors are n-type transistors.
As depicted the pull-down transistors PD1 and PD2 are each essentially a quadruple pitch transistor, with each transistor comprising two parallel coupled double pitch transistors PD1-1 and PD1-2 (for transistor PD1) and PD2-1 and PD2-1 (for transistor PD2). Further the pass-gate transistors PG1, PG2, PG3, and PG4 are each double pitch transistors.
A single gate pattern is used as the gates of transistors PD1, PU1, and IS2, and another single gate pattern is used as the gates of transistors PD2, PU2, and IS1. In this manner, each single gate pattern electrically couples the gates of the respective three transistors. A gate pattern for pass-gate transistor PG1 extends beyond a cell boundary so that the gate pattern can be shared by an adjacent bit cell, as does a gate pattern for pass-gate transistor PG2. Each of pass-gate transistors PG3 and PG4 has a gate pattern that does not extend to another transistor and remains internal to the bit cell.
Various contacts couple components in the bit cell. A first word line contact AWL is coupled to the gate of pass-gate transistor PG1, and another first word line contact AWL is coupled to the gate of pass-gate transistor PG2. A second word line contact BWL is coupled to the gate of pass-gate transistor PG3, and another second word line contact BWL is coupled to the gate of pass-gate transistor PG4. A first bit line contact ABL is coupled to the drain of pass-gate transistor PG1, and a complementary first bit line contact ABLB is coupled to the drain of pass-gate transistor PG2. A second bit line contact BBL is coupled to the drain of pass-gate transistor PG3, and a complementary second bit line contact BBLB is coupled to the drain of pass-gate transistor PG4. A power contact Vdd is coupled to the source of pull-up transistor PU1, and another power contact Vdd is coupled to the source of pull-up transistor PU2. A ground contact Vss is coupled to the source of pull-down transistor PD1 (or the sources of transistors PD1-2 and PD1-1 with the quadruple pitch transistor, as depicted), and another ground contact Vss is coupled to the source of pull-down transistor PD2 (or the sources of transistors PD2-2 and PD2-1 with the quadruple pitch transistor, as depicted). A node contact N1 couples together the sources of transistors PG1, PG3, and IS1 and drains of transistors PD1 (or drains of transistors PD1-2 and PD1-1) and PU1, and a node contact N2 couples together the sources of transistors PG2, PG4, and IS2 and drains of transistors PD2 (or drains of transistors PD2-2 and PD2-1) and PU2. A butted contact BC1 couples the source of isolation transistor IS1 to the gate of the isolation transistor IS1, and a butted contact BC2 couples the source of isolation transistor IS2 to the gate of the isolation transistor IS2.
Each active area in a bit cell extends through multiple bit cells in a column. In an embodiment, each active area in a bit cell extends through all of the bit cells in a column. In other embodiments, each active area extends through less than all of the bit cells in the column. In
In operation, the bit cells in
As previously discussed with respect to
By having the bit cells in the configuration in
The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a data latch. The gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2, and the gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1. Sources of the pull-up transistors PU1 and PU2 are coupled to power voltage Vdd, and the sources of the pull-down transistors PD1 and PD2 are coupled to a ground voltage Vss.
Storage node N1 of the data latch is coupled to write bit line WBL through pass-gate transistor PG1, and storage node N2 is coupled to complementary write bit line WBLB through pass-gate transistor PG2. Storage nodes N1 and N2 are complementary nodes that are often at opposite logic levels (logic high or logic low). Gates of pass-gate transistors PG1 and PG2 are coupled to write word line WWL. The source of the read pull-down transistor RPD is coupled to the ground voltage VSS, and the gate of the read pull-down transistor RPD is coupled to the storage node N1. The drain of the read pull-down transistor RPD is coupled to the source of the read pass-gate transistor RPG. The gate of transistor RPG is coupled to a read word line RWL, and the drain of transistor RPG is coupled to a read bit line RBL. The source and gate of the isolation transistor IS1 are coupled together and to the storage node N1, and the source and gate of the isolation transistor IS2 are coupled together and to the storage node N2. Drains of the isolation transistors IS1 and IS2 are depicted as floating, but may be coupled to respective isolation transistors in adjacent cells, as will be discussed.
The dashed lines that intersect the cell indicate boundaries between a p-type well in the substrate and an n-type well in the substrate in which respective active areas are formed. The active area of transistors PG1 and PD1 is formed in a p-type well, as these transistors are n-type transistors. The two active areas of transistors IS1, PU1, PU2, and IS2 are formed in an n-type well, as these transistors are p-type transistors. The three active areas of transistors PG2, PD2, RPD, and RPG are formed in a p-type well, as these transistors are n-type transistors.
As depicted transistors RPD and RPG are double pitch transistors, and the other transistors are single pitch.
A single gate pattern is used as the gates of transistors PD1, PU1, and IS2, and another single gate pattern is used as the gates of transistors PD2, PU2, IS1, and RPD. In this manner, each single gate pattern electrically couples the gates of the respective transistors. A gate pattern for pass-gate transistor PG1 extends beyond a cell boundary so that the gate pattern can be shared by an adjacent bit cell, as does a gate pattern for read pass-gate transistor RPG. A gate pattern for pass-gate transistor PG2 is internal to the bit cell and does not extend to another transistor.
Various contacts couple components in the bit cell. A write word line contact WWL is coupled to the gate of pass-gate transistor PG1, and another write word line contact WWL is coupled to the gate of pass-gate transistor PG2. A read word line contact RWL is coupled to the gate of read pass-gate transistor RPG. A write bit line contact WBL is coupled to drain of pass-gate transistor PG1, and a complementary write bit line contact WBLB is coupled to drain of pass-gate transistor PG2. A read bit line contact RBL is coupled to drain of read pass-gate transistor RPG. A power contact Vdd is coupled to the source of pull-up transistor PU1, and another power contact Vdd is coupled to the source of pull-up transistor PU2. A ground contact Vss is coupled to the source of pull-down transistor PD1, and another ground contact Vss is coupled to the sources of transistors PD2 and RPD. A node contact N1 couples together the sources of transistors PG1 and IS1 and drains of transistors PD1 and PU1, and a node contact N2 couples together the sources of transistors PG2 and IS2 and drains of transistors PD2 and PU2. A butted contact BC1 couples the source of isolation transistor IS1 to the gate of the isolation transistor IS1, and a butted contact BC2 couples the source of isolation transistor IS2 to the gate of the isolation transistor IS2.
Each active area in a bit cell extends through multiple bit cells in a column. In an embodiment, each active area in a bit cell extends through all of the bit cells in a column. In other embodiments, each active area extends through less than all of the bit cells in the column. In
In operation, the bit cells in
As previously discussed with respect to
By having the bit cells in the configuration in
In
In
In
In
In
In
In other embodiments, one interlayer dielectric layer can take the place of the two interlayer dielectrics ILD1 and ILD2, and the contacts 22, 24, and 26 can have openings formed from a single etch step and single deposition step.
In
The cross section view of
A first embodiment is a memory cell comprising a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first pass-gate transistor, a second pass-gate transistor, a first isolation transistor, and a second isolation transistor. A drain of the first pull-up transistor is electrically coupled to a drain of the first pull-down transistor at a first node. A drain of the second pull-up transistor is electrically coupled to a drain of the second pull-down transistor at a second node. A gate of the second pull-up transistor and a gate of the second pull-down transistor are electrically coupled to the first node, and a gate of the first pull-up transistor and a gate of the first pull-down transistor are electrically coupled to the second node. The first pass-gate transistor is electrically coupled to the first node, and the second pass-gate transistor is electrically coupled to the second node. The first isolation transistor is electrically coupled to the first node, and the second isolation transistor is electrically coupled to the second node.
Another embodiment is a memory array. The memory array comprises a first memory cell and a second memory cell. The first memory cell comprises a first set of transistors, and the second memory cell comprises a second set of transistors. Each of the first and second set of transistors comprises a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first pass-gate transistor, a second pass-gate transistor, a first isolation transistor, and a second isolation transistor. An active area of each one transistor of the first set of transistors extends beyond a boundary of the first memory cell and into the second memory cell, and the boundary is shared by the first memory cell and the second memory cell.
A further embodiment is a method for forming a memory array. The method comprises forming a first fin, a second fin, a third fin, and a fourth fin; and forming a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, a second pass-gate transistor, a first isolation transistor, and a second isolation transistor in each of a first memory cell area and a second memory cell area. Each of the first fin, second fin, third fin, and fourth fin extends across the first memory cell area and the second memory cell area. The first pull-up transistor and the first isolation transistor of each of the first memory cell area and the second memory cell area comprise the first fin. The second pull-up transistor and the second isolation transistor of each of the first memory cell area and the second memory cell area comprise the second fin. The first pass-gate transistor and the first pull-down transistor of each of the first memory cell area and the second memory cell area comprise the third fin. The second pass-gate transistor and the second pull-down transistor of each of the first memory cell area and the second memory cell area comprisw the fourth fin.
Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
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