Enhanced VSB viterbi decoder

Abstract

An enhanced VSB receiver includes a tuner which tunes an RF signal and converts it into an IF signal, an IF mixer which converts the IF signal into a baseband signal, and a demodulator which demodulates the baseband signal into a VSB signal. The enhanced VSB receiver further includes a map recovery unit which recovers VSB map information of the VSB signal, an enhanced equalizer for compensating channel distortion of the VSB signal and outputting an equalized symbol, and an enhanced Viterbi decoder for estimating whether polarity inversion occurred during a symbol period of the equalized symbol and Viterbi-decoding the equalized symbol based on the polarity estimation.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

More specifically, the VSB modulator 107 maps the 3 output bits (C2, C1, and C0) outputted from the trellis encoder 104 as the corresponding 8-level modulation value, and then the VSB modulator 107 outputs the mapped value. For example, when the value of C2C1C0 is ‘000 ’, the mapped value is ‘−7’, when the value of C2C1C0 is ‘011 ’, the mapped value is ‘−1’, and when the value of C2C1C0 is ‘100 ’, the mapped value is ‘+1’. Accordingly, when the value of C2C1C0, which is normally supposed to be ‘000’, becomes ‘100’ due to an inversion in the C2 value, the mapped value becomes ‘₊7’ instead of ‘−7’. Therefore, when the symbol is an enhanced symbol, the Viterbi decoder of the E8-VSB receiving system should assume whether the polarity of the output C2 bit, which is outputted from the trellis encoder of the transmitter, has been inversed. In the present invention, such process will be referred to as a polarity inversion of an enhanced symbol.

A “Viterbi algorithm” is an algorithm that calculates the probability of a state transition path according to the time of the trellis encoder and selects the path having the highest probability. A “branch metric” is a calculated value of the probability for each branch with respect to the state transition of the current time, and a “path metric” refers to an accumulation of the branch metric, which is obtained in accordance with the corresponding time. The branch metric can be obtained by calculating a Euclidean distance between the output level of each branch and the input signal of the Viterbi decoder. At this point, since each of the enhanced symbol and the main symbol received at the E8-VSB receiving system is an 8-level signal, the branch metric calculator calculates the Euclidean distance of the input signal for each of the 8 standard levels by using Equation 1 below, so as to obtain 8 different metric values BM(b):

Equation 1
BM(b)=(r_n−L_b)², wherein L_b=(2b−7) and 0≤b≤7,

wherein r_n represents the signal inputted to the Viterbi decoder at time n, and L_b corresponds to a reference 8-level VSB signal.

The path metric is a probability value of a transition process of a state, more specifically, a path, and which is an accumulated value of the branch metric. The accumulate/compare/select (ACS) unit of the Viterbi decoder calculates the value for each path metric and compares the calculated values, thereby selecting the path that has the lowest path metric value (i.e., the metric value having the highest probability). More specifically, the ACS unit adds the branch metric, which corresponds to 2 branches for each state, with the path metric of a previous state, which is connected to the corresponding branch, and then selects and stores the smaller value of the two calculated values. FIG. 9 illustrates an example of a path metric calculation process of the enhanced symbol and the main symbol. Referring to FIG. 9, the process of calculating the path metric is described by using state 0000 for each of the enhanced symbol and the main symbol.

When the input symbol is the enhanced symbol, as shown in part (a) of FIG. 9, the previous state (i.e., state of ‘t−1’) that can be merged as the state 0000 of ‘t’ are state 0000 and state 1000. During state 0000 of ‘t−1’, when ‘0’ is inputted as the input X2 of the enhanced symbol processor 402, the reference 8-level value that is outputted from the trellis encoder 104 becomes ‘−7’, if there is no polarity inversion, and becomes ‘+1’, if polarity inversion occurs, thereby creating a path for the state 0000 of ‘t−1’ to be transited to state 0000 of ‘t’. Meanwhile, during state 1000 of ‘t−1’, when ‘1’ is inputted as the input X2, the reference 8-level value becomes ‘+1’, if there is no polarity inversion, and becomes if polarity inversion occurs, thereby creating a path for the 1000 state of ‘t−1’ to be transited to state 0000 of ‘t’.

More specifically, if polarity inversion does not occur, the branch metric value of the transition path from state 0000 of ‘t−1’ to state 0000 of ‘t’ is equal to (inputted signal-(−7))². Conversely, if the polarity inversion occurs, the branch metric value of the transition path from state 0000 of ‘t−1’ to state 0000 of’ ‘t’ is equal to (inputted signal-(+1))². Thereafter, at state 0000 of ‘t’, the newly calculated branch metric value is added to the previously accumulated path metric value. Simultaneously, in another path that can be merged as state 0000 of ‘t’ (i.e., the transition path from state 1000 of ‘t−1’ to state 0000 of ‘t’), the branch metric value is added to the previously accumulated path metric value. Further, the added results of the two states that are merged as state 0000 of ‘t’ are compared, and the path having the lowest added value is selected as the surviving (or remaining) path.

The method for calculating the path metric value of state 0000 of ‘t’ will now be described in detail. Firstly, for each of the two branches that are merged as state 0000 of ‘t’, the branch metric value is added to the path metric value of ‘t−1’, thereby obtaining the current path metric values. Secondly, the two current path metric values are compared, so as to select the path having the lowest path metric value, as the surviving (or remaining) path. Thereafter, the path metric value is renewed (or updated) with the path metric value of the selected path for a following ACS calculation. Finally, a survivor of the selected path and a set of path selecting information are outputted to the path history unit. Herein, the survivor becomes the input X2 bit of the enhanced symbol processor 402. Furthermore, C2 bit is additionally included herein for the enhanced/main integrated Viterbi decoder, which will be described in detail in a later process with reference to FIG. 11, and outputted to the path history unit.

When the input symbol is the main symbol, as shown in part (b) of FIG. 9, the previous states (i.e., states of ‘t−1’) that can become the state 0000 of ‘t’ include state 0000 and state 0010. At state 0000 of ‘t−1’, when ‘0’ is inputted as the input X1 of the enhanced symbol processor 402, the level value that is outputted from the trellis encoder 104 becomes ‘−7’ or ‘+1’, depending upon the input X2 of the trellis encoder 104, thereby forming the state 0000 path of ‘t’. Meanwhile, during state 0010 of ‘t−1’, when ‘1’ is inputted as the input X1, the level value becomes ‘−3’ or ‘+5’, depending upon the input X2, thereby forming the state 0000 path of ‘t’.

Accordingly, the method for calculating the path metric value of state 0000 of ‘t’ will now be described in detail. First of all, in each path (i.e., branch) of state 0000, two output level values may be obtained depending upon the input X2. Therefore, the two branch metric values are compared, and the lower one of the two values is selected. Then, the C2 bit corresponding to the selected level value is outputted. Secondly, for each of the two branches that are merged as state 0000 of ‘t’, the branch metric value selected from the above-described first step, is added to the accumulated path metric value of ‘t−1’, thereby obtaining the current path metric values.

Thirdly, the two current path metric values that are calculated in the second step are compared, and the lower one of the two values is selected as the surviving (or remaining) path. Thereafter, the path metric value is renewed (or updated) with the path metric value of the selected path for a following ACS operation. And, finally, a survivor of the selected path and a set of path selecting information are outputted to the path history unit. The survivor includes X1 of the selected path and C2 bit of the first step. Herein, the C2 bit is one of the MSB among the output of the trellis encoder 104, which is decoded as the X2 bit after being processed with post-decoding. More specifically, in case of the main symbol, the survivor for each state is C2 and X1. An example of calculating an accumulated path metric of state 0000 and renewing (or updating) the calculated metric path is shown in part (b) of FIG. 9. The accumulated path metric of other states are also calculated and renewed (or updated) in accordance with the state transition diagram of each inputted symbol.

Since the state for each of the enhanced symbol and the main symbol is transited differently, the ACS unit requires an E/M flag that can identify the enhanced symbol and the main symbol. In addition, an H/Q flag that can identify whether the enhanced symbol is a ½ enhanced symbol or a ¼ enhanced symbol is also required. When the input symbol is the ¼ enhanced symbol, the ACS units require a PNEQ flag that indicates whether the repeated bits, which are repeated from the null byte expander, are identical to or different from one another after passing through the ATSC data randomizer. Meanwhile, in order to estimate the above-described polarity inversion of the enhanced symbol, the ACS units also requires a FLIP signal that indicates at which point the ATSC RS parity symbol is added to the enhanced data segment.

The above-described 4 control signals, more specifically, the E/M flag, the H/Q flag, the PNEQ flag, and the FLIP signal are E8-VSB symbol attribute information that is outputted from the map information recovery unit, which is included in the E8-VSB receiving system. In conclusion, the inputs that are required by the ACS unit includes the E/M flag, the H/Q flag, the PNEQ flag, the FLIP signal, and the branch metric values for 8 reference levels. In addition, a control signal indicating the sections for the field synchronization signal and the segment synchronization signal, which is identical to that of the Viterbi decoder of the conventional ATSC 8T-VSB receiver, is also required. Hereinafter, the description of the control signal indicating the field synchronization signal and the segment synchronization signal will be omitted. The E8-VSB transmitting system includes 12 enhanced symbol processors and 12 trellis encoders. And, accordingly, the E8-VSB receiving system includes 12 Viterbi decoders, which correspond to the enhanced symbol processors and the trellis encoders of the E8-VSB transmitting system.

FIG. 10 illustrates an example of a set of control signals being inputted to any one of the 12 Viterbi decoders. Referring to FIG. 10, M represents the main signal, represents the ½ (half) enhanced symbol, and Q represents the ¼ (quarter) enhanced symbol. Furthermore, P represents a symbol being a conversion of the ATSC RS parity byte that is added to the enhanced data packet. When the E/M flag is high, the current input symbol is an enhanced symbol, and when the E/M flag is low, the current input symbol is a main symbol.

The H/Q signal is only valid in the enhanced symbol section. In this case, when the H/Q signal is low, the enhanced symbol is the ½ enhanced symbol, and when the H/Q signal is high, the enhanced symbol is the ¼ enhanced symbol. Herein, the PNEQ signal is only valid in the ¼ enhanced symbol section, the level of which changes to 2 symbol units. When the level of the PNEQ signal is low, the repeated ¼ enhanced data are changed to different values at the ATSC randomizer. Conversely, when the level of the PNEQ signal is high, the repeated ¼ enhanced data are changed to identical values at the ATSC randomizer. The FLIP signal indicates the point where the polarity conversion of the enhanced symbol occurs. Herein, the FLIP signal is high during the section of the ATSC RS parity symbol that is added to the enhanced data packet.

Meanwhile, when performing an ACS operation of the ¼ enhanced symbol, the basic principle is identical to that of the ½ enhanced symbol. However, the operation of the ACS unit varies according to each symbol. More specifically, when the E/M flag is high and when the H/Q flag is high, the input symbol is the ¼ enhanced symbol. In this case, each of the two symbols performs an ACS operation depending upon the PNEQ signal. The decoding process based on the PNEQ signal is described above in detail with reference to FIG. 6 to FIG. 7B.

In the ACS unit, which is similar to the conventional ATSC 8T-VSB Viterbi decoder, a hardware for performing accumulating, comparing, and selecting operations shares 12 Viterbi decoders, wherein only the embodiment of the path metric for each Viterbi decoder is necessary. The hardware sharing is enabled because the 12 Viterbi decoders are operated sequentially (i.e., in turns) and not simultaneously. Each of the Viterbi decoders consists of a positive decoder and a negative decoder. Since each of the positive decoder and the negative decoder is formed of 12 different states, the total number of path metrics required herein is equal to (12×2×16=384).

As described above, since a polarity inversion may occur when the input symbol is the enhanced symbol, the occurrence of the polarity inversion needs to be estimated. In order to estimate such polarity inversion, a comparison should be made between a path metric value of a decoding process, which is performed under the assumption that polarity inversion did not occur, and a path metric value of another decoding process, which is performed under the assumption that polarity inversion occurred. After comparing the two path metric values, the lower one of the two values (i.e., the value having the higher probability) is selected. Then, the estimation is made in accordance with the selected result. Therefore, in order to estimate such polarity inversion of the enhanced symbol, 2 decoders are required. Hereinafter, one of the decoders is referred to as a “positive decoder”, provided that polarity inversion did not occur, and the other one of the decoders is referred to as a “negative decoder”, provided that the polarity inversion occurred.

The process of estimating the polarity inversion of the enhanced symbol will now be described. First of all, a minimum path metric value for each of the positive and negative decoders of the ACS unit is calculated. Herein, the minimum path metric value refers to the lowest value among the calculated minimum values for each state at ‘t’. Secondly, the minimum path metric values of the positive decoder and the negative decoder are compared, and the lower one of the two values is outputted as the polarity signal of the decoder. For example, when the minimum path metric value of the positive decoder is lower than the minimum path metric value of the negative decoder, the polarity signal is positive (+). In other words, the signal selects the positive decoder.

And, finally, in the section where the FLIP signal is low, the path metric values for each state of the decoders that are not selected by the polarity signal are overwritten by the path metric values corresponding to the selected decoders, and then the ACS operation is performed. For example, provided that the positive decoder is the selected decoder, the path metric values for each state of the positive decoder written over the path metric values for each state corresponding to the negative decoder. At this point, if the positive decoder is selected, then it is assumed that the polarity inversion did not occur. Conversely, if the negative decoder is selected, then it is assumed that the polarity inversion has occurred. Furthermore, the polarity inversion estimator, which estimates the polarity inversion as described above, may also be shared among the 12 Viterbi decoders.

In the Viterbi algorithm, the input of a surviving (or remaining) path, i.e., the survivor, which is selected from each state during the ACS operation, is stored, so as to maintain the path history during the time length of a decoding depth. The path history unit receives polarity signals (i.e., signals selecting one of the positive decoder and the negative decoder) outputted from the polarity inversion estimator and state numbers having minimum path metrics outputted from the ACS unit. Then, the path history unit traces-back the path history of the corresponding state, so as to output the final decision. In the path history unit, in the section where the FLIP signal is low, the path history for each state of the decoders that are not selected by the polarity signal are overwritten by the path history of the selected decoders, thereby renewing (or updating) the path history.

According to a general Viterbi decoding process, the symbols inputted to the Viterbi decoder includes the enhanced symbol and the main symbol. Therefore, the enhanced symbol survivor and the main symbol survivor are stored in the path history unit in the same order. Thus, the Viterbi decoder becomes the enhanced/main (E/M) integrated decoder, which decodes both the enhanced symbol and the main symbol. Also, the final outputs of the decoder are outputted in the same order at regular time intervals with the corresponding inputs. In the present invention, the E8-VSB Viterbi decoder includes 16 states, each state outputting 2 survivor bits from the ACS unit, which are then stored according to the time length of the decoding depth. Therefore, the E8-VSB Viterbi decoder requires a memory having the capacity of 16× decoding depth×2 bits. Furthermore, since the history for each of the positive decoder and the negative decoder should be maintained individually, the memory should have the capacity of 2×16× decoding depth×2 bits. Meanwhile, since 12 Viterbi decoders are required in the present invention, the memory of the E8-VSB Viterbi decoder requires a total capacity of 12×2×16× decoding depth×2 bits.

FIG. 11 illustrates an enhanced/main integrated Viterbi decoder according to a first embodiment of the present invention. The branch metric calculator 611 calculates the Euclidian distance between the input symbol and each of the 8 reference output levels, so as to obtain a total of 8 branch metric values. Then, the branch metric calculator 611 outputs the calculated branch metric values to the ACS unit 612 of the positive decoder and the ACS unit 613 of the negative decoder. At this point, the 8-level reference values used for calculating the branch metric value with the input symbol are −7, −5, −3, −1, +1, +3, +5, and +7. Particularly, −7, −5, −3, and −1 are reference output level values when C2 bit is equal to ‘0’, and +1, +3, +5, and +7 are reference output level values when C2 bit is equal to ‘1’.

In addition, as described above, the polarity inversion may occur when the input symbol is the enhanced symbol. More specifically, at state 0000 of ‘t−1’, when ‘0’ is inputted as the input X2 of the enhanced symbol processor 402, the reference 8-level value that is outputted from the trellis encoder 104 becomes-7, if the polarity inversion does not occur, and become +1, if the polarity inversion occurs, thereby forming a transition path from state 0000 of ‘t−1’ to state 0000 of ‘t’. Therefore, the metric value becomes different depending upon whether polarity inversion occurs or not within the same path.

Accordingly, the ACS unit 612 of the positive decoder receives the branch metric value of the instance when the polarity inversion has not occurred from the branch metric calculator 611. Then, the ACS unit 612 of the positive decoder receives the control signals, such as the E/M signal, the H/Q signal, the FLIP signal, and the PNEQ signal, from the map information recovery unit, so as to perform the ACS operation. In other words, for each two branches of each state, each of the ACS unit 612 of the positive decoder and the ACS unit 613 of the negative decoder respectively adds the corresponding branch metric value and the path metric value of a previous state, which is connected to the corresponding branch. Then, each of the ACS units 612 and 613 selects and stores the smallest value that is obtained. Thus, the survivor and the path selecting information are outputted to the path history units 615 and 616 of the positive decoder and the negative decoder, respectively. For example, when the inputted symbol is the enhanced symbol, the survivor for each state becomes the X2 and C2 bits, and when the inputted symbol is the main symbol, the survivor for each state becomes the X1 and C1 bits.

In addition, among the path metric values for each state, each of the ACS unit 612 of the positive decoder and the ACS unit 613 of the negative decoder selects the lowest value as the path metric value and outputs the selected value to the polarity inversion estimator 614. Then, the state number having the minimum (or lowest) path metric value is outputted to the path history unit 615 of the positive decoder and the path history unit 616 of the negative decoder.

In the present invention, in the symbol section (i.e., the section where the FLIP signal is high) causing the polarity inversion, the path metric value for each state of the selected decoder, which is selected in accordance with the polarity estimated from the polarity inversion estimator 614, is written over the path metric value for each state of the non-selected decoder. Thereafter, the ACS operation is performed. The polarity inversion estimator 614 receives the FLIP signal and the minimum path metric value from the ACS unit 612 of the positive decoder and the ACS unit 613 of the negative decoder and estimates the polarity inversion. For example, if it is determined that the minimum path metric value outputted from the ACS unit 613 of the negative decoder is smaller (or lower) than the minimum path metric value outputted from the ACS unit 612 of the positive decoder, then the polarity inversion estimator 614 estimates that polarity inversion has occurred. Conversely, if it is determined that the minimum path metric value outputted from the ACS unit 613 of the negative decoder is greater than the minimum path metric value outputted from the ACS unit 612 of the positive decoder, then the polarity estimator 614 estimates that polarity inversion has not occurred. Subsequently, the polarity estimator 614 outputs the polarity result to each of the ACS unit 612 and the path history unit 615 of the positive decoder and the ACS unit 613 and the path history unit 616 of the negative decoder, respectively.

Each of the path history unit 615 of the positive decoder and the path history unit 616 of the negative decoder receives the control signals, such as the E/M signal, the H/Q signal, the FLIP signal, and the PNEQ signal, the survivor, path selecting information, and the state number which has a minimum path metric value among states, so as to maintain the path history during the decoding depth. In addition, the state corresponding to the minimum path metric value for each of the decoders is back-traced, so that the survivor of a previous time, which precedes the time length of the decoding depth, is outputted to the decision selecting unit 617 as the decoding decision value. Furthermore, in the section where the FLIP signal is high, each of the path history units 615 and 616 of the positive decoder and the negative decoder writes the path history of the selected decoder, which is selected in accordance with the polarity signal, over the path history of the non-selected decoder.

The decision selecting unit 617 selects the decoding decision value of the selected decoder, which is selected in accordance with the polarity signal of the polarity inversion estimator 614, and outputs the selected value to the post-decoder 618 and the output multiplexer 619. For example, when the positive decoder is selected by the polarity inversion estimator 614, the decoding decision value outputted from the path history unit 615 of the positive decoder is selected and outputted. Among the decoding decision values, the C2 bit is outputted to the post-decoder 618, and the X2 or X1 bit is outputted to the output multiplexer 619.

More specifically, since the main symbol is pre-coded at the transmitting terminals, a post-decoding process (i.e., the reverse process of pre-coding) should be performed. In this case, the post-decoder 618 post-decodes the C2 bit without identifying whether the symbol is a main symbol or an enhanced symbol and, then, outputs the post-decoded C2 bit to the output multiplexer 619. When the symbol is the enhanced symbol, the output multiplexer 619 outputs the X2 bit instead of the post-decoded result, as the higher bit, and outputs a dummy bit as the X1 bit, which is the lower bit. On the other hand, when the symbol is the main symbol, the X1 bit is outputted as the lower bit and the post-decoded result is outputted as the higher bit.

Since the enhanced symbol is processed with additional convolution encoding, as compared with the main symbol, there is a significant difference between the enhanced symbol and the main symbol in performance after being decoded. However, when the enhanced symbol and the main symbol are inputted to the path history unit in combination, due to the small number of enhanced symbols within a set portion of the decoding depth, the valid decoding depth of the enhanced symbols may be reduced. As a result, the main symbols may cause the decoding effect of the enhanced symbols to be deficient. Such problems may worsen as the amount of the enhanced data becomes lower. Therefore, in order to reduce the influence of the main symbol on the enhanced symbol, only the enhanced symbols should be inputted to the path history unit, so as to ensure a set portion of valid decoding depth. Since the decision of the enhanced symbol is performed only on the X2 bit, the memory capacity required in the path history unit is 12×2×16× decoding depth×1 bit. However, since the main symbol and the enhanced symbol are multiplexed, the main symbol may interrupt the state transition of the enhanced symbol.

FIG. 12 illustrates an interruption of the state transition diagram of the enhanced symbol caused by the main symbol. Although the actual main symbol interruption occurs in multiples of 4 symbols, the interruption of only two symbols will be described with reference to FIG. 12 for simplicity. Herein, the enhanced symbol directly preceding the main symbol interruption will be referred to as a first enhanced symbol, and the enhanced symbol directly following the main symbol interruption will be referred to as a second enhanced symbol. The bold line shown in FIG. 12 describes the paths connected by state 0000 of the second enhanced symbol. Referring to FIG. 12, the first enhanced symbol includes 8 states, which can be connected to each state of the second enhanced symbol. In other words, each state of the second enhanced symbol includes 2 branches in accordance with the input X2 bit, and herein, 4 states can be connected to each branch. At this point, the enhanced-only Viterbi decoder should estimate the state transition from the first enhanced symbol to the second enhanced symbol. Therefore, two different methods of dealing with the main symbol interruption from the ACS unit of the enhanced-only Viterbi decoder may be proposed, which will now be described as follows.

In the first method, each of the 8 states that can be connected to each state of when performing the ACS operation during the second enhanced symbol section, without performing the ACS operation during the first the main symbol section, is compared to one another, so that the state having the minimum metric value can be selected. More specifically, there are two branches in each state during the second enhanced symbol, wherein each branch may be connected to 4 states of the first enhanced symbol. Accordingly, the state having the minimum metric value among the 4 states (i.e., the path metric value of the previous state) is selected, and the selected path metric of the previous state is added to the branch metric value of the corresponding branch. The added result becomes the current path metric value of each branch. At this point, since each state of the second enhanced symbol includes 2 branches, the current metric value of the two branches for each state is compared to one another, so as to select the smallest (or lowest) path metric value and to store the path metric value of the corresponding state. Thereafter, the survivor of the selected path and the path selecting information is outputted to the path history unit.

On the other hand, in the second method, by performing the ACS operation during the main symbol section, the state transition can be continuously estimated during the main symbol section. Although the ACS operation is performed during the main symbol section, the enhanced-only Viterbi decoder does not store the selected survivor in the path history unit during the main symbol section. However, the path selecting information, which is obtained by the ACS operation in the main symbol section, is used to exchange the path history of each state at the path history unit. For example, only the path selecting information, which is obtained by the ACS operation for the main symbol, is outputted to the path history unit, and the survivor of the selected path may not be outputted to the path history unit. In another example, the survivor and the path selecting information that are obtained by the ACS operation result are all outputted to the path history unit. And, when the symbol inputted from the path history unit is the main symbol, then the survivor may not be received and only the path selecting information may be received. Furthermore, since the path history unit of the enhanced-only Viterbi decoder only operates when the input survivor is the enhanced symbol, the order of the finally decoded and outputted symbol may be different from that of the symbol of the Viterbi decoder input.

FIG. 13 illustrates the above-described effect in detail. Part (a) of FIG. 13 shows an input symbol sequence being inputted to any one of the 12 Viterbi decoders. Referring to FIG. 13, E represents the enhanced symbol, M represents the main symbol, and the numeral following E or M represents the time index. Part (b) of FIG. 13 shows a symbol column being finally outputted from an enhanced/main integrated Viterbi decoder, wherein it is known that decoding decision values are outputted in the same order of the input symbol sequence, after a set portion of decoding depth. Finally, part (c) of FIG. 13 shows the output order of the decoding decision values of the enhanced-only Viterbi decoder.

As shown in part (c) of FIG. 13, since 8 enhanced symbols should be inputted to the path history unit in order to make a decision for an input E1 (i.e., decoding depth=8 assumptions), the decision for E1 can be made when E17 is inputted. In the input terminal of the Viterbi decoder, the symbols are inputted in the order of symbols E1, E2, E3, and E4, then symbols M5, M6, M7, and M8, followed by symbols E9, E10, E11, and E12. Subsequently, in the final output, symbols E1, E2, E3, and E4 and symbols E9, E10, E11, and E12 are outputted consecutively. This is because the path history unit of the enhanced-only Viterbi decoder is only operated when enhanced symbols are inputted. Therefore, the decoding decision of the enhanced-only Viterbi decoder should be re-ordered to be in the same order as that of the input symbol column.

FIG. 14 illustrates a re-ordering of decoded enhanced symbol outputs. The decoding decision, which is outputted from the path history unit of each 12 Viterbi decoders, is serially outputted in a time-division method. Accordingly, a demultiplexer stores the corresponding decoded decision value in a first-in first-out (FIFO) unit in accordance with a way signal (i.e., signal indicating which of the 12 decoders is being used). At this point, since the FIFO unit performs buffering only on the enhanced symbol, the demultiplexer operates only during the section where the E/M flag is high. In addition, a first multiplexer (MUX1) also operates only during the section where the E/M flag is high and receives a way signal, so as to output the output of the corresponding FIFO unit. Referring to FIG. 14, the E/M flag and the way signal used in the first multiplexer (MUX1) has a set amount of time delay as compared to the signals used in the demultiplexer. Meanwhile, an E/M flag used in a second multiplexer (MUX2) is identical to that of the first multiplexer (MUX1). Also, the second multiplexer (MUX2) multiplexes the output of the first multiplexer (MUX1) during the section where the E/M flag is high. Alternatively, during the section where the E/M flag is low, the second multiplexer (MUX2) either outputs a set of dummy data or multiplexes and outputs the output of the main-only Viterbi decoder. When the dummy data is multiplexed, the enhanced symbol and the main symbol are each outputted through a separate path from the final output of the Viterbi decoder. On the other hand, when the main symbol is multiplexed, the decoded result of the enhanced symbol and the main symbol is outputted through a single path.

FIG. 15 illustrates an enhanced-only Viterbi decoder according to a second embodiment of the present invention. A branch metric calculator 811 and a polarity inversion estimator 814 of the enhanced-only Viterbi decoder are identical to those of the enhanced/main integrated Viterbi decoder, shown in FIG. 11, and so the description of the same will be omitted for simplicity. Also, the operations of an ACS unit 812 of a positive decoder and an ACS unit 813 of a negative decoder have been described above. In the enhanced-only Viterbi decoder, the survivor being outputted to the path history unit includes only one X2 bit. Therefore, the memory capacity required in the path history units 815 and 816 is 12×2×16× decoding depth×1 bit. Furthermore, the enhanced-only Viterbi decoder further includes a re-ordering unit 818 for performing the re-ordering of the output as described in FIG. and FIG. 14. Since the main-only Viterbi decoder is identical to the Viterbi decoder of the conventional ATSC 8T-VSB receiver, the description of the same will be omitted.

The channel equalizing system used in the E8-VSB receiving system performs channel equalization by using an 8-level decision. The decision value obtained by using a Viterbi decoding process is more reliable than the decision value obtained by using an 8-level slicer. Therefore, in the present invention, by feeding-back the 8-level decision that is performed from the Viterbi decoder to the channel equalizing system, the capacity of channel equalization may be enhanced.

In order to feed-back decision from the ACS unit, a state having the minimum path metric value is identified from the ACS unit of the E8-VSB Viterbi decoder. Then, an output level (i.e., one of the 8 levels) of a selected path of the identified state is fed-back to the channel equalizing system. At this point, one of the output levels of each ACS unit of the positive and negative decoders is selected in accordance with the polarity signal, which is outputted from the polarity inversion estimator of the enhanced symbol. Thereafter, the selected output level is fed-back to the channel equalizing system. This generally corresponds to the decision feedback of the Viterbi decoder, when the decoding depth is ‘0’.

The reliability of a decision value of the Viterbi decoder may increase in accordance with an increase of the decoding depth to a certain extent. However, the increase of the decoding depth may cause a longer time delay before the decoding decision. When the decoding depth of the Viterbi decoder of the E8-VSB receiver increases by 1, the time delay of the decision feedback may increase as much as 12 symbols. However, in the channel equalizing system, when the path history unit feeds-back the decoding decision for each decoding depth, a decision value having a maximum reliability within a range allowed by the time delay may be obtained and used. Accordingly, when the survivor is outputted from the ACS unit of the Viterbi decoder, the output level information (i.e., 3 bits including C2C1C0) of a selected path should also be added. Then, the path history unit stores the output level information (i.e., the 3 bits C2C1C0) and maintains the history corresponding to the time equivalent to the decoding depth. Furthermore, the survivor of the state having the minimum path metric value is outputted at each trace-back stage, so as to feed-back the outputted survivor to the channel equalizing system.

In the channel equalizing system, the decisions for each of the enhanced symbol and the main symbol should all be fed-back and the decision delay should be reduced. Therefore, it is preferable that the feedback is performed while setting the enhanced/main integrated Viterbi decoder as the basic decoder. Accordingly, when the survivor is outputted from the ACS unit of FIG. 11, the 3 bits C2C1C0 are additionally outputted. Then, the 3 bits C2C1C0 are added to the conventional 2 bits and stored in the path history unit. Thereafter, the state having the minimum path metric value, which is inputted from the ACS unit, is identified, and C2C1C0 for each decoding depth are outputted and fed-back through the channel equalizing system. Evidently, the feedback outputted from the positive decoder and the feedback outputted from the negative decoder should be selected in accordance with the polarity signal of the polarity inversion estimator.

The Viterbi decoder of the E8-VSB receiving system has the following advantages. First of all, an enhanced symbol and a main symbol may all be decoded. When using the enhanced symbol, an enhanced symbol processor and a trellis encoder being concatenated to one another are collectively decoded, thereby enhancing the decoding capacity. Moreover, the enhanced symbol is divided into a ½ enhanced symbol and a ¼ enhanced symbol, which are decoded accordingly. Herein, the decoding of the ¼ enhanced symbol is more reliable than the decoding of the ½ enhanced symbol. Also, in the present invention, a polarity inversion of the enhanced symbol can be estimated. Furthermore, an enhanced-only Viterbi decoder is configured in order to minimize the adverse effect that the main symbol may cause to the decoding capacity of the enhanced symbol. Finally, an 8-level decision performed at the Viterbi decoder is fed-back to a channel equalizing system, thereby enhancing the channel equalizing capacity.

The terminologies used in the description of the present invention have been defined while taking into account the functions of the present invention. Such terminologies may vary depending upon the intentions or practice of those skilled in the art. Therefore, a specific definition for each term should be made and given based on the overall description of the present invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A method for processing a digital television (DTV) broadcast signal in a broadcasting receiver, the method comprising:

receiving, by a tuner, the DTV broadcast signal including enhanced data;

equalizing the received DTV broadcast signal by compensating channel distortion of the received DTV broadcast signal;

decoding signaling information from the equalized DTV broadcast signal, wherein the signaling information includes information indicating whether the enhanced data are coded at a ½ code rate or at a ¼ code rate;

decoding, by a decoder, the enhanced data included in the equalized DTV broadcast signal; and

derandomizing, by a derandomizer, the decoded enhanced data,

wherein the enhanced data in the received DTV broadcast signal are generated in a broadcast transmitter by:

randomizing original enhanced data,

first Reed Solomon (RS) encoding the randomized original enhanced data,

convolutional encoding the first RS-encoded original enhanced data,

second RS encoding the convolutional encoded original enhanced data,

interleaving the second RS-encoded original enhanced data, and

trellis encoding the interleaved original enhanced data.

2. The method of claim 1, wherein the received DTV broadcast signal further includes main data that the convolutional encoding is not performed.

3. The method of claim 1, wherein the enhanced data is decoded based on the signaling information.

4. The method of claim 1, wherein the received DTV broadcast signal further includes segment synchronization data and field synchronization data.

5. A broadcasting receiver for processing a digital television (DTV) broadcast signal, the broadcasting receiver comprising:

a tuner for receiving the DTV broadcast signal including enhanced data;

an equalizer for equalizing the received DTV broadcast signal by compensating channel distortion of the received DTV broadcast signal;

an information recovery unit for decoding signaling information from the equalized DTV broadcast signal, wherein the signaling information includes information indicating whether the enhanced data are coded at a ½ code rate or at a ¼ code rate;

a decoder for decoding the enhanced data included in the equalized DTV broadcast signal; and

a derandomizer for derandomizing the decoded enhanced data,

wherein the enhanced data in the received DTV broadcast signal are generated in a broadcast transmitter by:

randomizing original enhanced data,

first Reed Solomon (RS) encoding the randomized original enhanced data,

convolutional encoding the first RS-encoded original enhanced data,

second RS encoding the convolutional encoded original enhanced data,

interleaving the second RS-encoded original enhanced data, and

trellis encoding the interleaved original enhanced data.

6. The broadcasting receiver of claim 5, wherein the received DTV broadcast signal further includes main data that the convolutional encoding is not performed.

7. The broadcasting receiver of claim 5, wherein the decoder decodes the enhanced data based on the signaling information.

8. The broadcasting receiver of claim 5, wherein the received DTV broadcast signal further includes segment synchronization data and field synchronization data.

9. A method for processing a broadcast signal in a broadcasting receiver, the method comprising:

receiving the broadcast signal including first enhanced data encoded at a first code rate, second enhanced data encoded at a second code rate, and signaling information;

demodulating the received broadcast signal;

decoding the signaling information in the demodulated broadcast signal,

wherein the decoded signaling information includes information for identifying the first code rate of the first enhanced data and the second code rate of the second enhanced data;

deinterleaving the first enhanced data in the demodulated broadcast signal;

deinterleaving the second enhanced data in the demodulated broadcast signal;

decoding the deinterleaved first enhanced data; and

decoding the deinterleaved second enhanced data.

10. The method of claim 9, wherein the broadcast signal further includes main data multiplexed with the first and second enhanced data.

11. The method of claim 10, wherein the decoded signaling information further includes multiplexing information of the main data and the first and second enhanced data.

12. The method of claim 11, further comprising:

demultiplexing the main data and the first and second enhanced data based on the multiplexing information.