Liquid crystal display

Abstract

To reduce viewing angle dependence of γ characteristics in a normally black liquid crystal display.

Each pixel 10 has a first sub-pixel 10a and a second sub-pixel 10b which can apply mutually different voltages to their respective liquid crystal layers. Relationships ΔV12 (gk)>0 volts and ΔV12 (gk)≥ΔV12 (gk+1) are satisfied at least in a range 0<gk≤n−1 if it is assumed that ΔV12=V1−V2, where ΔV12 is the difference between root-mean-square voltage V1 applied to the liquid crystal layer of the first sub-pixel 10a and root-mean-square voltage V2 applied to the liquid crystal layer of the second sub-pixel 10b.

Description

Vlcb=Vs−Vd

At this time, the voltages Vcsa and Vcsb of the respective storage capacitor lines are:
Vcsa=Vcom−Vad
Vcsb=Vcom+Vad

At time T3, the voltage Vcsa of the storage capacitor line 24a connected to the storage capacitor Csa changes from “Vcom−Vad” to “Vcom+Vad” and the voltage Vcsb of the storage capacitor line 24b connected to the storage capacitor Csb changes by twice Vad from “Vcom+Vad” to “Vcom−Vad.” As a result of the voltage changes of the storage capacitor lines 24a and 24b, voltages Vlca and Vlcb of the respective sub-pixels change to:
Vlca=Vs−Vd+2×K×Vad
Vlcb=Vs−Vd−2×K×Vad
where, K=CCS/(CLC (V)+CCS)

At time T4, Vcsa changes from “Vcom+Vad” to “Vcom−Vad” and Vcsb changes from “Vcom−Vad” to “Vcom+Vad,” by twice Vad. Consequently, Vlca and Vlcb change from:
Vlca=Vs−Vd+2×K×Vad
Vlcb=Vs−Vd−2×K×Vad
To:
Vlca=Vs−Vd
Vlcb=Vs−Vd

At time T5, Vcsa changes from “Vcom−Vad” to “Vcom+Vad,” by twice Vad and Vcsb changes from “Vcom+Vad” to “Vcom−Vad,” by twice Vad. Consequently, Vlca and Vlcb change from:
Vlca=Vs−Vd
Vlcb=Vs−Vd
To:
Vlca=Vs−Vd+2×K×Vad
Vlcb=Vs−Vd−2×K×Vad

Vcsa, Vcsb, Vlca, and Vlcb alternate the above changes at T4 and T5 at intervals of an integral multiple of horizontal write time 1H. The multiple—1, 2, or 3—used for the alternating intervals can be set, as required, by taking into consideration a drive method (method of polarity inversion, etc.) and display conditions (flickering, graininess, etc.) of the liquid crystal display. These alternating cycles are repeated until the pixel 10 is rewritten the next time, i.e., until a time equivalent to T1. Thus, effective values of the voltages Vlca and Vlcb of the sub-pixels are:
Vlca=Vs−Vd+K×Vad
Vlcb=Vs−Vd−K×Vad

Thus, the root-mean-square voltages V1 and V2 applied to the liquid crystal layers 13a and 13b of the sub-pixels 10a and 10b are:
V1=Vlca−Vcom
V2=Vlcb−Vcom
Hence,
V1=Vs−Vd+K×Vad−Vcom
V2=Vs−Vd−K×Vad−Vcom

Therefore, difference ΔV12 (=V1−V2) between the root-mean-square voltages applied to the liquid crystal layers 13a and 13b of the sub-pixels 10a and 10b is given as ΔV12=2×K×Vad (where, K=CCS/(CLC (V)+CCS)). This means that mutually different voltages can be applied.

The relationship between V1 and V2 according to this embodiment shown in FIGS. 12 to 14 is shown schematically in FIG. 15.

As can be seen from FIG. 15, in the liquid crystal display 200 according to this embodiment, the smaller the value of V1, the larger the value of ΔV12. This is similar to the results obtained under the voltage condition C described above. The fact that the value of ΔV12 changes depending on V1 or V2 is attributable to voltage dependence of the capacitance value CLC (V) of the liquid crystal capacitor.

The γ characteristics of the liquid crystal display 200 according to this embodiment is shown in FIG. 16. The γ characteristics obtained when the same voltage is applied to the sub-pixels 10a and 10b are also shown in FIG. 16 for comparison. It can be seen from the figure that γ characteristics are improved also in the liquid crystal display according to this embodiment.

As described above, embodiments of the present invention can improve the γ characteristics of normally black liquid crystal displays, especially MVA liquid crystal displays. However, the present invention is not limited to this and can be applied to IPS liquid crystal displays as well.

Next, description will be given of liquid crystal displays according to embodiments in a second aspect of the present invention.

Description will be given of a preferred form of a pixel arrangement (array of sub-pixels) or drive method which can reduce “flickering” on a liquid crystal display where each pixel has at least two sub-pixels differing from each other in brightness when displaying an intermediate grayscale. Although configuration and operation of the liquid crystal display according to this embodiment will be described here taking as an example the liquid crystal display with the divided pixel structure according to the embodiment in the first aspect of the present invention, the effect produced by a pixel arrangement is not restricted by a method of pixel division, and a liquid crystal display with another divided-pixel structure may be used as well.

A problem of “flickering” on a liquid crystal display will be described first.

Typical liquid crystal displays are designed to use alternating voltage as the voltage applied to liquid crystal layers of pixels (sometimes referred to as an “ac driving method”) from a reliability point of view. Magnitude relationship in potential between pixel electrode and counter electrode is reversed at certain time intervals, and consequently, direction of the electric field (electric lines of force) applied to each liquid crystal layer is reversed at the time intervals. With typical liquid crystal displays in which the counter electrode and pixel electrode are mounted on different substrates, the direction of the electric field applied to each liquid crystal layer is reversed from the light source-to-viewer direction to the viewer-to-light source direction.

Typically, the direction reversal cycle of the electric field applied to each liquid crystal layer is twice (e.g., 33.333 ms) the frame period (e.g., 16.667 ms). In other words, in a liquid crystal display, the direction of the electric field applied to each liquid crystal layer is reversed each time a displayed image (frame image) changes. Thus, when displaying a still image, if electric field strengths (applied voltages) in alternate directions do not match exactly, i.e., if the electric field strength changes each time the direction of the electric field changes, the brightness of pixels changes with changes in the electric field strength, resulting in flickering of the display.

To prevent flickering, it is necessary to equate the electric field strengths (applied voltages) in alternate directions exactly. However, with liquid crystal displays produced industrially, it is difficult to exactly equate the electric field strengths in alternate directions. Therefore, to reduce flickering, pixels with electric fields opposite in direction are placed next to each other, thereby averaging brightness of pixels spatially. Generally, this method is referred to as “dot inversion” or “line inversion.” Various “inversion driving” methods are available, including inversion of a checkered pattern on a pixel by pixel basis (row-by-row, column-by-column polarity inversion: 1-dot inversion), line-by-line inversion (row-by-row inversion: 1-line inversion), and polarity inversion every two rows and every column. One of them is selected as required.

As described above, to implement high quality display, preferably the following three conditions are satisfied: (1) use ac driving so that the direction of the electric field applied to each liquid crystal layer is reversed at certain time intervals, for example, every frame period, (2) equate the voltages applied to each liquid crystal layer (or quantities of electric charge stored in the liquid crystal capacitor) in alternate field directions as well as quantities of electric charge stored in the storage capacitor, and (3) place pixels opposite in the direction of the electric field (sometimes referred to as “voltage polarity”) applied to the liquid crystal layer, next to each other in each vertical scanning period (e.g., frame period). Incidentally, the term “vertical scanning period” can be defined as the period after a scan line is selected until the scan line is selected again. One scanning period is equivalent to one frame period in the case of non-interlaced driving and corresponds to one field period in the case of interlaced driving. Also, in each vertical scanning period, the difference (period) between the time when a scan line is selected and the time when the scan line is selected again is referred to as one horizontal scanning period (1 H).

The above-described embodiment of the present invention implements display with excellent viewing angle characteristics by dividing each pixel into at least two sub-pixels and making their brightness (transmittance) different from each other. The inventor found that when each pixel is divided into a plurality of sub-pixels which are intentionally made to vary in brightness, it is preferable that a fourth condition concerning sub-pixel arrangement is satisfied in addition to the three conditions described above. Specifically, it is preferable that the sub-pixels which are intentionally made to vary in brightness are placed in random order of brightness whenever possible. It is most preferable in terms of display quality not to place sub-pixels equal in brightness next to each other in the column or row direction. In other word, most preferably sub-pixels equal in brightness are arranged in a checkered pattern.

A drive method, pixel arrangement, and sub-pixel arrangement suitable for the above-described embodiment of the present invention will be described below.

An example of a drive method for the liquid crystal display according to the embodiment of the present invention will be described with reference to FIGS. 17 and 18.

Description will be given below, citing an example in which pixels are arranged in a matrix (rp, cq) with a plurality of rows (1 to rp) and plurality of columns (1 to cq), where each pixel is expressed as P (p, q) (where 1≤p≤rp and 1≤q≤cq) and has at least two sub-pixels SPa (p, q) and SPb (p, q), as shown in FIG. 17. FIG. 17 is a schematic diagram partially showing a relative arrangement (8 rows×6 columns) of: signal lines S-C1, S-C2, S-C3, S-C4, . . . , S-Ccq; scan lines G-L1, G-L2, G-L3, . . . , G-Lrp; storage capacitor lines CS-A and CS-B; pixels P (p, q); and sub-pixels SPa (p, q) and SPb (p, q) which compose the pixels, in the liquid crystal display according to this embodiment.

As shown in FIG. 17, one pixel P (p, q) has sub-pixels SPa (p, q) and SPb (p, q) on either side of the scan line G-Lp which runs through the pixel horizontally at approximately the center. The sub-pixels SPa (p, q) and SPb (p, q) are arranged in the column direction in each pixel. The storage capacitor electrodes (not shown) of the sub-pixels SPa (p, q) and SPb (p, q) are connected to adjacent storage capacitor lines CS-A and CS-B, respectively. The signal lines S-Ccq which supply signal voltages to the pixels P (p, q) according to the image displayed run vertically (in the column direction) between pixels to supply the signal voltages to TFT elements (not shown) of the sub-pixels on the right of the signal lines. According to the configuration shown in FIG. 17, one storage capacitor line or one scan line is shared by two sub-pixels. This has the advantage of increasing the opening rate of pixels.

FIG. 18 shows the waveforms (a)-(j) of various voltages (signals) used to drive a liquid crystal display with the configuration shown in FIG. 17. By driving the liquid crystal display which has the configuration shown in FIG. 17 with voltages which have the voltage waveforms (a)-(j) shown FIG. 18, it is possible to satisfy the four conditions described above.

Next, description will be given of how the liquid crystal display according to this embodiment satisfies the four conditions described above. For the simplicity of explanation, it is assumed that all pixels are displaying an intermediate grayscale.

In FIG. 18, the waveform (a) is display signal voltage waveforms (source signal voltage waveforms) supplied to the signal lines S-C1, S-C3, S-C5, . . . (a group of odd-numbered signal lines are sometimes referred to as S-O); the waveform (b) is display signal voltage waveforms supplied to the signal lines S-C2, S-C4, S-C6, . . . (a group of even-numbered signal lines are sometimes referred to as S-E); the waveform (c) is a storage capacitor counter voltage waveform supplied to the storage capacitor line CS-A; the waveform (d) is a storage capacitor counter voltage waveform supplied to CS-B; the waveform (e) is a scan voltage waveform supplied to the scan line G-L1; the waveform (f) is a scan voltage waveform supplied to the scan line G-L2; the waveform (g) is a scan voltage waveform supplied to the scan line G-L3; the waveform (h) is a scan voltage waveform supplied to the scan line G-L4; the waveform (i) is a scan voltage waveform supplied to the scan line G-L5; and the waveform (j) is a scan voltage waveform supplied to the scan line G-L6. The period between the time when the voltage of a scan line changes from a low level (VgL) to a high level (VgH) and the time when the voltage of the next scan line changes from VgL to VgH constitutes one horizontal scanning period (1 H). The period during which the voltage of a scan line remains at a high level (VgH) is sometimes referred to as a selection period PS.

Since all pixels are displaying an intermediate grayscale, all display signal voltages (waveforms (a) and (b) in FIG. 18) have oscillating waveforms of fixed amplitude. Also, the oscillation period of the display signal voltages is two horizontal scanning periods (2 H). The reason why the display signal voltages are oscillating and the voltage waveforms of the signal lines S-O (S-C1, S-C3, . . . ) and voltage waveforms of the signal lines S-E (S-C2, S-C4, . . .) are 180 degrees out of phase is to satisfy the third condition above. Generally, in TFT driving, signal line voltages transmitted to a pixel electrode via TFT elements are affected by changes in scan voltage waveforms (sometimes called a drawing phenomenon). Considering the drawing phenomenon, the counter voltage is positioned approximately at the center of the signal line voltage waveform after the latter is transmitted to the pixel electrode. In FIG. 18, where the pixel electrode voltage waveform is higher than counter voltage, the signal voltage is indicated by a “+” sign and where the pixel electrode voltage waveform is lower than counter voltage, the signal voltage is indicated by a “−” sign. The “+” and “−” signs correspond to the directions of the electric field applied to the liquid crystal layers. The directions of the electric field are opposite between when the sign is “+” and when it is “−”.

As described above with reference to FIGS. 12 to 15, when the scan voltage of a scan line is VgH, the TFT connected to the scan line is turned on, causing the display signal voltage to be supplied to the sub-pixel connected to the TFT. Then, when the scan voltage of the scan line becomes VgL, the storage capacitor counter voltage changes. Since the changes (including the direction and sign of the changes) of the storage capacitor counter voltage differ between the two sub-pixels, so do the root-mean-square voltages applied to the sub-pixels.

In the example shown in FIG. 18, both oscillation amplitudes and periods of the storage capacitor counter voltages (waveforms (c) and (d)) take the same values between the storage capacitor lines CS-A and CS-B: for example, twice Vad (see FIGS. 14) and 1 H, respectively. Also, the oscillating waveforms of CS-A and CS-B will overlap if one of them is phase-shifted 180 degrees. That is, they are 0.5 H out of phase with each other. An average voltage of each sub-pixel electrode is higher than the display signal voltage of the corresponding signal line existing during the period when the corresponding scan line is in VgH state if the first voltage change of the corresponding storage capacitor line after the voltage of the corresponding scan line changes from VgH to VgL is an increase, but it is lower than the display signal voltage of the corresponding signal line existing during the period when the corresponding scan line is in VgH state if the first voltage change of the corresponding storage capacitor line is a decrease.

Consequently, if the display signal voltage (waveform (a) or (b)) in FIG. 18 is marked by a “+” sign, the root-mean-square voltage applied to the liquid crystal layer is higher when the voltage change of the storage capacitor line is on the rise than when it is on the decline. On the other hand, if the display signal voltage (waveform (a) or (b)) in FIG. 18 is marked by a “−” sign, the root-mean-square voltage applied to the liquid crystal layer is lower when the voltage change of the storage capacitor line is on the rise than when it is on the decline.

FIG. 17 shows states of the pixels P (p, q) and sub-pixels SPa (p, q) and SPb (p, q) in a vertical scanning period (frame period, in this example). The following three symbols shown symmetrically with respect to the scan line of each sub-pixel indicate states of the sub-pixel.

The first symbol H or L indicates the magnitude relationship of the root-mean-square voltage applied to the sub-pixel, where the symbol H means that the applied root-mean-square voltage is high while the symbol L means that the applied root-mean-square voltage is low. The second symbol “+” or “−” indicates the magnitude relationship of voltages between the counter electrode and sub-pixel electrode. In other words, it indicates the directions of the electric field applied to the liquid crystal layer. The symbol “+” means that the voltage of the sub-pixel electrode is higher than the voltage of the counter electrode while the symbol “−” means the voltage of the sub-pixel electrode is lower than the voltage of the counter electrode. The third symbol A or B indicates whether the appropriate storage capacitor line is CS-A or CS-B.

Look at the states of sub-pixels SPa (1, 1) and SPb (1, 1) of the pixel P (1, 1), for example. As can be seen from the waveforms (a) to (e) shown in FIG. 18, during the period when GL-1 is selected (period PS in which the scan voltage is VgH), the display signal voltage is “+.” When the scan voltage of GL-1 changes from VgH to VgL, the voltages of the storage capacitor lines of respective sub-pixels (waveforms (c) and (d)) are in the states indicated by the arrows (the first arrows from the left) shown in FIG. 18. Thus, after the scan voltage of GL-1 changes from VgH to VgL, the first voltage change of the storage capacitor counter voltage of SPa (1, 1) is an increase (indicated by “U” in the waveform (c)) as shown in FIG. 18. On the other hand, after the scan voltage of GL-1 changes from VgH to VgL, the first voltage change of the storage capacitor counter voltage of SPb (1, 1) is a decrease (indicated by “D” in the waveform (d)) as shown in FIG. 18. Therefore, the root-mean-square voltage of SPa (1, 1) increases while the root-mean-square voltage of SPb (1, 1) decreases. Hence, the applied root-mean-square voltage of SPa (1, 1) is higher than that of SPb (1, 1), and a symbol H is attached to SPa (1, 1) and a symbol L is attached to SPb (1, 1).

According to the waveform (b) shown in FIG. 18, during the period when GL-1 is selected, the display signal voltages for SPa (1, 2) and SPb (1, 2) of P (1, 2) is When the scan voltage of GL-1 changes from VgH to VgL, the voltages of the storage capacitor lines of respective sub-pixels (waveforms (c) and (d)) are in the states indicated by the arrows (the first arrows from the left) shown in FIG. 18. Thus, after the scan voltage of GL-1 changes from VgH to VgL, the first voltage change of the storage capacitor counter voltage of SPa (1, 2) is an increase (“U”) as shown in FIG. 18. On the other hand, after the scan voltage of GL-1 changes from VgH to VgL, the first voltage change of the storage capacitor counter voltage of SPb (1, 2) is a decrease (“D”) as shown in FIG. 18. Therefore, the root-mean-square voltage of SPa (1, 2) decreases while the root-mean-square voltage of SPb (1, 2) increases. Hence, the applied root-mean-square voltage of SPa (1, 2) is lower than that of SPb (1, 2), and a symbol L is attached to SPa (1, 2) and a symbol H is attached to SPb (1, 2).

According to the waveform (a) shown in FIG. 18, during the period when GL-2 is selected, the display signal voltages for (2, 1) and SPb (2, 1) of P (2, 1) is “−”. When the scan voltage of GL-2 changes from VgH to VgL, the voltages of the storage capacitor lines of respective sub-pixels (waveforms (c) and (d)) are in the states indicated by the arrows (the second arrows from the left) shown in FIG. 18. Thus, after the scan voltage of GL-2 changes from VgH to VgL, the first voltage change of the storage capacitor counter voltage of SPa (2, 1) is a decrease (“D”) as shown in FIG. 18D. On the other hand, after the scan voltage of GL-2 changes from VgH to VgL, the first voltage change of the storage capacitor counter voltage of SPb (2, 1) is an increase (“U”) as shown in FIG. 18C. Therefore, the root-mean-square voltage of SPa (2, 1) increases while the root-mean-square voltage of SPb (2, 1) decreases. Hence, the applied root-mean-square voltage of SPa (2, 1) is higher than that of SPb (2, 1), and a symbol H is attached to SPa (2, 1) and a symbol L is attached to SPb (2, 1). The states shown in FIG. 17 are brought about in this way.

The liquid crystal display according to this embodiment can be driven in such a way as to satisfy the first condition.

Since FIGS. 17 and 18 show states in a frame period, it is not possible to assess from the figures whether the first condition is satisfied. However, by shifting the phase of the voltage waveform on each signal line (S-O (FIG. 18A) or S-E (FIG. 18B)) by 180 degrees from frame to frame, for example, in FIG. 18, it is possible to implement ac driving where the direction of the electric field applied to each liquid crystal layer is reversed every frame period.

Furthermore, in the liquid crystal display according to this embodiment, to prevent the magnitude relationship of the sub-pixels of the pixels, i.e., the order of brightness of the sub-pixels in a display screen (relative positions of “H” and “L” in FIG. 17) from being changed from frame to frame, the phase of the voltage waveforms on the storage capacitor lines CS-A and CS-B is changed by 180 degrees as the phase of the voltage waveforms on the signal lines is changed. Consequently, the “+” signs and “−” signs shown in FIG. 17 are inverted in the next frame (for example, (+, H) ⇔(−, H), and (+, L) ⇔(−, L). The first condition described above can be satisfied in this way.

Now, we will examine whether the second condition is satisfied, i.e., whether the liquid crystal layer of each sub-pixel (storage capacitor of the sub-pixel) is charged to the same level in different field directions. In the liquid crystal display according to this embodiment, where different root-mean-square voltages are applied to the liquid crystal layers of the sub-pixels in each pixel, display quality such as flickering is decisively influenced by sub-pixels ranked high in brightness, i.e., the sub-pixels indicated by the symbol “H” in FIG. 17. Thus, the second condition is imposed especially on the sub-pixels indicated by the symbol “H.”

The second condition will be described with reference to voltage waveforms shown in FIG. 18.

The liquid crystal capacitor and storage capacitor of sub-pixels are charged during the period when the voltage of the corresponding scan line is VgH (selection period PS). The quantity of electric charge stored in the liquid crystal capacitor depends on the voltage difference between the display signal voltage of the signal line and counter voltage (not shown in FIG. 18) during the selection period while the quantity of electric charge stored in the storage capacitor depends on the voltage difference between the display signal voltage of the signal line and voltage of the storage capacitor line (storage capacitor counter voltage) during the selection period.

As shown in FIG. 18, the display signal voltage in each selection period can be one of the two types indicated by the “+” or “−” sign in the figures. In either case, there is no voltage change during each selection period. Regarding the counter voltage (not shown), the same DC voltage which does not vary with time is applied to all the sub-pixels.

There are two types of storage capacitor line CS-A and CS-B. The voltage waveform of CS-A is the same during the selection period of any scan line. Similarly, the voltage waveform of CS-B is the same during the selection period of any scan line. In other words, the DC component (DC level) of the voltage of the storage capacitor lines takes the same value during the selection period of any scan line.

Thus, it is possible to satisfy the second condition by adjusting the DC components (DC levels) of the following voltages as required: display signal voltage of each scan line, voltage of the counter electrode, and voltage of each storage capacitor line.

Next, we will verify whether the third condition is satisfied, i.e., whether pixels opposite in field direction are placed next to each other in each frame period. In the liquid crystal display according to this embodiment, where different root-mean-square voltages are applied to the liquid crystal layers of sub-pixels in each pixel, the third condition applies to the relationship between the sub-pixels which are supplied with the same root-mean-square voltage as well as to the pixels. It is especially important that the third condition be satisfied by the sub-pixels ranked high in brightness, i.e., the sub-pixels indicated by the symbol “H” in FIG. 17, as is the case with the second condition.

As shown in FIG. 17, the “+” and “−” symbols which indicate the polarities (directions of the electric field) of each pixel invert every two pixels (two columns) in the row direction (horizontal direction) such as (+, −), (+, −), (+, −), and every two pixels (two rows) in the column direction (vertical direction) such as (+, −), (+, −), (+, −), (+, −) Viewed on a pixel-by-pixel basis, they exhibit a state called dot inversion, satisfying the third condition.

Next, we will look at the sub-pixels ranked high in brightness, i.e., the sub-pixels indicated by the symbol “H” in FIG. 17.

Referring to FIG. 17, there is no polarity inversion in the row direction as shown, for example, by +H, +H, +H for the sub-pixels SPa in the first row, but the polarity is inverted every two pixels (two rows) in the column direction as shown, for example, by (+H, −H), (+H, −H), (+H, −H), (+H, −H) in the first column. The state known as line inversion can be observed at the level of the particularly important sub-pixels ranked high in brightness, which means that they satisfy the third condition. The sub-pixels indicated by the symbol L are also arranged in a regular pattern, satisfying the third condition.

Next, we will discuss the fourth condition. The fourth condition requires that sub-pixels equal in brightness should not be placed next to each other among the sub-pixels which are intentionally made to vary in brightness.

According to this embodiment, the sub-pixels which are intentionally made to vary in brightness, i.e., the sub-pixels which have different root-mean-square voltages applied to their liquid crystal layers intentionally are indicated by the symbol “H” or “L” in FIG. 17.

In FIG. 17, if sub-pixels are organized into groups of four consisting of two sub-pixels in the row direction and two sub-pixels in the column direction (e.g., SPa (1, 1), SPb (1, 1), SPa (1, 2), and SPb (1, 2)), the entire matrix is made up of the sub-pixel groups in each of which H and L are arranged from left to right in the upper row and L and H are arranged in the lower row. Thus, in FIG. 17, the symbols “H” and “L” are arranged in a checkered pattern at the sub-pixel level, satisfying the fourth condition.

Looking at the matrix, at the pixel level, the correspondence between the order of brightness of the sub-pixels in each pixel and position of the sub-pixels arranged in the column direction changes in the row direction periodically (every pixel) in the case of a pixel in an arbitrary row, but it is constant in the case of a pixel in an arbitrary column. Thus, in a pixel P (p, q) in an arbitrary row, the brightest sub-pixel (sub-pixel indicated by “H,” in this example) is SPa (p, q) when q is an odd number, and SPb (p, q) when q is an even number. Of course, conversely, the brightest sub-pixel may be SPb (p, q) when q is an odd number, and SPa (p, q) when q is an even number. On the other hand, in a pixel P (p, q) in an arbitrary column, the brightest sub-pixel is always SPa (p, q) or SPb (p, q) in the same column regardless of whether p is an odd number or even number. The alternative of SPa (p, q) or SPb (p, q) here means that the brightest sub-pixel is SPa (p, q) in an odd-numbered column regardless of whether p is an odd number or even number while it is SPb (p, q) in an even-numbered column regardless of whether p is an odd number or even number.

As described above with reference to FIGS. 17 and 18, the liquid crystal display according to this embodiment satisfies the four conditions described above, and thus it can implement high quality display.

Next, a liquid crystal display according to another embodiment using a different drive method for pixels and sub-pixels will be described with reference to FIGS. 19 and 20. FIG. 19 and FIG. 20 correspond to FIG. 17 and FIG. 18.

As shown in FIG. 20, in the liquid crystal display according to this embodiment, display signal voltage and storage capacitor counter voltage oscillate every 2 H. Thus the period of oscillation is 4 H (four horizontal write times). The oscillations of the signal voltages of odd-numbered signal lines S-O (S-C1, S-C3, S-C5, . . . ) and even-numbered signal lines S-E (S-C2, S-C4, S-C6, . . . ) are 180 degrees (2 H in terms of time) out of phase with each other. The oscillations of the voltages of the storage capacitor lines CS-A and CS-B are also 180 degrees (2H in terms of time) out of phase with each other. Furthermore, the oscillation of the voltage of the signal lines lags the oscillation of the voltage of the storage capacitor line CS-A by a phase difference of 45 degrees (⅛ period, i.e., H/2). Incidentally, the phase difference of 45 degrees is used to prevent the VgH-to-VgL voltage change of the scan line and the voltage change of the storage capacitor line from overlapping, and the value used here is not restrictive and another value may be used as required.

With the liquid crystal display according to this embodiment, again every pixel consists of two sub-pixels which are intentionally made to vary in brightness and are indicated by the symbol “H” or “L.” Furthermore, as shown in FIG. 19, the sub-pixels indicated by the symbol “H” or “L” are arranged in a checkered pattern, which means that the fourth condition is satisfied, as with the above embodiment. Regarding the first condition, it can be satisfied using the same inversion method as the one used by the embodiment described with reference to FIGS. 17 and 18.

However, the embodiment shown in FIGS. 19 and 20 cannot satisfy the second condition described above.

Now, we will look at the brighter sub-pixels Pa (1, 1), Pa (2, 1), Pa (3, 1), and Pa (4, 1) of the pixels P (1, 1), P (2, 1), P (3, 1), and P (4, 1) shown in the first to fourth rows of the first column in FIG. 19. When Pa (1, 1) is being charged, i.e., when G-GL1 is selected, the polarity symbol of the corresponding signal line is “+.”. When Pa (3, 1) is being charged, i.e., when G-GL3 is selected, the polarity symbol of the corresponding signal line is “−”. Also, when Pa (1, 1) is being charged, i.e., when G-GL1 is selected, the voltage waveform of the corresponding storage capacitor line CS-A decreases stepwise beginning at approximately the center of the selection period. When Pa (3, 1) is being charged, i.e., when G-GL3 is selected, the voltage waveform of the corresponding storage capacitor line CS-A increases stepwise beginning at approximately the center of the selection period. Thus, by controlling the phases of the signal voltage waveforms of both storage capacitor line CS-B and scan line precisely, it is possible to make the storage capacitor counter electrode have the same DC level both when Pa (1, 1) is being charged and when Pa (3, 1) is being charged. By setting the DC level to the average between the voltage (equal to the voltage of the sub-pixel electrode) of the storage capacitor counter electrode when Pa (1, 1) is being charged and the voltage (equal to the voltage of the sub-pixel electrode) of the storage capacitor counter electrode when Pa (3, 1) is being charged, it is possible to equate the quantities of electric charge stored in the storage capacitors of Pa (1, 1) and Pa (3, 1). Next, looking at Pa (2, 1), during the corresponding period, i.e., when G-L2 is selected, the polarity symbol of the corresponding signal line is “−” (the same as with Pa (3, 1) described above) and the voltage of the corresponding storage capacitor line takes a fixed value (not an oscillating waveform such as those above) regardless of time. Thus, by equating the voltage value of the storage capacitor line corresponding to Pa (2, 1) and the DC level described above in relation to Pa (1, 1) and Pa (3, 1), it is possible to equate the quantities of electric charge stored in the storage capacitors of Pa (1, 1), Pa (3, 1), and Pa (2, 1). However, it is impossible to equate the quantities of electric charge stored in the storage capacitor Pa (4, 1) with those in the storage capacitors of Pa (1, 1), Pa (2, 1), and Pa (3, 1) for the following reason. The polarity symbol of the signal line for Pa (4, 1) is the same as that for Pa (1, 1) and the voltage of the corresponding storage capacitor line takes a fixed value (not an oscillating waveform such as those above) regardless of time. Thus, it is necessary to equate the voltage value (the fixed value described above) of the storage capacitor line for Pa (4, 1) with the DC level described above in relation to Pa (1, 1) and Pa (3, 1), as in the case of Pa (2, 1), i.e., to equate the voltage value (the fixed value described above) of the storage capacitor line for Pa (4, 1) with that for Pa (2, 1). However, this is not possible because, as can be seen from FIGS. 19 and 20, both the storage capacitor lines for Pa (2, 1) and Pa (4, 1) are CS-B, which has a rectangular oscillating waveform, and the maximum value of the oscillating waveform is selected during the selection period of Pa (2, 1) while the minimum value of the oscillating waveform is selected during the selection period of Pa (4, 1), making the two voltages necessarily different.

Also, in terms of the third condition to arrange the sub-pixels with the same polarity so as not to adjoin each other as much as possible, this embodiment is inferior to the embodiment described with reference to FIGS. 17 and 18.

Referring to FIG. 19, we will look at the polarity inversion of the sub-pixels which have a large voltage applied to their liquid crystal layers intentionally, i.e., the sub-pixels indicated by the symbol H, out of the sub-pixels composing pixels. In FIG. 19, there is no polarity inversion in the row direction as shown, for example, by +H, +H, +H for the sub-pixels SPa in the first row (as with FIG. 17), but the polarity is inverted every four pixels in the column direction as shown, for example, by (+H, −H, −H, +H), (+H, −H, −H, +H) in the first column. In the embodiment described with reference to FIGS. 17 and 18, polarity inversion occurs every two pixels, 1/2 the polarity inversion cycle of this embodiment. In other words, in the embodiment described with reference to FIGS. 17 and 18, polarity inversion occurs twice as frequently as in this embodiment described with reference to FIGS. 19 and 20. In this respect, this embodiment (described with reference to FIGS. 19 and 20) is inferior to the embodiment described with reference to FIGS. 17 and 18.

Display quality was actually compared between the drive method of the previous embodiment which implements the pixel arrangement shown in FIG. 17 and the drive method of this embodiment and differences were observed in the display quality. Specifically, when, for example, a 64/255-grayscale display which produces relatively large brightness differences among sub-pixels which were intentionally made to vary in brightness was observed with the line of sight fixed, no significant difference was observed between the two drive methods. However, when the display was observed by moving the line of sight, horizontal streaks were observed in the case of the drive method of this embodiment (FIG. 19) whereas the drive method of the previous embodiment (FIG. 17) was free of such a problem. It is believed that the difference was caused by the difference in the polarity inversion cycle described above. Since the brighter of the two sub-pixels contained in each pixel is more conspicuous, it is preferable to minimize the polarity inversion cycle of the brighter sub-pixel. Each pixel is divided into two sub-pixels in the example described above, but if it is divided into three or more sub-pixels, it is preferable to arrange them in such a way as to minimize the polarity inversion cycle of the brightest sub-pixel. Needless to say, it is most preferable that all the other sub-pixels have the same polarity inversion cycle as the brightest sub-pixel.

Next, with reference to FIGS. 21A and 21B, description will be given of an embodiment which makes the above-described horizontal streaks more inconspicuous using a shorter polarity inversion cycle than the embodiment shown in FIG. 17 even if the display is observed by moving the line of sight.

According to the embodiment shown in FIG. 17, although the “+” and “−” signs of the brighter sub-pixels (indicated by the symbol “H”) composing pixels are inverted in the column direction as shown by (+, −), (+, −), (+, −), (+, −), they are not inverted in the row direction as shown by +, +, +, +, +, +or −, −, −, −, −, −. In contrast, according to the embodiment shown in FIG. 21, the “+” and “−” signs of the brighter sub-pixels are inverted not only in the column direction as shown by (+, −), (+, −), (+, −), (+, −), but also in the row direction as shown by (+, −), (+, −). Thus, this embodiment shown in FIG. 20 uses a shorter polarity inversion cycle than the embodiment shown in FIG. 17. In this respect, this embodiment shown in FIG. 20 is more preferable than the embodiment shown in FIG. 17.

Even in the embodiment shown in FIG. 21, out of the sub-pixels composing the pixels, the brighter sub-pixels indicated by the symbol “H” are arranged in a checkered pattern, satisfying the fourth condition.

The pixel arrangement shown in FIG. 21A can be implemented, for example, as follows.

As shown schematically in FIG. 21B, the storage capacitor counter electrodes for the sub-pixels in each row are connected alternately to the storage capacitor line CS-A or CS-B every two columns. This structural change can be seen clearly by comparing FIG. 21 for this embodiment and FIG. 17 or 18 for the embodiment described earlier. Specifically, this can be seen by looking at the storage capacitor lines selected at the sub-pixel in the row direction. For example, in the row of sub-pixels SPa (1, 1) to SPa (1, 6), out of the storage capacitor counter electrodes indicated by the symbol “A” or “B,” “A” is selected for SPa (1, 1), “B” for SPa (1, 2) and SPa (1, 2), “A” for SPa (1, 4) and SPa (1, 5), and “B” for SPa (1, 6) in FIG. 21 (this embodiment) whereas “A” is selected for all the sub-pixels SPa (1, 1) to SPa (1, 6) in FIG. 17 or 18 (the embodiment described earlier).

The voltage waveforms (a)-(j) shown in FIG. 18 can be used as the voltage waveforms supplied to the lines, including the storage capacitor lines CS-A and CS-B, according to this embodiment shown in FIG. 21. However, since display signal voltages are inverted every two columns, the display signal voltages having the waveform (a) shown in FIG. 18 are supplied to S-C1, S-C2, S-C5, S-C6, . . . shown in FIG. 21A, while the display signal voltages having the waveform (b) shown in FIG. 20 are supplied to S-C3, S-C4, S-C7 (not shown), S-C8 (not shown), . . . in FIG. 21A.

Although in the embodiments described above, the storage capacitor counter voltages supplied to the storage capacitor lines are oscillating voltages which have rectangular waveforms with a duty ratio of 1:1, the present invention can also use rectangular waves with a duty ratio of other than 1:1. Besides other waveforms such as sine waves or triangular waves may also be used. In that case, when TFTs connected to a plurality of sub-pixels are turned off, the changes which occur in the voltages supplied to the storage capacitor counter electrodes of sub-pixels can be varied depending on the sub-pixels. However, the use of rectangular waves makes it easy to equate quantities of electric charge stored in different sub-pixels (liquid crystal capacitors and storage capacitors) as well as root-mean-square voltages applied to different sub-pixels.

Also, although in the embodiments described above with reference to FIGS. 17 and 21, the oscillation period of the oscillating voltages supplied to the storage capacitor lines (waveforms (c) and (d)) are 1 H as shown in FIG. 18, it may be a fraction of 1 H, such as 1/1 H, ½ H, ⅓ H, ¼ H, etc., obtained by dividing 1 H by a natural number. However, as the oscillation period of the oscillating voltages becomes shorter, it becomes difficult to build drive circuits or power consumption of the drive circuits increases.

As described above, the first aspect of the present invention can reduce the viewing angle dependence of γ characteristics in a normally black liquid crystal display. In particular, it can achieve extremely high display quality by improving γ characteristics of liquid crystal displays with a wide viewing angle such as MVA or ASV liquid crystal displays.

The second aspect of the present invention can reduce flickering on a liquid crystal display driven by alternating voltage. By combining the first and second aspects of the present invention it is possible to provide a normally black liquid crystal display with reduced flickering, improved viewing angle characteristics, and high quality display.

Claims

1. A liquid crystal display used in normally black mode, comprising a plurality of pixels each of which has a liquid crystal layer and a plurality of electrodes for applying voltage to the liquid crystal layer, wherein:

each of the plurality of pixels comprises a first sub-pixel and a second sub-pixel which can apply mutually different voltages to their respective liquid crystal layers; and

when each of the plurality of pixels displays a grayscale gk which satisfies 0≤gk≤n, where gk and n are integers not less than zero and a larger value of gk corresponds to higher brightness, n represents the highest grayscale, and at least the range of 0<gk≤n−1 includes gk which satisfies relationships ΔV12 (gk)>0 volts and ΔV12 (gk)≥ΔV12 (gk+1) if it is assumed that ΔV12 (gk)=V1 (gk)−V2 (gk), where V1 (gk) and V2 (gk) are root-mean-square voltages applied to the liquid crystal layers of the first sub-pixel and the second sub-pixel, respectively.

2. The liquid crystal display according to claim 1, wherein:

each of the plurality of pixels comprises a third sub-pixel which can apply a voltage different from those of the first sub-pixel and the second sub-pixel to its liquid crystal layer; and

when each of the plurality of pixels displays a grayscale gk, a relationship 0 volts<ΔV13 (gk)<ΔV12 (gk) is satisfied if the root-mean-square voltage applied to the liquid crystal layer of the third sub-pixel is V3 (gk) and ΔV13 (gk)=V1 (gk)−V3 (gk).

3. The liquid crystal display according to claim 1, wherein a relationship ΔV12 (gk)≥ΔV12 (gk+1) is satisfied at least in a range 0<gk≤n−1.

4. The liquid crystal display according to claim 2, wherein a relationship ΔV13 (gk)≥ΔV13 (gk+1) is satisfied at least in a range 0<gk≤n−1.

5. The liquid crystal display according to claim 1, wherein:

the first sub-pixel and the second sub-pixel each comprise:

a liquid crystal capacitor formed by a counter electrode and a sub-pixel electrode opposing the counter electrode via the liquid crystal layer, and

a storage capacitor formed by a storage capacitor electrode connected electrically to the sub-pixel electrode, an insulating layer, and a storage capacitor counter electrode opposing the storage capacitor electrode via the insulating layer; and

the counter electrode is a single electrode shared by the first sub-pixel and the second sub-pixel, and the storage capacitor counter electrodes of the first sub-pixel and the second sub-pixel are electrically independent of each other.

6. The liquid crystal display according to claim 5, comprising two switching elements provided for the first sub-pixel and the second sub-pixel, respectively,

wherein the two switching elements are turned on and off by scan line signal voltages supplied to a common scan line; display signal voltages are applied to the respective sub-pixel electrodes and storage capacitor electrodes of the first sub-pixel and the second sub-pixel from a common signal line when the two switching elements are on; voltages of the respective storage capacitor counter electrodes of the first sub-pixel and the second sub-pixel change after the two switching elements are turned off; and the amounts of change defined by the direction and magnitude of the change differ between the first sub-pixel and the second sub-pixel.

7. The liquid crystal display according to claim 6, wherein the liquid crystal layer is a vertically aligned liquid crystal layer and contains nematic liquid crystal material with negative dielectric anisotropy.

8. The liquid crystal display according to claim 7, wherein the liquid crystal layers of the first sub-pixel and the second sub-pixel each contain four domains which are approximately 90 degrees apart in azimuth direction in which their liquid crystal molecules incline when a voltage is applied.

9. The liquid crystal display according to claim 8, wherein:

the first sub-pixel and the second sub-pixel are placed on opposite sides of the common signal line;

the first sub-pixel and the second sub-pixel each have, on the counter electrode side, a plurality of ribs protruding towards the liquid crystal layer and the plurality of ribs include a first rib extending in a first direction and a second rib extending in a second direction approximately orthogonal to the first direction; and

the first rib and the second rib are placed symmetrically with respect to a center line parallel to the common scan line in each of the first sub-pixel and the second sub-pixel and the arrangement of the first rib and the second rib in one of the first and second sub-pixels is symmetrical with respect to the arrangement of the first rib and the second rib in the other sub-pixel.

10. The liquid crystal display according to claim 9, wherein the areas of the first sub-pixel and the second sub-pixel are practically equal and the center line parallel to the common scan line in each of the first sub-pixel and the second sub-pixel is placed at an interval equal to approximately one half of an array pitch of the scan lines in both the first sub-pixel and the second sub-pixel.

11. The liquid crystal display according to claim 1, wherein the area of the first sub-pixel is equal to or smaller than the area of the second sub-pixel.

12. A liquid crystal display, comprising a plurality of pixels each of which has a liquid crystal layer and a plurality of electrodes for applying an electric field across the liquid crystal layer, wherein:

the plurality of pixels are arranged in a matrix (rp, cq) with a plurality of rows (1 to rp) and plurality of columns (1 to cq) and each pixel is expressed as P (p, q), where 1≤p≤rp and 1≤q≤cq;

each of the plurality of pixels has at least two sub-pixels spa (p, q), SPb (p, q), arranged in the column direction;

the at least two sub-pixels differ from each other in brightness when displaying an intermediate grayscale;

the at least two sub-pixels include two sub-pixels spa (p, q) and SPb (p, q);

spa (p, q) and SPb (p, q) each comprise:

a liquid crystal capacitor formed by a counter electrode and a sub-pixel electrode opposing the counter electrode via the liquid crystal layer, and

a storage capacitor connected electrically to the liquid crystal capacitor and having a storage capacitor counter electrode;

the counter electrode is a single electrode shared by spa (p, q) and SPb (p, q), and the storage capacitor counter electrodes of spa (p, q) and SPb (p, q) are electrically independent of each other;

the liquid crystal display comprises two switching elements provided for spa (p, q) and SPb (p, q), respectively;

the two switching elements are turned on and off by a common scan line signal voltage; a common display signal voltage is applied to the respective sub-pixel electrodes of spa (p, q) and SPb (p, q) when the two switching elements are on; voltages of the respective storage capacitor counter electrodes of spa (p, q) and SPb (p, q) change after the two switching elements are turned off; and

the sub-pixels are arranged so that, in each vertical scanning period, any two sub-pixels which pertain to a same pixel or different pixels and which are adjacent to each other in the column direction differ from each other in terms of an exclusive disjunction of: a) the direction of the electric field applied across the liquid crystal layer; and b) the direction of the change of the voltage of the storage capacitor counter electrode, where a logical value of a) the direction of the electric field applied across the liquid crystal layer is true (T) if the direction is toward the counter electrode and false (F) if the direction is toward the sub-pixel electrode, and a logical value of b) the direction of the change of the voltage of the storage capacitor counter electrode is true (T) if the change is an increase and false (F) if the change is a decrease.

13. The liquid crystal display according to claim 12, wherein the position of the brightest of the at least two sub-pixels arranged in the column direction changes periodically in the row direction in the case of a pixel in an arbitrary row, but it is constant in the case of a pixel in an arbitrary column.

14. The liquid crystal display according to claim 13, wherein in each of the plurality of pixels, correspondence between the order of brightness of the at least two sub-pixels and position of the at least two sub-pixels arranged in the column direction changes in the row direction periodically in the case of a pixel in an arbitrary row, but it is constant in the case of a pixel in an arbitrary column.

15. The liquid crystal display according to claim 13, wherein when displaying an intermediate grayscale, the at least two sub-pixels in each of the plurality of pixels are placed such that sub-pixels equal in the order of brightness will not adjoin each other.

16. The liquid crystal display according to claim 12, wherein when displaying an intermediate grayscale:

the brightest sub-pixel in a pixel P (p, q) in an arbitrary row is spa (p, q) in the case where q is an odd number and SPb (p, q) in the case where q is an even number, or SPb (p, q) in the case where q is an odd number and spa (p, q) in the case where q is an even number; and

the brightest sub-pixel in a pixel P (p, q) in an arbitrary column is either spa (p, q) or SPb (p, q) regardless of whether p is an odd number.

17. The liquid crystal display according to claim 16, wherein when displaying an intermediate grayscale, the at least two sub-pixels in each of the plurality of pixels are placed such that the brightest sub-pixels form a checkered pattern.

18. The liquid crystal display according to claim 12, wherein:

direction of the electric field applied across the liquid crystal layers in the plurality of pixels is reversed every vertical scanning period; and

when displaying an intermediate grayscale, the direction of the electric field is reversed periodically in the row direction in the case of pixels in an arbitrary row.

19. The liquid crystal display according to claim 18, wherein the direction of the electric field is reversed every pixel in the row direction in the case of pixels in an arbitrary row.

20. The liquid crystal display according to claim 18, wherein the direction of the electric field is reversed every two pixels in the row direction in the case of pixels in an arbitrary row.

21. The liquid crystal display according to claim 12, wherein:

the liquid crystal display operates in normally black mode, and

when each of the plurality of pixels displays a grayscale gk which satisfies 0≤gk≤n, where gk and n are integers not less than zero and a larger value of gk corresponds to higher brightness, relationships ΔV12 (gk)>0 volts and ΔV12 (gk)≥ΔV12 (gk+1) are satisfied if it is assumed that ΔV12 (gk)=V1 (gk)−V2 (gk), where V1 (gk) and V2 (gk) are root-mean-square voltages applied to the liquid crystal layers of the first sub-pixel and the second sub-pixel, respectively.

22. The liquid crystal display according to claim 21, wherein a relationship ΔV12 (gk)≥ΔV12 (gk+1) is satisfied.

23. The liquid crystal display according to claim 12, wherein the changes in the voltages of the storage capacitor counter electrodes of spa (p, q) and SPb (p, q) are equal in amount and opposite in direction.

24. The liquid crystal display according to claim 12, wherein the voltages of the storage capacitor counter electrodes of spa (p, q) and SPb (p, q) are oscillating voltages 180 degrees out of phase with each other.

25. The liquid crystal display according to claim 24, wherein the oscillating voltages of the storage capacitor counter electrodes of spa (p, q) and SPb (p, q) each have a period approximately equal to one horizontal scanning period.

26. The liquid crystal display according to claim 24, wherein the oscillating voltages of the storage capacitor counter electrodes of spa (p, q) and SPb (p, q) each have a period shorter than one horizontal scanning period.

27. The liquid crystal display according to claim 24, wherein the oscillating voltages of the storage capacitor counter electrodes of spa (p, q) and SPb (p, q) are approximately equal within any horizontal scanning period if averaged over the period.

28. The liquid crystal display according to claim 26, wherein the period of the oscillation is one-half of one horizontal scanning period.

29. The liquid crystal display according to claim 24, wherein the oscillating voltages are rectangular waves with a duty ratio of 1:1.

30. The liquid crystal display according to claim 12, wherein spa (p, q) and SPb (p, q) have different areas, of which the smaller area belongs to spa (p, q) or SPb (p, q) whichever has a larger root-mean-square voltage applied to its liquid crystal layer.

31. The liquid crystal display according to claim 12, wherein the area of spa (p, q) and area of SPb (p, q) are practically equal.

32. The liquid crystal display according to claim 12, wherein the storage capacitor is formed by the storage capacitor counter electrode, an insulating layer, and a storage capacitor electrode opposing the storage capacitor counter electrode via the insulating layer and connected electrically to the sub-pixel electrode.

33. A liquid crystal display, comprising a plurality of pixels each of which has a liquid crystal layer and a plurality of electrodes for applying an electric field across the liquid crystal layer, wherein:

the plurality of pixels are arranged in a matrix (rp, cq) with a plurality of rows (1 to rp) and plurality of columns (1 to cq) and each pixel is expressed as P (p, q), where 1≤p≤rp and 1≤q≤cq;

each of the plurality of pixels has at least two sub-pixels spa (p, q), SPb (p, q), arranged in the column direction;

the at least two sub-pixels differ from each other in brightness when displaying an intermediate grayscale;

the at least two sub-pixels include two sub-pixels spa (p, q) and SPb (p, q);

spa (p, q) and SPb (p, q) each comprise:

a liquid crystal capacitor formed by a counter electrode and a sub-pixel electrode opposing the counter electrode via the liquid crystal layer, and

a storage capacitor connected electrically to the liquid crystal capacitor and having a storage capacitor counter electrode;

the counter electrode is a single electrode shared by spa (p, q) and SPb (p, q), and the storage capacitor counter electrodes of spa (p, q) and SPb (p, q) are electrically independent of each other;

the liquid crystal display comprises two switching elements provided for spa (p, q) and SPb (p, q), respectively;

the two switching elements are turned on and off by a common scan line signal voltage; a common display signal voltage is applied to the respective sub-pixel electrodes of spa (p, q) and SPb (p, q) when the two switching elements are on; voltages of the respective storage capacitor counter electrodes of spa (p, q) and SPb (p, q) change after the two switching elements are turned off; and

in each vertical scanning period, any two sub-pixels which pertain to a same pixel or different pixels and which are adjacent to each other in the column direction are opposite in the direction of the electric field applied across the liquid crystal layer and equal in the direction of the change of the voltage of the storage capacitor counter electrode, or, equal in the direction of the electric field applied across the liquid crystal layer and opposite in the direction of the change of the voltage of the storage capacitor counter electrode.