Power converter with demand pulse isolation

Abstract

The present invention provides a switched-mode power converter with regulation demand pulses sent across a galvanic isolation barrier.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

though through a switch 502c, during the pulse of generator 503c, under the command of gate 506c, appear as voltage pulses across the primary winding of transformer 100c. These pulses are detected and processed to logic levels by a demand pulse detector 215c and passed through an OR gate 214c to a pulse generator that turns ON switch 200c to energize transformer 100c to begin an energy-bearing cycle. When switch 200c turns OFF, the subsequent flyback pulse charges capacitor 301c through diode 300c, as previously described. Since capacitor 501c is charged from the converter forward pulse, its voltage persists even in the presence of a short-circuit load, allowing the converter to recover once the short-circuit is removed.

Had no energy-bearing cycle ever occurred, there might be insufficient, or no, charge in capacitor 501c to be used to initiate energy-bearing cycles as described above. Therefore, a slow pulse oscillator 213c, preferably about 1 KHz, is also connected to gate 214c, through which it initiates energy-bearing cycles by triggering a pulse generator 216c, thus turning on switch 200c. These infrequent pulses cause energy-bearing cycles that are sufficient to charge capacitor 501c, which also may supply power to generator 503c, gate 506c, oscillator 505c, reference 400c, and comparison circuit 401c. Of course, slow oscillator 213c must somehow be powered along with gate 214c and pulse generator 216c. A bias supply (not shown but well known in the art) powered from terminals 11c and 12c, may be used to power these components of the circuit.

FIG. 4 shows a schematic diagram of a power converter 10d, comprising a separate transformer 110d to transmit demand pulses across a galvanic isolation barrier. As in FIG. 1 above, converter 10d is powered, through terminals 11d and 12d, from an external source 5d, and power output from converter 10d flows through terminals 13d and 14d.

Input voltage from terminals 11d and 12d powers a slow oscillator 213d, preferably of less than 1 KHz frequency, and a start-up regulator 232d which, through a supply node +5d, initially powers, with a voltage preferably about 4V, logic and drive circuitry described below. Each label “+5d” in FIG. 4 refers to a supply node that is initially about 4 volts when the input-side logic is starting to function and about 5 volts when in regulation. A capacitor 221d and a resistor 222d differentiate transitions of a slow pulse oscillator 213d to provide pulses of about 200 nS duration. These pulses pass though through a NAND gate 223d to clock a D-type flip-flop 220d through a node CKa.

Responsive to its clock pulse, flip-flop 220d turns ON a switch 200d, preferably a MOSFET, ON Semiconductor type NDD02N60, which is in circuit with a primary winding 101d of a transformer 100d, with a sense resistor 209d, and with terminals 11d and 12d. Current then flows in this circuit, and the voltage of source 5d is impressed upon primary winding 101d. According to the turns-ratio between primary winding 101d and a secondary winding 104d of transformer 100d, a voltage appears across winding 104d. This latter voltage charges a capacitor 416d through a diode 417d.

As current in resistor 209d rises, a voltage is applied to an input of a comparator 217d, which voltage is compared with a reference 216d, also connected to an input of comparator 217d. When current in resistor 209d exceeds a value set by reference 216d, comparator 217d issues a reset signal which propagates through NAND gates 218d and 219d to a node /Ra where the reset signal resets flip-flop 220d, turning OFF switch 200d.

When switch 200d is turned ON, unavoidable gate-to-source capacitance of MOSFET switch 200d causes a current spike in resistor 209d. To prevent comparator 217d from prematurely resetting flip-flop 220d responsive to this spike, the rise of node Qa charges a capacitor 231d through a resistor 230d to reach the threshold of a gate 219d in about 75 nS, prior to which the low voltage of capacitor 231d inhibits gate 219d from resetting flip-flop 220d.

Prior to its rise, node Qa has been low, and a complementary node/Qa has been high. When node Qa rises, node/Qa falls, discharging a capacitor 229d through a resistor 228d to the threshold of NAND gate 218d in about 2 uS, and though through NAND gate 219d resetting flip-flop 220d, thus limiting the maximum ON time of switch 200d, should comparator 217d fail to reset flip-flop 220d.

In addition to limiting ON times of switch 200d, it is desirable to limit maximum frequency of these ON times. To this end, the voltage across a capacitor 226d is charged to a logic high through a resistor 225d and applied to a node Da, the D-input of flip-flop 220d. When node/Qa falls, capacitor 226d is discharged through a diode 227d, slowly to be recharged through resistor 225d. Until the capacitor 226d voltage is recharged to the D-input threshold voltage, flip-flop 220d is inhibited from turning ON switch 200d.

When switch 200d is turned OFF, the energy in the magnetic field of transformer 100d generates flyback voltage across its windings. Flyback voltage of winding 104d is rectified by a diode 300d and begins to charge a filter capacitor 301d to begin to supply output voltage to terminals 13d and 14d. This flyback voltage also raises the voltage on capacitor 416d, causing diode 417d to turn OFF and a diode 418d to turn ON, charging a capacitor 419d. Voltage across capacitor 419d supplies an auxiliary regulator 420d, which in turn powers a fast oscillator 505d, preferably of about 60 KHz frequency. Regulator 420d also powers logic and drive circuitry on the winding 104d side of the power converter.

The ON pulses of switch 200d responsive to oscillator 213d are sufficiently frequent to start the converter of this embodiment, but insufficiently frequent to drive it to full output. To initiate more frequent pulses, an oscillator 505d drives a capacitor 507d and a resistor 508d to supply differentiated pulses of about 100 nS width to a NAND gate 509d, which in turn drives a primary winding 111d of demand pulse transformer 110d, thus producing demand pulses across a secondary winding 112d thereof. These winding 112d pulses are conveyed through a NAND gate 223d to clock flip-flop 220d at up to the frequency of oscillator 505d.

If all of the pulses of oscillator 505d were allowed to clock flip-flop 220d, under some conditions, the converter of this embodiment would produce excess output. To regulate this output, a flip-flop 412d is used to gate the pulses passed by NAND gate 509d. At a node CKc, oscillator 505d clocks a flip-flop 412d, which generates a logic high at a node Qc only when a logic high is present at a node Dc at the rising edge of its clock. Thus, pulses driving transformer 110d are permitted responsive to a logic high only at node Dc.

It would be wasteful of power to drive winding 111d for the full duration of the differentiated pulse at resistor 508d. Therefore, when switch 200d turns ON causing a negative transition at the dotted end of winding 101d, a corresponding negative transition appears at the dotted end of winding 104d. This transition is coupled through a small capacitor 414d, preferably about 10 pF, through a current-limiting resistor 415d to a node/Rc, the reset input of flip-flop 412d, which is normally held high by a resistor 413d. Thus, once the turning ON of switch 200d has propagated through transformer 100d, flip-flop 412d is reset, usually in less than 20 nS.

Node Dc is usually held at a logic high by a resistor 411d, thus enabling pulses gated by flip-flop 412d. However, between terminals 13d and 14d is disposed a voltage divider comprising resistors 408d and 409d, the voltage at the junction of which is applied to an input of a comparator 401d. Should the voltage at that junction exceed the voltage of a reference 400d, also applied to a comparator 401d input, an output of comparator 401d will drop to a logic low, drawing current through a diode 410d, thus presenting a logic low at node Dc and, after clocking, responsively at node Qc, inhibiting pulses through gate 509d that would otherwise turn ON switch 200d. Thus, the voltage between terminals 13d and 14d is regulated responsive to the voltage of reference 400d.

Since the voltage between terminals 11d and 12d may be high, perhaps 375V, and the desired regulated voltage at node +5d is typically 5V, it might be inefficient to obtain the power to supply the logic and drive circuitry associated with winding 101d from regulator 232d. Therefore, transformer 100d is fitted with an auxiliary winding 102d, which is connected in circuit with an inductor 235d, a diode 241d, and a switch 233d, preferably a MOSFET. While switch 200d is ON, current flows in this circuit. When switch 200d turns OFF, diode 241d also turns OFF and energy in inductor 235d generates a positive flyback voltage, causing current through a diode 236d to charge a filter capacitor 237d, raising the voltage of node +5d. As node +5d approaches 5V, regulator 232d ceases to supply energy to node +5d, but continues to power a voltage reference 242d, which drives an input of a comparator 240d. Should the voltage of node +5d exceed 5V, the voltage at the junction of resistors 238d and 239d, connected to another input of comparator 240d, will exceed that of reference 242d, causing the output of comparator 240d at node Db to drop to a logic low.

A flip-flop 234d drives node Qb to turn ON switch 233d responsive to clock pulses on node Qa, and to a logic high being present at node Db. When node Db drops to a logic low, node Qb follows it upon the next clock, and switch 233d turns OFF. In this state, inductor 235d no longer receives energy and no longer charges capacitor 237d through diode 236d. Thus, node +5d is regulated to approximately 5V, and the energy supplying node +5d is provided efficiently through transformer 100d.

In one embodiment, the invention is a switched-mode power-converter comprising a power input port, a transformer comprising windings, a commutating switch connected in circuit with the input port and a winding of the transformer, a driver circuit for toggling the commutating switch, a power output port, a rectifier circuit for supplying power to the power output port, a reference voltage or current source, a comparison circuit for comparing the voltage or current at the power output port with the reference voltage or current, and a demand pulse source circuit coupled to the transformer for transmitting galvanically isolated trigger information through the transformer to the driver circuit responsive to the comparison circuit.

The converter may comprise as its driver circuit a blocking oscillator comprising the converter transformer. The converter may further comprise an input-side, master blocking oscillator for power conversion and an output-side, slave blocking oscillator for generating demand pulses. Both blocking oscillators may be mutually coupled through the converter power transformer or may drive separate transformers.

The converter may comprise inductive, capacitive, opto-coupled, or piezoelectric galvanic isolation circuitry to transmit demand pulses across the galvanic isolation barrier.

The converter may have one or more output rectifier circuits poled to rectify flyback pulses of its transformer.

The converter may comprise one or more auxiliary rectifier circuits which may be poled as forward converters.

The converter may be powered by a rectifier circuit to provide an AC/DC converter.

It should be understood that replicas of pulses generated and applied to one winding of the power transformer appear, suitably modified by turns-ratio, across all other windings of the power transformer.

Though blocking oscillators usually require tickler windings, single output embodiments of this invention may comprise a power transformer with as few as two, and in excess of five windings, with multiple output embodiments possibly comprising yet more windings.

Startup pulse generation circuitry resides on the powered side of the isolation barrier, though its pulses appear on both sides of the isolation barrier. This circuitry may comprise a blocking oscillator, another form of oscillator with drive circuitry to turn ON the commutating switch, or this circuitry may comprise an external source of pulses.

Demand pulse generator circuitry resides with the output port to be regulated, though its pulses appear on both sides of the isolation barrier. This circuitry may comprise a slave blocking oscillator, another form of oscillator with drive circuitry to turn ON the demand pulse generator switch, or may be externally applied.

Demand pulses may be generated to regulate the power converter to provide either a desired output voltage or a desired output current responsive to the voltage across or a current through an output port.

Between the commencement of start-up and the attainment of regulation, a pulse generator sources pulses to turn ON the commutating switch. This pulse generator may be the same generator that sources regulation pulses, or may be a separate pulse generator.

Each internal pulse generator is powered. The startup pulse generator is powered from the input port. The demand pulse generator is only indirectly powered from the input port by DC-DC power conversion through the power transformer and one or more rectifiers and filters powering the power output port with which the generator is associated.

Power for pulse generation circuitry may be rectified from either forward pulses, from flyback pulses, or both, appearing across one or more power transformer windings. Rectification of forward pulses helps to assure startup.

Windings, switches, and diodes may be poled to provide either polarity of input, and either polarity of output.

In each of the embodiments of FIGS. 1-4, galvanic isolation circuitry transfers (i) power from the input-port side to the output-port side of the power converter and (ii) demand pulses from the output-port side to the input-port side. In particular, in FIG. 1, the galvanic isolation circuitry consists of transformer 100a, which transfers (i) power from winding 101a to winding 104a and (ii) demand pulses from winding 104a to winding 102a. In FIG. 2, the galvanic isolation circuitry consists of transformer 100b, which transfers (i) power from winding 101b to winding 104b and (ii) demand pulses from winding 104b to winding 102b. In FIG. 3, the galvanic isolation circuitry consists of transformer 100c, which transfers (i) power from winding 101c to winding 104c and (ii) demand pulses from winding 104c to winding 101c. In FIG. 4, the galvanic isolation circuitry consists of (i) transformer 100d, which transfers power from winding 101d to winding 104d and (ii) transformer 110d, which transfers demand pulses from winding 111d to winding 112d. Winding 102d generates the bias supply for powering the +5d node.

In each of the embodiments of FIGS. 1-4, a demand pulse generator on the output-port side of the converter generates the demand pulses that are conveyed to the input-port side of the converter via the galvanic isolation circuitry. In FIGS. 1, 2, and 3, the demand pulse generator comprises elements 503a, 503b, and 503c, respectively. In FIG. 4, the demand pulse generator comprises NAND Gate 509d and flip-flop 412d.

In each of the embodiments of FIGS. 1-4, slow-pulse source circuitry generates pulses on the input side of the power converter. In FIGS. 1 and 2, the slow-pulse source circuitry is the corresponding input-side blocking oscillator. In FIGS. 3 and 4, the slow-pulse source circuitry is slow oscillator 213c and slow oscillator 213d, respectively. Note that, depending on the particular implementation, the slow-pulse source circuitry may be implemented internal to or external to the switched-mode power converter. Similarly, depending on the particular implementation, fast oscillator 505c and fast oscillator 505d of FIGS. 3 and 4, respectively, may be implemented internal to or external to the switched-mode power converter.

Embodiments of the invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes, including possible implementation as one or more integrated circuits (such as an ASIC or an FPGA), a multichip module, a single card, or a multicard circuit pack.

Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy or signals are allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements.

Also, for purposes of this disclosure, it is understood that all gates are powered from a fixed voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources.

Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here.

Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors.

The terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bipolar device when an embodiment of the invention is implemented using bi-polar transistor technology. p Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.

It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims.

The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.

It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the invention.

Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”

The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to nonstatutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.

Claims

1. Apparatus configured to provide switched-mode power conversion, the apparatus comprising:

an input port configured to receive input power;

a switch configured to commutate the input power;

galvanic isolation circuitry configured to provide galvanic isolation between the input port and an output port, wherein the galvanic isolation circuitry comprises a transformer comprising (i) a primary winding arranged in circuit with the input port and the switch and (ii) a secondary winding arranged in circuit with a rectifier and the output port, wherein the transformer is configured to transfer power from the input port to supply voltage or current to a load connected to the output port; and

a demand pulse generator galvanically connected to the secondary winding and configured to generate demand pulses applied via the galvanic isolation circuitry to the switch to adjust a frequency of the commutation of the input power to supply a desired amount of voltage or current to the load.

2. The apparatus of claim 1, further comprising:

a source configured to provide a reference signal; and

comparison circuitry configured to compare the output port voltage or current to the reference signal wherein frequency of the demand pulses is responsive to the comparison between the output port voltage or current and the reference signal.

3. The apparatus of claim 1, further comprising input-side blocking oscillator circuitry configured to drive the switch.

4. The apparatus of claim 3, wherein the demand pulse generator comprises output-side blocking oscillator circuitry configured to generate the demand pulses.

5. The apparatus of claim 1, further comprising:

a fast oscillator configured to initiate the generation of the demand pulses; and

logic circuitry configured to provide gating of the demand pulses applied to the galvanic isolation circuitry.

6. The apparatus of claim 1, wherein the galvanic isolation circuitry further comprises dedicated circuitry configured to convey the demand pulses across the galvanic isolation.

7. The apparatus of claim 1, wherein the demand pulses are conveyed from the demand pulse generator to the switch via the transformer.

8. The apparatus of claim 1, wherein:

the galvanic isolation circuitry divides the apparatus into (i) an input side corresponding to the primary winding of the transformer and (ii) an output side corresponding to the secondary winding of the transformer; and

the demand pulse generator is located on the output side of the apparatus.

9. The apparatus of claim 1, further comprising a capacitor and a diode both galvanically connected to the secondary winding, wherein:

the diode is different from the rectifier and is poled to charge the capacitor during forward pulses of the apparatus; and

the demand pulse generator is powered by energy stored in the capacitor to generate the demand pulses.

10. Apparatus configured to provide galvanically isolated switched-mode power conversion, the apparatus comprising:

an input port configured to receive input power;

a switch configured to commutate the input power;

a transformer comprising (i) a primary winding arranged in circuit with the input port and the switch and (ii) a secondary winding arranged in circuit with a rectifier and an output port, wherein the transformer is configured to supply power from the input port to a load connected to the output port; and

a first pulse source circuitry located on an input side of the apparatus and configured to generate pulses to control the switch to start the power conversion; and

a second pulse source circuitry located on an output side of the apparatus and configured to generate pulses to control the switch to continue the power conversion after being started by the first pulse source circuitry.

11. The apparatus of claim 10, wherein the frequency of pulses generated by the second pulse source circuitry is different from the frequency of pulses generated by the first pulse source circuitry.

12. The apparatus of claim 11, wherein the frequency of pulses generated by the second pulse source circuitry is greater than the frequency of pulses generated by the first pulse source circuitry.

13. The apparatus of claim 10, wherein the frequency of pulses generated by the first pulse source circuitry is about 1 KHz or smaller.

14. The apparatus of claim 13, wherein the frequency of pulses generated by the second pulse source circuitry is about 60 KHz or greater.

15. The apparatus of claim 10, further comprising a capacitor and a diode both galvanically connected to the secondary winding, wherein:

the diode is different from the rectifier and is poled to charge the capacitor during forward pulses of the apparatus; and

the second pulse source circuitry is powered by energy stored in the capacitor to generate the pulses.

16. In an isolated switched-mode power converter having an input port and an output port, a method of regulation comprising:

(a) comparing a voltage or current at the output port with a reference that is galvanically associated therewith;

(b) generating or gating demand pulses responsive to that comparison;

(c) applying the demand pulses to an output-port side of galvanic isolation circuitry;

(d) receiving replicas of the demand pulses from an input-port side of the galvanic isolation circuitry; and

(e) adjusting commutation frequency of the converter responsive to the demand pulses to cause the voltage or current at the output port to attain a desired value.

17. The method of claim 16, wherein step (b) comprises:

(b1) using a diode to charge a capacitor during forward pulses of the power converter, wherein the diode and the capacitor are galvanically connected within the output-port side of the galvanic isolation circuitry; and

(b2) generating or gating the demand pulses using energy stored in the capacitor.

18. Circuitry for controlling a flyback converter, the flyback converter comprising:

a converter primary side comprising an input port;

a converter secondary side comprising an output port, wherein the converter secondary side is galvanically isolated from the converter primary side; and

a power transformer configured to transfer input power received at the input port to provide output power at the output port, wherein:

the converter primary side further comprises a primary-side switch configured to selectively transfer the input power at the input port via the power transformer to the output power at the output port;

the circuitry comprises primary-side circuitry and secondary-side circuitry, wherein, when the circuitry is configured to control the flyback converter, (i) the primary-side circuitry is on the converter primary side and (ii) the secondary-side circuitry is on the converter secondary side;

the secondary-side circuitry (i) determines when to turn on the primary-side switch based on output port voltage or current at the output port and (ii) generates corresponding demand pulses;

the converter secondary side is configured to transmit the demand pulses to the converter primary side;

the primary-side circuitry is configured to turn on the primary-side switch in response to the demand pulses conveyed from the converter secondary side to the converter primary side, wherein the primary-side circuitry, and not the secondary-side circuitry, originates the determination of when to turn off the primary-side switch;

frequency with which the primary-side switch is turned on is adjusted by the demand pulses conveyed from the converter secondary side to the converter primary side to regulate the output port voltage or current; and

the converter secondary side further comprises:

a first capacitor; and

a first rectifier poled to charge the first capacitor during forward power converter pulses of the flyback converter, wherein the demand pulses are generated using energy stored in the first capacitor.

19. The circuitry of claim 18, wherein the converter secondary side further comprises a second capacitor, different from the first capacitor, and a second rectifier, different from the first rectifier, wherein flyback voltage of the power transformer is rectified by the second rectifier and charges the second capacitor to supply the output port voltage or current.

20. The circuitry of claim 18, wherein

the first rectifier is part of the secondary-side circuitry.

21. The circuitry of claim 18, wherein the flyback converter is configured to charge the first capacitor during flyback power converter pulses of the flyback converter.

22. The circuitry of claim 18, wherein the flyback converter is configured to charge the first capacitor during forward power converter pulses of the flyback converter even if the output port is short-circuited.

23. The circuitry of claim 18, wherein:

the secondary-side circuitry is configured to generate a demand pulse when a feedback signal based on the output port voltage or current is lower in magnitude than a magnitude of a reference signal such that the demand pulses regulate the output port by driving the feedback signal to match the reference signal;

the flyback converter regulates the output port to have the feedback signal match the reference signal;

frequency of the demand pulses generated by the secondary-side circuitry is greater than frequency of pulses initiated on the converter primary side that turn on the primary-side switch;

the secondary-side circuitry generates a demand pulse whenever a magnitude of the output port voltage or current is below a magnitude of the output port's regulation voltage or current;

the primary-side switch is turned on for a duration that is independent of duration of the demand pulse that caused the primary-side switch to be turned on;

the secondary-side circuitry is configured to adjust the frequency of turning on the primary-side switch to supply a desired amount of voltage or current to the output port in order to regulate the output port; and

the converter secondary side comprises:

a reference source configured to provide a reference signal; and

a secondary-side comparator configured to compare a feedback signal based on the output port voltage or current to the reference signal wherein the frequency of the demand pulses is responsive to a comparison between the feedback signal and the reference signal.

24. The circuitry of claim 23, wherein:

the primary-side circuitry comprises the primary-side switch;

the converter secondary side further comprises a second capacitor, different from the first capacitor, and a second rectifier, different from the first rectifier, wherein flyback voltage of the power transformer is rectified by the second rectifier and charges the second capacitor to supply the output port voltage or current;

the converter secondary side is configured to charge the first capacitor during flyback power converter pulses of the flyback converter;

the converter secondary side is configured to charge the first capacitor during forward power converter pulses of the flyback converter even if the output port is short-circuited;

the first rectifier is part of the secondary-side circuitry;

feedback from the converter secondary side to the converter primary side for regulating the output port voltage or current is provided solely by the demand pulses generated by the secondary-side circuitry;

the secondary-side comparator generates a comparator output;

the secondary-side circuitry comprises:

an oscillator configured to generate a stream of oscillator pulses independent of the comparator output; and

logic circuitry configured to (i) receive the comparator output and the stream of oscillator pulses and (ii) process, based on the comparator output, the stream of oscillator pulses to generate the demand pulses by selectively blocking certain oscillator pulses;

regulation of the output port is based solely on the demand pulses generated on the converter secondary side;

the flyback converter is configured such that the power transformer transfers unipolar input power received at the input port to provide the output power at the output port;

the converter primary side further comprises a primary-side magnetically coupled conductor;

the converter secondary side further comprises a secondary-side magnetically coupled conductor configured to be magnetically coupled to the primary-side magnetically coupled conductor to convey the demand pulses from the converter secondary side to the converter primary side;

the power transformer has a primary-side winding and a secondary-side winding;

the primary-side switch is connected in series with the primary-side winding of the power transformer;

the secondary-side winding of the power transformer is connected to the output port;

the primary-side magnetically coupled conductor is different from the primary-side winding of the power transformer;

the secondary-side magnetically coupled conductor is different from the secondary-side winding of the power transformer;

the primary-side circuitry comprises a primary-side oscillator configured to generate one or more primary-side pulses;

the primary-side switch is configured to be turned on based on (i) the one or more primary-side pulses generated by the primary-side oscillator and (ii) the demand pulses received from the converter secondary side;

the primary-side circuitry is configured to turn on the primary-side switch at power up, in order to transfer input power to the converter secondary side via the power transformer to power the secondary-side circuitry to generate the demand pulses; and

the converter secondary side does not generate pulses instructing the converter primary side to turn off the primary-side switch.

25. The circuitry of claim 18, wherein the secondary-side circuitry is configured to generate a demand pulse when a feedback signal based on the output port voltage or current is lower in magnitude than a magnitude of a reference signal such that the demand pulses regulate the output port by driving the feedback signal to match the reference signal.

26. The circuitry of claim 25, wherein the flyback converter regulates the output port to have the feedback signal match the reference signal.

27. The circuitry of claim 18, wherein feedback from the converter secondary side to the converter primary side for regulating the output port voltage or current is provided solely by the demand pulses generated by the secondary-side circuitry.

28. The circuitry of claim 18, wherein:

each demand pulse conveyed from the converter secondary side to the converter primary side has a leading edge; and

when a particular demand pulse results in a particular occurrence of the primary-side switch turning on, the particular occurrence of the primary-side switch turning on is in response to detecting the leading edge of the particular demand pulse independent of any other demand pulses conveyed from the converter secondary side to the converter primary side and independent of any other pulse edges appearing on the converter primary side.

29. The circuitry of claim 18, wherein the secondary-side circuitry comprises:

an oscillator that generates oscillator pulses, each oscillator pulse representing logic 1; and

logic circuitry that selectively blocks certain oscillator pulses in generating the demand pulses.

30. The circuitry of claim 29, wherein the logic circuitry is not an OR gate.

31. The circuitry of claim 29, wherein the logic circuitry selectively blocks certain oscillator pulses from becoming demand pulses that would otherwise result in the primary-side switch being turned on, while selectively allowing other oscillator pulses to become the demand pulses that do result in the primary-side switch being turned on.

32. The circuitry of claim 18, wherein frequency of the demand pulses generated by the secondary-side circuitry is greater than frequency of pulses initiated on the converter primary side that turn on the primary-side switch.

33. The circuitry of claim 18, wherein the secondary-side circuitry generates a demand pulse whenever a magnitude of the output port voltage or current is below a magnitude of the output port's regulation voltage or current.

34. The circuitry of claim 18, wherein the secondary-side circuitry processes, based on a comparator output, a secondary-side stream of pulses to generate the demand pulses.

35. The circuitry of claim 18, wherein the secondary-side circuitry comprises:

a comparator configured to generate a comparator output based on a comparison between (i) a feedback signal based on the output port voltage or current and (ii) a reference signal;

an oscillator configured to generate a stream of pulses independent of the comparator output; and

logic circuitry configured to (i) receive the comparator output and the stream of pulses and (ii) process, based on the comparator output, the stream of pulses to generate the demand pulses.

36. The circuitry of claim 18, wherein regulation of the output port is based solely on the demand pulses generated on the converter secondary side.

37. The circuitry of claim 18, wherein the determination of when to turn off the primary-side switch is always originated on the converter primary side and never on the converter secondary side.

38. The circuitry of claim 18, wherein the flyback converter is configured such that the power transformer transfers unipolar input power received at the input port to provide the output power at the output port.

39. The circuitry of claim 18, wherein, unless the primary-side switch is already on due to a pulse generated on the primary side, the primary-side switch is turned on once for each different demand pulse.

40. The circuitry of claim 18, wherein:

the converter primary side further comprises a primary-side magnetically coupled conductor; and

the converter secondary side further comprises a secondary-side magnetically coupled conductor configured to be magnetically coupled to the primary-side magnetically coupled conductor to convey the demand pulses from the converter secondary side to the converter primary side.

41. The circuitry of claim 40, wherein:

the power transformer has a primary-side winding and a secondary-side winding;

the primary-side switch is connected in series with the primary-side winding of the power transformer;

the secondary-side winding of the power transformer is connected to the output port;

the primary-side magnetically coupled conductor is different from the primary-side winding of the power transformer; and

the secondary-side magnetically coupled conductor is the secondary-side winding of the power transformer.

42. The circuitry of claim 40, wherein:

the power transformer has a primary-side winding and a secondary-side winding;

the primary-side switch is connected in series with the primary-side winding of the power transformer;

the secondary-side winding of the power transformer is connected to the output port;

the primary-side magnetically coupled conductor is different from the primary-side winding of the power transformer; and

the secondary-side magnetically coupled conductor is different from the secondary-side winding of the power transformer.

43. The circuitry of claim 42, wherein:

the primary-side circuitry comprises the primary-side magnetically coupled conductor; and

the secondary-side circuitry comprises the secondary-side magnetically coupled conductor.

44. The circuitry of claim 40, wherein:

the power transformer has a primary-side winding and a secondary-side winding;

the primary-side switch is connected in series with the primary-side winding of the power transformer;

the secondary-side winding of the power transformer is connected to the output port;

the primary-side magnetically coupled conductor is the primary-side winding of the power transformer; and

the secondary-side magnetically coupled conductor is the secondary-side winding of the power transformer.

45. The circuitry of claim 18, wherein:

the primary-side circuitry comprises a primary-side oscillator configured to generate one or more primary-side pulses; and

the primary-side switch is configured to be turned on based on (i) the one or more primary-side pulses generated by the primary-side oscillator and (ii) the demand pulses received from the secondary-side circuitry.

46. The circuitry of claim 18, wherein primary-side circuitry is configured to turn on the primary-side switch for a duration that is independent of duration of the demand pulse that caused the primary-side switch to be turned on.

47. The circuitry of claim 18, wherein the primary-side circuitry is configured to turn on the primary-side switch at power up, in order to transfer input power to the converter secondary side via the power transformer to power the secondary-side circuitry to generate the demand pulses.

48. The circuitry of claim 18, wherein the primary-side circuitry does not receive pulses from the converter secondary side instructing the primary-side circuitry to turn off the primary-side switch.

49. The circuitry of claim 18, wherein the primary-side circuitry is configured to avoid premature turnoff of the primary-side switch due to capacitive charging of the primary-side switch.

50. The circuitry of claim 18, wherein the primary-side circuitry is configured to establish a maximum duration for which the primary-side switch is allowed to stay on.

51. The circuitry of claim 18, wherein the primary-side circuitry is configured to receive power from a bias winding of the converter primary side.

52. The circuitry of claim 18, wherein the primary-side circuitry is configured to determine when to turn off the primary-side switch based on either (i) current flowing through the primary-side switch or (ii) a maximum duration for which the primary-side switch is allowed to stay on.

53. The circuitry of claim 18, wherein the secondary-side circuitry is configured to adjust the frequency of turning on the primary-side switch to supply a desired amount of voltage or current to the output port in order to regulate the output port.

54. The circuitry of claim 18, wherein the secondary-side circuitry comprises:

a reference source configured to provide a reference signal; and

a secondary-side comparator configured to compare a feedback signal based on the output port voltage or current to the reference signal wherein frequency of the demand pulses is responsive to the comparison between the feedback signal and the reference signal.

55. The circuitry of claim 24, wherein:

each demand pulse conveyed from the converter secondary side to the converter primary side has a leading edge; and

when a particular demand pulse results in a particular occurrence of the primary-side switch turning on, the particular occurrence of the primary-side switch turning on is in response to detecting the leading edge of the particular demand pulse independent of any other demand pulses conveyed from the converter secondary side to the converter primary side and independent of any other pulse edges appearing on the converter primary side.

56. The circuitry of claim 24, wherein the determination of when to turn off the primary-side switch is always originated on the converter primary side and never on the converter secondary side.

57. The circuitry of claim 24, wherein, unless the primary-side switch is already on due to a pulse generated on the converter primary side, the primary-side switch is turned on once for each different demand pulse.

58. The circuitry of claim 24, wherein the primary-side circuitry is configured to avoid premature turnoff of the primary-side switch due to capacitive charging of the primary-side switch.

59. The circuitry of claim 24, wherein the primary-side circuitry is configured to establish a maximum duration for which the primary-side switch is allowed to stay on.

60. The circuitry of claim 24, wherein the primary-side circuitry is configured to receive power from a bias winding of the converter primary side.

61. The circuitry of claim 24, wherein the primary-side circuitry is configured to determine when to turn off the primary-side switch based on either (i) current flowing through the primary-side switch or (ii) a maximum duration for which the primary-side switch is allowed to stay on.

62. The circuitry of claim 18, wherein the demand pulses are transmitted from the secondary-side circuitry to the primary-side circuitry via inductive galvanic isolation circuitry.

63. The circuitry of claim 18, wherein the demand pulses are transmitted from the secondary-side circuitry to the primary-side circuitry via capacitive galvanic isolation circuitry.

64. The circuitry of claim 18, wherein the demand pulses are transmitted from the secondary-side circuitry to the primary-side circuitry via optocoupled galvanic isolation circuitry.

65. The circuitry of claim 18, wherein the demand pulses are transmitted from the secondary-side circuitry to the primary-side circuitry via piezoelectric galvanic isolation circuitry.