Charge pump for PLL/DLL

Abstract

A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Description

RELATED APPLICATIONS

NMOS PMOS transistors 310 and 312. Voltage V_bn sets the bias voltage for current mirror M1 and sets the current that flows through PMOS transistor 314. PMOS transistors 314 and 313 provide a reference current source which supplies current to a pull-down circuit and a pull-up circuit. The current through PMOS transistor 314 is mirrored in PMOS transistors 312 and 310. The current that flows through each transistor in a current mirror can be modified by varying the sizes (width/length ratios) of these devices as is well-known to those skilled in the art.

PMOS device 314 in current mirror M1 provides the initial current to the charge pump dependent on the voltage provided by bias voltage V_bn at the node of the source-drain connection of PMOS device 314. When the charge pump is used in a DLL system, the bias voltage adjusts the maximum current of the charge pump according to the total delay of the delay chain so that the ratio between the reference frequency and DLL bandwidth stays constant.

The gate of PMOS transistor 314 is coupled to the drain of PMOS transistor 314. The gates of PMOS devices 312 and 310 are coupled to the gate of PMOS device 314 allowing this initial current to be mirrored to PMOS transistors 312 and 310. The drain of NMOS device 316 is coupled to the drain of PMOS device 312. Thus, the current mirrored to PMOS device 312 is the same current provided to NMOS device 316 in current mirror M3. The gate of NMOS device 316 is coupled to the gate of NMOS device 315, allowing the drain current of NMOS device 316 to be mirrored to NMOS device 315 in current mirror M3 to provide the pull-down current.

Generally, when the charge pump is enabled (signal ENABLE is asserted or driven to a logic 1) and signal UP is asserted, transistor 309 is turned ‘on’ by the voltage applied to the gate of transistor 309 through NAND gate 301, inverters 302 and 304 and pass gate 303. This allows current to flow through PMOS transistors 309 and 310 in the pull-up circuit. This current adds charge into the OUT node which is coupled to the loop filter 206 (FIG. 1). This increase in charge while transistor 309 is ‘on’ results in an increase in voltage at node OUT, which when the charge pump 300 replaces the charge pump 105 shown in the prior art DLL 100 shown in FIG. 1 causes an increase in the delay generated by the voltage controlled delay line 102. Similarly, when the charge pump is enabled (ENABLE high) and signal DOWN is asserted, transistor 317 is turned ‘on’ by the voltage applied to the gate through NAND gate 305 and inverters 306, 307 and 308. This allows current to flow through transistors 315 and 317 in the pull-down circuit. This current flow from node OUT to ground through transistors 315, 317 takes charge away from node OUT. This reduction in charge while transistor 315 is ‘on’ results in a decrease in voltage at node OUT and a decrease in the delay generated by the voltage controlled delay line 102 (FIG. 1). The paths from the UP/DOWN signals at the input of NAND gates 302, 304 through inverters 303, 304 and through inverters 307, 308 to the gate of transistors 310, 315 are matched to provide the same insertion delay. The pass gate 303 is included in the path to replicate the delay added by inverter 307 in the path from the DOWN signal to the gate of transistor 317. To compensate for the small voltage drop across the source drain path of NMOS transistor 309 when transistor 309 is ‘on’, PMOS transistors 311 and 313 are added to provide symmetry with the current path through PMOS transistor 309. NMOS transistor 318 provides symmetry with the current path through PMOS transistor 315.

Current mirror M3 controls the ratio between pull-down current (through NMOS transistor 315 to ground) and pull up current (from V_dd through PMOS transistor 310). The pull-down current reduces the voltage at node OUT and the pull-up current increases the voltage at node OUT. Thus, the M1 current mirror sets the maximum current of the charge pump through PMOS device 310 and the M3 current mirror controls the ratio between the pull up and pull down current. Current mirrors M1 and M3 may be adjustable or programmable through the use of well-known techniques. Transistors 315 and 316 in current mirror M3 may be sized to deliver more or less current. This allows the circuit designer to compensate for other factors such as parasitic resistances and capacitances and parameter variations. However, such adjustments are static and cannot be re-adjusted once the chip has been packaged and it cannot compensate for voltage change at the OUT node.

According to one embodiment of the invention, an active adjustment of the current mirrors is provided through the use of an operational amplifier, as shown in FIG. 4. The inverting input of the operational amplifier 323 in active current mirror M3 is coupled to node OUT and the non-inverting input of operational amplifier 323 is coupled to node ‘n14’. The output node of the operational amplifier 323 is coupled to node ‘ctrl’ and the gates of NMOS devices 315, 316. Operational amplifier 323 adjusts the voltage on the control node ‘ctrl’, if there is any voltage difference between nodes OUT and ‘n14’. A change in voltage on control node ‘ctrl’ results in a corresponding change in voltage on node OUT and node ‘n14’ through NMOS devices 315, 316.

During operation of the charge pump, the operational amplifier 323 minimizes the static phase error by actively keeping the voltage on node ‘n14’ substantially equal to the output voltage on node OUT. It is important to be able to produce the same pull-up and pull-down current pulses at the output (“OUT”) when the DLL is in lock condition. In a DLL which has achieved lock condition, node OUT is not actively being charged or discharged most of the time as the UP and DOWN pulses are of equal duration. Furthermore, the UP and DOWN pulses can be of shorter duration than in the prior art charge pump described in conjunction with FIG. 2 resulting in a reduction of power required in the device. Thus, the voltage at node OUT remains substantially constant. Changes in voltage at node ‘ctrl’ result in a corresponding change in the currents flowing in NMOS transistors 315, 316. However, the change in voltage at node ‘ctrl’ affects node ‘n14’ more quickly than node OUT because the capacitance of node ‘n14’ is smaller than the capacitance present at node OUT.

The operational amplifier 323 actively controls the voltage at node OUT as follows: if the voltage on node ‘n14’ is higher than the voltage at node OUT, the operational amplifier 323 increases the voltage at node ‘ctrl’. The increase in voltage at node ‘ctrl’ results in an increase in the current flowing through NMOS transistor 316 and NMOS transistor 315 which reduces the voltage on node ‘n14’ until it is the same as the voltage at node OUT. If the voltage on node ‘n14’ is less than the voltage on node OUT, the operational amplifier 323 decreases the voltage on node ‘ctrl’. This decrease in the voltage on node ‘ctrl’ results in a decrease in the current flowing in NMOS transistor 316 and NMOS transistor 315. As the voltage at node ‘ctrl’ changes the voltage on node ‘n14’ faster than on node OUT, a new balance point is reached with the voltage on node ‘n14’ equal to the voltage on node OUT. With the voltage on node ‘n14’ and the output voltage OUT being substantially the same, the source/drain current (pull-down current) through NMOS device 315 is substantially equal to the source/drain current (pull-up current) through PMOS device 310.

By providing an active current mirror including an operational amplifier to the charge pump, the voltage conditions at drain, source and gate of NMOS transistors pair 315 and 316 and PMOS transistors pair 312 and 310 are substantially equal and much closer than in the prior art circuit shown in FIG. 2, resulting in a very accurate matching current through NMOS transistor 315 and PMOS transistor 310. Transistors 319 and 320 are simple buffer capacitances, which prevent the noise caused by NMOS device 315 and PMOS device 310 to couple into the respective bias nodes of the current mirrors M1, M2.

The operational amplifier 323 preferably has an input range from rail to rail (Vdd to Vss (ground)). In an embodiment in which transistors 315, 316 are NMOS devices as shown in FIG. 4, the required output range is from Vdd down to a predetermined voltage close to above ground, i.e. one threshold voltage of an NMOS transistor above ground (Vtn). This output voltage range ensures that NMOS transistors 315 and 316 can never be fully turned ‘off’, as this would make the circuit inoperable. In an alternate embodiment in which transistors 315, 316 are PMOS devices as shown in FIG. 9, the required output range is from Vss to Vtp (i.e, one threshold voltage of a PMOS transistor below Vdd). Thus, an operational amplifier 323 with a rail to rail output range is preferred].

During the power up phase, if the voltage at node ‘n14’ is lower than the voltage at node OUT, the output of the operational amplifier, that is, node ‘ctrl’ is driven low. As node ‘ctrl’ is coupled to the gate of NMOS device 315, NMOS device 315 will likely turn ‘off’. The circuit may freeze in this state or may take a long time to recover. Either case is undesirable.

A start up circuit including NMOS device 321 and NMOS device 322 assists the charge pump in reaching its operating point during the power up phase. The start up circuit initially sets the voltage of node OUT to a value less than V_dd. This allows the operational amplifier 323 to operate properly after the power up phase. A startup signal that is asserted for a predetermined time period after power up during the power up phase is coupled to the gate of NMOS device 322. NMOS device 322 is diode coupled with both the gate and source coupled to the node OUT. The drain of NMOS device 322 is coupled to the drain of NMOS device 322.

While the startup signal coupled to the drain of NMOS device 321 is asserted, the NMOS device 322 is ‘on’. Node OUT is approximately equal to V_dd, thus, with both NMOS device 321 and NMOS device 322 ‘on’, current flows through NMOS device 321 and NMOS device 322 resulting in a decrease in the voltage at node OUT.

Thus, the startup circuit ensures that the voltage at node OUT is less than the voltage at node ‘n14’ during the power up phase, so that the differential input voltage to the operational amplifier 323 is initially positive and node ‘ctrl’ at the output of the operational amplifier 323 is driven ‘high’ during the startup phase holding NMOS device 315 is on. This forces node OUT to approximately the threshold voltage of an NMOS transistor for this predetermined time period. After the power up phase, the startup signal is de-asserted and the startup circuit is no longer required to be enabled.

The present invention reduces the current offset, i.e. the difference in currents flowing between NMOS transistor 315 and PMOS transistor 310 to about 4%. This results in a highly reduced static phase error for the overall DLL system. By reducing the current offset of the charge pump from 20% to 4% in this embodiment, the overall static phase error of the PLL/DLL is reduced from 300 ps to 60 ps.

FIG. 5 is a graph that illustrates the source and sink current pulses in the charge pump shown in FIG. 4 prior to lock condition. In this example, trace 154 corresponds to the source current through transistor 309 in FIG. 4 and trace 156 corresponds to the sink current through transistor 317 in FIG. 4. In the embodiment according to the present invention, the source current and the sink currents are substantially equal in magnitude. Since FIG. 5 illustrates the pulses prior to lock condition, the DLL will start changing the voltage in the node OUT, in order to have the edges of the source and the sink pulses aligned, in search for the lock condition. When the lock condition is reached, the areas below each of the traces 154, 156 will be the same resulting in a stable level of voltage at node OUT. When the source and sink currents are substantially equal in magnitude, the alignment of the edges of the pulses is more accurate, eliminating one of the largest components contributing to static phase error.

FIG. 6 is a schematic of an embodiment of the operational amplifier 323 shown in FIG. 4. The operational amplifier based on complementary input pairs that operate at very low voltage. In the embodiment shown, the operational amplifier can operate with 1V total power supply voltage from Vdd to Vss with Vss assumed to be about 0V (connected to ground).

The operational amplifier 323 includes two differential amplifiers 442, 444, a biasing circuit 446 and an output stage 440. The differential amplifiers 442, 444 have complementary input pairs with the first differential amplifier having an NMOS transistor input pair 411, 412 and the second differential amplifier having a PMOS transistor input pair 404, 405. The first differential amplifier 442 also includes transistors PMOS transistor 403 and NMOS transistors 406, 407. The second differential amplifier 444 also includes PMOS transistors 409, 410, and NMOS transistor 413.

The output stage 440 includes transistors 401 and 402. The biasing circuit includes transistors 414, 415, 416, 417, 418 and 419 and provides bias voltages to transistor 401 in the output stage 440, transistor 403 in the first differential amplifier 442 and transistor 413 in the second differential amplifier 444.

Node OUT shown in FIG. 4 is coupled to differential input ‘inm’ of each differential amplifier and node ‘n14’ shown in FIG. 4 is coupled to differential input ‘inp’ of each differential amplifier. The output stage of the operational amplifier ‘diff_out’ is coupled to node ‘ctrl’ shown in FIG. 4.

When the charge pump 300 (FIG. 4) is enabled (signal ENABLE is asserted or driven to logic 1), transistor 419 is turned on allowing current to flow through transistors 416, 417, 418 and 419. The current in transistor 409 in the second differential amplifier 444 is mirrored in transistor 408. Transistor 408 provides the output of the second differential amplifier. The current from transistor 404 (representing the output of the first differential amplifier) and transistor 408 (representing the output of the second differential amplifier) is summed in transistor 406 in the first differential amplifier 440 and mirrored to transistor 402 in the output stage. When the charge pump 300 is disabled (signal ENABLE is deasserted or driven to a logic 0), due to the logic 0 at the gate of transistor 419, transistor 419 is off and the operational amplifier does not modify the voltage on the ctrl node.

Other embodiments can use programmable arrayed master transistors for the reference current source in the current mirrors to configure or test the operation of the circuit. FIG. 7 is a schematic 500 of such a programmable array of transistors suitable to replace both transistor 313 and transistor 314 of FIG. 4. Four active low select signals (SEL0b, SEL1b, SEL2b and SEL3b) are coupled to four select PMOS transistors 501, 502, 503 and 504. Each select transistor is coupled to a different current mirror master PMOS transistor 505, 506, 507, 508. One or more of the SEL signals is active low, which allows a variable current to flow. The magnitude of the current varies dependent on the number of SEL signals that are active low. For example, with only SEL0b active low, current only flows through PMOS transistor 505 and select transistor 501 and this current is mirrored in transistors 312 and 310 in FIG. 4. The magnitude of the current is increased with all four select signals active low, as current flows through PMOS transistors 505, 506, 507 and 508 and all of the select transistors. This current is mirrored in transistors 312 and 310 through the V_bn node which is coupled to the drains of transistors 310 and 312.

The SEL signals can be controlled by a register, fuse programming, mask programming or any other technique well-known to those skilled in the art. While four sets of programmable master transistors are shown, any number can be used. A similar circuit using NMOS transistors may be used to add programmability by replacing both transistors 416 316 and 418 318 of FIG. 4 with a programmable array of transistors.

The invention is not limited to charge pumps used in DLLs. For example, the invention can also be used in a charge pump in a phase locked loop. A Phase-Locked Loop (PLL) is another well-known circuit for synchronizing a first clock signal with a second clock signal.

FIG. 8 is a block diagram of a prior art PLL 600. An externally supplied clock (CLK) is buffered by clock buffer 601 to provide a reference clock (CLK_REF) that is coupled to a phase detector 604. The phase detector 604 generates phase control signals (UP, DOWN) dependent on the phase difference between CLK_REF and CLK_FB.

The phase control signals (UP/DOWN) of the phase detector 604 are integrated by a charge pump 605 and a loop filter 606 to provide a variable bias voltage V_CTRL 110. The bias voltage V_CTRL controls a voltage controlled oscillator (VCO) 602 which outputs a clock signal CLK_OUT. The frequency of the output clock signal CLK_OUT is proportional to the bias voltage V_CTRL 610. VCOs are well known to those skilled in the art.

The CLK_OUT signal is optionally coupled to a divider 603 to produce a feedback clock signal CLK_FB. If the phase detector detects the rising edge of CLK_REF prior to the rising edge of CLK_FB it asserts the UP signal which causes V_CTRL to increase, thereby increasing the frequency of the CLK_OUT signal. If the phase detector detects the rising edge of CLK_FB prior to the rising edge of CLK_REF it asserts the DOWN signal which causes V_CTRL to decrease, thereby decreasing the frequency of the CLK_OUT signal.

FIG. 9 is a schematic of another embodiment of the charge pump having a different configuration with the operational amplifier controlling P-MOS devices instead of the NMOS transistors as shown in the embodiment of FIG. 4. By applying the same principle of the invention, the operational amplifier 323 equalizes the drains of transistors 310′, 312′, 315, and 316′ in the same way as described in conjunction with the embodiment shown in FIG. 4.

This invention has been described for use in a charge pump in a PLL/DLL system. However, the invention is not limited to a PLL/DLL system. The invention can be used in any system in which a very precise current mirror is required and where the output voltage of the current mirror does not reach ground, which would render the op amp in the active current mirror inoperable.

While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

1. A charge pump comprising:

pull-up circuitry configured to generate pull-up current to increase voltage at a charge pump output, the pull-up circuitry comprising a current source and a controlled transistor having a gate adapted for connection to a first input signal for being controlled thereby, the pull-up circuitry connected between a positive voltage supply and a charge pump output node;

pull-down circuitry configured to generate pull-down current to decrease voltage at the charge pump output, the pull-down circuitry comprising a current source and a controlled transistor having a gate adapted for connection to a second input signal for being controlled thereby, the pull-down circuitry connected between a ground voltage supply and the charge pump output node, and the first and second input signals being derived from up and down signals, respectively;

an operation operational amplifier having two inputs and an output, the operational amplifier configured to reduce phase error, one of the inputs of the operational amplifier connected to the charge pump output node; and

a reference current source having a plurality of select transistors and a plurality of mirror master transistors to provide variable current, the mirror master transistors coupled to slave transistors of either the pull-up circuitry or to mirror the variable current to the slave transistors of the pull-up circuitry when the mirror master transistors are PMOS transistors, and the mirror master transistors coupled to slave transistors of the pull-down circuitry to mirror the variable current in to the slave transistors of the pull-down circuitry when the mirror master transistors are NMOS transistors.

2. The charge pump of claim 1 wherein the current sources in each of the pull-up circuitry and the pull-down circuitry comprises a transistor connected in series with the respective controlled transistor.

3. The charge pump of claim 2 wherein the controlled transistor in the pull-up circuitry is connected to the positive voltage supply, and the current source transistor in the pull-up circuitry is connected to the charge pump output node.

4. The charge pump of claim 2 wherein the controlled transistor in the pull-down circuitry is connected to the ground voltage supply, and the current source transistor in the pull-down circuitry is connected to the charge pump output node.

5. The charge pump of claim 1 further comprising additional pull-up circuitry and additional pull-down circuitry connected together at an additional node.

6. The charge pump of claim 5 wherein the additional pull-up circuitry and the pull-up circuitry have corresponding transistors with source and drain terminals connected in the same manner, and the additional pull-down circuitry and the pull-down circuitry have corresponding transistors with source and drain terminals connected in the same manner.

7. The charge pump of claim 6 wherein a gate of a controlled transistor in the additional pull-up circuitry is connected to a first voltage supply, and a gate of a controlled transistor in the additional pull-down circuitry is connected to a second voltage supply.

8. The charge pump of claim 6 wherein the additional pull-up circuitry and the pull-up circuitry have correspondingly same sized transistors, and the additional pull-down circuitry and the pull-down circuitry have correspondingly same sized transistors.

9. The charge pump of claim 5 wherein the other input of the operational amplifier is connected to the additional node.

10. The charge pump of claim 9 wherein the output of the operational amplifier is connected to and the reference current source are each connected to a different respective one of the current source of the pull-down circuitry and the current source of the pull-up circuitry, and the reference current source is connected to the current source of the other circuitry.

11. The charge pump of claim 1 wherein the operational amplifier has an output range substantially from rail to rail.

12. The charge pump of claim 1 wherein the operational amplifier comprises two differential input stages.

13. The charge pump of claim 12 wherein the differential input stages comprise one PMOS input differential stage and one NMOS input differential stage.

14. The charge pump of claim 1 wherein the charge pump output node is connected to a voltage controlled oscillator to form part of a phase locked loop.

15. The charge pump of claim 1 wherein the charge pump output node is connected to a voltage controlled delay line to form part of a delay locked loop.

16. The charge pump of claim 1 further comprising registers coupled to the plurality of select transistors.

17. The charge pump of claim 1 further comprising fuses coupled to the plurality of select transistors.

18. The charge pump of claim 1 wherein the plurality of select transistors and the plurality of mirror master transistors include a programmable array of field-effect transistors.