An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.
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0. 18. An output buffer circuit for avoiding voltage overshoot, comprising:
an input circuit, configured to generate a current signal according to an input voltage;
an output circuit, coupled to the input circuit and configured to generate an output voltage according to the current signal;
a clamp circuit, coupled to the input circuit and the output circuit, and configured to clamp the output voltage within a predefined range; and
a controller, configured to activate the clamp circuit when the input voltage is received and deactivate the clamp circuit to prevent a leakage current flowing through the clamp circuit when the output voltage reaches a steady state.
14. A method of avoiding voltage overshoot for an output buffer circuit, the output buffer circuit comprising an input stage circuit, an output stage circuit and a clamp circuit, the input stage circuit generating a current signal according to an input voltage, the output stage circuit generating an output voltage according to the current signal, the clamp circuit, coupled to the input stage circuit and the output stage circuit, for clamping the output voltage within a predefined range, the method comprising:
activating the clamp circuit when the input voltage is received;
starting to output the output voltage; and
deactivating the clamp circuit to prevent a leakage current resulted by flowing through the clamp circuit when the output voltage reaches a steady state.
1. An output buffer circuit for avoiding voltage overshoot, the output buffer circuit comprising:
an input stage circuit comprising a positive input terminal, for receiving an input voltage, and a negative input terminal, — the input stage circuit generating a current signal according to the input voltage;
an output bias circuit, coupled to the input stage circuit, for generating a dynamic bias according to the current signal;
an output stage circuit, coupled to the input stage circuit and the output bias circuit, comprising:
an output terminal, reversely coupled to the negative input terminal; and
at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage;
a clamp circuit, coupled to the input stage circuit, the output bias circuit and the output stage circuit, for drawing currents from the output terminal to help the current signal to return the dynamic bias to a proper level when the output voltage exceeds a predefined range; and
a control unit controller, coupled to the clamp circuit, for activating the clamp circuit when the output buffer circuit receives the input voltage and for deactivating the clamp circuit to prevent a leakage current resulted by flowing through the clamp circuit when the output voltage reaches a steady state.
2. The output buffer circuit of
3. The output buffer circuit of
a trigger circuit, for generating a trigger signal when the output buffer circuit receives the input voltage; and
a timer, coupled to the trigger circuit, for calculating the predefined time according to the trigger signal controlling the controller to switch a voltage for the clamp circuit to deactivate the clamp circuit after the timer receives the trigger signal and then counts the predefined time.
4. The output buffer circuit of
5. The output buffer circuit of
a voltage detection circuit, coupled to the positive input terminal and the output terminal, for detecting voltage levels of the positive input terminal and the output terminal; and
a comparison unit comparator, coupled to the voltage detection circuit, for determining the output voltage reaches the steady state when the voltage difference between the output terminal and the positive input terminal is smaller than a predefined value.
6. The output buffer circuit of
a first metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a source first terminal coupled to the output terminal, a gate second terminal coupled to an operating bias, and a drain third terminal; and
a second metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a source first terminal coupled to the drain third terminal of the first MOSFET, a gate second terminal coupled to the output bias circuit and the at least one output transistor, and a drain third terminal coupled to the gate second terminal of the second MOSFET;
wherein a level of the operating bias is switched by the control unit controller.
7. The output buffer circuit of
8. The output buffer circuit of
9. The output buffer circuit of
10. The output buffer circuit of
11. The output buffer circuit of
12. The output buffer circuit of
13. The output buffer circuit of
15. The method of
determining the output voltage reaches the steady state when the input voltage is received for a predefined time.
16. The method of
determining whether the output voltage reaches the steady state by detecting voltage difference between the output voltage and the input voltage after the input voltage is received.
17. The method of
determining the output voltage reaches the steady state when the voltage difference between the output voltage and the input voltage is smaller than a predefined value.
0. 19. The output buffer circuit of claim 18, wherein the controller determines the output voltage reaches the steady state when the output buffer circuit receives the input voltage for a predefined time.
0. 20. The output buffer circuit of claim 19, wherein the controller comprises:
a trigger circuit, for generating a trigger signal when the output buffer circuit receives the input voltage; and
a timer, coupled to the trigger circuit, for controlling the controller to switch a voltage for the clamp circuit to deactivate the clamp circuit after the timer receives the trigger signal and then counts the predefined time.
0. 21. The output buffer circuit of claim 18, wherein the controller determines whether the output voltage reaches the steady state by detecting voltage difference between the output voltage and the input voltage after the output buffer circuit receives the input voltage.
0. 22. The output buffer circuit of claim 21, wherein the controller comprises:
a voltage detection circuit, coupled to the input circuit and the output circuit, for detecting voltage levels of the input voltage and the output voltage; and
a comparator, coupled to the voltage detection circuit, for determining the output voltage reaches the steady state when the voltage difference between the output voltage and the input voltage is smaller than a predefined value.
0. 23. The output buffer circuit of claim 18, wherein the input circuit is a differential input circuit having a rail-to-rail input range.
0. 24. The output buffer circuit of claim 18, further comprises
an output bias circuit coupled to the input circuit and the output circuit, for generating a dynamic bias according to the current signal.
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1. Field of the Invention
The present invention relates to an output buffer circuit for avoiding voltage overshoot, and more particularly, to an output buffer circuit that prevents leakage currents from changing a systematic offset voltage by timely closing a clamping circuit.
2. Description of the Prior Art
An output stage of a present display driver adopts an operational amplifier circuit to rapidly charge and discharge a load end, such that driving capability of the display driver is enhanced. However, if inner currents of the operational amplifier cannot be recovered immediately, the rapid charging or discharging of the load end would a voltage overshoot. In general, a clamping circuit is added between an output terminal of the operational amplifier and an input terminal of the output stage thereof to avoid the voltage overshoot. However, under a situation that the operational amplifier has full swing output, the clamping circuit may not be completely closed, resulting in certain leakage currents (in approximate nA degree). For low power application, such leakage currents may change a systematic offset voltage of the display driver.
Please refer to
In the embodiment of the present invention, the transistors POS1 and POS2 are P-type metal-oxide-semiconductor field-effect (MOSFET) transistors, for clamping the output voltage under a predefined high voltage level; while the transistors NOS1 and NOS2 are N-type MOSFETs, for clamping the output voltage over a predefined low voltage level. A gate of the transistor POS2 is coupled to an operating bias VBPOS, while a gate of the transistor NOS2 is coupled to an operating bias VBNOS. The operating biases VBPOS and VBNOS are switched by the control unit 25. When the output buffer circuit 20 receives the input voltage, the control unit 25 switches the operating biases VBPOS and VBNOS to a normal bias level to activate the clamping circuit 24; whereas, when a voltage level of the output terminal AVF reaches a steady state, the control unit 25 switches the operating biases VBPOS and VBNOS to a power supply voltage VDDA and a ground voltage GNDA, respectively. Such that the transistors POS2 and NOS2 are closed, so as to deactivate the clamping circuit 24.
Please refer to
In the embodiment of the present invention, the control unit 25 can determine whether the output voltage reaches the steady state by following two methods, and is not limited to these. One method is determining the output voltage reaches the steady state when the output buffer circuit 20 receives the output input voltage for a predefined time; while the other method is determining whether the output voltage reaches the steady state by detecting voltage difference between the output terminal AVF and the positive input terminal AVP after the output buffer circuit 20 receives the input voltage.
For example, please refer to
Please refer to
Through the above embodiments, the present invention is able to solve a problem that the clamping circuit cannot be completely closed and therefore influences the systematic offset voltage of the operational amplifier. Additionally, circuit characteristics become more stable without extra current consumption and area cost for the operational amplifier.
Please refer to
Step 600: Start.
Step 610: Activate the clamp circuit 24 when the input voltage is received.
Step 620: Start to output the output voltage.
Step 630: Deactivate the clamp circuit 24 when the output voltage reaches the steady state.
Step 640: End.
According to the voltage overshoot elimination process 60, the output buffer circuit 20 activates the clamp circuit 24 when receiving the input voltage. Next, the output buffer circuit 20 starts to output the output voltage. Not until the output voltage reaches the steady state, does the output buffer circuit 20 deactivates the clamping circuit 24. Operations of the output buffer circuit are detailed in the above embodiments, and are not narrated herein.
To sum up, by adding the clamping circuit to the output buffer circuit, the present invention eliminates the voltage overshoot caused by the strong driving capability of the output stage and avoids the systematic offset voltage being influenced in the low power application via the timing control. In addition, the current consumption and area cost of the operational amplifier are not increased.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
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