Clock generation circuit with fast-startup standby mode

Abstract

A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).

Description

FIG. 22 is a block diagram of a wireless modem.105 106) and power and clocks are supplied. This transition (block 112 to 106) incurs a significant delay.

When it is again decided to place the system 10 in sleep mode (block 108) but a fast startup time is required (e.g., to respond to activity on an external bus, to process an incoming wireless signal, or the like), the status information (block 110) may indicate that the PMU 12 may place the clock generation circuit 14 in STANDBY mode (block 116). In STANDBY mode, the clock generation circuit 14 does not generate an output; however, a voltage is maintained on internal nodes by a small pre-bias current. Because of the pre-bias current, when a circuit 24, 26, 28 again requests a clock signal (block 118), the clock generation circuit 14 may exit STANDBY and be fully ON (block 106) and operational in a very short startup time (e.g., 1.5 usec). The fast startup time enables greater use of STANDBY mode, reducing overall power consumption.

FIG. 3 depicts one embodiment of a clock generation circuit 14. The clock generation circuit 14 includes an RC oscillator 30, clock quality analyzer 32, AND gate function 34, and output driver 36. As well known in the art, the op amp in the RC oscillator 30 will generate a periodic output signal, the frequency of which depends on the values of the capacitor C and resistor R, when a bias driver 38 powers up the oscillator 30 op amp, and provides a relatively large bias current. A clock quality analyzer circuit 32 monitors the oscillator 30 output, and will only output a “1” toward the AND function 34 when the clock signal meets predetermined quality specifications regarding voltage, frequency, jitter, ripple, duty cycle, and the like. The AND gate function 34 allows the RC oscillator 30 output to pass to the output buffer 36 only if the ClockRequest input is asserted, and the clock quality analyzer circuit 32 determines that the clock signal is within specification. In conventional clock generation circuits, the clock quality analyzer circuit 32 may suspend the clock signal for 10 usec or more, in transitioning from OFF to ON.

According to embodiments of the present invention, a StandBy input signal triggers a pre-bias driver 40 to provide a lower, pre-bias current to the amplifier in the RC oscillator 30 when the oscillator 14 is in STANDBY mode. The pre-bias current keeps the amplifier charged, but is insufficient to enable oscillation. When the ClockRequest signal is asserted, full bias is established and the RC oscillator 30 starts up, quickly settling to the proper output point, generating a high quality clock signal at the correct frequency. The clock quality analyzer circuit 32 verifies this, and rapidly enables the AND gate function 34 to pass the clock signal to the output buffer 36.

FIG. 4 is a timing diagram depicting the operational state of the system 10 and the clock generation circuit 14, as well as control signals StandBy and ClockRequest. Initially, the system 10 (including the clock generation circuit 14) is OFF. Upon power-up, the system 10 is in a STARTUP state during which various circuits 12, 20 power up and initialize. During this time, the clock generation circuit 14 transitions from OFF to ON states, as indicated by the relatively long hashed startup time. Generally, the clock generation circuit 14 startup time is not the critical system startup parameter, as other circuits (e.g., processors 24, 26) have much longer initialization/boot-up sequences.

Once all circuits initialize, the clock generation circuit 14 provides at least one clock signal to the SMPS 16, which provides power to circuits 24, 26, 28. The system 10 is in ACTIVE state. When operational conditions permit, for power conservation purposes the system 10 goes into SLEEP mode, and the clock generation circuit 14 is placed in STANDBY. This occurs because ClockRequest is deasserted, indicating no circuit 16, 24, 26, 28 requires clock signals. However, the StandBy signal remains asserted. This causes a pre-bias current to be applied to the RC oscillator circuit 30 within the clock generation circuit 14, almost fully charging the amplifier and maintaining the output node at near its operational voltage. When the system 10 exits SLEEP mode by again asserting ClockRequest, only a very short startup time is required to transition the clock generation circuit 14 from STANDBY to ON. This translates to a corresponding brief duration in which the system 10 transitions from SLEEP to ACTIVE mode.

FIG. 5 is a qualitative graph depicting the relationship between current consumption and startup time for each of the three operating modes of the clock generation circuit 14. When the clock generation circuit 14 is ON, there is no problem with startup time; however, the current consumption is at a maximum. When the clock generation circuit 14 is OFF there is zero current consumption, but the startup time is long. The STANDBY mode provides a compromise. The power consumption is only 1/10 that during the fully ON state, and while the startup time is not zero, it is only 1/7 the time required to transition out of the OFF state. For use cases where tight startup time requirements preclude turning the clock generation circuit 14 fully OFF, the STANDBY mode provides an additional way to save 90% of the power, while still satisfying startup time requirements.

The clock generation circuit 14 depicted in FIG. 3 is based on an RC oscillator 30. A more complex, and more commonly deployed, form of clock generation circuit 14 employs a relaxation oscillator, depicted in block diagram form in FIG. 6. A relaxation oscillator operates by repeatedly charging and discharging an integration capacitor via a feedback loop.

A bandgap reference circuit 40 generates a reference voltage Vref, and provides it to both a scaling/buffering circuit 42 and the current generation circuit 44. The scaling and buffering circuit 42 scales and buffers the reference voltage Vref, outputting a steady threshold voltage Vth. The current generation with trimming circuit 44 generates a charging current Icharge, which charges an integration capacitor in an integration circuit 46. As indicated by the dashed-line box, the current generation circuit 44 and integration circuit 46 are tightly coupled.

The integration circuit 46 outputs a saw-tooth integrated voltage Vint, which increases as the integration capacitor charges and returns to zero when the capacitor discharges. A comparison circuit 50 compares the integrated voltage Vint to the threshold voltage Vth, and generates a reset impulse when they are equal. The reset signal is fed back to the integration circuit 46, as a trigger to discharge the integration capacitor. The integration capacitor then begins charging again to generate the next cycle. A shaping and buffering circuit 52 conditions the saw-tooth wave of the integrated voltage Vint, outputting a square clock signal Clock. The frequency of the Clock signal is determined by the threshold voltage Vth and the magnitude of the current Icharge, which directly controls the charging time of the integration capacitor.

FIG. 7 depicts a conventional implementation of the current generation circuit 44 and integration circuit 46. A trim code applied to the chain of resistors sets the resistance in the current generating path 44 (i.e., through transistor M1, the gate of which is controlled by the amplifier 45), thus controlling the current through this path. A current mirror comprising matched transistors M2 and M3 copies this current to a proportional charging current Icharge in the integration path 46, where it charges the integration capacitor Cint. The integration circuit 46 outputs the integrated voltage Vint as the voltage across the capacitor Cint. The reset signal received in feedback from the comparison circuit 50 discharges the capacitor to begin the next charging iteration. When the ClockRequest=0 to place the clock generation circuit 14 in OFF state, the gates of the current mirror are pulled high, shutting off both transistors and halting the charging current flow. When these circuits 44, 46 are again turned ON, transients at the output of the amplifier 45 must settle before a stable charging current Icharge is reestablished, which is necessary for frequency-stable clock generation.

However, the current generation circuit 44 and integration circuit 46 are not the only sources of startup transients that cause a lengthy startup time in transitioning the clock generation circuit 14 from OFF to ON. FIG. 8 depicts transients in the threshold voltage Vth caused by the amplifier startup. Additionally, the charging current Icharge experiences transients. Furthermore, transients appear in the biasing of the comparator in the comparison circuit 50. All of these transients must settle, and the relevant nodes reach a steady-state voltage, before a clock signal can be output.

As indicated in FIG. 9, according to embodiments of the present invention, the StandBy signal is distributed to the scaling and buffering circuit 42, the current generation circuit 44, the integration circuit 46, and the comparison circuit 50, and the shaping and buffering circuit 52. When ClockRequest=0 but StandBy=1, the clock generation circuit 14 enters a STANDBY mode, in which pre-bias currents are supplied to amplifiers in the clock generation circuit 14 to reduce startup transients, and hence startup time, when the clock generation circuit 14 is turned fully ON.

FIG. 10 depicts the current generation circuit 44 and integration circuit 46 in STANDBY mode, according to one embodiment. As with the prior art circuit of FIG. 7, ClockRequest=0 pulls the gates of the mirror current transistors M2, M3 high, turning M3 off and making Icharge=0 in the integration circuit 46. The amplifier 45 receives a low pre-bias current. Logic in the current generation circuit 44 replaces the trim resistors with a series of diode-connected transistors when ClockRequest=0 AND StandBy=1. In this configuration, both the amplifier 45 and the transistor M1 are biased very close to their operating points. M1 can then return to full conduction very rapidly when ClockRequest=1, with low transients that quickly settle, yielding a very short startup time to a stable clock output.

FIG. 11 depicts the StandBy input providing a pre-bias current to the comparator amplifier in the scaling and buffering circuit 42 during STANDBY mode. This biases the amplifier to near its operational point. The values of resistors R1 and R2 are increased so that the amplifier with lower biasing can drive them. Higher resistor values are not problematic since the threshold voltage Vth is always constant and there is no need to settle fast. The amplifier bias is increased when the clock generation circuit 14 is turned ON so that the threshold voltage Vth is more stable, even when the comparator is switching.

FIG. 12 depicts the StandBy input providing a pre-bias current to the comparator amplifier in the comparison circuit 50 during STANDBY mode. This biases the amplifier to near its operational point. The amplifier bias is increased when the clock generation circuit 14 is turned ON so that the comparator can switch rapidly enough.

FIGS. 13-16 depict transistor-level views of various embodiments of the current generation circuit 44 and integration circuit 46 of the relaxation oscillator of a clock generation circuit 14. For clarity, a single control signal “enable” and its inverse “disable” are shown controlling switches. The enable/disable signals result from the ClockRequest signal described above (and possibly other system logic).

FIG. 13 depicts a conventional circuit, in which the clock generation circuit 14 is OFF. FIG. 14 depicts the same circuit in the ON state. The current generation path 44 includes transistors M2, M1, and the variable (trim) resistors. An amplifier 45 drives the gate of M1. A bias current circuit 47 provides additional current Ibias to the amplifier 45, in the ON state.

FIG. 13 depicts the clock generation circuit 14 in the OFF state. The transistor M1 is isolated, with no current flowing through the variable resistance R to generate current in the current generating path 44. Thus, no charging current Icharge flows in the integration path 46 to charge a capacitor (not shown). The amplifier 45 is disabled, and its inverting input is grounded. The bias current circuit 47 is disabled.

FIG. 14 depicts the same circuits in the ON state. The transistor M1 is connected to both M2 and the resistors R, generating current in the path 44, which is mirrored in the integration path 46 as Icharge. The amplifier 45 is enabled, its inverting input is connected to the source of M1, and a bias current Ibias is applied to the amplifier 45 by the bias circuit 47. Because Ibias goes from zero to its full value when the oscillator 14 is switched ON, transients at the output of the amplifier 45 require several microseconds to stabilize.

FIGS. 15 and 16 depict similar circuits, but in which a small bias current Ibias/10 is continuously applied to the amplifier 45. That is, FIG. 15 depicts the clock generation circuit 14 in STANDBY mode, and FIG. 16 shows it in the fully ON state.

In FIG. 15, the amplifier 45 is enabled, and its inverting input is connected to the current generation path 44, in which a small current flows through M1 and the chain of diodes. A small bias current Ibias/10 is continuously applied to the amplifier 45 by the bias circuit 47. This keeps the amplifier 45 biased very close to its operating point.

In FIG. 16, the clock generation circuit 14 is switched ON, and the trim resistors R are switched into the current generating path 44. Charging current Icharge is established in the integration path 46. The amplifier 45 is fully enabled, and Ibias/10 is continuously applied by the bias circuit 47.

FIG. 17A is a graph of transients on Icharge and the bias current Ibias as the clock generation circuit 14 switches from OFF to ON. FIG. 17B depicts the same for transitioning the clock generation circuit 14 between STANDBY and ON modes. With constant bias (i.e., the STANDBY mode), the bias points of the amplifier 45 are almost constant all the time, and therefore the transients are much smaller. They also settle faster, allowing for a faster startup time. Additionally, the bias current can be much lower (e.g., in the range of 10% of the full bias current).

FIGS. 18-21 depict transistor-level views of other embodiments of the current generation circuit 44 and integration circuit 46 of a relaxation oscillator in a clock generation circuit 14, wherein the integration circuit generates a integration capacitor charging voltage Vcharge rather than the reference current Icharge described above. FIGS. 18 and 19 depict the case of switched biasing, where the clock generation circuit 14 is in OFF and ON states, respectively. FIGS. 20 and 21 depict the same circuit with constant biasing, where the clock generation circuit 14 is in STANDBY and ON states, respectively.

In FIG. 18, the current generating path 44 and amplifier 45 are disabled, and no current flows through the variable (trim) resistors. The bias current circuit 47 is also disabled. Vcharge=0, so the integration capacitor (not shown) does not charge/discharge to generate a Clock signal.

In FIG. 19, the current generating path 44 and amplifier 45 are enabled, and current through the variable (trim) resistors generates a charging voltage Vcharge. The bias circuit 47 is enabled, providing a bias current Ibias to the amplifier 45.

FIG. 20 depicts an embodiment where a partial bias is applied to the amplifier 45, when the clock generation circuit 14 is in STANDBY mode. No current flows through the variable (trim) resistors, so Vcharge=0. However, the amplifier 45 is enabled and the bias circuit 47 applies a partial bias current. Note that transistor 49 is disabled, limiting the bias current to only that required to bias the amplifier 45 to near its operating point.

FIG. 21 depicts the clock generation circuit 14 in fully ON state. Current flowing through the variable (trim) resistors generates a charging voltage Vcharge. The amplifier 45 is fully on, and the bias current circuit 47 provides both the standby bias current, and additionally enables transistor 49, providing additional bias current. This additional bias current during operation helps the amplifier 45 deal with transient loads.

In all of the embodiments described above, a clock generation circuit 14 transitions from a STANDBY mode, in which a small, pre-bias current is applied to amplifiers, to a fully ON state, with fewer transients, which quickly settle to a steady-state. Hence, the clock generation circuit 14 startup time is dramatically shorter than in prior art designs, which only transition the clock generation circuit 14 between OFF and ON states. The pre-bias current consumption in the STANDBY state is small, such as in the range of 10% of the bias current applied in the ON state. The very fast startup time allows the clock generation circuit 14 to be placed in STANDBY more often than conventional circuits, thus reducing overall power consumption, despite the small pri-bias current consumption in the STANDBY state. For example, the clock generation circuit 14 may be placed in STANDBY mode when an external bus or wireless interface is dormant, but may become active at any time, requiring e.g., the capture of burst data transfers.

The STANDBY bias current circuits disclosed herein are straightforward. As such, they are robust on silicon variation, and portable between silicon technologies. Additionally, by providing a very short startup time from STANDBY to ON, designers may optimize the ON mode power consumption and performance, without concern for startup performance.

The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.

Claims

1. A method of operating a clock generation circuit on an integrated circuit, the clock generation circuit including an oscillator circuit, comprising:

monitoring clock request indicators from one or more circuits;

if at least one circuit requests a an associated clock signal, operating the clock generation circuit in a first, full power mode in which the clock generation circuit outputs at least one clock signal;

if no circuit requests a an associated clock signal, determining whether a second, sleep mode is allowed, in which the oscillator circuit is disabled and the clock generation circuit outputs no clock signal;

if the second, sleep mode is allowed, operating the clock generation circuit in the second, sleep mode;

if the second, sleep mode is not allowed, operating the clock generation circuit in a third, standby mode in which one or more circuit nodes in the clock generation circuit are biased near their operating voltages but the oscillator circuit does not oscillate and the clock generation circuit outputs no clock signal.

2. The method of claim 1 further comprising, when the clock generation circuit is in the third, standby mode:

detecting at least one clock request indication;

in response to detecting at least one clock request indication, transitioning the clock generation circuit from the third, standby mode to the first, full power mode;

wherein a start-up time from detecting at least one clock request indication to outputting a stable clock signal is less than 10 usec.

3. The method of claim 2 wherein the start-up time is less than 2 usec.

4. The method of claim 1 wherein power consumption of the clock generation circuit in the third, standby mode is at least 50% less than in the first, full power mode.

5. The method of claim 4 wherein power consumption of the clock generation circuit in the third, standby mode is at least 90% less than in the first, full power mode.

6. The method of claim 1 wherein the clock generation circuit has separate first and second enable inputs, and wherein

operating the clock generation circuit in the first, full power mode comprises asserting both first and second enable signals applied to the first and second enable inputs, respectively;

operating the clock generation circuit in the second, sleep mode comprises deasserting both of the first and second enable signals; and

operating the clock generation circuit in the third, standby mode comprises asserting the first enable signal and deasserting the second enable signal.

7. The method of claim 1 wherein

operating the clock generation circuit in the first, full power mode comprises providing a first bias current to the clock generation circuit;

operating the clock generation circuit in the second, sleep mode comprises providing no bias current to the clock generation circuit; and

operating the clock generation circuit in the third, standby mode comprises providing a second bias current, less than the first bias current, to the clock generation circuit.

8. The method of claim 7 wherein the second bias current is about 10% of the first bias current or less.

9. The method of claim 1 wherein the oscillator circuit is an RC oscillator.

10. The method of claim 1 wherein the oscillator circuit is a relaxation oscillator.

11. A clock generation circuit, comprising:

an oscillator circuit operative to selectively generate a periodic signal;

an output circuit receiving a the periodic signal from the oscillator circuit and operative to selectively output at least one clock signal;

a bias circuit operative to control the clock generation circuit to operate in one of three modes, selected from the group consisting of

a first, full power mode in which the output circuit outputs the at least one clock signal;

a second, sleep mode in which the oscillator circuit is disabled and the output circuit outputs no clock signal; and

a third, standby mode in which nodes within the oscillator circuit and output circuit are biased near their operating voltages but the oscillator circuit does not oscillate and the output circuit outputs no clock signal.

12. The clock generation circuit of claim 11 further comprising at least one control input, and wherein, in response to one or more signals received at the at least one control input, the clock generation circuit is operative to transition from the third, standby mode to the first, full power mode, and wherein a start-up time from the one or more control signals to outputting a stable clock signal is less than 10 usec.

13. The clock generation circuit of claim 12 wherein the start-up time is less than 2 usec.

14. The clock generation circuit of claim 11 wherein power consumption of the clock generation circuit in the third, standby mode is at least 50% less than in the first, full power mode.

15. The clock generation circuit of claim 14 wherein power consumption of the clock generation circuit in the third, standby mode is at least 90% less than in the first, full power mode.

16. The clock generation circuit of claim 12 wherein the at least one control input comprises separate first and second enable inputs, and wherein the bias circuit is operative to

operate the clock generation circuit in the first, full power mode in response to both first and second enable signals received at the first and second enable inputs, respectively, being asserted;

operate the clock generation circuit in the second, sleep mode in response to both first and second enable signals being deasserted; and

operating the clock generation circuit in the third, standby mode in response to the first enable signal being asserted and the second enable signal being deasserted.

17. The clock generation circuit of claim 11 wherein the bias circuit is operative to

operate the clock generation circuit in the first, full power mode by providing a first bias current to the clock generation circuit;

operate the clock generation circuit in the second, sleep mode by providing no bias current to the clock generator circuit; and

operate the clock generation circuit in the third, standby mode by providing a second bias current, less than the first bias current, to the clock generation circuit.

18. The clock generation circuit of claim 17 wherein the second bias current is about 10% of the first bias current or less.

19. The clock generation circuit of claim 11 wherein the oscillator circuit is an RC oscillator.

20. The clock generation circuit of claim 11 wherein the oscillator circuit is a relaxation oscillator.

21. A clock generation circuit comprising:

an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;

a bias circuit connected to the amplifier; and

an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;

wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein

in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;

in the second sleep mode, the oscillator circuit is disabled; and

in the third standby mode, the amplifier is biased to a voltage close to its amplifier operating voltage but the oscillator circuit does not generate the periodic signal.

22. The clock generation circuit of claim 21 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.

23. The clock generation circuit of claim 22 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.

24. The clock generation circuit of claim 23 wherein, in the third standby mode, a first transistor in the current generation circuit is biased to a voltage close to its transistor operating voltage.

25. The clock generation circuit of claim 23 wherein, in the first full power mode the first transistor is connected between a second transistor and a variable resistance unit and in the third standby mode the first transistor is connected between the second transistor and a plurality of diodes and wherein, in both the first full power mode and the third standby mode, the bias circuit provides a low bias current to the amplifier circuit.

26. The clock generation circuit of claim 25 wherein the gate of the second transistor in the current generation circuit is connected in a current mirror arrangement to the gate of a third transistor in the integration circuit of the relaxation oscillator circuit and wherein in the first full power mode, a mirrored current is provided to a capacitor of the relaxation oscillator circuit.

27. The clock generation circuit of claim 21 wherein the indication comprises a clock request and a standby signal.

28. The clock generation circuit of claim 21 further comprising at least one control input to receive a clock request and a standby signal from a control unit.

29. A power management unit comprising a clock generation circuit including:

an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;

a bias circuit connected to the amplifier; and

an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;

wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein

in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;

in the second sleep mode, the oscillator circuit is disabled; and

in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal; and

a switch mode power supply circuit;

wherein, in the first full power mode, the switch mode power supply circuit receives the clock signal from the output circuit and provides power to an electronic circuit.

30. The power management unit of claim 29 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.

31. The power management unit of claim 29 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.

32. A wireless modem comprising a clock generation circuit including:

an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;

a bias circuit connected to the amplifier; and

an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;

wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein

in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;

in the second sleep mode, the oscillator circuit is disabled; and

in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal.

33. The wireless modem of claim 32 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.

34. The wireless modem of claim 32 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.

35. The wireless modem of claim 32 further comprising at least one of a digital broadband integrated circuit, a radio frequency integrated circuit, and a power amplifier.

36. A wireless communication terminal comprising a clock generation circuit including:

an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;

a bias circuit connected to the amplifier; and

an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;

wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein

in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;

in the second sleep mode, the oscillator circuit is disabled; and

in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal.

37. The wireless communication terminal of claim 36 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.

38. The wireless communication terminal of claim 36 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.