A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).
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11. A clock generation circuit, comprising:
an oscillator circuit operative to selectively generate a periodic signal;
an output circuit receiving a the periodic signal from the oscillator circuit and operative to selectively output at least one clock signal;
a bias circuit operative to control the clock generation circuit to operate in one of three modes, selected from the group consisting of
a first, full power mode in which the output circuit outputs the at least one clock signal;
a second, sleep mode in which the oscillator circuit is disabled and the output circuit outputs no clock signal; and
a third, standby mode in which nodes within the oscillator circuit and output circuit are biased near their operating voltages but the oscillator circuit does not oscillate and the output circuit outputs no clock signal.
0. 21. A clock generation circuit comprising:
an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;
a bias circuit connected to the amplifier; and
an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;
wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;
in the second sleep mode, the oscillator circuit is disabled; and
in the third standby mode, the amplifier is biased to a voltage close to its amplifier operating voltage but the oscillator circuit does not generate the periodic signal.
0. 32. A wireless modem comprising a clock generation circuit including:
an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;
a bias circuit connected to the amplifier; and
an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;
wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;
in the second sleep mode, the oscillator circuit is disabled; and
in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal.
0. 36. A wireless communication terminal comprising a clock generation circuit including:
an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;
a bias circuit connected to the amplifier; and
an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;
wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;
in the second sleep mode, the oscillator circuit is disabled; and
in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal.
1. A method of operating a clock generation circuit on an integrated circuit, the clock generation circuit including an oscillator circuit, comprising:
monitoring clock request indicators from one or more circuits;
if at least one circuit requests a an associated clock signal, operating the clock generation circuit in a first, full power mode in which the clock generation circuit outputs at least one clock signal;
if no circuit requests a an associated clock signal, determining whether a second, sleep mode is allowed, in which the oscillator circuit is disabled and the clock generation circuit outputs no clock signal;
if the second, sleep mode is allowed, operating the clock generation circuit in the second, sleep mode;
if the second, sleep mode is not allowed, operating the clock generation circuit in a third, standby mode in which one or more circuit nodes in the clock generation circuit are biased near their operating voltages but the oscillator circuit does not oscillate and the clock generation circuit outputs no clock signal.
0. 29. A power management unit comprising a clock generation circuit including:
an oscillator circuit including an amplifier and operative to selectively generate a periodic signal;
a bias circuit connected to the amplifier; and
an output circuit receiving the periodic signal from the oscillator circuit and operative to output a clock signal;
wherein the clock generation circuit is adapted to operate in one of a first full power mode, a second sleep mode or a third standby mode, dependent on an indication provided for the clock generation circuit; wherein
in the first full power mode, the oscillator circuit provides the periodic signal to the output circuit and the output circuit generates the clock signal;
in the second sleep mode, the oscillator circuit is disabled; and
in the third standby mode, the amplifier is biased to an amplifier voltage close to its operating voltage but the oscillator circuit does not generate the periodic signal; and
a switch mode power supply circuit;
wherein, in the first full power mode, the switch mode power supply circuit receives the clock signal from the output circuit and provides power to an electronic circuit.
2. The method of
detecting at least one clock request indication;
in response to detecting at least one clock request indication, transitioning the clock generation circuit from the third, standby mode to the first, full power mode;
wherein a start-up time from detecting at least one clock request indication to outputting a stable clock signal is less than 10 usec.
3. The method of
4. The method of
5. The method of
6. The method of
operating the clock generation circuit in the first, full power mode comprises asserting both first and second enable signals applied to the first and second enable inputs, respectively;
operating the clock generation circuit in the second, sleep mode comprises deasserting both of the first and second enable signals; and
operating the clock generation circuit in the third, standby mode comprises asserting the first enable signal and deasserting the second enable signal.
7. The method of
operating the clock generation circuit in the first, full power mode comprises providing a first bias current to the clock generation circuit;
operating the clock generation circuit in the second, sleep mode comprises providing no bias current to the clock generation circuit; and
operating the clock generation circuit in the third, standby mode comprises providing a second bias current, less than the first bias current, to the clock generation circuit.
8. The method of
0. 12. The clock generation circuit of
0. 13. The clock generation circuit of
0. 14. The clock generation circuit of
0. 15. The clock generation circuit of
0. 16. The clock generation circuit of
operate the clock generation circuit in the first, full power mode in response to both first and second enable signals received at the first and second enable inputs, respectively, being asserted;
operate the clock generation circuit in the second, sleep mode in response to both first and second enable signals being deasserted; and
operating the clock generation circuit in the third, standby mode in response to the first enable signal being asserted and the second enable signal being deasserted.
0. 17. The clock generation circuit of
operate the clock generation circuit in the first, full power mode by providing a first bias current to the clock generation circuit;
operate the clock generation circuit in the second, sleep mode by providing no bias current to the clock generator circuit; and
operate the clock generation circuit in the third, standby mode by providing a second bias current, less than the first bias current, to the clock generation circuit.
0. 18. The clock generation circuit of
0. 19. The clock generation circuit of
0. 20. The clock generation circuit of
0. 22. The clock generation circuit of claim 21 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.
0. 23. The clock generation circuit of claim 22 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.
0. 24. The clock generation circuit of claim 23 wherein, in the third standby mode, a first transistor in the current generation circuit is biased to a voltage close to its transistor operating voltage.
0. 25. The clock generation circuit of claim 23 wherein, in the first full power mode the first transistor is connected between a second transistor and a variable resistance unit and in the third standby mode the first transistor is connected between the second transistor and a plurality of diodes and wherein, in both the first full power mode and the third standby mode, the bias circuit provides a low bias current to the amplifier circuit.
0. 26. The clock generation circuit of claim 25 wherein the gate of the second transistor in the current generation circuit is connected in a current mirror arrangement to the gate of a third transistor in the integration circuit of the relaxation oscillator circuit and wherein in the first full power mode, a mirrored current is provided to a capacitor of the relaxation oscillator circuit.
0. 27. The clock generation circuit of claim 21 wherein the indication comprises a clock request and a standby signal.
0. 28. The clock generation circuit of claim 21 further comprising at least one control input to receive a clock request and a standby signal from a control unit.
0. 30. The power management unit of claim 29 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.
0. 31. The power management unit of claim 29 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.
0. 33. The wireless modem of claim 32 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.
0. 34. The wireless modem of claim 32 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.
0. 35. The wireless modem of claim 32 further comprising at least one of a digital broadband integrated circuit, a radio frequency integrated circuit, and a power amplifier.
0. 37. The wireless communication terminal of claim 36 wherein the oscillator circuit is an RC oscillator circuit and the amplifier is included in the RC oscillator circuit.
0. 38. The wireless communication terminal of claim 36 where the oscillator circuit is a relaxation oscillator circuit comprising a current generation circuit connected to an integration circuit and the amplifier is included in the current generation circuit.
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FIG. 22 is a block diagram of a wireless modem.105 106) and power and clocks are supplied. This transition (block 112 to 106) incurs a significant delay.
When it is again decided to place the system 10 in sleep mode (block 108) but a fast startup time is required (e.g., to respond to activity on an external bus, to process an incoming wireless signal, or the like), the status information (block 110) may indicate that the PMU 12 may place the clock generation circuit 14 in STANDBY mode (block 116). In STANDBY mode, the clock generation circuit 14 does not generate an output; however, a voltage is maintained on internal nodes by a small pre-bias current. Because of the pre-bias current, when a circuit 24, 26, 28 again requests a clock signal (block 118), the clock generation circuit 14 may exit STANDBY and be fully ON (block 106) and operational in a very short startup time (e.g., 1.5 usec). The fast startup time enables greater use of STANDBY mode, reducing overall power consumption.
According to embodiments of the present invention, a StandBy input signal triggers a pre-bias driver 40 to provide a lower, pre-bias current to the amplifier in the RC oscillator 30 when the oscillator 14 is in STANDBY mode. The pre-bias current keeps the amplifier charged, but is insufficient to enable oscillation. When the ClockRequest signal is asserted, full bias is established and the RC oscillator 30 starts up, quickly settling to the proper output point, generating a high quality clock signal at the correct frequency. The clock quality analyzer circuit 32 verifies this, and rapidly enables the AND gate function 34 to pass the clock signal to the output buffer 36.
Once all circuits initialize, the clock generation circuit 14 provides at least one clock signal to the SMPS 16, which provides power to circuits 24, 26, 28. The system 10 is in ACTIVE state. When operational conditions permit, for power conservation purposes the system 10 goes into SLEEP mode, and the clock generation circuit 14 is placed in STANDBY. This occurs because ClockRequest is deasserted, indicating no circuit 16, 24, 26, 28 requires clock signals. However, the StandBy signal remains asserted. This causes a pre-bias current to be applied to the RC oscillator circuit 30 within the clock generation circuit 14, almost fully charging the amplifier and maintaining the output node at near its operational voltage. When the system 10 exits SLEEP mode by again asserting ClockRequest, only a very short startup time is required to transition the clock generation circuit 14 from STANDBY to ON. This translates to a corresponding brief duration in which the system 10 transitions from SLEEP to ACTIVE mode.
The clock generation circuit 14 depicted in
A bandgap reference circuit 40 generates a reference voltage Vref, and provides it to both a scaling/buffering circuit 42 and the current generation circuit 44. The scaling and buffering circuit 42 scales and buffers the reference voltage Vref, outputting a steady threshold voltage Vth. The current generation with trimming circuit 44 generates a charging current Icharge, which charges an integration capacitor in an integration circuit 46. As indicated by the dashed-line box, the current generation circuit 44 and integration circuit 46 are tightly coupled.
The integration circuit 46 outputs a saw-tooth integrated voltage Vint, which increases as the integration capacitor charges and returns to zero when the capacitor discharges. A comparison circuit 50 compares the integrated voltage Vint to the threshold voltage Vth, and generates a reset impulse when they are equal. The reset signal is fed back to the integration circuit 46, as a trigger to discharge the integration capacitor. The integration capacitor then begins charging again to generate the next cycle. A shaping and buffering circuit 52 conditions the saw-tooth wave of the integrated voltage Vint, outputting a square clock signal Clock. The frequency of the Clock signal is determined by the threshold voltage Vth and the magnitude of the current Icharge, which directly controls the charging time of the integration capacitor.
However, the current generation circuit 44 and integration circuit 46 are not the only sources of startup transients that cause a lengthy startup time in transitioning the clock generation circuit 14 from OFF to ON.
As indicated in
In
In
In
In
In all of the embodiments described above, a clock generation circuit 14 transitions from a STANDBY mode, in which a small, pre-bias current is applied to amplifiers, to a fully ON state, with fewer transients, which quickly settle to a steady-state. Hence, the clock generation circuit 14 startup time is dramatically shorter than in prior art designs, which only transition the clock generation circuit 14 between OFF and ON states. The pre-bias current consumption in the STANDBY state is small, such as in the range of 10% of the bias current applied in the ON state. The very fast startup time allows the clock generation circuit 14 to be placed in STANDBY more often than conventional circuits, thus reducing overall power consumption, despite the small pri-bias current consumption in the STANDBY state. For example, the clock generation circuit 14 may be placed in STANDBY mode when an external bus or wireless interface is dormant, but may become active at any time, requiring e.g., the capture of burst data transfers.
The STANDBY bias current circuits disclosed herein are straightforward. As such, they are robust on silicon variation, and portable between silicon technologies. Additionally, by providing a very short startup time from STANDBY to ON, designers may optimize the ON mode power consumption and performance, without concern for startup performance.
The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.
Ruotsalainen, Tarmo, Jäntti, Joni Tuomas
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