A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.
|
0. 21. A semiconductor device comprising:
a plurality of chips each comprising:
a substrate having a first surface and a second surface opposite the first surface;
a plurality of through electrodes penetrating the substrate from the first surface to the second surface;
a test pad connected to a first through electrode of the plurality of through electrodes; and
a circuit to be tested;
wherein the plurality of chips are stacked and interconnected through the plurality of electrodes, and test access is provided to the circuit to be tested on each of the plurality of chips through the test pad on a first chip of the plurality of chips.
9. A method of producing a tested semiconductor device comprising:
forming a semiconductor device; and
testing the semiconductor device, the testing including:
stacking a first wafer onto a second wafer having the semiconductor device such that a first electrode formed on the first wafer is connected with a second electrode formed on the second wafer, the first electrode penetrating the first wafer, the second electrode penetrating the second wafer and being coupled electrically with the semiconductor device; and
supplying a test signal to the first electrode of the first wafer to input the test signal into the semiconductor device via the first electrode and the second electrode.
16. A method of producing a semiconductor device comprising:
stacking a plurality of semiconductor chips, wherein each of the plurality of semiconductor chips has already been tested by a testing method, the testing method including;
stacking a first wafer onto a second wafer comprising the semiconductor chip such that a first electrode formed on the first wafer is connected with a second electrode formed on the second wafer, the first electrode penetrating the first wafer, the second electrode penetrating the second wafer and being connected electrically with the semiconductor chip; and
supplying a test signal to the first electrode of the first wafer to input the test signal into the semiconductor chip via the first electrode and the second electrode.
1. A method of testing a semiconductor device comprising;
providing a first wafer that comprises a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode;
providing a second wafer that comprises a second electrode penetrating the second wafer;
stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer;
probing a needle to the pad; and
supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.
2. The method as claimed in
a circuit to be tested is included in the second wafer; and
the test signal is supplied to the circuit via the first electrode and the second electrode.
3. The method as claimed in
4. The method as claimed in
5. The method as claimed in
6. The method as claimed in
7. The method as claimed in
8. The method as claimed in
10. The method as claimed in
11. The method as claimed in
12. The method as claimed in
13. The method as claimed in
14. The method as claimed in
15. The method as claimed in
17. The method as claimed in
a circuit to be tested is included in the semiconductor chip of the second wafer; and
the test signal is supplied to the circuit via the first electrode and the second electrode.
18. The method as claimed in
the second wafer comprises a switch that is formed between the second electrode and the circuit; and
the switch connects the second electrode with the circuit when the circuit is under test.
19. The method as claimed in
20. The method as claimed in
0. 22. The semiconductor device as claimed in claim 21, wherein the test pad on the first chip is connected to the circuit to be tested on a second chip of the plurality of chips through a switch.
0. 23. The semiconductor device as claimed in claim 22, wherein the switch connects the test pad on the first chip to the first through electrode on the first chip.
0. 24. The semiconductor device as claimed in claim 22, wherein the switch connects the first through electrode on the second chip to the circuit to be tested on the second chip.
|
|||||||||||||||||||
The present application is a Continuation Application of U.S. patent application Ser. No. 12/656,485, filed on Feb. 1, 2010 now U.S. Pat. No. 8,243,486, which is based on Japanese patent application No. 2009-024486, filed on Feb. 5, 2009, the entire contents of which is incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device having a DRAM or the like, and particularly to a semiconductor device formed by stacking a plurality of chip dies.
2. Description of the Related Art
An example of this type of semiconductor devices is a semiconductor device in which a memory module is formed by stacking a plurality of DRAM chips on an IOIOIOIOIO I/O circuits, input/output lines, a plurality of switches (SW) connected to the input/output lines, through electrodes formed in TSV vias and connected to the respective switches, and ROMs.
On the other hand, each of the chip dies 63 on the dummy wafer 62 has TSV vias formed at the same positions as those in the chip dies on the wafer to be measured 60, and ESD protection circuits 65 at least connected to the through electrodes. Further, in the chip dies 63 on the dummy wafer 62, a pad is connected to each of the through electrodes, such that the pad comes into contact with a probing needle only during a wafer test. The chip dies 63 may be mounted with other functional circuits for conducting tests.
In order to conduct a wafer test on the chip dies 61 on the wafer, to be measured 60, as shown in
When a memory module (stacked memory device including an IO I/O chip such as a controller) is fabricated by stacking the chip dies 61 obtained from the wafer to be measured and packaging them, the chip dies are electrically connected only to the memory controller through the vias but not connected to any terminal outside the memory module. Thus, an additional advantage is provided that the human model (HM) resistance need not be taken into consideration.
It should be understood that the invention is applicable regardless of fabrication methods and configurations of the TSVs and bumps.
Furthermore, according to this invention, it is obvious that information of the ROMs for controlling the switches or the like as disclosed here, or switch controlling information replaceable with the ROMs can be supplied by the controller to each of the chip dies stacked by means of the TSV technology.
Here are exemplary aspects of this invention.
A first aspect of this invention provides a semiconductor device including a plurality of electrodes passing through a semiconductor substrate; switches connected to the respective electrodes; first signal lines each connected in common to a plurality of the switches; and first circuits connected to the respective first signal lines, wherein only one of the switches is selectively rendered electrically conductive.
In a second aspect of this invention according to the first aspect, the invention provides the semiconductor device further including ROMs which are preset to a predetermined value for selectively rendering the switches electrically conductive.
In a third aspect of this invention according to the second aspect, the invention provides the semiconductor device wherein the ROMs are set in association with groups which at least data signals of the semiconductor device belong to.
In a fourth aspect of this invention according one of the first to third aspects, the invention provides the semiconductor device further including second switches for connecting a plurality of the first signal lines to one of the first circuits.
In a fifth aspect of this invention according to the fourth aspect, the invention provides the semiconductor device further including second ROMs which are preset to a predetermined value for selectively rendering the second switches electrically conductive, wherein it is set in the second ROMs whether data is compressed or not.
In a sixth aspect of this invention according to one of the first to fifth aspects, the invention provides the semiconductor device wherein each of the first signal line has a probing terminal which is used only during probing.
In a seventh aspect of this invention according to the sixth aspect, the invention provides the semiconductor device including an ESD protection circuit connected to each of the first signal lines.
In an eighth aspect of this invention according to one of the first to sixth aspects, the invention provides the semiconductor device including ESD protection circuits respectively connected to the plurality of electrodes.
In a ninth aspect of this invention according one of the first to eighth aspects, the invention provides the semiconductor device including a third switch and a latch circuit between the switches and the ROM.
In a tenth aspect of this invention according to the ninth aspect, the invention provides the semiconductor device wherein the third switch is supplied, by a test signal, with an input of a control signal to render the third swich electrically conductive.
In an eleventh aspect of this invention according to the tenth aspect, the invention provides the semiconductor device wherein a plurality of the electrodes are connected to the first signal lines by activation of the test signal.
In a twelfth aspect of this invention according to the first aspect, the invention provides the semiconductor device including ESD protection circuits respectively connected to the plurality of electrodes, and a third switch and a latch circuit between the switches and the ROM, wherein the third switch is rendered electrically conductive by a test signal, and a plurality of the ESD circuits are connected to the first signal lines by activation of the test signal.
In a thirteenth aspect of this invention according to the first aspect, the invention provides the semiconductor device wherein each of the first circuits has a plurality of output transistors for driving the first signal lines, and a control signal is supplied to change the number of the output transistors to be activation-controlled according to the number of the semiconductor devices stacked.
In a fourteenth aspect of this invention according to the thirteenth aspect, the invention provides the semiconductor device further including a third ROM, the control signal being connected to the third ROM.
In a fifteenth aspect of this invention according to the first aspect, the invention provides the semiconductor device wherein the operating power supply voltage of the first circuits is changeable according to the number of stacked semiconductor devices.
In a sixteenth aspect of this invention according to the fifteenth embodiment, the invention provides the semiconductor device wherein each of the first circuits is a circuit for inputting and outputting stored information, and the stored information of multiple bits (I/O) is formed by a plurality of the electrodes.
In a seventeenth aspect of this invention, the invention provides a semiconductor device having a semiconductor substrate provided with a plurality of electrodes passing through the substrate, wherein the semiconductor substrate has switches connected to the respective electrodes, first signal lines each connected in common to a plurality of the switches, and first circuits connected to the respective first signal line, and is designed such that one of the plurality of the switches is selectively made electrically conductive, and wherein a plurality of the semiconductor substrates are stacked, the electrodes are connected to each other, and the switches selectively made conductive are located at mutually different positions among the semiconductor substrates.
In an eighteenth aspect of this invention according to the seventeenth aspect, the invention provides the semiconductor device wherein the electrodes connected to the respective switches made conductive at the mutually different positions form memory information of multiple bits (I/O).
In a nineteenth aspect of this invention according to the seventeenth aspect, the invention provides the semiconductor device wherein the electrodes connected to the respective switches made conductive at the mutually different positions form an activation select group (CS0, CS1 or CLK) for the semiconductor substrates.
In a twentieth aspect of this invention according to one of the seventeenth to nineteenth aspects, the invention provides the semiconductor device having a second semiconductor substrate (controller chip) for controlling a plurality of the semiconductor substrates, wherein the mutually connected electrodes of the plurality of the semiconductor substrate are connected to electrodes of the second semiconductor substrate.
In a twenty-first aspect of this invention according to the twentieth aspect, the invention provides the semiconductor device wherein the electrodes of the second semiconductor substrate are connected to external electrodes of the semiconductor device.
In a twenty-second aspect of this invention according to the twentieth or twenty-first aspect, the invention provides the semiconductor device wherein ESD circuits are respectively connected to the stacked and mutually connected electrodes.
In a twenty-third aspect of this invention according the seventeenth aspect, the invention provides the semiconductor device wherein each of the first circuits has a plurality of output transistors for driving the first signal lines, and the semiconductor device further has a control signal for changing the number of the output transistors to be activation controlled according the number of the stacked semiconductor substrates.
In a twenty-fourth aspect of this invention according to the seventeenth aspect, the invention provides the semiconductor device wherein the operating power supply voltage of the first circuits is changeable according to the number of the stacked semiconductor substrates.
Although the above description of the exemplary embodiments of the invention has been made in terms of a case in which the invention is applied to a memory module formed of a DRAM, this invention is applicable not only to DRAM (volatile memory) but also to other semiconductor devices formed by stacking chips, for example a semiconductor device formed by stacking nonvolatile memories. For example, the semiconductor device including the memory chips of the invention may include other types of chips. Such chips may, for example, be a controller chip for controlling a plurality of memory chips performing high-bandwidth data communication through the memory chips and TSVs according to this invention. Specifically, such other types of chips include a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an ASSP (Application Specific Standard Circuit) and so on. This invention is applicable in general to semiconductor products including these chips. A device to which this invention is applied is applicable to semiconductor devices such as a POP (Package on Package) or the like. Transistors used in the memory cells or logic circuits may be field effect transistors (FETs), and are applicable not only to an MOS (Metal Oxide Semiconductor) but also to various FETs such as an MIS (Metal-Insulator Semiconductor), and a TFT (Thin Film Transistor). Some of the transistors may be the types of transistors than FETs. Further, P-channel type transistors or PMOS transistors forming a so-called CMOS logic circuit are representative examples of first conduction type transistors, while N-channel type transistors or NMOS transistors are representative examples of second conduction type transistors. Further, the semiconductor substrates are not limited to P-type semiconductor substrates, but may be N-type semiconductor substrates, semiconductor substrates of an SOI (Silicon on Insulator) structure, or even other types of semiconductor substrates.
According to this invention, the degree of freedom in design can be improved by combining chip dies having the same configuration. Further, according to this invention, the data transfer speed of the memory module as a whole can be increased without the need of increasing the data transfer speed from the chip dies, which provides an advantage that the consumption current of the chip dies can be reduced. Still further, the chip dies can be operated at a low operating frequency, and thus the manufacturing yield of the chip dies can be enhanced.
| Patent | Priority | Assignee | Title |
| Patent | Priority | Assignee | Title |
| 5504369, | Jul 23 1993 | NXP, B V F K A FREESCALE SEMICONDUCTOR, INC | Apparatus for performing wafer level testing of integrated circuit dice |
| 6065143, | Dec 05 1996 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of fast testing without externally considering address scramble or data scramble |
| 6839260, | Jan 18 2000 | Hitachi, LTD | Semiconductor device having different types of memory cell arrays stacked in a vertical direction |
| 7123497, | Apr 21 2003 | Longitude Licensing Limited | Memory module and memory system |
| 7126836, | Mar 27 2003 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, system device using it, and manufacturing method of a semiconductor device |
| 20060262587, | |||
| 20070047284, | |||
| 20070153588, | |||
| 20120242346, | |||
| EP2302403, | |||
| JP2004327474, | |||
| JP2007293982, | |||
| KR20120062281, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Aug 29 2013 | PS4 LUXCO S A R L | PS5 LUXCO S A R L | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 039818 | /0506 | |
| Nov 12 2013 | PS5 LUXCO S A R L | LONGITUDE SEMICONDUCTOR S A R L | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 039793 | /0880 | |
| Aug 06 2015 | Longitude Licensing Limited | (assignment on the face of the patent) | / | |||
| Jul 31 2018 | LONGITUDE SEMICONDUCTOR S A R L | Longitude Licensing Limited | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 046864 | /0001 |
| Date | Maintenance Fee Events |
| Jan 25 2021 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Date | Maintenance Schedule |
| Feb 04 2023 | 4 years fee payment window open |
| Aug 04 2023 | 6 months grace period start (w surcharge) |
| Feb 04 2024 | patent expiry (for year 4) |
| Feb 04 2026 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Feb 04 2027 | 8 years fee payment window open |
| Aug 04 2027 | 6 months grace period start (w surcharge) |
| Feb 04 2028 | patent expiry (for year 8) |
| Feb 04 2030 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Feb 04 2031 | 12 years fee payment window open |
| Aug 04 2031 | 6 months grace period start (w surcharge) |
| Feb 04 2032 | patent expiry (for year 12) |
| Feb 04 2034 | 2 years to revive unintentionally abandoned end. (for year 12) |