Three-dimensionally stacked nonvolatile semiconductor memory

Abstract

A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

Furthermore, the coefficient B indicates the intercept of the linear function, the coefficient B is calculated by the following equation using, for example, the calculated coefficient A, the address X1 and a sample value Y1 at the address X1:
B=Y1−A×X1

Consequently, the linear function Y=AX+B as an approximation function is obtained. In addition, the coefficient B may be obtained by the following equation:
B=Y2−A×X2

Subsequently, the obtained approximation function is inspected (ST14), and the coefficients A, B of the approximation function are stored (ST15).

As described above, in the third adjustment example of the embodiment of the present invention as well, characteristic variations are represented by the approximation function, so that the characteristic variations of the memory cells can be compensated for.

Although the coefficients A, B are calculated by the two-point approximation here, the number of samples may be increased to improve accuracy.

Moreover, the example shown here illustrates one method of setting the coefficients A, B suitable for the approximation function for providing potentials suitable for the respective word lines. As long as the characteristic variations of the memory cells can be compensated for using the approximation function, the present invention is not limited to the example in FIGS. 16 and 17.

2. Modification

A modification of the embodiment of the present invention is described with FIG. 18. It should be noted that the same symbols are assigned to the same members as the members described above and such members are described as needed.

In the configurations described in the first to third adjustment examples, the internal circuits provided in the memory chip 1 such as the register circuit 33 and the potential control circuit 35 are used to adjust and set the potential provided to each of the word lines to a suitable potential. However, in the embodiment of the present invention, an instruction (command) from the controller 2 or the host 3 may be output to the memory chip 1 via the pads 11A to 11H to adjust the supply potential for each of the word lines to a potential suitable therefor.

In FIG. 18, for example, four memory chips 1 are connected in parallel to one controller 2. In this configuration, instructions for writing, erasing or reading in the memory cells in each of the memory chips 1 are given by the command issued by the controller 2. At the same time, for example, the setting and adjustment of the supply potentials described in the first to third adjustment examples may also be carried out using the I/O pin 11H and the control pins 11A to 11G so that a suitable potential is supplied to each of the selected word lines. Moreover, the write voltages of the word lines may also be adjusted by the command from the host 3.

Thus, the devices outside the memory chip 1 such as the controller 2 and the host 3 can be used to adjust the supply potential for each of the word lines.

Consequently, in the modification of the embodiment of the present invention, the characteristic variations of the memory cells can be compensated for.

3. Application

The technique of the present invention is advantageous to a BiCS-NAND flash memory in which one cell unit is composed of a plurality of serially connected memory cells (NAND strings) to achieve bit cost scalability. While one example of the BiCS-NAND flash memory has been described with FIGS. 1 to 4, the BiCS memory used in the embodiment of the present invention is not limited thereto.

For example, the embodiment of the present invention can also be applied to a BiCS-NAND flash memory shown in FIGS. 19 to 21. It should be noted that the same symbols are assigned in FIGS. 19 to 21 to members substantially similar in function to the members shown in FIGS. 1 to 4.

FIG. 19 shows a bird's-eye view of the BiCS-NAND flash memory different in configuration from the example shown in FIG. 1. FIG. 20 shows a bird's-eye view of an extraction of a block (memory cell array). Further, FIG. 21 shows an equivalent circuit diagram of one NAND cell unit provided in the block.

In the BiCS-NAND flash memory of the configuration shown in FIGS. 19 and 20 as well, three or more conductive layers made of, for example, conductive polysilicon are stacked (in this example, a six-layer structure). Further, a plurality of active layers (active areas) UAA extend through the plurality of stacked conductive layers. Moreover, a memory cell is formed at the intersection of the active layer and the conductive layer. While the lowermost one of the stacked conductive layers is plate-shaped in the BiCS-NAND flash memory shown in FIGS. 19 and 20, the other conductive layers except for the lowermost conductive layer are linearly shaped. In addition, as shown in FIG. 19, the ends of the stacked conductive layers in the x-direction are stepped to allow contact with each of these layers as in the example shown in FIG. 1.

In the BiCS-NAND flash memory shown in FIGS. 19 and 20, the plurality of active layers UAA are U-shaped when viewed from, for example, the x-direction. As shown in FIG. 20, the U-shaped active layer UAA is structured so that the lower ends of two semiconductor columns SP are connected together by a joint portion JP.

Accordingly, the source line SL is provided on the side of the semiconductor substrate 23 in the configuration shown in FIGS. 1 to 4. In contrast, in the configuration shown in FIGS. 19 to 20, a source line SL is provided in a layer higher than drain side select gate lines SGD<4>, SGD<5> which are provided on the upper end side of the active layers UAA. More specifically, in the BiCS memory shown in FIGS. 19 and 20, the source line SL is provided between a layer in which bit lines BL<0> to BL<m> are provided and a layer in which the drain side select gate lines SGD<4>, SGD<5> are provided. The source line SL extends in the x-direction, and is connected to one of the two semiconductor columns SP constituting one U-shaped active layer UAA. Further, one source line SL is shared by two NAND cell units NU adjacent in the y-direction.

Source line side select gate lines SGS<4>, SGS<5> are provided, for example, in the same layer as the bit line side select gate lines SGD<4>, SGD<5>, and are linear (straight) conductive interconnections extending in the x-direction.

In the example shown in FIGS. 19 and 20, word lines WL<0> to WL<7> are linear (straight) conductive interconnections extending in the x-direction.

Thus, in the BiCS-NAND flash memory shown in FIGS. 19 and 20, one NAND cell unit NU includes two semiconductor columns SP, so that the number of memory cells in one NAND cell unit is large (eight in this example) as shown in FIG. 21. In addition, four memory cells MC are provided in one semiconductor column SP.

As in the example shown in FIGS. 20 and 21, the joint portion JP may be connected to a back gate line BG via a back gate transistor BGTr. A conductive layer serving as the back gate line BG is located in a layer lower than a conductive layer serving as the word line, and the plane shape of the back gate line BG is in the shape of, for example, a plate two-dimensionally expanding on the semiconductor substrate 23. The back gate transistor BGTr is provided at the intersection of the joint portion JP and the plate-shaped back gate line BG. The joint portion JP serves as the channel area of the back gate transistor BGTr. The back gate transistor BGTr has, for example, the same structure as the memory cell MC. In addition, in the case of the configuration provided with the back gate line BG as in this example, the joint portion JP is not electrically connected to the semiconductor substrate 23.

Thus, the BiCS-NAND flash memory shown in FIGS. 19 to 21 also has the configuration in which the memory cells are three-dimensionally stacked, so that there are variations in element characteristics between the memory cell on the side of the select gate lines SGD<5>, SGS<5> and the memory cell on the side of the semiconductor substrate 23 (back gate line BG).

In the BiCS-NAND flash memory shown in FIGS. 19 to 21, the circuit configuration and coordination method described in the first to third adjustment examples of the embodiment of the present invention can be used to compensate for the variations in element characteristics.

In addition, in the BiCS-NAND flash memory shown in FIGS. 19 to 21, the diameters of the active layers UAA show about the same tendency (dimension) in the word lines which are provided in the same memory cell unit and which are located at the same position (height from the semiconductor substrate 23) in the z-direction, for example, the word line WL<3> and the word line WL<4>. In this case, the same common switch circuit may be used for the word line WL<3> and the word line WL<4> out of switch circuits 36A0 to 36A3 in a row decoder circuit 36A. Similarly, potentials supplied to the word lines WL<3>, WL<4> can be adjusted using about the same value, so that the same register in the register circuit 33 may be shared between the word line WL<3> and the word line WL<4>.

It goes without saying that, similarly to the two word lines WL<3>, WL<4>, the switch circuit and the register can be shared between the word line WL<2> and the word line WL<5>, between the word line WL<1> and the word line WL<6> and between the word line WL<0> and the word line WL<7> as long as the two word lines are located at the same position in the z-direction.

Thus, the embodiment of the present invention can be applied to the BiCS memory shown in FIGS. 19 to 21. Moreover, as shown in FIGS. 19 to 21, even if the number of memory cells (the number of word lines) constituting one NAND cell unit is increased, the switch circuit and the register are shared by the word lines having the same characteristic tendency, so that an increase in circuit scale can be inhibited.

However, it goes without saying that the number of registers provided in the register circuit 33 or the number of switch circuits in the row decoder circuit 36A, for example, may be changed in accordance with the number (e.g., eight) of word lines in the BiCS-NAND flash memory shown in FIGS. 19 to 21.

The embodiment of the present invention is not only applicable to the BiCS-NAND flash memories shown in FIGS. 1 to 19 but also to a three-dimensionally stacked nonvolatile semiconductor memory to which the BiCS technique is applied.

Furthermore, as the memory cell structure of the BiCS memory, a MONOS type or MNOS type structure in which a charge storage layer is made of an insulator (e.g., nitride) is considered effective. However, the present invention is not limited to this example and can also be applied to a floating gate type structure in which a charge storage layer is made of conductive polysilicon.

Moreover, a data value stored in one memory cell may be binary or multi-level equal to or more than ternary.

4. Alternatives

The trimming processing for the write potential has been mainly described in the embodiment of the present invention. However, a similar configuration and method can be employed to various potentials provided to the word line, such as a supply potential for a selected word line during reading operation, a supply potential for a nonselected word line during writing or reading operation, or a supply potential for a word line during erasing operation.

In the embodiment of the present invention, processing in the test step during the manufacture of a memory chip has been described by way of example. However, in a user service environment, the optimum value of the write voltage may change due to the deterioration of writing characteristics associated with the deterioration of memory cells. Accordingly, the present embodiment can also be applied to such a case where a potential suitably supplied to each of the word lines is reset.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims

1. A three-dimensionally stacked nonvolatile semiconductor memory comprising:

a memory cell array provided in a semiconductor substrate;

conductive layers stacked above the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another;

a bit line which is disposed above the conductive layers in such a manner as to be insulated from the conductive layers;

a semiconductor column which extends through the conductive layers and which has an upper end connected to the bit line and a lower end connected to the semiconductor substrate;

word lines for which the conductive layers except for the uppermost and lowermost conductive layers are used;

memory cells provided at intersections of word lines and the semiconductor column, respectively;

a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the word lines; and

a potential control circuit which controls the potentials supplied to the word lines and which reads the information retained in the register circuit in accordance with a position of a word line in a direction perpendicular to the surface of the semiconductor substrate and which supplies a potential suitable for the word line corresponding to an input address signal.

2. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the register circuit has registers which retain potential codes indicating the potentials suitable for the word lines, respectively, and

the potential control circuit selects the potential code corresponding to the input address signal from registers, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the selected potential code.

3. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the register circuit has

a first register which retains, as a reference code, a value indicating the potential suitable for one of the word lines, and

one or more second registers which are respectively provided to correspond to the remaining word lines except for the one word line corresponding to the reference code and which retain a difference code between the reference code and a value indicating the potential suitable for each of the remaining word lines; and

the potential control circuit selects the difference code corresponding to the input address signal from the one or more second registers, and supplies the suitable potential to a word line corresponding to the input address signal in accordance with a calculation result obtained from the selected difference code and the reference code.

4. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the register circuit has first and second registers which retain first and second coefficients of an approximation function, respectively, and

the potential control circuit uses the input address signal as a variable of the approximation function, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the approximation function using the first and second coefficients.

5. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, further comprising:

an external device which externally controls the operation of the memory cell array,

wherein the potential suitable for each of the word lines is set by an instruction from the external device.

6. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the potential control circuit has

an arithmetic unit which outputs a value indicating the potential supplied to the one word line in accordance with an output of the register circuit and the address signal,

a converter which outputs a converted value of the value indicating the potential supplied to the one word line,

a comparator which outputs a comparison value between a reference value and the converted value, and

a potential generator which generates a potential suitable for each of the word lines in accordance with the comparison value.

7. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the uppermost conductive layer is a straight first select gate line extending in a second direction intersecting with a first direction, and

the lowermost conductive layer is a plate-like second select gate line.

8. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the potential supplied to upper one of word lines is equal to or more than the potential supplied to lower one of the word lines.

9. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the memory cell has an insulating film functioning as a charge storage layer.

10. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 3, wherein

the number of bits indicating the difference value in each of the second registor is smaller than the number of bits indicating the reference value in the first registor.

11. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 3, wherein the difference code using writing operation differs from the difference code using reading operation.

12. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

at least one of the operation setting information and the information to supply a potential suitable for each of the word lines includes adjusted values in each of the word lines to supply the potential suitable for the word line, and the adjusted values are determined based on arithmetic processing for driving results of each of the word lines.

13. A semiconductor memory comprising:

a semiconductor substrate;

a stacked body disposed above the substrate, the stacked body including:

a first conductive layer disposed above the semiconductor substrate and configured as a first word line,

a second conductive layer disposed above the first conductive layer and configured as a second word line,

a third conductive layer disposed above the second conductive layer and configured as a third word line, and

a semiconductor column formed in a hole which penetrates the first conductive layer, the second conductive layer, and the third conductive layer in the stacked body, and extends in a first direction perpendicular to the semiconductor substrate;

a first storage portion which surrounds the semiconductor column, is disposed between the first conductive layer and the semiconductor column, and is configured as a first memory cell, a gate of the first memory cell being electrically connected to the first word line, wherein the first word line, the first storage portion, and a portion of the semiconductor column surrounded by the first storage portion are disposed along a second direction parallel to the semiconductor substrate;

a second storage portion which surrounds the semiconductor column, is disposed between the second conductive layer and the semiconductor column, and is configured as a second memory cell, a gate of the second memory cell being electrically connected to the second word line, wherein the second word line, the second storage portion, and a portion of the semiconductor column surrounded by the second storage portion are disposed along the second direction;

a third storage portion which surrounds the semiconductor column, is disposed between the third conductive layer and the semiconductor column, and is configured as a third memory cell, a gate of the third memory cell being electrically connected to the third word line, wherein the third word line, the third storage portion, and a portion of the semiconductor column surrounded by the third storage portion are disposed along the second direction, and wherein the first memory cell, the second memory cell, and the third memory cell are connected in series and configured as a memory string; and

a control circuit configured to perform a read operation on a condition that a first read voltage for reading first level data is applied to the first word line when the first word line is selected, a second read voltage for reading the first level data is applied to the second word line when the second word line is selected, or a third read voltage for reading the first level data is applied to the third word line when the third line is selected,

wherein the third read voltage is larger than the second read voltage, and second voltage is larger than the first read voltage, and

wherein a third diameter of the semiconductor column surrounded by the third storage portion in the second direction is larger than a second diameter of the semiconductor column surrounded by the second storage portion in the second direction, and the second diameter of the semiconductor column is larger than a first diameter of the semiconductor column surrounded by the first storage portion in the second direction.

14. The semiconductor memory according to claim 13, wherein

the control circuit is configured to perform the read operation on a condition that:

a first un-selection voltage is applied to the first word line when the second word line is selected,

a second un-selection voltage is applied to the second word line when the first word line is selected, the first un-selection voltage being different from the second un-selection voltage, and

a third un-selection voltage different from the first and second un-selection voltages is applied to the third word line when either of the first and second word lines is selected.

15. The semiconductor memory according to claim 14, wherein

the first un-selection voltage is lower than the second and third un-selection voltages.

16. The semiconductor memory according to claim 13, wherein the control circuit is configured to perform the read operation on a condition that:

a first un-selection voltage is applied to the first word line when the second word line is selected,

a second un-selection voltage is applied to the second word line when the first word line is selected, the first un-selected voltage being different from the second un-selection voltage, and

a third un-selection voltage different from the first and second un-selection voltages is applied to the third word line when either of the first and second word lines is selected.

17. The semiconductor memory according to claim 16, wherein

the first un-selection voltage is lower than the second and third un-selection voltages.

18. The semiconductor memory according to claim 13, wherein

the control circuit is configured to a perform a program operation on a condition that:

a first program voltage is applied to the first word line when the first word line is selected,

a second program voltage is applied to the second word line when the second word line is selected, the first program voltage being different from the second program voltage, and

a third program voltage different from the first and second program voltages is applied to the third word line when the third word line is selected.

19. The semiconductor memory according to claim 18, wherein

the control circuit is configured to perform the program operation on a condition that:

a first pass voltage is applied to the first word line when the second word line is selected,

a second pass voltage is applied to the second word line when the first word line is selected, the first pass voltage being different from the second pass voltage, and

a third pass voltage different from the first and second pass voltages is applied to the third word line when either of the first and second word lines is selected.

20. The semiconductor memory according to claim 13, wherein the control circuit is configured to perform a program operation on a condition that:

a first program voltage is applied to the first word line when the first word line is selected,

a second program voltage is applied to the second word line when the second word line is selected, the first program voltage being different from the second program voltage, and

a third program voltage different from the first and second program voltages is applied to the third word line when the third word line is selected.

21. The semiconductor memory according to claim 20, wherein

the control circuit is configured to perform the program operation on a condition that:

a first pass voltage is applied to the first word line when the second word line is selected,

a second pass voltage is applied to the second word line when the first word line is selected, the first pass voltage being different from the second pass voltage, and

a third pass voltage different from the first and second pass voltages is applied to the third word line when either of the first and second word lines is selected.