16K mode interleaver in a digital video broadcasting (DVB) standard

Abstract

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an orthogonal frequency division multiplexed (ofdm) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the ofdm sub-carrier signals. The interleaver memory reads-out the data symbols on to the ofdm sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application
y_q=y′_H(q) for odd symbols for q=0, . . . ,N_max−1

In other words, for even OFDM symbols the input words are written in a permutated way into a memory and read back in a sequential way, whereas for odd symbols, they are written sequentially and read back permutated. In the above case, the permutation H(q) is defined by the following table:

TABLE 1
permutation for simple case where Nmax = 4
q	0	1	2	3
H(q)	1	3	0	2

As shown in FIG. 4, the de-interleaver 340 operates to reverse the interleaving applied by the interleaver 100, by applying the same set of addresses as generated by an equivalent address generator, but applying the write-in and read-out addresses in reverse. As such, for even symbols, the write-in addresses 342 are in sequential order, whereas the read out address 344 are provided by the address generator. Correspondingly, for the odd symbols, the write-in order 346 is determined from the set of addresses generated by the address generator, whereas read out 348 is in sequential order.

Address Generation for the 16k Mode

A schematic block diagram of the algorithm used to generate the permutation function H(q) is represented in FIG. 5 for the 16k mode.

An implementation of the address generator 102 for the 16k mode is shown in FIG. 5. In FIG. 5 a linear feed back shift register is formed by thirteen register stages 200 and a xor-gate 202 which is connected to the stages of the shift register 200 in accordance with a generator polynomial. Therefore, in accordance with the content of the shift register 200 a next bit of the shift register is provided from the output of the xor-gate 202 by xoring the content of shift registers R[0], R[1], R[4], R[5], R[9], R[11] according to the generator polynomial:
R_i′[12]=R_i−1′[0]⊕ R_i−1′[1]⊕ R_i−1′[4]⊕ R_i−1′[5]⊕ R_i−1′[9]⊕ R_i−1′[11]

According to the generator polynomial a pseudo random bit sequence is generated from the content of the shift register 200. However, in order to generate an address for the 16k mode as illustrated, a permutation circuit 210 is provided which effectively permutes the order of the bits within the shift register 200 from an order

R′_i[n] to an order R_i[n] at the output of the permutation circuit 210. Thirteen bits from the output of the permutation circuit 210 are then fed on a connecting channel 212 to which is added a most significant bit via a channel 214 which is provided by a toggle circuit 218. A fourteen bit address is therefore generated on channel 212. However, in order to ensure the authenticity of an address, an address check circuit 216 analyses the generated address to determine whether it exceeds a predetermined maximum value. The predetermined maximum value may correspond to the maximum number of sub-carrier signals, which are available for data symbols within the COFDM symbol, available for the mode which is being used. However, the interleaver for the 16k mode may also be used for other modes, so that the address to generator 102 may also be used for the 2k mode, 4k mode, 8k mode, 16k mode and the 32k mode, by adjusting accordingly the number of the maximum valid address.

If the generated address exceeds the predetermined maximum value then a control signal is generated by the address check unit 216 and fed via a connecting channel 220 to a control unit 224. If the generated address exceeds the predetermined maximum value then this address is rejected and a new address regenerated for the particular symbol.

For the 16k mode, an (N_r−1) bit word R′_i is defined, with N_r=log₂ M_max, where M_max=16384 using a LFSR (Linear Feedback Shift Register). The polynomials used to generate this sequence is:
16K mode: R_i′[12]=R_i−1′[0]⊕ R_i−1′[1]⊕ R_i−1′[4]⊕R_i−1′[5]⊕R_i−1′[9]R_i−1′[11]

where i varies from 0 to M_max−1

Once one R′_i, word has been generated, the R′_i, word goes through a permutation to produce another (N_r−1) bit word called R_i. R_i is derived from R′_i by the bit permutations given as follows:

	R′i bit positions
	12	11	10	9	8	7	6	5	4	3	2	1	0
Ri bit	8	4	3	2	0	11	1	5	12	10	6	7	9
positions

Bit permutation for the 16k mode

As an example, this means that for the mode 16k, the bit number 12 of R′_i is sent in bit position number 8 of R_i.

The address H(q) is then derived from R, through the following equation:

$H\left(q\right)=\left(\mathrm{imod}2\right)·2^{N_r-1}+\sum _{j=0}^{N_r-2}{R}_i\left(j\right)·2^j$

The (i mod2)·2^Nr−1 part of the above equation is represented in FIG. 5 by the toggle block T 218.

An address check is then performed on H(q) to verify that the generated address is within the range of acceptable addresses: if (H(q)<N_max), where N_max=12096 for example in the 16k mode, then the address is valid. If the address is not valid, the control unit is informed and it will try to generate a new H(q) by incrementing the index i.

The role of the toggle block is to make sure that we do not generate an address exceeding N_max twice in a row. In effect, if an exceeding value was generated, this means that the MSB (i.e. the toggle bit) of the address H(q) was one. So the next value generated will have a MSB set to zero, insuring to produce a valid address.

The following equations sum up the overall behaviour and help to understand the loop structure of this algorithm:

$q=0;$ $\mathrm{for}\left(i=0;i<M_{\max };i=i+1\right)$ $\left\{H\left(q\right)=\left(\mathrm{imod}2\right)·2^{N_r-1}+\sum _{j=0}^{N_r-2}{R}_i\left(j\right)·2^j;\mathrm{if}\left(H\left(q\right)<N_{\max }\right)q=q+1;\right\}$

As will be explained shortly, in one example of the address generator, the above mentioned permutation code is used for generating addresses for all OFDM symbols. In another example, the permutation codes may be changed between symbols, with the effect that a set of permutation codes are cycled through for successive OFMD symbols. To this end, the control lines 108, 110 providing an indication as to whether the OFDM symbol is odd or even and the current mode are used to select the permutation code. This example mode in which a plurality of permutation codes are cycled through is particularly appropriate for the example in which the odd interleaver only is used, which will be explained later. A signal indicating that a different permutation code should be used is provided via a control channel 111. In one example the possible permutation codes are pre-stored in the permutation code circuit 210. In another example, the control unit 224 supplies the new permutation code to be used for an OFDM symbol.

Analysis Supporting the Address Generator for the 16k Mode

The selection of the polynomial generator and the permutation code explained above for the address generator 102 for the 16k mode has been identified following simulation analysis of the relative performance of the interleaver. The relative performance of the interleaver has been evaluated using a relative ability of the interleaver to separate successive symbols or an “interleaving quality”. As mentioned above, effectively the interleaving must perform for both odd and even symbols, in order to use a single interleaver memory. The relative measure of the interleaver quality is determined by defining a distance D (in number of sub-carriers). A criterion C is chosen to identify a number of sub-carriers that are at distance≤D at the output of the interleaver that were at distance≤D at the input of the interleaver, the number of sub-carriers for each distance D then being weighted with respect to the relative distance. The criterion C is evaluated for both odd and even COFDM symbols. Minimising C produces a superior quality interleaver.

$C=\sum _1^{d=D}{N}_{\mathrm{even}}\left(d\right)/d+\sum _1^{d=D}{N}_{\mathrm{odd}}\left(d\right)/d$

where: N_even(d) and N_odd(d) are number of sub-carriers in an even and odd symbol respectively at the output of the interleaver that remain within d sub-carrier spacing of each other.

Analysis of the interleaver identified above for the 16k mode for a value of D=5 is shown in FIG. 6(a) for the even COFDM symbols and in FIG. 6(b) for the odd COFDM symbol. According to the above analysis, the value of C for the permutation code identified above for the 16k mode produced a value of C=22.43, that the weighted number of sub-carriers with symbols which are separated by five or less in the output according to the above equation was 22.43.

A corresponding analysis is provided for an alternative permutation code for even COFDM symbols in FIG. 6(c) for odd COFDM symbols in FIG. 6(d). As can be seen in comparison to the results illustrated in FIGS. 6(a) and 6(b), there are more components present which represent symbols separated by small distances such as D=1, and D=2, when compared with the results shown in FIGS. 6(a) and 6(b), illustrating that the permutation code identified above for the 16k mode symbol interleaver produces a superior quality interleaver.

Alternative Permutation Codes

The following nine alternative possible codes ([a]R_i bit positions, where n=1 to 9) have been found to provide a symbol interleaver with a good quality as determined by the criterion C identified above.

	R′i bit positions
	12	11	10	9	8	7	6	5	4	3	2	1	0
[1]Ri bit	7	12	5	8	9	1	2	3	4	10	6	11	0
positions
[2]Ri bit	8	5	4	9	2	3	0	1	6	11	7	12	10
positions
[3]Ri bit	7	5	6	9	11	2	3	0	8	4	1	12	10
positions
[4]Ri bit	11	5	10	4	2	1	0	7	12	8	9	6	3
positions
[5]Ri bit	3	9	4	10	0	6	1	5	8	11	7	2	12
positions
[6]Ri bit	4	6	3	2	0	7	1	5	8	10	12	9	11
positions
[7]Ri bit	10	4	3	2	1	8	0	6	7	9	11	5	12
positions
[8]Ri bit	10	4	11	3	7	1	5	0	2	12	8	6	9
positions
[9]Ri bit	2	4	11	9	0	10	1	7	8	6	12	3	5
positions

Bit permutation for the 16k mode

Receiver

FIG. 7 provides an example illustration of a receiver which may be used with the present technique. As shown in FIG. 7, a COFDM signal is received by an antenna 300 and detected by a tuner 302 and converted into a digital form by an analogue-to-digital converter 304. A guard interval removal processor 306 removes the guard interval from a received COFDM symbol, before the data is recovered from the COFDM symbol using a Fast Fourier Transform (FFT) processor 308 in combination with a channel estimator and correction 310 in co-operation with a embedded-signalling decoding unit 311, in accordance with known techniques. The demodulated data is recovered from a mapper 312 and fed to a symbol de-interleaver 314, which operates to effect the reverse mapping of the received data symbol to regenerate an output data stream with the data de-interleaved.

The symbol de-interleaver 314 is formed from a data processing apparatus as shown in FIG. 8 with an interleaver memory 540 and an address generator 542. The interleaver memory is as shown in FIG. 4 and operates as already explained above to effect de-interleaving by utilising sets of addresses generated by the address generator 542. The address generator 542 is formed as shown in FIG. 8 and is arranged to generate corresponding addresses to map the data symbols recovered from each COFDM sub-carrier signals into an output data stream.

The remaining parts of the COFDM receiver shown in FIG. 7, including the Bit De-Interleaver 316, are provided to effect error correction decoding 318 to correct errors and recover an estimate of the source data.

One advantage provided by the present technique for both the receiver and the transmitter is that a symbol interleaver and a symbol de-interleaver operating in the receivers and transmitters can be switched between the 1k, 2k, 4k, 8k, 16k and the 32k mode by changing the generator polynomials and the permutation order. Hence the address generator 542 shown in FIG. 8 includes an input 544, providing an indication of the mode as well as an input 546 indicating whether there are odd/even COFDM symbols. A flexible implementation is thereby provided because a symbol interleaver and de-interleaver can be formed as shown in FIGS. 3 and 8, with an address generator as illustrated in either of FIG. 5. The address generator can therefore be adapted to the different modes by changing to the generator polynomials and the permutation orders indicated for each of the modes. For example, this can be effected using a software change. Alternatively, in other embodiments, an embedded signal indicating the mode of the DVB-T2 transmission can be detected in the receiver in the embedded-signalling processing unit 311 and used to configure automatically the symbol de-interleaver in accordance with the detected mode.

Optimal Use of Odd Interleavers

As shown in FIG. 4, two symbol interleaving processes, one for even COFDM symbols and one for odd COFDM symbols allows the amount of memory used during interleaving to be reduced. In the example shown in FIG. 4, the write in order for the odd symbol is the same as the read out order for the even symbol therefore, while an odd symbol is being read from the memory, an even symbol can be written to the location just read from; subsequently, when that even symbol is read from the memory, the following odd symbol can be written to the location just read from.

As mentioned above, during an experimental analysis of the performance of the interleavers (using criterion C as defined above) and for example shown in FIG. 9(a) and FIG. 9(b) it has been discovered that the interleaving schemes designed for the 2k and 8k symbol interleavers for DVB-T and the 4k symbol interleaver for DVB-H work better for odd symbols than even symbols. Thus from performance evaluation results of the interleavers, for example, as illustrated by FIGS. 9(a) and 9(b) have revealed that the odd interleavers work better than the even interleavers. This can be seen by comparing FIG. 9(a) which shows results for an interleaver for even symbols and FIG. 6(b) illustrating results for odd symbols: it can be seen that the average distance at the interleaver output of sub-carriers that were adjacent at the interleaver input is greater for an interleaver for odd symbols than an interleaver for even symbols.

As will be understood, the amount of interleaver memory required to implement a symbol interleaver is dependent on the number of data symbols to be mapped onto the COFDM carrier symbols. Thus a 16k mode symbol interleaver requires half the memory required to implement a 32k mode symbol interleaver and similarly, the amount of memory required to implement an 8k symbol interleaver is half that required to implement a 16k interleaver. Therefore a transmitter or receiver which is arranged to implement a symbol interleaver of a mode, which sets the maximum number of data symbols which can be carried per OFDM symbol, then that receiver or transmitter will include sufficient memory to implement two odd interleaving processes for any other mode, which provides half or smaller than half the number of sub-carriers per OFDM symbol in that given maximum mode. For example a receiver or transmitter including a 32k interleaver will have enough memory to accommodate two 16k odd interleaving processes each with their own 16k memory.

Therefore, in order to exploit the better performance of the odd interleaving processes, a symbol interleaver capable of accommodating multiple modulation modes can be arranged so that only an odd symbol interleaving process is used if in a mode which comprises half or less than half of the number of sub-carriers in a maximum mode, which represents the maximum number of sub-carriers per OFDM symbol. This maximum mode therefore sets the maximum memory size. For example, in a transmitter/receiver capable of the 32k mode, when operating in a mode with fewer carriers (i.e. 16k, 8k, 4k or 1k) then rather than employing separate odd and even symbol interleaving processes, two odd interleavers would be used.

An illustration of an adaptation of the symbol interleaver 33 which is shown in FIG. 3 when interleaving input data symbols onto the sub-carriers of OFDM symbols in the odd interleaving mode only is shown in FIG. 10. The symbol interleaver 33.1 corresponds exactly to the symbol interleaver 33 as shown in FIG. 3, except that the address generator 102 is adapted to perform the odd interleaving process only. For the example shown in FIG. 10, the symbol interleaver 33.1 is operating in a mode where the number of data symbols which can be carried per OFDM symbol is less than half of the maximum number which can be carried by an OFDM symbol in an operating mode with the largest number of sub-carriers per OFDM symbol. As such, the symbol interleaver 33.1 has been arranged to partition the interleaver memory 100. For the present illustration shown in FIG. 10 the interleaver memory then 100 is divided into two parts 401, 402. As an illustration of the symbol interleaver 33.1 operating in a mode in which data symbols are mapped onto the OFDM symbols using the odd interleaving process, FIG. 10 provides an expanded view of each half of the interleaver memory 401, 402. The expanded provides an illustration of the odd interleaving mode as represented for the transmitter side for four symbols A, B, C, D reproduced from FIG. 4. Thus as shown in FIG. 10, for successive sets of first and second data symbols, the data symbols are written into the interleaver memory 401, 402 in a sequential order and read out in accordance with addresses generated by the address generator 102 in a permuted order in accordance with the addresses generated by the address generator as previously explained. Thus as illustrated in FIG. 10, since an odd interleaving process is being performed for successive sets of first and second sets of data symbols, the interleaver memory must be partitioned into two parts. Symbols from a first set of data symbols are written into a first half of the interleaver memory 401, and symbols from a second set of data symbols are written into a second part of the interleaver memory 402, because the symbol interleaver is no longer able to reuse the same parts of the symbol interleaver memory as can be accommodated when operating in an odd and even mode of interleaving.

A corresponding example of the interleaver in the receiver, which appears in FIG. 8 but adapted to operate with an odd interleaving process only is shown in FIG. 11. As shown in FIG. 11 the interleaver memory 540 is divided into two halves 410, 412 and the address generator 542 is adapted to write data symbols into the interleaver memory and read data symbols from the interleaver memory into respective parts of the memory 410, 412 for successive sets of data symbols to implement an odd interleaving process only. Therefore, in correspondence with representation shown in FIG. 10, FIG. 11 shows the mapping of the interleaving process which is performed at the receiver and illustrated in FIG. 4 as an expanded view operating for both the first and second halves of the interleaving memory 410, 412. Thus a first set of data symbols are written into a first part of the interleaver memory 410 in a permuted order defined in accordance with the addresses generated by the address generator 542 as illustrated by the order of writing in the data symbols which provides a write sequence of 1, 3, 0, 2. As illustrated the data symbols are then read out of the first part of the interleaver memory 410 in a sequential order thus recovering the original sequence A, B, C, D.

Correspondingly, a second subsequent set of data symbols which are recovered from a successive OFDM symbol are written into the second half of the interleaver memory 412 in accordance with the addresses generated by the address generator 542 in a permuted order and read out into the output data stream in a sequential order.

In one example the addresses generated for a first set of data symbols to write into the first half of the interleaver memory 410 can be reused to write a second subsequent set of data symbols into the interleaver memory 412. Correspondingly, the transmitter may also reuse addresses generated for one half of the interleaver for a first set of data symbols for reading out a second set of data symbols which have been written into the second half of the memory in sequential order.

Odd Interleaver with Offset

The performance of an interleaver, which uses two odd interleavers could be further improved by using a sequence of odd only interleavers rather than a single odd only interleaver, so that any bit of data input to the interleave does not always modulate the same carrier in the OFDM symbol.

A sequence of odd only interleavers could be realised by either:

• • adding an offset to the interleaver address modulo the number of data carriers, or
  • using a sequence of permutations in the interleaver
    Adding an Offset

Adding an offset to the interleaver address modulo the number of data carriers effectively shifts and wraps-round the OFDM symbol so that any bit of data input to the interleaver does not always modulate the same carrier in the OFDM symbol. Thus the address generator, could optionally include an offset generator, which generates an offset in an address generated by the address generator on the output channel H(q).

The offset would change each symbol. For example, this offset could provide be a cyclic sequence. This cyclic sequence could be, for example, of length 4 and could consist of, for example, prime numbers. For example, such a sequence could be:

0, 41, 97, 157

Furthermore, the offset may be a random sequence, which may be generated by another address generator from a similar OFDM symbol interleaver or may be generated by some other means.

Using a Sequence of Permutations

As shown in FIG. 5, a control line 111 extends from the control unit of the address generator to the permutation circuit. As mentioned above, in one example the address generator can apply a different permutation code from a set of permutation codes for successive OFDM symbols. Using a sequence of permutations in the interleaver address generator reduces a likelihood that any bit of data input to the interleaver does not always modulate the same sub-carrier in the OFDM symbol.

For example, this could be a cyclic sequence, so that a different permutation code in a set of permutation codes in a sequence is used for successive OFDM symbols and then repeated. This cyclic sequence could be, for example, of length two or four. For the example of the 16k symbol interleaver a sequence of two permutation codes which are cycled through per OFDM symbol could be for example:

8 4 3 2 0 11 1 5 12 10 6 7 9

7 9 5 3 11 1 4 0 2 12 10 8 6

whereas a sequence of four permutation codes could be:

8 4 3 2 0 11 1 5 12 10 6 7 9

7 9 5 3 11 1 4 0 2 12 10 8 6

6 11 7 5 2 3 0 1 10 8 12 9 4

5 12 9 0 3 10 2 4 6 7 8 11 1

The switching of one permutation code to another could be effected in response to a change in the Odd/Even signal indicated on the control channel 108. In response the control unit 224 changes the permutation code in the permutation code circuit 210 via the control line 111.

For the example of a 1k symbol interleaver, two permutation codes could be:

4 3 2 1 0 5 6 7 8

3 2 5 0 1 4 7 8 6

whereas four permutation codes could be:

4 3 2 1 0 5 6 7 8

3 2 5 0 1 4 7 8 6

7 5 3 8 2 6 1 4 0

1 6 8 2 5 3 4 0 7

Other combinations of sequences may be possible for 2k, 4k and 8k carrier modes or indeed 0.5k carrier mode. For example, the following permutation codes for each of the 0.5k, 2k, 4k and 8k provide good de-correlation of symbols and can be used cyclically to generate the offset to the address generated by an address generator for each of the respective modes:

2k Mode:

0 7 5 1 8 2 6 9 3 4*

4 8 3 2 9 0 1 5 6 7

8 3 9 0 2 1 5 7 4 6

7 0 4 8 3 6 9 1 5 2

4k Mode:

7 10 5 8 1 2 4 9 0 3 6**

6 2 7 10 8 0 3 4 1 9 5

9 5 4 2 3 10 1 0 6 8 7

1 4 10 3 9 7 2 6 5 0 8

8k Mode:

5 11 3 0 10 8 6 9 2 4 1 7*

10 8 5 4 2 9 1 0 6 7 3 11

11 6 9 8 4 7 2 1 0 10 5 3

8 3 11 7 9 1 5 6 4 0 2 10

For the permutation codes indicated above, the first two could be used in a two sequence cycle, whereas all four could be used for a four sequence cycle. In addition, some further sequences of four permutation codes, which are cycled through to provide the offset in an address generator to produce a good de-correlation in the interleaved symbols (some are common to the above) are provided below:

0.5k Mode:

3 7 4 6 1 2 0 5

4 2 5 7 3 0 1 6

5 3 6 0 4 1 2 7

6 1 0 5 2 7 4 3

2k Mode:

0 7 5 1 8 2 6 9 3 4*

3 2 7 0 1 5 8 4 9 6

4 8 3 2 9 0 1 5 6 7

7 3 9 5 2 1 0 6 4 8

4k Mode:

7 10 5 8 1 2 4 9 0 3 6**

6 2 7 10 8 0 3 4 1 9 5

10 3 4 1 2 7 0 6 8 5 9

0 8 9 5 10 4 6 3 2 1 7

8k Mode:

5 11 3 0 10 8 6 9 2 4 1 7*

8 10 7 6 0 5 2 1 3 9 4 11

11 3 6 9 2 7 4 10 5 1 0 8

10 8 1 7 5 6 0 11 4 2 9 3

* these are the permutations in the DVB-T standard

** these are the permutations in the DVB-H standard

Examples of address generators, and corresponding interleavers, for the 2k, 4k and 8k modes are disclosed in European patent application number 04251667.4, which corresponds to U.S. Patent Application Publication No. 2008/298487, the contents of which are incorporated herein by reference. An address generator for the 0.5k mode are disclosed in our co-pending UK patent application number 0722553.5. Various modifications may be made to the embodiments described above without departing from the scope of the present invention. In particular, the example representation of the generator polynomial and the permutation order which have been used to represent aspects of the invention are not intended to be limiting and extend to equivalent forms of the generator polynomial and the permutation order.

As will be appreciated the transmitter and receiver shown in FIGS. 1 and 7 respectively are provided as illustrations only and are not intended to be limiting. For example, it will be appreciated that the position of the symbol interleaver and the de-interleaver with respect, for example to the bit interleaver and the mapper can be changed. As will be appreciated the effect of the interleaver and de-interleaver is un-changed by its relative position, although the interleaver may be interleaving I/Q symbols instead of v-bit vectors. A corresponding change may be made in the receiver. Accordingly the interleaver and de-interleaver may be operating on different data types, and may be positioned differently to the position described in the example embodiments.

As explained above the permutation codes and generator polynomial of the interleaver, which has been described with reference to an implementation of a particular mode, can equally be applied to other modes, by changing the predetermined maximum allowed address in accordance with the number of sub-carriers for that mode.

As mentioned above, embodiments of the present invention find application with DVB standards such as DVB-T, DVB-T2 (published as EN 302 755) and DVB-H (published as ETSI EN 302 304 V 1.1.1 (November 2004)), which are incorporated herein by reference. For example embodiments of the present invention may be used in a transmitter or receiver operating in accordance with the DVB-H standard, in hand-held mobile terminals. The mobile terminals may be integrated with mobile telephones (whether second, third or higher generation) or Personal Digital Assistants or Tablet PCs for example. Such mobile terminals may be capable of receiving DVB-H or DVB-T compatible signals inside buildings or on the move in for example cars or trains, even at high speeds. The mobile terminals may be, for example, powered by batteries, mains electricity or low voltage DC supply or powered from a car battery. Services that may be provided by DVB-H may include voice, messaging, internet browsing, radio, still and/or moving video images, television services, interactive services, video or near-video on demand and option. The services might operate in combination with one another. In other examples embodiments of the present invention finds application with the DVB-T2 standard as specified in accordance with ETSI standard EN 302 755. In other examples embodiments of the present invention find application with the cable transmission standard known as DVB-C2. However, it will be appreciated that the present invention is not limited to application with DVB and may be extended to other standards for transmission or reception, both fixed and mobile.

Claims

1. A data processing apparatus configured to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an orthogonal frequency division multiplexed (ofdm) symbol, the data processing apparatus comprising:

an interleaver configured to read-into a memory the predetermined number of data symbols for mapping onto the ofdm sub-carrier signals, and to read-out of the memory the data symbols for the ofdm sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and

an address generator configured to generate the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising:

a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,

a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the ofdm subcarriers, and

a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein #13# #14# the predetermined maximum valid address is approximately sixteen thousand,

the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of r_i′[12]=R_i−1′[0]⊕ r_i−1′[1]⊕ r_i−1′[4]⊕ r_i−1′[5]⊕ r_i−1′[9]⊕ r_i−1′[11], and the permutation order forms, with an additional bit, a fourteen bit address r_i[n] for the i-th data symbol from the bit present in the n-th register stage r_i′[n] in accordance with a code defined by the table:

2. The data processing apparatus as claimed in claim 1, wherein the predetermined maximum valid address is a value substantially between twelve thousand and sixteen thousand three hundred and eighty four.

3. The data processing apparatus as claimed in claim 1, wherein the ofdm symbol includes pilot sub-carriers, which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the ofdm symbol.

4. The data processing apparatus as claimed in claim 1, wherein the interleaver memory is configured to effect the mapping of the input data symbols onto the sub-carrier signals for even ofdm symbols by reading in the data symbols according to the set of addresses generated by the address generator and reading out in a sequential order, and for odd ofdm symbols by reading in the symbols into the memory in a sequential order and reading out the data symbols from the memory in accordance with the set of addresses generated by the address generator.

5. The data processing apparatus as claimed claim 1, wherein the permutation circuit is configured to change the permutation code, which permutes the order of the bits of the register stages to form the addresses from one ofdm symbol to another.

6. The data processing apparatus as claimed in claim 5, wherein the permutation circuit is configured to cycle through a sequence of different permutation codes for successive ofdm symbols.

7. The data processing apparatus as claimed in claim 6, wherein the sequence of permutation codes comprises two permutation codes, which are

8. The data processing apparatus as claimed in claim 5, wherein for both odd ofdm symbols and even ofdm symbols the interleaver is configured to read-into the memory the predetermined number of data symbols for mapping onto the ofdm sub-carrier signals in a sequential order, and to read-out of the memory the data symbols for the ofdm sub-carriers to effect the mapping according to the set of addresses generated by the address generator.

9. A transmitter for transmitting data using orthogonal frequency division Multiplexing (ofdm), the transmitter including the data processing apparatus according to claim 1.

10. The transmitter as claimed in claim 9, wherein the transmitter is configured to transmit data in accordance with a Digital Video Broadcasting standard such as including the Digital Video Broadcasting-Terrestrial standard, the Digital Video Broadcasting-Handheld standard, or the Digital Video Broadcasting-Terrestrial2 standard.

11. A method of mapping input symbols to be communicated onto a predetermined number of sub-carrier signals of an orthogonal frequency division multiplexed (ofdm) symbol, the method comprising;

reading-into a memory the predetermined number of data symbols for mapping onto the ofdm sub-carrier signals,

reading-out of the memory the data symbols for the ofdm sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and

generating the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the generating the set of addresses comprising:

using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial,

using a permutation circuit configured to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and #13# #14# re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein

the predetermined maximum valid address is approximately sixteen thousand,

the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of r_i′[12]=R_i−1′[0]⊕ r_i−1′[1]⊕ r_i−1′[4]⊕ r_i−1′[5]⊕ r_i−1′[9]⊕ r_i−1′[11], and the permutation order forms, with an additional bit, a fourteen bit address r_i[n] for the i-th data symbol from the bit present in the n-th register stage r_i′[n] in accordance with a code defined by the table:

12. The method as claimed in claim 11, wherein the predetermined maximum valid address is a value substantially between twelve thousand and sixteen thousand three hundred and eighty four.

13. The method as claimed in claim 11, wherein the ofdm symbol includes pilot sub-carriers, which are arranged to carry known symbols, and the predetermined maximum valid address depends on a number of the pilot sub-carrier symbols present in the ofdm symbol.

14. The method as claimed in claim 11, wherein the using a permutation circuit to receive the content of the shift register stages and permuting the bits present in the register stages in accordance with a permutation code to form an address, includes changing the permutation code, which permutes the order of the bits of the register stages to form the addresses, from one ofdm symbol to another.

15. The method as claimed in claim 14, wherein the changing the permutation code, which permutes the order of the bits of the register stages to form the addresses, from one ofdm symbol to another includes cycling through a sequence of different permutation codes for successive ofdm symbols.

16. The method as claimed in claim 15, wherein the sequence of permutation codes comprises two permutation codes, which are

17. The method as claimed in claim 14, wherein the reading-into the memory the predetermined number of data symbols from the ofdm sub-carrier signals, includes for both odd ofdm symbols and even ofdm symbols reading in the data symbols into the memory the predetermined number of data symbols for mapping onto the ofdm sub-carrier signals in a sequential order, and the reading-out of the memory the data symbols for the ofdm sub-carriers, includes for both odd ofdm symbols and even ofdm symbols reading-out of the memory the data symbols for the ofdm sub-carriers to effect the mapping according to addresses generated by the address generator.

18. A method of transmitting data symbols via a predetermined number of sub-carrier signals of an orthogonal frequency division multiplexed (ofdm) symbol, the method comprising;

receiving a predetermined number of data symbols for mapping onto the predetermined number of sub-carrier signals,

reading-into a memory the predetermined number of data symbols for mapping onto the ofdm sub-carrier signals,

reading-out of the memory the data symbols for the ofdm sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and

generating the set of addresses, an address being generated for each of the input symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the generating the set of addresses comprising:

using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial, #13# #14# using a permutation circuit configured to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and

re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein

the predetermined maximum valid address is approximately sixteen thousand,

the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of r_i′[12]=R_i−1′[0]⊕ r_i−1′[1]⊕ r_i−1′[4]⊕ r_i−1′[5]⊕ r_i−1′[9]⊕ r_i−1′[11], and the permutation order forms, with an additional bit, a fourteen bit address r_i[n] for the i-th data symbol from the bit present in the n-th register stage r_i′[n] in accordance with a code defined by the table:

19. An address generator for use with transmission of data symbols interleaved onto sub-carriers of an orthogonal frequency division multiplexed symbol, the address generator being configured to generate a set of addresses, each address being generated for each of the data symbols to indicate one of the sub-carrier signals onto which the data symbol is to be mapped, the address generator comprising:

a linear feedback shift register including a predetermined number of register stages and being configured to generate a pseudo-random bit sequence in accordance with a generator polynomial,

a permutation circuit configured to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address, and

a control unit configured in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein

the predetermined maximum valid address is approximately sixteen thousand,

the linear feedback shift register has thirteen register stages with a generator polynomial for the linear feedback shift register of r #13# i #14# ′[12]=R_i−1′[0]⊕ r_i−1′[1]⊕ r_i−1′[4]⊕ r_i−1′[5]⊕ r_i−1′[9]⊕ r_i−1′[11], and the permutation order forms, with an additional bit, a fourteen bit address r_i[n] for the i-th data symbol from the bit present in the n-th register stage r_i′[n] in accordance with the table:

20. A data processing apparatus configured to map symbols received from sub-carrier signals of an orthogonal frequency division multiplexed (ofdm) symbol into an output symbol stream, the data processing apparatus comprising:

de-interleaver circuitry configured to read, into a memory, data symbols from the ofdm sub-carrier signals, and to read out of the memory the data symbols into the output symbol stream to effect the mapping, the read out being in a different order than the read in, the order being determined from a set of addresses, so that the data symbols are de-interleaved from the ofdm sub-carrier signals, and

address generating circuitry configured to generate the set of addresses, an address being generated for each of the received data symbols to indicate the ofdm sub-carrier signal from which the received data symbol is to be mapped into the output symbol stream, wherein

the address generating circuitry is further configured to form an address comprising 14 bits with an offset, when a maximum valid address is approximately sixteen thousand for a 16k mode, and

the address generating circuitry is further configured to generate a first 13 bits of the 14 bits in accordance with a first generator polynomial being R′ #13# i #14# [12]=R′_i−1[0] ⊕ R′_i−1[1] ⊕ R′_i−1[4] ⊕ R′_i−1[5] ⊕ R′_i−1[9] ⊕ R′_i−1[11], with a fourteenth bit of the 14 bits being a toggle bit.

21. The data processing apparatus as claims in claim 20, wherein the address generating circuitry is further configured to regenerate an address when the generated address exceeds the maximum valid address.

22. The data processing apparatus as claimed in claim 20, wherein the address generating circuitry is further configured to determine the offset based on a random sequence.

23. The data processing apparatus as claimed in claim 20, wherein a number of the sub-carrier signals is in accordance with one of a plurality of modes including an 8k mode, the 16k mode and a 32k mode; and

the address generating circuitry is further configured to determine the offset in accordance with a generator polynomial to be used with one of the plurality of modes.

24. The data processing apparatus as claimed in claim 20, wherein the address generating circuitry is further configured to generate the first 13 bits of the 14 bits in accordance with a first permutation and a second permutation.

25. The data processing apparatus as claimed in claim 24, wherein the first permutation and the second permutation are defined according to a table:

26. The data processing apparatus as claimed in claim 24, wherein the first permutation and the second permutation are changed from one symbol to another.

27. A receiver configured to receive data using orthogonal frequency division Multiplexing (ofdm), the receiver comprising:

the data processing apparatus of claim 20; and

a recovering circuit configured to correct errors and recover an estimate of source data.

28. A method of mapping symbols received from sub-carrier signals of an orthogonal frequency division multiplexed (ofdm) symbol into an output symbol stream, the method comprising:

de-interleaving by reading into a memory data symbols from the ofdm sub-carrier signals, and reading out of the memory the data symbols into the output symbol stream to effect the mapping, the reading out being in a different order than the reading in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the ofdm sub-carrier signals, and

generating the set of addresses, an address being generated for each of the received data symbols to indicate the ofdm sub-carrier signal from which the received data symbol is to be mapped into the output symbol stream, wherein the generating includes

forming an address comprising 14 bits with an offset when a maximum valid address is approximately sixteen thousand for a 16k mode, and

generating the first 13 bits of the 14 bits in accordance with a first generator polynomial being R′_{i #13# [12]=R′ #14# i−1}[0] ⊕ R′_i−1[1] ⊕ R′_i−1[4] ⊕ R′_i−1[5] ⊕ R′_i−1[9] ⊕ R′_i−1[11], with the fourteenth bit of the 14 bits being a toggle bit.

29. The method of claim 28, wherein the generating of the set of addresses comprises regenerating an address when the generated address exceeds the maximum valid address.

30. The method of claim 28, wherein the offset is determined based on a random sequence.

31. The method of claim 28, wherein a number of the sub-carrier signals is in accordance with one of a plurality of modes including an 8k mode, the 16k mode and a 32k mode; and

the generating of the set of addresses comprises determining the offset in accordance with a generator polynomial to be used with one of the plurality of modes.

32. The method of claim 28, wherein the generating of the set of addresses comprises generating the first 13 bits of the 14 bits in accordance with a first permutation and a second permutation.

33. The method of claim 32, wherein the first permutation and the second permutation are defined according to a table:

34. The method of claim 32, wherein the first permutation and the second permutation are changed from one symbol to another.

35. The method of claim 28, further comprising:

correcting errors and recovering an estimate of source data.