Nonvolatile semiconductor memory device and method for driving same

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

Description

(Reading Operation)

A reading operation in which the data written to any of the memory transistors 35 is read will now be described. As illustrated in FIG. 7, the drive circuit 41 applies the ON potential V_on to the back gate BG, and the back gate transistors 37 are switched to the ON state. The drive circuit 41 applies the ON potential V_on (e.g., 3.0 V) to the selection gate electrodes SGs and SGb of the selected strings, and the selection transistors 36 are switched to the ON state. On the other hand, the drive circuit 41 applies the OFF potential V_off (e.g., 0 V) to the selection gate electrodes SGs and SGb of the unselected memory strings 38, and the selection transistors 36 are switched to the OFF state.

The drive circuit 41 applies a potential to the control gate electrode CG of the selected cells, i.e., the control gate electrode CGb of the third layer from the bottom, such that the conducting state differs due to the value of the selected cells. The potential is, for example, the reference potential Vss (e.g., 0 V) and is a potential such that a current does not flow in the body in the case where the value of the selected cell is “0,” i.e., when electrons are stored in the charge storage film 26 and the threshold is shifted to positive, and a current flows in the body in the case where the value of the selected cell is “1,” i.e., when electrons are not stored in the charge storage film 26 and the threshold is not shifted. For the memory transistors 35 other than those of the selected cells, a reading potential V_read (e.g., 4.5 V) is applied to the control gate electrodes thereof such that the memory transistors 35 are switched to the ON state regardless of the values thereof.

In this state, a potential Vb1 (e.g., 0.7 V) is applied to each of the bit lines BL, and the reference potential Vss (e.g., 0 V) is applied to each of the source lines SL. As a result, a current flows in the selected string if the value of the selected cell is “1” and a current does not flow in the selected string if the value of the selected cell is “0.” Accordingly, the value of the selected cell can be read by detecting the current flowing in the source line SL from the bit line BL via the selected string or by detecting the potential drop of the bit line BL. For example, because the potential of the bit line BL changes when the value of the selected cell is “1,” the change is amplified by a bit line amplifier circuit (not illustrated) and detected; and the detection result is stored as data in a data buffer (not illustrated). For the unselected memory strings 38, a current does not flow regardless of the values stored in the memory transistors 35 because the selection transistors 36 are in the OFF state.

In this embodiment, the drive circuit 41 varies the value of the reading potential V_read by the level where the control gate electrode CG to which the potential is to be applied is disposed using the pump circuit 45. In other words, as illustrated in FIG. 8, the value of the reading potential V_read applied to the control gate electrode CG4 of the uppermost level, i.e., the 4th level from the bottom, is set to be (V_read0); the value of the reading potential V _read applied to the control gate electrode CG3 of the third level from the bottom is set to be (V_read0−ΔV_read1) which is lower than (V_read0); the value of the reading potential V_read applied to the control gate electrode CG2 of the 2nd level from the bottom is set to be (V_read0−ΔV_read2) which is lower than (V_read0−ΔV_read1); and the value of the reading potential V_read applied to the control gate electrode CG1 of the lowermost level is set to be (V_read0−ΔV_read3) which is lower than (V_read0−ΔV_read2). Here, 0<ΔV_read1<ΔV_read2<ΔV_read3.

As described above, supposing that the same potential is applied to each of the control gate electrodes CG, the intensity of the electric field applied to the tunneling film 27 of each of the memory transistors increases as the through-hole 21 diameter decreases. In the case where the electric field applied to the tunneling film 27 during the reading operation is too strong, electron current undesirably flows in the tunneling film 27 due to tunneling; and a phenomenon (read disturbance) occurs in which the value “0” written to the memory transistor undesirably changes to the value “1.”

Therefore, in this embodiment as described above, the reading potential V_read has a lower potential as the control gate electrode CG is positioned lower with a smaller through-hole 21 diameter. Thereby, the increase of the electric field intensity caused by smaller through-hole 21 diameters is canceled by reducing the reading potential V_read; and the electric field intensity applied to the tunneling film 27 is made to be uniform. As a result, read disturbance of the memory transistor can be prevented. It is favorable for the value of the reading potential V_read to be determined according to Formula 1 recited above for reasons similar to those of the case of the writing operation described above.

(Erasing Operation)

An erasing operation in which data written to the memory transistor is erased will now be described. The unit of erasing data is by block. As illustrated in FIG. 7, the drive circuit 41 applies the ON potential V_on to the back gate BG, and the back gate transistors 37 are switched to the ON state. The reference potential Vss (e.g., 0 V) is applied to all of the control gate electrodes CG of the block to be erased (hereinbelow referred to as “selected block”). The potentials of the bit lines BL and the source lines SL are increased to an erasing potential V_erase (e.g., 15 V). Also, the selection gate potential V_sg which is lower than the erasing potential V_erase is applied to the selection gate electrodes SGb and SGs. That is, V_sg<V_erase.

Thereby, the potential of the bit lines BL and the source lines SL is the erasing potential V_erase (e.g., 15 V), and the potential of the selection gate electrodes SGb and SGs is the selection gate potential V_sg. Therefore, a hole current is produced by tunneling between bands due to the potential difference between the bit lines BL and the selection gate electrodes SGb and the potential difference between the source lines SL and the selection gate electrodes SGs; and the potential of the silicon pillars 31, i.e., the body potential, increases. On the other hand, the reference potential Vss (e.g., 0 V) is applied to the control gate electrodes CG of the block to be erased (the selected block). Therefore, holes are injected into the charge storage films 26 of the memory transistors 35 due to the potential difference between the silicon pillars 31 and the control gate electrodes CG, and electrons in the charge storage film 26 undergo pair annihilation. As a result, the data is erased. Although it is necessary to provide a potential difference between the erasing potential V_erase and the selection gate potential V_sg sufficient to inject sufficient holes into the charge storage film 26 because the body potential increases due to the injection of the hole current, it is simultaneously necessary to adjust such that the gate insulating film 28 of the selection transistor 36 is not destructed by an excessive potential difference.

On the other hand, for the blocks not to be erased (the unselected blocks), the potential of the selection gate electrodes SGb and SGs is increased to a potential approaching the potential of the bit lines BL and the source lines SL, and the electric field between a diffusion layer connected to the bit lines BL or the source lines SL and the selection gate electrodes SGb or SGs is reduced so that a hole current is not produced. Or, the potential of the control gate electrodes CG is increased simultaneously with that of the silicon pillars 31 so that holes in the silicon pillars 31 are not injected into the charge storage films 26. Thereby, the values already written to the memory transistors 35 of the unselected blocks are maintained as-is.

In the erasing operation as well, when the drive circuit 41 supplies a higher potential as the reference potential Vss as the control gate electrode CG is disposed lower, the potential difference between the silicon pillar 31 and the control gate electrode CG decreases as the memory transistor is disposed lower; and the electric field applied to the ONO film 24 can be uniform. Thereby, the application of an excessive electric field to the memory transistors having small through-hole diameters and the injection of electrons from the control gate electrode CG into the charge storage film 26 due to tunneling during the erasing operation can be prevented. As a result, the undesirable cancellation of the injection of the holes necessary for the erasing operation, that is, the hole injection from the silicon pillar 31 toward the charge storage film 26, by the reverse injection of electrons from the control gate electrode CG toward the charge storage film 26 is prevented; and the erasing operation can be implemented reliably.

Effects of this embodiment will now be described.

According to this embodiment as described above, the drive circuit 41 includes the multiple pump circuits 45; and each of the pump circuits 45 is connected to the control gate electrodes CG of each of the levels via each of the switch elements 47. Thereby, mutually different driving potentials can be applied to the control gate electrodes CG of each of the levels. Thereby, the potential difference between the control gate electrode CG and the silicon pillar 31 can be reduced as the memory transistor is positioned lower and has a smaller through-hole 21 diameter; and the electric field intensity applied to the ONO films 24 of the memory transistors can be uniform. As a result, misoperation of the memory transistor can be prevented. Great effects can be obtained by applying such technology to at least one operation selected from the writing operation, the reading operation, and the erasing operation when supplying the potential to the control gate electrode to provide the greatest potential difference with the silicon pillar of the operation.

A second embodiment will now be described.

FIG. 10 schematically illustrates features of a nonvolatile semiconductor memory device according to this embodiment.

In this embodiment as illustrated in FIG. 10, the through-hole has a two-level configuration. In each level, the through-hole becomes finer downward. In other words, the stacked body ML is made of two partial stacked bodies ML1 and ML2 arranged in the Z direction; and the partial stacked body ML2 is stacked on the partial stacked body ML1. Multiple insulating films 15 and multiple electrode films 14 are stacked in each of the partial stacked bodies ML1 and ML2. Each of a lower portion 21a of the through-hole 21 made in the partial stacked body ML1 and an upper portion 21b made in the partial stacked body ML2 have a tapered configuration that becomes finer downward. Therefore, the upper end portion of the lower portion 21a is wider than the lower end portion of the upper portion 21b; and a step is formed in the inner face of the through-hole 21 at the boundary portion between the lower portion 21a and the upper portion 21b.

The drive circuit 41 applies potentials to the multiple electrode films 14 disposed in the partial stacked body ML1 such that the potential difference with the silicon pillar 31 decreases as the electrode film 14 is disposed lower, that is, toward the silicon substrate 11 side. Similarly, the drive circuit 41 applies potentials to the multiple electrode films 14 disposed in the partial stacked body ML2 such that the potential difference with the silicon pillar 31 decreases as the electrode film 14 is disposed lower. Thereby, in this embodiment as well, the fluctuation of the electric field intensity caused by the fluctuation of the through-hole 21 diameter can be compensated by varying the driving potential; and the electric field intensities applied to the ONO films 24 of the memory transistors 35 can be uniform. As a result, the misoperation of the memory transistor can be prevented. Otherwise, the configuration, operations, and effects of this embodiment are similar to those of the first embodiment described above.

Three or more levels of partial stacked bodies may be stacked. In such a case, it is sufficient for the drive circuit 41 to apply the potential to the electrode film 14 (the control gate electrode CG) disposed in each of the partial stacked bodies such that the potential difference with the silicon pillar 31 decreases as the electrode film is disposed lower.

A third embodiment of the invention will now be described.

This embodiment is an embodiment of a method for manufacturing the nonvolatile semiconductor memory device 1 according to the first embodiment described above.

FIG. 11 to FIG. 19 are cross-sectional views of processes, illustrating the method for manufacturing the nonvolatile semiconductor memory device according to this embodiment.

FIG. 11 to FIG. 19 illustrate the same cross section as that of FIG. 3.

First, as illustrated in FIG. 11, the silicon substrate 11 is prepared. A memory cell region is set in the silicon substrate 11. A peripheral circuit region (not illustrated) is set around the memory cell region. An element separation film is formed in a prescribed region of the upper layer portion of the silicon substrate 11. Then, a thick film gate insulating film for high breakdown voltage transistors and a thin film gate insulating film for low breakdown voltage transistors are made separately in the peripheral circuit region. At this time, the insulating film 10 is formed on the silicon substrate 11 also in the memory cell region.

Then, the polysilicon film 12 is deposited on the insulating film 10 as a conductive film with a thickness of, for example, 200 nm. Photolithography and RIE (Reactive Ion Etching) are performed on the upper layer portion of the polysilicon film 12 in the memory cell region to make multiple trenches 52 having rectangular configurations aligned in the Y direction on the upper face of the polysilicon film 12. The trenches 52 are arranged in a matrix configuration along the X direction and the Y direction. The trenches 52 are recesses made in the upper face of the polysilicon film 12.

Continuing as illustrated in FIG. 12, a silicon nitride film is deposited by, for example, CVD (Chemical Vapor Deposition) to form a sacrificial film 53 on the polysilicon film 12. At this time, the sacrificial film 53 also is filled into the trenches 52. Then, the sacrificial film 53 and the polysilicon film 12 are patterned by, for example, photolithography and RIE. Thereby, the polysilicon film 12 in the memory cell region is divided for every block 50 (referring to FIG. 5); the back gates BG made of the polysilicon film 12 are formed in flat-plate configurations in each of the blocks 50; and gate electrodes made of the polysilicon film 12 are formed in the peripheral circuit region.

Subsequently, a spacer made of silicon oxide is formed and a diffusion layer is formed by ion implantation in the peripheral circuit region. Then, an inter-layer insulating film is deposited in the peripheral circuit region, planarized, and recessed so that the upper face thereof is the same height as the upper face of the polysilicon film 12. Then, the sacrificial film 53 is recessed so that the sacrificial film 53 is removed from the polysilicon film 12 and left only in the interiors of the trenches 52.

Continuing as illustrated in FIG. 13, the insulating films 15 made of, for example, silicon oxide are deposited alternately with the electrode films 14 made of, for example, polysilicon on the back gate BG (the polysilicon film 12) in the memory cell region to form the stacked body ML.

Then, as illustrated in FIG. 14, the multiple through-holes 21 are collectively made in the stacked body ML by dry etching such as RIE to align in the Z direction. The through-holes 21 are arranged in a matrix configuration along the X direction and the Y direction. Also, the bottom portions of the through-holes 21 reach both end portions of the sacrificial films 53 filled into the trenches 52. Thereby, two through-holes 21 adjacent to each other in the Y direction reach each of the sacrificial films 53. The through-hole 21 has a circular configuration as viewed from the Z direction. At this time, the inner side face of the through-hole 21 unavoidably has a tapered configuration inclined with respect to the Z direction. As a result, the through-hole 21 is made in an inverted circular-conic trapezoidal configuration becoming finer downward such that the upper end portion is the widest.

Continuing as illustrated in FIG. 15, wet etching is performed via the through-holes 21 to remove the sacrificial film 53 (referring to FIG. 14) from the trenches 52. Thereby, the trench 52 becomes the communicating hole 22; and one continuous U-shaped hole 23 is formed of the communicating hole 22 and the two through-holes 21 communicating with both end portions thereof.

Then, as illustrated in FIG. 16, a barrier film (not illustrated) made of, for example, silicon nitride is formed; and subsequently, a silicon oxide film, a silicon nitride film, and a silicon oxide film are continuously deposited. Thereby, the blocking film 25 made of the silicon oxide film, the charge storage film 26 made of the silicon nitride film, and the tunneling film 27 made of the silicon oxide film are stacked in this order on the inner face of the U-shaped hole 23 via the barrier film to form the ONO film 24.

Then, amorphous silicon is deposited on the entire surface. Thereby, amorphous silicon is filled into the U-shaped hole 23 to form the U-shaped silicon member 33. The U-shaped silicon member 33 is formed from the pair of silicon pillars 31 filled into the through-holes 21 and the one connection member 32 filled into the communicating hole 22. Subsequently, the amorphous silicon, the silicon oxide film, the silicon nitride film, and the silicon oxide film deposited on the stacked body ML are removed.

Continuing as illustrated in FIG. 17, the stacked body ML is patterned by, for example, RIE to make trenches 54 in the stacked body ML. The trench 54 is made to align in the X direction to link the regions between the two silicon pillars 31 connected to the connection member 32 and reach the insulating film 15 of the lowermost layer.

At this time, as illustrated in FIG. 5, the trenches 54 are made to divide the electrode films 14 into a pair of mutually meshed comb-shaped patterns. In other words, the trenches 54 are made in the X-direction central portion of the stacked body ML to align in the X direction. Thereby, the electrode films 14 are divided into multiple control gate electrodes CG aligned in the X direction. At this time, the trenches 54 are not made in the regions directly above the regions between the connection members 32 in the Y direction. Thereby, each of the control gate electrodes CG is pierced by two of the silicon pillars 31 arranged along the Y direction. At both X-direction end portions of the stacked body ML, the trenches 54 are not aligned in the X direction and are made to align intermittently in the Y direction. Thereby, the control gate electrodes CGb and CGs alternately disposed along the Y direction at the X-direction central portion of the stacked body ML have common connections to each other at each of the X-direction end portions of the stacked body ML.

Then, as illustrated in FIG. 18, an insulating film 16 is deposited on the stacked body ML and planarized. The insulating film 16 also is filled into the trenches 54. Then, the conductive film 17 made of, for example, amorphous silicon is deposited, etched, and left only in the memory cell region.

Then, a resist film (not illustrated) is formed, for example, on the conductive film 17; and the stacked body ML is patterned into a stairstep configuration by repeatedly performing etching using the resist film as a mask and performing slimming of the resist film. Thereby, both X-direction end portions of the control gate electrodes CG for each level are not covered with the control gate electrodes CG of the level thereabove as viewed from above (the Z direction); and in subsequent processes, contacts can be formed from above to the control gate electrodes CG of each level. Then, an etching stopper film (not illustrated) made of, for example, silicon nitride is formed to cover the stacked body ML patterned into the stairstep configuration; an inter-layer insulating film (not illustrated) is formed thereupon; and the upper face is planarized. Thereby, the inter-layer insulating film is filled around the stacked body ML.

Subsequently, the insulating film 18 is formed on the conductive film 17. The through-holes 51 are made to pierce the insulating film 18, the conductive film 17, and the insulating film 16 to reach the upper ends of the through-holes 21 in the stacked body ML.

Then, as illustrated in FIG. 19, an insulating film is deposited on the entire surface, and amorphous silicon is deposited. Etch-back is performed on the amorphous silicon and the insulating film to leave the amorphous silicon and the insulating film only in the through-holes 51. Thereby, the gate insulating film 28 is formed on the inner face of the through-holes 51 and the amorphous silicon is filled. Then, heat treatment is performed at a temperature of, for example, 600° C. to crystallize the amorphous silicon in the through-holes 51 to form polysilicon. Ion implantation is performed on the polysilicon using arsenic (As) with, for example, an acceleration voltage of 40 keV and a dose of 3×10¹⁵ cm⁻² to form a drain diffusion layer (not illustrated). Thereby, the silicon pillars 34 are formed in the through-holes 51. The silicon pillars 34 connect to the silicon pillars 31.

Continuing, patterning by RIE and the like is performed on the insulating film 18 and the conductive film 17 to make trenches 55 aligned in the X direction in the regions between the silicon pillars 34 adjacent to each other in the Y direction. Thereby, the conductive film 17 is divided along the Y direction to form multiple selection gate electrodes SG aligned in the X direction.

Then, as illustrated in FIG. 3, the insulating film 19 is formed on the insulating film 18; source plugs SP are buried in the insulating film 19; and the source lines SL are formed on the insulating film 19 to align in the X direction. At this time, the source lines SL are connected to the drain diffusion layers of some of the silicon pillars 34 via the source plugs SR Contacts (not illustrated) are formed in the inter-layer insulating film (not illustrated) provided around the stacked body ML to connect to each of the control gate electrodes CG and each of the selection gate electrodes SG from above. Then, the insulating film 20 is formed on the insulating film 19 to cover the source lines SL. Then, the bit plugs BP are buried in the insulating films 20 and 19 and the bit lines BL are formed on the insulating film 20 to align in the Y direction. At this time, the bit lines BL are connected to the drain diffusion layers of the remaining silicon pillars 34 via the bit plugs BP. On the other hand, the drive circuit 41 (referring to FIG. 6) is formed in the peripheral circuit region by normal methods. Thereby, the nonvolatile semiconductor memory device 1 is manufactured.

According to this embodiment, the nonvolatile semiconductor memory device 1 according to the first embodiment described above can be manufactured. According to this embodiment, the drive circuit 41 supplies mutually different potentials to the control gate electrode CG of each of the levels. Thereby, the electric fields applied to the ONO films 24 of the memory transistors 35 are made to be uniform. Therefore, it is unnecessary to make the through-hole 21 diameters to be excessively uniform. Therefore, the aspect ratio of the through-hole 21 can be increased; the number of times that the through-holes 21 are made can be reduced when manufacturing the device 1 in which the prescribed number of levels of the electrode film 14 is stacked; and accordingly, the number of lithography processes can be reduced. As a result, the manufacturing cost of the nonvolatile semiconductor memory device 1 can be reduced.

The series of processes described above forming the stacked body ML, making the through-hole 21 in the stacked body ML, and filling the silicon pillar 31 into the through-hole 21 may be performed twice to manufacture a nonvolatile semiconductor memory device 2 according to the second embodiment described above. By performing the processes described above three times or more, a nonvolatile semiconductor memory device can be manufactured in which partial stacked bodies are stacked in three levels or more. In other words, portions of the through-holes 21 made in each of the partial stacked bodies are made collectively for the partial stacked body by dry etching.

Hereinabove, the invention is described with reference to exemplary embodiments. However, the invention is not limited to these exemplary embodiments. Additions, deletions, or design modifications of components or additions, omissions, or condition modifications of processes appropriately made by one skilled in the art in regard to the exemplary embodiments described above are within the scope of the invention to the extent that the purport of the invention is included.

For example, although an example is illustrated in the first embodiment described above in which the drive circuit 41 supplies mutually different potentials to the control gate electrodes CG of each of the levels for each of the writing operation, the reading operation, and the erasing operation, the invention is not limited thereto. For example, mutually different potentials may be supplied to the control gate electrodes of each of the levels only for the writing operation and the reading operation. In such a case, a common reference potential Vss may be used; and the drive circuit can be simplified. Further, mutually different potentials may be supplied to the control gate electrodes of each of the levels only for one operation selected from the writing operation, the reading operation, and the erasing operation. The configurations of the control gate electrodes and the like are not limited to those of the exemplary embodiments described above.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a substrate;

a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction;

a semiconductor pillar buried in an interior of the through-hole;

a charge storage film provided between the electrode film and the semiconductor pillar; and

a drive circuit supplying a potential to the electrode film,

a diameter of the through-hole differing by a position in the stacking direction,

the drive circuit supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

2. The device according to claim 1, wherein a diameter of the through-hole decreases toward the substrate.

3. The device according to claim 2, wherein the through-holes are made collectively by dry etching.

4. The device according to claim 1, wherein

the stacked body includes a plurality of partial stacked bodies arranged in the stacking direction, a plurality of the insulating films and a plurality of the electrode films being disposed in the partial stacked body, and

in each of the partial stacked bodies, a diameter of the through-hole decreases toward the substrate.

5. The device according to claim 4, wherein portions of the through-holes made in each of the partial stacked bodies are made collectively for the partial stacked body by dry etching.

6. The device according to claim 1, wherein

the through-hole has a circular configuration as viewed from the stacking direction, and

a potential provided by the drive circuit to one of the electrode films is determined according to

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7. The device according to claim 1, wherein the drive circuit includes:

a decoder to output a control signal;

a pump circuit to increase a supplied potential; and

a switch element to switch between connecting and disconnecting the pump circuit and the electrode film based on the control signal.

8. The device according to claim 7, wherein the pump circuit and the switch element are provided for each of the electrode films.

9. The device according to claim 1, further comprising:

a back gate disposed between the substrate and the stacked body; and

a connection member provided in the back gate to connect two adjacent semiconductor pillars to each other.

10. The device according to claim 1, wherein a memory cell region and a peripheral circuit region are set in the substrate, the semiconductor pillar and the charge storage film are disposed in the memory cell region, and the drive circuit is disposed in the peripheral circuit region.

11. A method for driving a nonvolatile semiconductor memory device, the device including: a substrate; a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction; a semiconductor pillar buried in an interior of the through-hole; and a charge storage film provided between the electrode film and the semiconductor pillar, a diameter of the through-hole differing by a position in the stacking direction, the method comprising:

when applying a potential to the electrode film, supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

12. The method according to claim 11, comprising providing a potential to one of the electrode films, the potential being determined according to

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13. The method according to claim 11, wherein the potential is a writing potential to inject an electron from the semiconductor pillar into the charge storage film.

14. The method according to claim 11, wherein the potential is a reading potential to detect whether or not an electron is stored in the charge storage film.

15. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a source line provided above the semiconductor substrate;

a bit line provided above the source line;

a memory string including

a first selection transistor connected to the bit line,

a second selection transistor connected to the source line, and

a plurality of electrically-series-connected memory transistors connected between the first selection transistor and the second selection transistor, the memory transistors including

a first memory cell transistor being above the semiconductor substrate,

a second memory cell transistor being above the first memory cell transistor, and

a third memory cell transistor being above the second memory cell transistor;

a first word line being above the semiconductor substrate and electrically connected to a gate of the first memory cell transistor;

a second word line being above the first word line and electrically connected to a gate of the second memory cell transistor;

a third word line being above the second word line and electrically connected to a gate of the third memory cell transistor;

a driver circuit configured to apply voltages to the first to third word lines, respectively; and

a control circuit configured to perform a read operation on a condition that

the driver circuit applies a second voltage to the second word line and applies a third voltage which is higher than the second voltage to the third word line when a read operation for the first memory cell transistor is performed,

the driver circuit applies a first voltage which is lower than the second voltage to the first word line and applies the third voltage to the third word line when a read operation for the second memory cell transistor is performed, and

the driver circuit applies the first voltage to the first word line and applies the second voltage to the second word line when a read operation for the third memory cell transistor is performed.

16. The device according to claim 15, further comprising:

a fourth memory cell transistor being above the third memory cell transistor; and

a fourth word line electrically connected to a gate of the fourth memory cell transistor,

wherein the control circuit is configured to perform a read operation on a condition that a fourth voltage is applied to the fourth word line when the read operation for the first memory cell transistor is performed, when the read operation for the second memory cell transistor is performed and when the read operation for the third memory cell transistor is performed,

the third voltage is lower than the fourth voltage.

17. The device according to claim 15, wherein the first memory cell transistor includes a first portion of a semiconductor body, the second memory cell transistor includes a second portion of the semiconductor body, the third memory cell transistor includes a third portion of the semiconductor body, a first diameter of the first portion is smaller than a second diameter of the second portion, and the second diameter is smaller than a third diameter of the third portion.

18. The device according to claim 15, wherein

the driver circuit includes:

a pump circuit unit configured to apply voltages to the first to third word lines, respectively, and

a switch circuit unit connected between the pump circuit unit and the first to third word lines and configured to transfer the voltages applied from the pump circuit unit to the first to third word lines, respectively; and

the control circuit is configured to perform a read operation on a condition that

the pump circuit unit applies a second voltage and a third voltage to the switch circuit unit and the switch circuit unit transfers the second voltage and the third voltage to the second word line and the third word line, respectively, when a read operation for the first memory cell transistor is performed,

the pump circuit unit applies a first voltage and the third voltage to the switch circuit unit and the switch circuit unit transfers the first voltage and the third voltage to the first word line and the third word line, respectively, when a read operation for the second memory cell transistor is performed, and

the pump circuit unit applies the first voltage and the second voltage to the switch circuit unit and the switch circuit unit transfers the first voltage and the second voltage to the first word line and the second word line, respectively, when a read operation for the third memory cell transistor is performed.

19. A nonvolatile semiconductor memory device, comprising:

a substrate;

a first electrode film provided on the substrate, the first electrode film being spaced from the substrate;

a second electrode film provided on the first electrode film, the second electrode film being positioned above and spaced from the first electrode film;

a third electrode film provided on the second electrode film, the third electrode film being positioned above and spaced from the second electrode film;

a semiconductor pillar intersecting the first electrode film, the second electrode film and the third electrode film, a first portion of the semiconductor pillar being disposed in the first electrode film, a second portion of the semiconductor pillar being disposed in the second electrode film and a third portion of the semiconductor pillar being disposed in the third electrode film, a first diameter of the first portion being smaller than a second diameter of the second portion, and the second diameter being smaller than a third diameter of the third portion;

a bit line connected to the semiconductor pillar above the third electrode film;

a charge storage film provided between the semiconductor pillar and the first electrode film, between the semiconductor pillar and the second electrode film and between the semiconductor pillar and the third electrode film; and

a drive circuit supplying a first potential to the first electrode film, supplying a second potential to the second electrode film and supplying a third potential to the third electrode film, the first potential being lower than the second potential, and the second potential being lower than the third potential.

20. The device according to claim 19, further comprising a fourth electrode film provided on the third electrode film, the fourth electrode film being spaced from the third electrode film,

the semiconductor pillar intersecting the fourth electrode film,

a fourth portion of the semiconductor pillar being disposed in the fourth electrode film,

the third diameter being smaller than a fourth diameter of the fourth portion,

the drive circuit supplying a fourth potential to the fourth electrode film, the third potential being lower than the fourth potential.

21. The device according to claim 19, wherein the drive circuit includes:

a decoder to output a control signal;

a pump circuit to increase a supplied potential; and

a switch element to switch between connecting and disconnecting the pump circuit and one of the first electrode film, the second electrode film and the third electrode film based on the control signal.

22. A method for driving a nonvolatile semiconductor memory device, the device including: a first memory cell transistor being above a semiconductor substrate; a second memory cell transistor being above the first memory cell transistor; a third memory cell transistor being above the second memory cell transistor; a first word line electrically connected to a gate of the first memory cell transistor; a second word line electrically connected to a gate of the second memory cell transistor; a third word line electrically connected to a gate of the third memory cell transistor, a bit line; a source line; a first selection transistor connected to the bit line; a second selection transistor connected to the source line; the first to third memory cell transistors connected between the first and second selection transistors; the first selection transistor being above the third memory cell transistor; and a driver circuit, the method comprising using the driver circuit to:

apply a second voltage to the second word line and apply a third voltage to the third word line when a read operation for the first memory cell transistor is performed;

apply a first voltage to the first word line and apply the third voltage to the third word line when a read operation for the second memory cell transistor is performed; and

apply the first voltage to the first word line and apply the second voltage to the second word line when a read operation for the third memory cell transistor is performed,

wherein the first voltage is lower than the second voltage, and the second voltage is lower than the third voltage.

23. The method according to claim 22, the device further including: a fourth memory cell transistor being above the third memory cell transistor; and a fourth word line electrically connected to a gate of the fourth memory cell transistor,

the method further comprising:

applying a fourth voltage to the fourth word line when the read operation for the first memory cell transistor is performed, when the read operation for the second memory cell transistor is performed and when the read operation for the third memory cell transistor is performed,

wherein the third voltage is lower than the fourth voltage.

24. The method according to claim 22, wherein the first memory cell transistor includes a first portion of a semiconductor body, the second memory cell transistor includes a second portion of the semiconductor body, the third memory cell transistor includes a third portion of the semiconductor body, a first diameter of the first portion is smaller than a second diameter of the second portion, and the second diameter is smaller than a third diameter of the third portion.