A non-volatile semiconductor memory device has a nand string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.
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0. 30. A non-volatile semiconductor memory device comprising:
a nand string including first to nth memory cells (n is a natural number and is equal to or more than 5), the first to nth memory cells being connected in series;
first to nth word lines electrically connected to the first to nth memory cells;
a voltage generation circuit configured to generate a first voltage and a second voltage higher than the first voltage; and
a control circuit configured to apply a selected voltage to a kth word line (k is a natural number and the range of k is from 3 to n−2), apply the second voltage to both (k−1)th word line and (k+1)th word line, and apply the first voltage to both (k−2)th word line and (k+2)th word line in a read procedure, the selected voltage is different from the first voltage and the second voltage.
0. 34. A non-volatile semiconductor memory device comprising:
a nand string including first to nth memory cells (n is a natural number and is equal to or more than 5), the first to nth memory cells being connected in series;
first to nth word lines electrically connected to the first to nth memory cells; and,
a voltage generation circuit configured to generate a selected voltage, a first voltage and a second voltage higher than the first voltage,
wherein the selected voltage is applied to the kth word line (k is a natural number and the range of k is from 3 to n−2), the second voltage is applied to both (k−1)th word line and (k+1)th word line, and the first voltage is applied to both (k−2)th word line and (k+2)th word line when a read procedure is executed, the selected voltage is different from the first voltage and the second voltage.
0. 26. A non-volatile semiconductor memory device comprising:
a nand string, in which first to nth memory cells (n is a natural number and is equal to or more than 5) are connected in series, first to nth word lines being electrically connected to the first to nth memory cells;
a voltage generation circuit configured to generate a first voltage and a second voltage higher than the first voltage, and
a control circuit configured to perform a read procedure for kth memory cell (k is a natural number and the range of k is from 3 to n−2) in the nand string, wherein a selected voltage is applied to the kth word line, the second voltage is applied to both (k−1)th word line and (k+1)th word line, and the first voltage is applied to both (k−2)th word line and (k+2)th word line, the selected voltage is different from the first voltage and the second voltage.
0. 17. A non-volatile semiconductor memory device comprising:
at least three memory cells connected in series;
a control circuit configured to perform a read procedure for a selected memory cell, wherein a selected voltage is applied to the selected memory cell while voltages are applied to unselected memory cells; and
a voltage generation circuit configured to generate a first voltage and a second voltage higher than the first voltage, the first voltage and the second voltage being different from the selected voltage,
wherein, during the read procedure, the first voltage generated by the voltage generation circuit is applied to at least one of the unselected memory cells except for the unselected memory cells that are disposed adjacent to the selected memory cell, and the second voltage generated by the voltage generation circuit is applied to at least one of the unselected memory cells that are disposed adjacent to the selected memory cell.
0. 22. A non-volatile semiconductor memory device comprising:
at least three memory cells connected in series;
a voltage generation circuit configured to generate unselected voltages including a first voltage and a second voltage higher than the first voltage; and
a control circuit configured to perform a read procedure for a selected memory cell, wherein a selected voltage is applied to a selected word line and the unselected voltages are applied to unselected word lines, the selected word line being connected to the selected memory cell, the unselected word lines being connected to unselected memory cells, the selected voltage being different from the first voltage and the second voltage,
wherein, during the read procedure, the first voltage generated by the voltage generation circuit is applied to at least one of the unselected word lines except for the unselected word lines that are disposed adjacent to the selected word line, and the second voltage generated by the voltage generation circuit is applied to at least one of the unselected word lines that are disposed adjacent to the selected word line.
0. 1. A method for controlling a non-volatile semiconductor memory device having a nand string, in which multiple memory cells are connected in series, comprising:
a read procedure performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
a first read pass voltage and a second read pass voltage higher than the first read pass voltage are generated by a voltage generation circuit, and wherein
the first read pass voltage generated by the voltage generation circuit is applied to unselected memory cells except adjacent and unselected memory cells disposed adjacent to the selected memory cell, and the second read pass voltage generated by the voltage generation circuit is applied to at least one of the adjacent and unselected memory cells in the read procedure.
0. 2. The method according to
the second read pass voltage is applied to the adjacent and unselected memory cell being completed in data write later than the selected memory cell.
0. 3. The method according to
the read procedure is a normal read procedure for reading data of the selected memory cell after data writing.
0. 4. The method according to
the read procedure is a write-verify read procedure for verify-reading data of the selected memory cell in a data write mode.
0. 5. The method according to
in the normal read procedure, the second read pass voltage is applied to one cell in two adjacent and unselected memory cells disposed adjacent to the selected memory cell, the one cell having been written previously to the selected memory cell; and a third pass voltage is applied to the other cell in the two adjacent and unselected memory cells, the other cell having been written later than the selected memory cell, the third read pass voltage being selected in level in accordance with the cell's threshold shift amount.
0. 6. The method according to
the third read pass voltage is set to be lower than the first read pass voltage in case the cell's threshold shift amount is less than a certain level while the third read pass voltage is set to be equal to the second read pass voltage in case the cell's threshold shift amount is greater than the certain level.
0. 7. The method according to
the normal read procedure includes:
a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and
a second read operation performed for reading data of the selected memory cell on the condition that the third read pass voltage is selected in level with reference to the read data of the first read operation.
0. 8. The method according to
the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and
a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and
in the data write procedure, the memory cells in the nand string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in the successive lower page write mode; and then the first memory cell is written in an upper page write mode.
0. 9. A method for controlling a non-volatile semiconductor memory device having a nand string, in which multiple memory cells are connected in series, comprising:
a write-verifying procedure performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and
a normal read procedure performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except two adjacent and unselected memory cells disposed adjacent to the selected memory cell; a second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and a third read pass voltage lower than the first read pass voltage is applied to the other cell, which is written later than the selected memory cell, and
in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the two adjacent and unselected memory cells; the second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and a fourth read pass voltage is applied to the other cell, which has been written later than the selected memory cell, the fourth read pass voltage being selected in level in accordance with the cell's threshold shift amount.
0. 10. The method according to
the fourth read pass voltage is set to be lower than the first read pass voltage in case the cell's threshold shift amount is less than a certain level while the fourth read pass voltage is set to be equal to the second read pass voltage in case the cell's threshold shift amount is greater than the certain level.
0. 11. The method according to
the normal read procedure includes:
a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and
a second read operation performed for reading data of the selected memory cell on the condition that the fourth read pass voltage is selected in level with reference to the read data of the first read operation.
0. 12. The method according to
the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and
a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and
in the data write procedure, the memory cells in the nand string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and then the first memory cell is written in an upper page write mode.
0. 13. A method for controlling a non-volatile semiconductor memory device having a nand string, in which multiple memory cells are connected in series, comprising:
a write-verifying procedure performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and
a normal read procedure performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell; a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and
in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell; a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell's threshold shift amount, the maximum vale of which is higher than the first read pass voltage.
0. 14. The method according to
the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and
a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and
in the data write procedure, the memory cells in the nand string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and then the first memory cell is written in an upper page write mode.
0. 15. A method for controlling a non-volatile semiconductor memory device having a nand string, in which multiple memory cells are connected in series, comprising:
a write-verifying procedure performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and
a normal read procedure performed for a selected memory cell in the nand string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell; a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and
in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell; a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell data, the maximum value of which is higher than the first read pass voltage.
0. 16. The method according to
the memory cell stores multi-level data defined as a cell threshold voltage, and
in a data write procedure, the memory cells in the nand strings are selected in order from a source line side, and the multi-level data writing are completed for each selected memory cell.
0. 18. The non-volatile semiconductor memory device according to claim 17, wherein
the second voltage is applied to the unselected memory cell that is disposed adjacent to the selected memory cell and to which data is written later than the selected memory cell.
0. 19. The non-volatile semiconductor memory device according to claim 17, wherein
the read procedure is a read procedure for reading data of the selected memory cell after data writing and for outputting the read data.
0. 20. The non-volatile semiconductor memory device according to claim 17, wherein
the read procedure is a write-verify read procedure perfomed in a data write mode.
0. 21. The non-volatile semiconductor memory device according to claim 17, further comprising:
first and second transistors electrically connected to the at least three memory cells, the first transistor being connected to a bit line, the second transistor being connected to a source line, wherein
a third voltage generated by the voltage generation circuit is applied to the first transistor in the read procedure, and
the third voltage is applied to the first transistor and the second voltage is applied to at least one of the unselected memory cells that are disposed adjacent to the selected memory cell, at the same time.
0. 23. The non-volatile semiconductor memory device according to claim 22, wherein
the read procedure is a read procedure for reading data of the selected memory cell after data writing and for outputting the read data.
0. 24. The non-volatile semiconductor memory device according to claim 22, wherein
the read procedure is a write-verify read procedure performed in a data write mode.
0. 25. The non-volatile semiconductor memory device according to claim 22, further comprising:
first and second transistors electrically connected to the at least three memory cells, the first transistor being connected to a bit line, the second transistor being connected to a source line, wherein
a third voltage generated by the voltage generation circuit is applied to the first transistor in the read procedure, and
the third voltage is applied to the first transistor and the second voltage is applied to at least one of the unselected memory cells that are disposed adjacent to the selected memory cell, at the same time.
0. 27. The non-volatile semiconductor memory device according to claim 26, wherein
the read procedure is a read procedure for reading data of the kth memory cell after data writing and for outputting the read data.
0. 28. The non-volatile semiconductor memory device according to claim 26, wherein
the read procedure is a write-verify read procedure performed in a data write mode.
0. 29. The non-volatile semiconductor memory device according to claim 26, wherein
the nand string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,
a third voltage generated by the voltage generation circuit is applied to the first transistor in the read procedure, and
the third voltage is applied to the first transistor and the second voltage is applied to both (k−1)th word line and (k+1)th word line, at the same time.
0. 31. The non-volatile semiconductor memory device according to claim 30, wherein
the read procedure is a read procedure for reading data of the kth memory cell after data writing and for outputting the read data.
0. 32. The non-volatile semiconductor memory device according to claim 30, wherein
the read procedure is a write-verify read procedure performed in a data write mode.
0. 33. The non-volatile semiconductor memory device according to claim 30, wherein
the nand string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,
a third voltage generated by the voltage generation circuit is applied to the first transistor in the read procedure, and
the third voltage is applied to the first transistor and the second voltage is applied to both (k−1)th word line and (k+1)th word line, at the same time.
0. 35. The non-volatile semiconductor memory device according to claim 34, wherein
the read procedure is a read procedure for reading data of the kth memory cell after data writing and for outputting the read data.
0. 36. The non-volatile semiconductor memory device according to claim 34, wherein
the read procedure is a write-verify read procedure performed in a data write mode.
0. 37. The non-volatile semiconductor memory device according to claim 34, wherein
the nand string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,
a third voltage generated by the voltage generation circuit is applied to the first transistor in the read procedure, and
the third voltage is applied to the first transistor and the second voltage is applied to both (k−1)th word line and (k+1)th word line, at the same time.
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is coupled
where, Cr=C2/Call (Call is the total capacitance value of FGn).
By use of the following
In Exp. 2, ΔVt is the threshold voltage change amount due to the interference effect. Rewriting it into another threshold shift amount ΔVt_swing due to data writing in the adjacent and unselected cell, the following Exp. 3 is obtained.
ΔVwl={C2/(C4+C3·Cr)}ΔVt_swing [Exp. 3]
A detailed numerous example is as follows. Assuming that the coefficient of ΔVt_swing is defined as: C3·Cr/(C4+C3·Cr)=0.41; and assuming that ΔVt_swing is about 3V as defined by the cell data change from E-level to A-level, ΔVwl=1.24V is obtained.
As explained above, by increasing the potential of word line WLn+1 by 1.24V, it becomes possible to cancel the interference effect due to the threshold shift amount, 3V, of the adjacent cell.
Further, to make the influence of the back pattern noise on the word line WLn+1 due to the selected word line WLn, as explained with reference to
A setting example of pass voltage Vread2 is as follows. Since, as shown in the calculation example, the threshold voltage of the adjacent cell appears to be shifted with an order of 0.3V or 0.6V, keeping constant the difference between Vread2 and Vread3, Vread2 should be set at a voltage higher than Vread by 0.3V or 0.6V.
At Step1, prior to the read operation of the selected word line WLn, data read for correcting data is performed for word line WLn+1, and read data is latched at node PDC. At Step2, Read1 shown in
At Step3, data at node PDC is transferred to node DDC, and the product of data at TDC by inverted data at DDC is obtained. This is achieved in the operation circuit 34 in the sense amplifier shown in
That is, if DDC=“H”, TDC is discharged to be “L”. If DDC=“1”, TDC is not discharged, and keeps the last data level as it is. This operation result is transferred to and held at node PDC.
At Step4, this being which is a read step, Read2, shown in
Therefore, the threshold of “cell2” in Read1 and that of “cell1” in Read2 become substantially equal to each other. Latched data of (cell1, cell2, cell3) at node TDC are (L, L, H).
Next, at Step5, data previously latched at node PDC is transferred to node DDC, and an addition operation of data at node TDC and data at node DDC is performed at node TDC. Explaining that in detail, in the operation circuit 34 in
As a result, if DDC=“H”, TDC is forced to be “H” due to a bootstrap operation. If DDC=“L”, the last TDC data will be kept as it is. The operation result at TDC is transferred to node PDC, and latched as the lower page data.
Therefore, according to this operation, in case “L” is initially stored at node PDC in the sense amplifier, finally latched data at the node PDC is read data in Read1, while in case “H” is initially stored at node PDC, read data in Read2 is finally latched at the node PDC.
As described above, data read with threshold correction may be performed for the respective bit lines, i.e., for the respective selected cells, which are coupled to a selected word line to be simultaneously read.
The sense amplifier configuration and the operational function are not limited to those shown in
As another embodying mode in this embodiment, it is possible to correct the interference effect between cells at multiple steps, i.e., two or more steps. This is, for example, achieved by disposing another operational circuit between node N1 (PDC) and TDC in the sense amplifier shown in
Fourth R/W Scheme in the Embodiment
So far, it has been explained such a case has been explained that the write order is selected to make the interference between adjacent cells as small as possible. By contrast, in case word lines are selected in order from the source line side, and the lower page write and the upper page write are completed for each selected word line, each cell's threshold will be shifted due to the interference between adjacent cells after writing.
However, in the above-described case, by precisely controlling the read pass voltage applied to the unselected word lines WLn+1 disposed adjacent to the selected word line WLn on the bit line side in accordance with cell data, the influence of the interference between cells will be reduced.
In detail, as similar to the third R/W scheme explained above, the read pass voltage of the adjacent and unselected word line at a write-verify time is set to be lower than the read pass voltage, Vread, applied to the remaining unselected word lines. After data writing for WLn+1,the read pass voltage applied to the unselected word line WLn+1 at a read time for the selected word line WLn is optimized in accordance with which the level is of cell data in E, A, B and C levels.
As a result, the influence of the interference between cells will be reduced.
In the third R/W scheme, the read pass voltage applied to the unselected word line WLn−1 is set to be Vread2, higher than Vread. According to the explanation for the first R/W scheme, it is not necessary to set the unselected word line WLn−1 at Vread2. Using Vread in place of Vread2, it will be expected the same operation and effect as described above can be realized.
In the above-described embodiment, the operation control example has been explained for a four-level data storage scheme (i.e., 2 bits/cell). However, this invention is in a method for controlling a an unselected word line disposed adjacent to a selected word line, and is not limited to the four-level storage scheme. That is, this invention may be adapted to other memory devices of a binary data storage scheme (1 bit/cell), an eight-level storage scheme (3 bits/cell) and other multi-level data storage schemes.
Application Devices
As an embodiment, an electric card using the non-volatile semiconductor memory devices according to the above-described embodiment of the present invention and an electric device using the card will be described bellow below.
The case of the digital still camera 1001 accommodates a card slot 1002 and a circuit board (not shown) connected to this card slot 1002. The memory card 61 is detachably inserted in the card slot 1002 of the digital still camera 1001. When inserted in the slot 1002, the memory card 61 is electrically connected to electric circuits of the circuit board.
If this electric card is a non-contact type IC card, it is electrically connected to the electric circuits on the circuit board by radio signals when inserted in or approached to the card slot 1002.
To monitor the image, the output signal from the camera processing circuit 1005 is input to a video signal processing circuit 1006 and converted into a video signal. The system of the video signal is, e.g., NTSC (National Television System Committee). The video signal is input to a display 1008 attached to the digital still camera 1001 via a display signal processing circuit 1007. The display 1008 is, e.g., a liquid crystal monitor.
The video signal is supplied to a video output terminal 1010 via a video driver 1009. An image picked up by the digital still camera 1001 can be output to an image apparatus such as a television set via the video output terminal 1010. This allows the pickup image to be displayed on an image apparatus other than the display 1008. A microcomputer 1011 controls the image pickup device 1004, analog amplifier (AMP), A/D converter (A/D), and camera signal processing circuit 1005.
To capture an image, an operator presses an operation button such as a shutter button 1012. In response to this, the microcomputer 1011 controls a memory controller 1013 to write the output signal from the camera signal processing circuit 1005 into a video memory 1014 as a flame frame image. The flame frame image written in the video memory 1014 is compressed on the basis of a predetermined compression format by a compressing/stretching circuit 1015. The compressed image is recorded, via a card interface 1016, on the memory card 61 inserted in the card slot.
To reproduce a recorded image, an image recorded on the memory card 61 is read out via the card interface 1016, stretched decompressed by the compressing/stretching decompressing circuit 1015, and written into the video memory 1014. The written image is input to the video signal processing circuit 1006 and displayed on the display 1008 or another image apparatus in the same manner as when image is monitored.
In this arrangement, mounted on the circuit board 1000 are the card slot 1002, image pickup device 1004, analog amplifier (AMP), A/D converter (A/D), camera signal processing circuit 1005, video signal processing circuit 1006, display signal processing circuit 1007, video driver 1009, microcomputer 1011, memory controller 1013, video memory 1014, compressing/stretching circuit 1015, and card interface 1016.
The card slot 1002 need not be mounted on the circuit board 1000, and can also be connected to the circuit board 1000 by a connector cable or the like.
A power circuit 1017 is also mounted on the circuit board 1000. The power circuit 1017 receives power from an external power source or battery and generates an internal power source voltage used inside the digital still camera 1001. For example, a DC-DC converter can be used as the power circuit 1017. The internal power source voltage is supplied to the respective circuits described above, and to a strobe 1018 and the display 1008.
As described above, the electric card according to this embodiment can be used in portable electric devices such as the digital still camera explained above. However, the electric card can also be used in various apparatus such as shown in
This invention is not limited to the above-described embodiments. It will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit, scope, and teaching of the invention.
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