A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
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0. 8. A transistor of a semiconductor memory device, comprising:
a semiconductor substrate having a plurality of active regions and a device isolation region;
a plurality of first and second trench device isolation layers arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness, and the second trench device isolation layers having a second thickness smaller than the first thickness;
a recess region having a predetermined depth formed in each of the active regions, the recess region having a stepped profile and an upwardly protruded portion between two adjacent second trench device isolation layers;
a plurality of gate insulation layers and gate stacks; and
at least one of the gate stacks formed on one of the gate insulation layers and having a stripe form crossing one of the active regions to partially fill the recess region,
wherein the transistor has a fin field effect transistor structure, and
wherein each active region of the plurality of active regions has a central region and opposite edge regions, a height of an upper surface of the central region being lower than a height of an upper surface of the opposite edge regions.
0. 1. A method for manufacturing a transistor of a semiconductor memory device, comprising:
forming a hard mask layer pattern on a semiconductor substrate over a plurality of active regions;
forming a plurality of device isolation trenches in a device isolation region of the semiconductor substrate by using the hard mask layer pattern as an etching mask;
forming a trench device isolation layer by filling up the device isolation trenches with an insulation layer;
etching a part of the trench device isolation layer by a predetermined depth by use of a first mask layer pattern, to form a plurality of first and second trench device isolation layers arranged alternately with each other, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height;
removing the hard mask layer pattern;
etching the active regions by a predetermined depth by use of a second mask layer pattern, to form a recess region in each of the active regions, the recess region having a stepped profile at a boundary portion thereof and a height higher than that of the second trench device isolation layers to form an upwardly protruded portion between two adjacent second trench device isolation layers; and
forming a plurality gate insulation layers and plurality of gate stacks on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
0. 2. The method of
0. 3. The method of
0. 4. The method of
0. 5. The method of
0. 6. The method of
0. 7. The method of
0. 9. The transistor of claim 8, wherein the first thickness of the first trench device isolation layers is in a range from about 2000 Å to about 4000 Å.
0. 10. The transistor of claim 9, wherein the second thickness of the second trench device isolation layers is about one third of the first thickness of the first trench device isolation layers.
0. 11. The transistor of claim 8, wherein the thickness of the protruded portion of the recess region is substantially equal to the second thickness of the second trench device isolation layers.
0. 12. The transistor of claim 8, wherein each of the gate stacks has a stripe form, and is formed to overlap with the second trench device isolation layers.
0. 13. The transistor of claim 8, wherein the plurality of gate insulation layers and gate stacks overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
0. 14. The transistor of claim 8, wherein each of the gate stacks includes a doped polysilicon layer having a thickness of about 400 Å to about 700 Å.
0. 15. The transistor of claim 14, wherein each of the gate stacks includes a tungsten-silicide layer having a thickness of about 1000 Å to about 1500 Å.
0. 16. The transistor of claim 8, wherein the plurality of gate insulation layers and the plurality of gate stacks are formed at least in part in the recess region.
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This More than one reissue application has been filed for the reissue of U.S. Pat. No. 7,776,711. This application is a Continuation Reissue of U.S. patent application Ser. No. 13/586,272, filed Aug. 15, 2012, now issued as Reissue U.S. Pat. No. RE 44,532, which is a Reissue of U.S. patent application Ser. No. 12/331,830, filed Dec. 10, 2008, now issued as U.S. Pat. No. 7,776,711, which is a divisional of co-pending, commonly-assigned U.S. application Ser. No. 11/450,096 filed Jun. 9, 2006, now issued as U.S. Pat. No. 7,479,676, which in turn claims the convention priority of Korean application 2005-86497 filed Sep. 15, 2005.
1. Field of the Invention
The invention relates generally to a semiconductor memory device and a method for manufacturing the same and, more particularly, to a transistor of a semiconductor memory device and a method for manufacturing the same.
2. Description of the Related Art
The degree of integration of semiconductor memory devices, for example, a dynamic random access memory (DRAM) device, is increasing. Such an increase in the degree of integration causes a variety of problems due to the short channel effect of a transistor that is an element of the semiconductor memory device. As one example of the problems, a general rule that a threshold voltage has no relation to the length or width of a channel is no longer applicable to certain channel structures, in particular, to sub-100 nm channel structures. For this reason, in a conventional transistor having a planar structure it is difficult to obtain a desired threshold voltage. Moreover, it will be easily expected that obtaining the desired threshold voltage becomes more difficult to a sub-50 nm channel structure.
In accordance with the this trend, a variety of transistors having a three-dimensional structure, rather than the planar structure, have been proposed. Examples of three-dimensional transistors include a transistor having a recess channel, and a transistor having a stepped profile. In particular, the transistor having a stepped profile is configured such that the surface of an active region has a stepped profile, and a gate stack is laminated on the stepped profile, thereby achieving an increase in an effective channel length while maintaining a constant area of the transistor.
In addition, one example of transistors, which are mainly used in logic devices rather than memory devices, is a fin field effect transistor (FINFET). The fin field effect transistor is configured such that the surface of an active region partially protrudes to form a fin, and a gate stack is laminated on the fin. The fin field effect transistor having the above described configuration exhibits good On/Off characteristics, high current drive ability, and low back-bias dependency. However, when the fin field effect transistor is employed in a memory device, the fin field effect transistor forms a triple channel in a small region. This results in an increase in a source of leakage current with respect to bonding, and makes it difficult to ensure a sufficient data retention time.
The invention provides a transistor of a semiconductor memory device having a structure, which integrates the structure of a transistor having a stepped profile and the structure of a fin field effect transistor, thereby achieving an improvement in operational characteristics and ensuring sufficient data retention time.
The invention also provides a method for manufacturing a transistor of a semiconductor memory device using a damascene process.
In accordance with one aspect, the invention provides a transistor of a semiconductor memory device including: a semiconductor substrate having a plurality of active regions and a device isolation region; a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height; a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers; a gate insulation layer; and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
Preferably, the first thickness of the first trench device isolation layers may be in a range from 2000 Å to 4000 Å, and the second thickness of the second trench device isolation layers may be one third of the first thickness of the first trench device isolation layers.
Preferably, the thickness of the protruded portion of the recess region may be substantially equal to the second thickness of the second trench device isolation layers.
Preferably, each of the gate stacks may have a stripe form, and may be formed to overlap with one of the second trench device isolation layers along with the stepped profile and the protruded portion of the relevant recess region.
In accordance with another aspect, the invention provides a method for manufacturing a transistor of a semiconductor memory device, including the steps of:
forming a hard mask layer pattern on a semiconductor substrate over a plurality of active regions;
forming a plurality of device isolation trenches in a device isolation region of the semiconductor substrate by using the hard mask layer pattern as an etching mask;
forming a trench device isolation layer by filling up the device isolation trenches with an insulation layer;
etching a part of the trench device isolation layer by a predetermined depth by use of a first mask layer pattern, to form a plurality of first and second trench device isolation layers arranged alternately with each other, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height;
removing the hard mask layer pattern;
etching the active regions by a predetermined depth by use of a second mask layer pattern, to form a recess region in each of the active regions, the recess region having a stepped profile at a boundary portion thereof and an upwardly protruded portion between adjacent two second trench device isolation layers;
forming a gate insulation layer; and
forming a plurality of gate stacks on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
Preferably, the hard mask layer pattern may include a pad oxide layer pattern having a thickness of 100 Å to 200 Å, and a pad nitride layer pattern having a thickness of 2000 Å to 800 Å, which are laminated in this sequence.
Preferably, the device isolation trenches may be formed to have a depth of 2000 Å to 4000 Å.
Preferably, the etching of the trench device isolation layer using the first mask layer pattern may be performed to remove two thirds of the entire thickness of the trench device isolation layer.
Preferably, the etching of each active region using the second mask layer pattern may be performed such that the resulting recess region has a depth equal to one third of the first thickness of the first trench device isolation layers.
Preferably, the formation of the gate stacks may be performed by use of the first mask layer pattern.
Preferably, each of the gate stacks may include a doped poly-silicon layer having a thickness of 400 Å to 700 Å, and a tungsten-silicide layer having a thickness of 1000 Å to 1500 Å.
The invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
A preferred embodiment of the invention will be explained in detail with reference to the accompanying drawings. The preferred embodiment of the invention may be modified into various different forms, and the scope of the invention is not intended to be limited by the following description of the preferred embodiment.
Referring to
As shown in
A gate insulation layer 102 is laminated on a semiconductor substrate over the active regions 110. The gate insulation layer 102 may be made of an oxide layer having a thickness of about 30 Å to about 50 Å, or may be made of an insulation material having a high dielectric constant, such as for example, alumina (Al2O3). Then, a plurality of gate stacks 130 are laminated on the gate insulation layer 102. Specifically, each of the gate stacks 130 is overlapped with the stepped profile of the relevant active region 110, and has a stripe form crossing the active region 110. The gate stack 130 includes a gate conductive layer pattern 131, and a hard mask layer pattern 132, which are laminated in this sequence. In turn, the gate conductive layer pattern 131 illustratively includes a polysilicon layer pattern having a thickness of about 400 Å to about 700 Å, and a tungsten-silicide layer pattern having a thickness of about 1000 Å to about 1500 Å, which are laminated in this sequence. Of course, other conductive layers may be used to form the gate conductive layer pattern 131. Also, the hard mask layer pattern 132 is illustratively formed of a nitride layer pattern.
The transistor having the above described configuration has a structure, which integrates the structure of a transistor having the stepped profile as shown in
Referring first to
Next, the photoresist layer pattern is removed, and the device isolation region of the semiconductor substrate is etched by using the hard mask layer pattern 200 as an etching mask, to form a plurality of device isolation trenches T. In this case, the etching depth of the device isolation region is, for example, in a range from about 2000 Å to about 4000 Å. After forming the device isolation trenches T, an insulation layer, for example, high density plasma (HDP) oxide layer, is laminated to fill up the trenches T. Then, a conventional flattening process is performed to expose an upper surface of the hard mask layer pattern 200, to form the trench device isolation layer 120 that defines the active regions 110.
Referring next to
Referring to
Referring to
Referring to
Then, a conventional gate stack forming process is performed. Specifically, a gate oxide layer, gate conductive layer, and hard mask layer are laminated in this sequence. The gate oxide layer has a thickness of about 30 Å to about 50 Å. The gate conductive layer includes a poly-silicon layer having a thickness of 400 Å to 700 Å, and a tungsten-silicide layer having a thickness of 100 Å to 1500 Å, which are laminated in this sequence. The hard mask layer may be formed of a nitride layer. In succession, a patterning process using a certain mask layer pattern is performed, whereby each of the gate stacks 130 is formed to overlap with the relevant stepped profile as shown in
As apparent from the above description, the invention provides a transistor of a semiconductor memory device having a structure, which integrates the structure of a transistor having a stepped profile and the structure of a fin field effect transistor. Therefore, in addition to advantages of the fin field effect transistor, for example, good On/Off characteristics, high current drive ability, and low back-bias dependency, the transistor can achieve an improvement in various characteristics, including a reduced source of current leakage with respect to bonding and an improved data retention time, by virtue of the structure of the transistor having a stepped profile.
Further, the invention provides a method for manufacturing a transistor of a semiconductor memory device, which can shield the entire region of a semiconductor substrate, except for a channel ion injection region, by use of a device isolation layer, thereby enabling local injection of channel ions within a limited region where a channel is formed. As a result, the channel can be formed without the risk of junction overlap, and thus, the quantity of leaked current can be reduced. Also, in accordance with the transistor manufacturing method of the invention, when a gate stack is formed, a thickness difference between a poly-silicon layer and a tungsten silicide layer, which are located between a bit line contact and a storage node contact, can be restricted. This has the effect of preventing the generation of gate leaning during a subsequent heat treatment.
Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.
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