A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
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14. A device comprising:
a first semiconductor fin over a substrate;
a first gate dielectric on sidewalls of the first semiconductor fin;
a first gate electrode over the first gate dielectric;
a Shallow trench isolation (sti) region at least partially overlapped by the first gate electrode;
a first source/drain region on a side of the first gate electrode;, wherein the first semiconductor fin extends into the first source/drain region, the first source/drain region comprising:
a first portion of the first semiconductor fin, wherein the first portion of the first semiconductor fin extends above a top surface of the sti region; and
a semiconductor capping layer on a top surface and sidewalls of the first portion of the first semiconductor fin, wherein the semiconductor capping layer is made of a material different from a material of the substrate; and
a first dislocation plane in the first source/drain region; and
a Shallow trench isolation (sti) region comprising a portion overlapped by a portion of the first gate electrode, wherein an entirety of the first dislocation plane is higher than a top surface of the sti region, wherein an entirety of the first dislocation plane is higher than a top surface of the sti region, wherein a portion of the first dislocation plane overlaps the sti region.
7. A device comprising:
a semiconductor fin over a substrate;
a gate dielectric on sidewalls of the semiconductor fin;
a gate electrode over the gate dielectric;
a Shallow trench isolation (sti) region comprising a portion overlapped by a portion of the gate electrode and adjoining the semiconductor fin;
a source region and a drain region on opposite sides of the gate electrode, wherein the sti region is located substantially between the source region and the drain region, wherein the semiconductor fin extends into the source region and the drain region, the source region and the drain region each comprising:
a first portion of the semiconductor fin; and
a semiconductor capping layer on a top surface and sidewalls of the first portion of the semiconductor fin;
a first dislocation plane extending into the source region; and
a second dislocation plane extending into the drain region, wherein at least a first portion of each of the first dislocation plane and the second dislocation plane is over a top surface of the sti region, wherein a second portion of each of the first dislocation plane and the second dislocation plane overlap the sti region.
0. 20. A device comprising:
a first semiconductor fin over a substrate;
a first gate dielectric on sidewalls of the first semiconductor fin;
a first gate electrode over the first gate dielectric;
a first source/drain region on a side of the first gate electrode, the first source/drain region comprising:
a semiconductor capping layer directly contacting the first semiconductor fin, the semiconductor capping layer comprising a first material, wherein the first material is different from a material of the substrate;
a first semiconductor region over the semiconductor capping layer, the first semiconductor region comprising a second material different from the first material; and
a second semiconductor region over a top and side of the first semiconductor region, the second semiconductor region comprising a third material different from the first material, wherein the second semiconductor region has a higher concentration of dopants than the first semiconductor region and the semiconductor capping layer;
a first dislocation plane in the first source/drain region; and
a Shallow trench isolation (sti) region adjacent the first semiconductor fin, wherein the first dislocation plane comprises a first portion higher than a top surface of the sti region, and a second portion lower than the top surface of the sti region.
0. 35. A device comprising:
a substrate having a fin structure, the fin structure having a mesa and a plurality of fins extending from the mesa;
a Shallow trench isolation (sti) region extending along sidewalls of the mesa and over the mesa between adjacent ones of the plurality of fins;
a gate structure extending over the plurality of fins; and
a first source/drain region and a second source/drain region on opposing sides of the gate structure, the first source/drain region having a first dislocation plane, the first dislocation plane extending into an underlying semiconductor material of the substrate, the first source/drain region comprising:
a first semiconductor layer made of a first material, wherein the first material is different from a material of the substrate, wherein the first semiconductor layer is in direct contact with one of the plurality of fins;
a first epitaxy region over the first semiconductor layer, the first epitaxy region comprising a second material different from the first material; and
a second epitaxy region, wherein the second epitaxy region is over a top and side of the first epitaxy region, wherein the second epitaxy region comprises a third material different from the first material, wherein the second epitaxy region has a higher concentration of dopants than the first semiconductor layer and the first epitaxy region.
1. A device comprising:
a first semiconductor fin over a substrate;
a first gate dielectric on sidewalls of the first semiconductor fin;
a first gate electrode over the first gate dielectric;
a first source/drain region on a side of the first gate electrode;, the first source/drain region comprising:
a semiconductor capping layer directly contacting the first semiconductor fin, the semiconductor capping layer comprising a first material, wherein the first material is different from a material of the substrate;
a first semiconductor region over the semiconductor capping layer, wherein the first semiconductor region comprises a second material different from the first material; and
a second semiconductor region over a top and side of the first semiconductor region, the second semiconductor region comprising a third material different from the first material, wherein the second semiconductor region has a higher concentration of dopants than the semiconductor capping layer and the first semiconductor region;
a first dislocation plane in the first source/drain region; and
a Shallow trench isolation (sti) region comprising a first portion overlapped by a portion of the first gate electrode, wherein the first dislocation plane comprises a first portion higher than a top surface of the sti region, and a second portion lower than the top surface of the sti region.
0. 24. A device comprising:
a substrate having a fin structure, the fin structure having a base portion and a plurality of upper portions extending from the base portion;
a Shallow trench isolation (sti) region extending along sidewalls of the base portion and over the base portion between adjacent ones of the plurality of upper portions;
a gate structure extending over the plurality of upper portions; and
a first source/drain region and a second source/drain region on opposing sides of the gate structure, the first source/drain region having a first dislocation plane, the first dislocation plane extending above an upper surface of the sti region, the first source/drain region comprising:
a first semiconductor layer made of a first material, wherein the first material is different from a material of the substrate, wherein the first semiconductor layer is in direct contact with one of the plurality of upper portions;
a second semiconductor layer over the first semiconductor layer, the second semiconductor layer comprising a second material different from the first material; and
a third semiconductor layer over a top and side of the second semiconductor layer, the third semiconductor layer comprising a third material different from the first material, wherein the third semiconductor layer has a higher concentration of dopants than the second semiconductor layer and the first semiconductor layer.
2. The device of
3. The device of
a second semiconductor fin over the substrate and parallel to the first semiconductor fin;
a second gate dielectric on sidewalls of the second semiconductor fin;
a second gate electrode over the second gate dielectric, wherein the first and the second gate electrodes are interconnected to form a continuous gate electrode;
a second source/drain region on a side of the second gate electrode, wherein the first and the second source/drain regions are interconnected to form a continuous source/drain region; and
a second dislocation plane in the second source/drain region.
4. The device of
5. The device of
6. The device of
8. The device of
9. The device of
an additional semiconductor fin over the substrate and adjacent to the semiconductor fin, wherein the semiconductor fin and the additional semiconductor fin are on opposite sides of an entirety of the sti region, and wherein the gate electrode extends over the additional semiconductor fin.
10. The device of
11. The device of
12. The device of
13. The device of
15. The device of
16. The device of
a second semiconductor fin over the substrate and parallel to the first semiconductor fin;
a second gate dielectric on sidewalls of the second semiconductor fin;
a second gate electrode over the second gate dielectric, wherein the first and the second gate electrodes are interconnected to form a continuous gate electrode;
a second source/drain region on a side of the second gate electrode, wherein the first and the second source/drain regions are interconnected to form a continuous source/drain region; and
a second dislocation plane in the second source/drain region.
17. The device of
18. The device of
19. The device of
0. 21. The device of claim 20, wherein the first dislocation plane has a bottom higher than a bottom surface of the sti region.
0. 22. The device of claim 20 further comprising:
a second semiconductor fin over the substrate and parallel to the first semiconductor fin;
a second gate dielectric on sidewalls of the second semiconductor fin;
a second gate electrode over the second gate dielectric, wherein the first and the second gate electrodes are interconnected to form a continuous gate electrode;
a second source/drain region on a side of the second gate electrode, wherein the first and the second source/drain regions are interconnected to form a continuous source/drain region; and
a second dislocation plane in the second source/drain region.
0. 23. The device of claim 22, wherein the sti region is free from substantial portions overlapped by the continuous source/drain region.
0. 25. The device of claim 24, wherein the second source/drain region has a second dislocation plane.
0. 26. The device of claim 25, wherein the second dislocation plane extends above an upper surface of the sti region.
0. 27. The device of claim 25, wherein outer portions of the first dislocation plane is farther away from the gate structure are higher than inner portions of the first dislocation plane closer to the gate structure, and wherein outer portions of the second dislocation plane is farther away from the gate structure are higher than inner portions of the second dislocation plane closer to the gate structure.
0. 28. The device of claim 24, further comprising a gate spacer adjacent the gate structure, wherein the first dislocation plane extends below the gate spacer.
0. 29. The device of claim 28, wherein the first dislocation plane has a bottom higher than a bottom surface of the sti region.
0. 30. The device of claim 24, wherein the first dislocation plane terminates between a first distance under the gate structure of 4 nm or less from an edge of the gate structure and a second distance of 12 nm or less laterally spaced apart from the edge of the gate structure.
0. 31. The device of claim 24, wherein the sti region extends partially over an upper surface of the base portion of the fin structure.
0. 32. The device of claim 24, wherein an entirety of the first dislocation plane is above the upper surface of the sti region.
0. 33. The device of claim 24, wherein the first source/drain region and the second source/drain region comprise a different semiconductor material than the substrate.
0. 34. The device of claim 33, wherein the first source/drain region extends directly over a portion of the sti region.
0. 36. The device of claim 35, wherein the plurality of fins do not extend into the first source/drain region and the second source/drain region.
0. 37. The device of claim 35, wherein the first dislocation plane extends higher than an upper surface of the sti region.
0. 38. The device of claim 35, wherein the first dislocation plane extends under a gate spacer adjacent the gate structure.
0. 39. The device of claim 35, wherein a height of the plurality of fins in the first source/drain region and the second source/drain region is less than a height of plurality of fins under the gate structure.
0. 40. The device of claim 39, wherein the sti region extends between the plurality of fins in the first source/drain region and the second source/drain region.
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This application is a reissue application of U.S. Pat. No. 8,866,235.
To enhance the performance of metal-oxide-semiconductor (MOS) devices, stresses may be introduced into the channel regions of the MOS devices to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type MOS (“PMOS”) device in a source-to-drain direction. Techniques for improving the stresses in the MOS devices are thus explored.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
A Fin Field-Effect Transistor (FinFET) with dislocation planes therein and the method of forming the same are provided in accordance with various embodiments. The intermediate stages of forming the FinFET are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Referring to
Referring to
Referring to
Referring to
Referring to
In some other embodiments, the recessing step for forming recesses 270 (
Referring to
When the step shown in
Referring to
As a result of PAI 261, as shown in
Referring to
Referring to
As the result of the annealing, dislocation planes 157 (
Next, an etch step is performed, and strained capping layer 181 is removed. In the embodiments in which the step in
As also shown in
A second epitaxy is performed to form stressors 300 on un-doped epitaxy semiconductor layers 290. Similarly, stressors 300 may comprise silicon germanium or silicon carbon when the respective FinFET 440 is a p-type FinFET or an n-type FinFET, respectively. Accordingly, stressors 300 may apply a compressive stress or a tensile stress to the channel region of FinFET 440. Stressors 300 may be doped heavily with a p-type or an n-type impurity, wherein the doping concentration may be between about 5×1019/cm3 and about 3×1021/cm3. During the first and the second epitaxy steps, dislocation planes 157 grow into un-doped epitaxy semiconductor layers 290 and stressors 300, respectively.
In the embodiments shown in
The embodiments of the present disclosure may be applied to various types of FinFETs, including, and not limited to, depletion mode FinFETs, accumulation mode FinFETs, and the like. One of ordinary skill in the art will realize the respective structures.
In accordance with embodiments, a device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
In accordance with other embodiments, a device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and an STI region having a portion overlapped by a portion of the gate electrode and adjoining the semiconductor fin. A source region and a drain region are disposed on opposite sides of the gate electrode, wherein the STI region is located substantially between the source region and the drain region. A first dislocation plane extends into the source region. A second dislocation plane extends into the drain region.
In accordance with yet other embodiments, a method includes forming a gate dielectric on sidewalls of a middle portion of a semiconductor fin, forming a gate electrode over the gate dielectric, forming a source/drain region on a side of the gate electrode, and forming a strained capping layer. The strained capping layer includes a portion overlapping the gate electrode. After the step of forming the strained capping layer, an annealing is performed to form a dislocation plane in a semiconductor material underlying the strained capping layer. After the annealing, the strained capping layer is removed.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Wu, Zhiqiang, Diaz, Carlos H., Hsieh, Wen-Hsing, Shen, Tzer-Min, Cheng, Ya-Yun, Chen, Hua Feng, Wu, Ting-Yun
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