Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (rf) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the rf circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The rf circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the rf circuitry occurs at frequencies which are harmonics of the carrier signal.
|
0. 12. Circuitry comprising:
two or more oscillators;
a clock generator coupled to the oscillators;
first digital circuitry coupled to the clock generator; and
second digital circuitry coupled to the clock generator;
wherein the clock generator comprises a selector, a first frequency divider, and a second frequency divider,
wherein the first frequency divider and the second frequency divider are coupled to the oscillators,
wherein the first frequency divider is configured to provide a first clock signal to the first digital circuitry,
wherein the second frequency divider is configured to provide a second clock signal to the second digital circuitry,
wherein the selector is configured to select which of the two or more oscillators is used as a source to generate the first clock signal and the second clock signal, and comprises a monitor to monitor stability of signals from the oscillators.
8. A method of generating a digital clock for clocking digital circuitry associated with any of a transceiver, a transmitter, and a receiver, the method comprising:
generating a carrier signal for radio frequency (rf) circuity, wherein the rf circuitry is susceptible to interference from harmonics of the clocking of the digital circuitry;
deriving a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal such that the interference to the rf circuitry occurs at frequencies which are harmonics of the carrier signal;
programming one or more programmable frequency dividers to alter the frequency of the digital clock;
estimating a digital clock frequency needed by a respective type of digital receiver processing to achieve a predetermined minimum signal to noise ratio for a signal being received;
determining whether the interference caused by that estimated digital clock frequency is within an acceptable threshold; and
selecting a change in frequency for the digital clock based on whether the interference caused by the estimated clock frequency is within the acceptable threshold.
1. Circuitry for any of a transceiver, a transmitter, and a receiver, the circuitry comprising:
radio frequency (rf) circuitry;
digital circuitry;
a carrier signal generator;
a clock generator to generate a digital clock for clocking the digital circuitry; and
a fallback oscillator,
wherein the rf circuitry is susceptible to interference from harmonics of the clocking of the digital circuitry,
wherein the carrier signal generator is coupled to provide a carrier signal to the rf circuitry,
wherein the clock generator is arranged to derive a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal such that the interference to the rf circuitry occurs at frequencies that are harmonics of the carrier signal, wherein the fallback oscillator generates a fallback reference frequency,
wherein the clock generator has a fallback selector to select the fallback reference frequency as a source from which to generate the digital clock when the carrier frequency is not suitable, wherein the fallback selector has a monitor to monitor a stability of the carrier signal, and
wherein the fallback selector is operable to select the fallback reference frequency depending on the stability of the carrier signal.
7. Circuitry for any of a transceiver, a transmitter, and a receiver, the circuitry comprising:
radio frequency (rf) circuitry;
digital circuitry;
a carrier signal generator; and
a clock generator to generate a digital clock for clocking the digital circuitry,
wherein the rf circuitry is susceptible to interference from harmonics of the clocking of the digital circuitry,
wherein the carrier signal generator is coupled to provide a carrier signal to the rf circuitry,
wherein the clock generator is arranged to derive a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal such that the interference to the rf circuitry occurs at frequencies that are harmonics of the carrier signal,
wherein the clock generator has a controller to select a change in frequency of the digital clock based on a quality of an output of digital processing of received or transmitted signals clocked by the digital clock and based on the interference caused by the clocking, and
wherein the controller is configured to:
estimate a digital clock rate needed by a respective type of digital receiver processing to achieve a predetermined minimum signal to noise ratio for a signal being received; and
determine whether the interference caused by that estimated digital clock rate is within an acceptable threshold as a basis for selecting a change in frequency for the digital clock.
2. The circuitry of
3. The circuitry of
two or more oscillators to generate the carrier signal at different carrier frequencies; and
a selector to select which of the carrier frequencies is used as a source to generate the digital clock.
4. The circuitry of
5. The circuitry of
6. The circuitry of
9. The method of
generating two or more carrier signals at different carrier frequencies; and
selecting which of the carrier frequencies is used as a source to generate the digital clock.
10. The method of
11. The method of
0. 13. The circuitry of claim 12, further comprising radio frequency (rf) circuitry, wherein one of the oscillators is configured to provide a carrier signal to the rf circuitry.
0. 14. The circuitry of claim 12, wherein the first digital circuitry further comprises an analog-to-digital converter (ADC), and wherein the second digital circuitry comprises a digital-to-analog converter (DAC).
|
This application is a Reissue Application of patent application Ser. No. 14/194,956 filed on Mar. 3, 2014, now U.S. Pat. No. 9,655,130, which is a continuation of International Application No. PCT/EP2012/066951, filed on Aug. 31, 2012, which claims priority to British Patent Application No. GB1115119.8, filed on Sep. 1, 2011, all of which are hereby incorporated by reference in their entireties.
Not applicable.
Not applicable.
The present invention relates to circuitry for any of a transceiver, receiver and transmitter, and having digital circuitry and having radio frequency (RF) circuitry susceptible to interference from the harmonics of the clocking of the digital circuitry. It can be applied generally to digital communication techniques and radio transceivers. More specifically, some embodiments involve dynamically selecting the frequencies of clock signals used in a radio system.
The rapid global spread of modern cellular communication systems has been primarily driven by three factors: standardisation, cost and performance. The availability of universal communication standards promulgated by organisations such as 3rd Generation Partnership Project (3GPP) allows manufacturers to produce a single product for a global market. The low cost of cellular communications is primarily due to the high levels of functional integration achievable in modern microchip technology and the size of the global market which offers significant economy of scale benefits to manufacturers. The high performance of cellular communications is achieved through exploitation of the functional capabilities of modern semiconductor technology.
Increased functional integration in a radio transceiver leads to the analog and digital functions of the radio transceiver being closely located to each other. It is well known in the prior art that reduced physical separation between radio circuit components leads to an increase in mutual self-interference. Typically, a digital clock will consist of a train of rectangular pulses and will be rich in harmonic content. The integration of digital circuit elements which utilise a digital clock can therefore lead to radio frequency (RF) interference at harmonic frequencies of the digital clock. Typically, the transceiver will be most vulnerable to this type of interference when it tries to receive low power signals at RF frequencies at or close to harmonics of any digital clock used in the transceiver.
Modern cellular radio transceivers are required to operate in a plurality of frequency bands. It is also necessary for a modern transceiver to achieve the desired performance levels required by standards such as 3GPP, and it is therefore necessary for the modern transceiver to contain a significant digital signal processing capability. Furthermore, as it is expensive and time consuming to develop a radio transceiver in an advanced semiconductor manufacturing process, it is a desirable requirement that a radio transceiver be sufficiently flexible to operate in frequency bands that might in the future be designated as cellular bands by the standardisation authorities.
U.S. Pat. No. 5,926,514 discloses changing a clock signal used by a microcontroller unit in a radio transceiver in response to changes in the operating frequency of the radio transceiver.
U.S. Pat. No. 7,103,342 discloses changing a clock signal used by a microcontroller unit in a radio transceiver in order to minimise interference at the selected operating frequency of the radio transceiver.
U.S. Pat. No. 6,898,420 discloses toggling a clock signal used by a microcontroller between two possible frequencies.
U.S. Pat. No. 7,676,192 discloses a technique to change the operating frequency of a device and the signal frequency of a co-located signal source in order to minimise interference that is introduced on the wireless interface of that device.
There remains a need for techniques which can be employed to address the impact of clock harmonic interference in a radio transceiver.
An object of the present invention is to provide alternative circuitry for radio wireless systems, especially transceivers for radio wireless systems with an enhanced immunity to clock harmonic interference.
According to a first aspect of the invention, there is provided circuitry for any of a transceiver, a transmitter, and a receiver, and having RF circuitry, digital circuitry, a carrier signal generator and a clock generator for generating a digital clock for clocking at least some of the digital circuitry, the RF circuitry being susceptible to interference from harmonics of the clocking of the digital circuitry, the carrier signal generator being coupled to provide a carrier signal to the RF circuitry, and the clock generator being arranged to derive a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.
Since any interference from harmonics of the digital clock are at frequencies which are harmonics of the carrier, they can be compensated more easily, or can be arranged to have frequencies far enough away from useful parts of the RF signals to be filtered out more easily. The digital circuitry can encompass analog-to-digital converter (ADC), digital-to-analog converter (DAC), or digital processing circuitry in a receiver or transmitter chain for example. References to digital can encompass discrete time clocked analog for example. The transceiver example is for use in communications applications for example, though one way radio applications include global positioning system (GPS) receivers for example.
Embodiments of the invention can have any other features added, or any other features disclaimed. Some such additional features are set out in dependent claims and described in more detail below.
Another aspect provides a corresponding method of generating a digital clock for clocking digital circuitry associated with any of a transceiver, a transmitter, and a receiver, and the method having the steps of generating a carrier signal for RF circuitry, the RF circuitry being susceptible to interference from harmonics of the clocking of the digital circuitry, and deriving a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.
Embodiments of the present invention can provide novel implementations of radio wireless communication systems. Its advantages are particularly useful for communication systems involved in simultaneously transmitting and receiving RF signals.
Some additional features are as follows.
The clock generator can have one or more programmable frequency dividers to generate the digital clock. With reference to
The clock generator can have two or more oscillators for generating the carrier signal at different carrier frequencies, and have a selector for selecting which of the carrier frequencies is used as a source to generate the digital clock. With reference to
The circuitry can have a fallback oscillator for generating a fallback reference frequency, and the clock generator can have a fallback selector to select the fallback reference frequency as a source from which to generate the digital clock if the carrier frequency is not suitable. With reference to
The fallback selector can have a monitor for monitoring a stability of the carrier signal, and can be operable to select the fallback reference frequency depending on the monitor output. With reference to
The clock generator can have a controller for selecting a change in frequency of the digital clock, based on a quality of an output of digital processing of received or transmitted signals clocked by the digital clock and based on the interference caused by the clocking. With reference to
The controller can be arranged to estimate a digital clock rate needed by a respective type of digital receiver processing to achieve a predetermined minimum signal to noise ratio for a signal being received, and to determine whether the interference caused by that estimated digital clock rate is within an acceptable threshold, as a basis for selecting a change in frequency for the digital clock. This can be useful for example where downstream processing relies on a given minimum noise. It can take into account that the error-free decoding of higher order modulations requires a certain signal-to-noise and distortion ratio (SINAD) out of the transceiver and reassigns the SINAD contribution of clock-related interference to be relatively higher in favor of enhanced processing speed.
The circuitry can have a digital compensation circuit for digitally compensating at least some of the digital processing circuitry clocked by the digital clock, based on a change in the frequency of the digital clock. With reference to
The circuitry can be part of an integrated circuit. This can enable a cost reduction from more integration, but the interference can be more critical. The circuitry or the integrated circuit can be part of a mobile device such as a mobile phone or hand held computing device.
The method can have additional steps corresponding to the additional features set out above. There can be a step of programming one or more programmable frequency dividers to alter the frequency of the digital clock. The method can have the step of generating two or more carrier signals at different carrier frequencies, and selecting which of the carrier frequencies is used as a source to generate the digital clock. There can be steps of estimating a digital clock frequency needed by a respective type of digital receiver processing to achieve a predetermined minimum signal to noise ratio for a signal being received, determining whether the interference caused by that estimated digital clock frequency is within an acceptable threshold, and based on this determination, selecting a change in frequency for the digital clock. There can be a step of resampling a digital signal used by the digital circuitry by a ratio inversely proportional to the change in frequency of the digital clock. Another step can be compensating for the interference in the RF circuitry from the harmonics of the clocking of the digital circuitry.
Any of the additional features can be combined together and combined with any of the aspects. Other advantages will be apparent to those skilled in the art, especially over other prior art. Numerous variations and modifications can be made without departing from the claims of the present invention. Therefore, it should be clearly understood that the form of the present invention is illustrative only and is not intended to limit the scope of the present invention.
How the present invention may be put into effect will now be described by way of example with reference to the appended drawings, in which:
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Where the term “comprising” is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun e.g. “a” or “an”, “the”, this includes a plural of that noun unless something else is specifically stated.
The term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and. B.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
The invention will now be described by a detailed description of several embodiments of the invention. It is clear that other embodiments of the invention can be configured according to the knowledge of persons skilled in the art without departing from the technical teaching of the invention, the invention being limited only by the terms of the appended claims.
Introduction,
By way of introduction to the embodiments, an arrangement corresponding to known systems will be described with reference to
Some embodiments of the invention help enable a radio transceiver to operate in the possible presence of a harmonic interference from one or more clock signals without degrading performance when the clock harmonic interference is not present. The radio transceiver can be made sufficiently robust in the presence of this interference to maintain the required level of performance.
A carrier signal generation part 80 feeds a local carrier signal 47 to the receiver RF circuitry 70. The carrier signal generation part 80 also generates a local carrier signal 46 for the transmitter side of the transceiver. A selected one of the carrier signals is also sent to a clock generator part 90, for generating one or more digital clocks derived by dividing down the selected carrier frequency. In the example shown, the digital clocks derived in this way are used for the ADC, DAC as well as the digital processor. In some cases other digital circuitry within the radio transceiver can be clocked in this way from one or other of the transmitter or receiver carrier signals. Generating the digital clocks (152, 153 and 151 respectively) in this fashion guarantees that any clock harmonic interference that occurs will be located at the same frequency as the selected carrier signal. Interference occurring at this location is similar to direct current (DC) offset in the baseband signal for which many compensating techniques are known in the prior art. By extension, the method may also target the clock harmonic interference at frequencies that are benign from a radio point of view, for instance due to filter attenuation in other places in the system and/or due to more relaxed spectrum restrictions, without loss of generality.
There is also a reference clock part 110, for generating a reference clock to provide as a stable frequency reference source 011 for the carrier generation, and a backup signal 111 for the clock generator 90. The transmitter side includes a DAC 250, transmitter baseband circuitry 50, and transmitter RF circuitry 40, which uses the transmitter local carrier 46, and feeds transmit antenna 72. Examples of how to implement the carrier signal generation part 80 and clock generator part 90 will be described with reference to
Reference clock generator 110 delivers a reference clock signal to the input of VCO1 frequency control 180 which can be implemented as shown in
LO frequency divider units 210, 220 and 230 are subsidiary components of LO divider network 150 with intermediate signals 205 and 215 being available as shown here. Carrier signal 145 is frequency divided using LO1 frequency divider 210 producing intermediate signal 205. Signal 205 is further frequency divided using LO2 frequency divider 220 producing intermediate signal 215. Finally, signal 215 is frequency divided using LO3 frequency divider 230 producing final digital clock signals 151, 152 and 153, which need not be the same frequency but are all derived from the carrier. In this figure, 153 is an example of the digital clock signal sent to digital circuitry associated with the receiver, transmitter or transceiver. Examples of such digital circuitry are DAC 250 and ADC 260. Another example of the digital clock is signal 152, which is the digital clock signal for ADC 260. Digital clock signal 151 is sent to fallback control unit 240. Fallback control unit 240 also receives signal 111 from the reference clock generator. Signal 241, which is the output of fallback control unit 240, is used as the clock signal for microcontroller 160. More details of how to implement the fallback control part will be described below with reference to
Signal 151 is used as a clock for microcontroller 160 and other digital logic within the transceiver, signal 152 is used as a sampling clock for ADC 260 and signal 153 is used as a sampling clock for DAC 250. Signals 151, 152 and 153 are all derived from signal 145, which is also used as an RF carrier signal by the transceiver, therefore provided all the divisors implemented within blocks 140, 210, 220 and 230 are individually integers not fractions, then any clock harmonic interference caused by signals 151, 152 or 153 will be seen at the RF carrier frequency. This relationship between the frequency of clock harmonic interference and the carrier signal frequency will remain even if the frequency of the carrier signal changes. Therefore, it becomes possible to change the carrier signal frequency and still compensate the clock harmonic interference in the same way.
After starting at terminal step 910, step 920 determines the current frequency of LO signal 145. In step 930, the target clock frequencies for ADC 152, DAC 353 and digital clock 151 are read. In step 940, the frequency divider setting Nadc is chosen to meet the constraint in step 940 subject to Nadc being implementable as a divisor from the combination of frequency dividers 210, 220 and 230. In step 950, the frequency divider setting Ndac is chosen to meet the constraint in step 950 subject to Ndac being implementable as a divisor from the combination of frequency dividers 310, 320 and 330. In step 960, the frequency divider setting Ndig is chosen to meet the constraint in step 960 subject to Ndig being implementable as a divisor from the combination of frequency dividers 210, 220 and 230.
In some cases, the microcontroller 160 will take into account link layer parameters such as data rate, modulation order, channel code strength and so on in order to optimize the clock frequencies for ADC sampling clock 152, DAC sampling clock 353 and digital clock 151. The generation of the clocks can take into account the required input signal-to-noise ratio (SNR) as a function of the link layer control parameters. For example, it can take into account that the error-free decoding of higher order modulations requires a certain SINAD out of the transceiver and reassigns the SINAD contribution of clock-related interference to be relatively higher in favor of enhanced processing speed.
When the received power level of the desired signal is high, then the influence of ADC noise on the ability of the receiver to recover information from the desired signal is small. Therefore in this scenario, the ADC sampling rate can be reduced with little or no impact on receiver performance. This can provide a benefit in the form of reduced power consumption by the ADC which leads to longer battery life in portable devices. When the received power level of the desired signal is low—a condition typically referred to as the sensitivity case, the ADC noise is a relatively more significant influence on receiver performance. In this scenario, it is therefore desirable to operate the ADC at the highest sampling rate.
Analog signal 1001 is converted to a digital signal by ADC 260 using a sampling clock 152. Digital filter 1010 performs digital filtering operations at the same sampling rate as ADC 260. Resampling filter 1020 resamples the output of filter 1010 into a new signal 1031. The sampling rate adjustment effected by resampling filter 1020 is controlled by signal 1011, which comes from microcontroller 160. Digital filter 1030 performs digital filtering operations at the same sampling rate as signal 1031. Analog signal 1061 is created from a digital signal by DAC 250 using a sampling clock 353. Digital filter 1060 performs digital filtering operations at the same sampling rate as DAC 250. Resampling filter 1050 resamples the output of filter 1040 into a new signal 1041. The sampling rate adjustment effected by resampling filter 1050 is controlled by signal 1051 which comes from microcontroller 160. Digital filter 1040 performs digital filtering operations at the same sampling rate as signal 1071.
At step 1165, a frequency of ADC clock 152 is read in. At step 1175, a sampling rate of signal 1031 is read in. At step 1185, a ratio of ADC sampling rate and signal 1031 sampling rate is calculated. At step 1195, the resampling filter 1020 is programmed using control signal 1011.
Numerous modifications, changes, variations, substitutions, and equivalents will occur to those skilled in the art without departing from the claims.
Vandenameele, Patrick, Beamish, Norman
Patent | Priority | Assignee | Title |
11277819, | Jan 21 2019 | HUAWEI TECHNOLOGIES CO , LTD | Method and apparatus for sidelink transmission and resource allocation |
11310822, | Nov 02 2018 | HUAWEI TECHNOLOGIES CO , LTD | Methods and apparatus for sidelink communications and resource allocation |
11765746, | Nov 02 2018 | Huawei Technologies Co., Ltd. | Methods and apparatus for sidelink communications and resource allocation |
Patent | Priority | Assignee | Title |
5926514, | Mar 03 1997 | MOTOROLA SOLUTIONS, INC | Apparatus for clock shifting in an integrated transceiver |
6628968, | Nov 02 2000 | CLUSTER, LLC; Optis Wireless Technology, LLC | Providing timing reference for radio heads |
6898420, | Aug 23 2002 | Google Technology Holdings LLC | Method and apparatus for avoiding spurious signal receiver desensitizing |
7103342, | Nov 29 2001 | Kyocera Corporation | System and method for reducing the effects of clock harmonic frequencies |
7580691, | Aug 02 2005 | HUAWEI TECHNOLOGIES CO , LTD | System and method for reducing self interference |
7620131, | Nov 22 2005 | SIGMATEL, LLC | Digital clock controller, radio receiver, and methods for use therewith |
7676192, | Dec 21 2005 | General Wireless IP Holdings LLC; GENERAL WIRELESS OPERATIONS INC | Radio scanner programmed from frequency database and method |
7949015, | Aug 28 2006 | TELEFONAKTIEBOLAGET LM ERICSSON PUBL | Clock skew compensation |
8306524, | Dec 08 2009 | LG Electronics Inc. | Mobile terminal with camera clock frequency control |
8488568, | Jun 02 2010 | WI-LAN INC | Method and system of interferer signal detection |
8548104, | Nov 23 2010 | SHENZHEN XIN SINUO TECHNOLOGY PARTNERSHIP LIMITED PARTNERSHIP | Receiver with configurable clock frequencies |
8599825, | Sep 29 2008 | Samsung Electronics Co., Ltd. | System clock synchronization apparatus and method for mobile communication system |
20010040932, | |||
20010047325, | |||
20010055354, | |||
20020142745, | |||
20070011482, | |||
20070116148, | |||
20070165747, | |||
20080024339, | |||
20080025379, | |||
20090003496, | |||
20090080498, | |||
20090221235, | |||
20100002683, | |||
20110075721, | |||
20110136475, | |||
CN101204055, | |||
CN101335531, | |||
CN101383613, | |||
CN101506754, | |||
CN101803218, | |||
CN101960720, | |||
CN1309835, | |||
CN1518804, | |||
CN1897464, | |||
JP2009118149, | |||
JP2010050780, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 15 2019 | Huawei Technologies Co., Ltd. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
May 15 2019 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Oct 30 2024 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Date | Maintenance Schedule |
Dec 29 2023 | 4 years fee payment window open |
Jun 29 2024 | 6 months grace period start (w surcharge) |
Dec 29 2024 | patent expiry (for year 4) |
Dec 29 2026 | 2 years to revive unintentionally abandoned end. (for year 4) |
Dec 29 2027 | 8 years fee payment window open |
Jun 29 2028 | 6 months grace period start (w surcharge) |
Dec 29 2028 | patent expiry (for year 8) |
Dec 29 2030 | 2 years to revive unintentionally abandoned end. (for year 8) |
Dec 29 2031 | 12 years fee payment window open |
Jun 29 2032 | 6 months grace period start (w surcharge) |
Dec 29 2032 | patent expiry (for year 12) |
Dec 29 2034 | 2 years to revive unintentionally abandoned end. (for year 12) |