Methods of metal assisted chemical etching iii-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a iii-V semiconductor. At least a portion of the iii-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

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Patent
   RE48407
Priority
Apr 18 2012
Filed
Feb 10 2017
Issued
Jan 26 2021
Expiry
Mar 15 2033
Inventors
Li, Xiuling
Assg.orig
The Board …
Assg.curr
The Board …
Entity
Small
Referenced by
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References
2
Maint.:
currently ok
DISCUSSION AND ADDIT…
0. 19. An electronic device comprising:
an array of nanopillars protruding from a base substrate, each nanopillar having a quantum well structure comprising a portion of the base substrate, a second layer on the base substrate and a first layer on the second layer,
wherein the first layer comprises a p-type or an n-type iii-V semiconductor, the second layer comprises a semi-insulating iii-V semiconductor, and the base substrate comprises a p-type or an n-type iii-V semiconductor opposite to that of the first layer.
1. A method of metal assisted chemical etching, the method comprising:
providing an electrically conductive film pattern disposed on a semiconductor substrate, the semiconductor substrate comprising a iii-V semiconductor; and
selectively removing at least a portion of the iii-V semiconductor immediately below the conductive film pattern by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide.
15. A method of metal assisted chemical etching,
the method comprising:
providing a conductive film pattern disposed on a semiconductor substrate, the semiconductor substrate comprising a iii-V semiconductor; and
selectively removing at least a portion of the iii-V semiconductor immediately below the conductive film pattern by immersing the conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent selected from the group consisting of potassium permanganate (KMnO4) and potassium persulfate (K2S2O8).
2. The method of claim 1, wherein the etchant solution does not remove substantial portions of the iii-V semiconductor which do not have the conductive film pattern disposed thereon.
3. The method of claim 1, wherein the iii-V semiconductor comprises GaAs.
4. The method of claim 1, wherein the iii-V semiconductor is doped.
5. The method of claim 1, wherein the conductive film comprises gold.
6. The method of claim 1, wherein the oxidizing agent comprises potassium permanganate (KMnO4).
7. The method ofclaim 1, wherein the acid is selected from the group consisting of sulfuric acid (H2SO4) and hydrofluoric acid (H F).
8. The method of claim 1, further comprising varying a concentration of the oxidizing agent in the etchant solution.
9. The method of claim 1, wherein the selectively removing the portion of the iii-V semiconductor takes place at a temperature of from about 40° C. to about 45° C.
10. The method of claim 1, wherein the conductive film pattern and the semiconductor substrate are immersed in the etchant solution for about 3 to about 5 minutes.
11. The method of claim 1, further comprising:
generating holes (h+) from the oxidizing agent on the conductive film pattern;
diffusing the holes (h+) to a boundary of the conductive film pattern, iii-V semiconductor, and etchant solution; and
removing the holes (h+) from semiconductor substrate substantially immediately upon the holes (h+) reaching the boundary.
12. The method of claim 1, further comprising forming features in the semiconductor substrate having a length-to-width aspect ratio of at least about 5:1, thereby forming an array of high aspect ratio semiconductor nanostructures.
13. The method of claim 12, wherein the array of high aspect ratio semiconductor nanostructures is an ordered array of nanowires.
14. The method of claim 1, wherein a concentration of the oxidizing agent in the etchant solution is in a range of from about 20 mM to about 150 mM.
16. The method of claim 15, wherein the iii-V semiconductor comprises gallum arsenide.
17. The method of claim 15, wherein a concentration of the oxidizing agent in the etchant solution is in a range of from about 20 mM to about 150 mM.
18. The method of claim 15, wherein the selectively removing the portion of the iii-V semiconductor takes place at a temperature of from about 40° C. to about 45° C.
0. 20. The electronic device of claim 19, wherein the iii-V semiconductor is selected from the group consisting of GaAs, InAs, GaP, InP, InGaAs and InGaP.
0. 21. The electronic device of claim 19, wherein the nanopillars have a width or diameter in a range from about 10 nm to about 1000 nm.
0. 22. The electronic device of claim 21, wherein the width or diameter is in the range from about 500 nm to about 1000 nm.
0. 23. The electronic device of claim 19, further comprising an electrically insulating material on the base substrate, the electrically insulating material surrounding each nanopillar and extending from the base substrate to a tip portion of the first layer.
0. 24. The electronic device of claim 23, further comprising an electrically conductive material on the tip portion of the first layer.
0. 25. The electronic device of claim 24, wherein the electrically conductive material comprises an electrically conductive transparent oxide, and wherein the electrically insulating material comprises an oxide or a polymer.
0. 26. The electronic device of claim 25, wherein the polymer comprises a photopolymer.
0. 27. The electronic device of claim 19, wherein the nanopillars comprise a length-to-width aspect ratio of at least about 5:1.
0. 28. The electronic device of claim 19, wherein the first layer comprises p-type GaAs, the second layer comprises intrinsic GaAs or intrinsic InGaAs, and the base substrate comprises n-type GaAs.
0. 29. The electronic device of claim 19 being selected from the group consisting of LED, solar cell and laser.

S2O82−(aq)→2SO42−(aq)+2h+
These holes can then diffuse into the substrate, forming Ga3+ and As5+ or As3+. The oxidized gallium and arsenic can dissolve into the solution at any interface not covered by gold. The holes diffuse to this interface for this reaction to occur. Once in the solution, arsenic has the potential to form orthoarsenic acid (AsH3O4). If controlled properly, the oxidized GaAs can dissociate into the solution directly near the edge of the gold, forming high aspect ratio structures, as illustrated in FIG. 1. As such, the reaction process of the method can include generating holes (h+) from the oxidizing agent on the conductive film pattern, diffusing the holes (h+) to a boundary of the conductive film pattern, III-V semiconductor, and etchant solution, and then removing the holes (h+) from the semiconductor substrate substantially immediately upon the holes (h+) reaching the boundary.

The n-type GaAs samples described herein were initially prepared on a quarter of a purchased n-type GaAs wafer. These wafers were then cut into many smaller pieces to allow for multiple trials. The GaAs wafers used were (100) interface with a doping of Nd=2×1018 cm−3. Two different patterns were used for the GaAs MacEtch. The larger of the two patterns includes 0.3 mm×0.3 mm squares while the others are nanowire arrays of 1.0, 0.6, and 0.4 μm. The pattern, schematically illustrated in FIG. 1, was formed by lithography of photoresist AZ5214. The nanowire array was patterned by soft lithography with liftoff. A 20 nm gold metal film was deposited using a CHA e-beam evaporator.

The samples were individually subjected to a different etching solution that included deionized water (DI), H2SO4 or HF, and KMnO4 or K2S2O8. All of the square patterned samples were subjected to 30 mL HF and 15 mL DI for a duration of 3 minutes with varying concentrations of oxidizing agent. During etching, the acid and oxidizing agent concentrations were kept stable within a range that typically varied between 15 and 30 mL of acid with 0 to 15 mL of DI water. The hydrofluoric acid used was 49% by mass purchased from J. T. Baker. Since both of the oxidizing agents are solid reagents, they were mixed in the solution of HF:DI for five minutes prior to adding the GaAs sample. When both oxidizing agents were in the concentration at the same time, KMnO4 was always added first. All the GaAs samples were analyzed and measured using a Hitachi S4800 SEM.

Large Pattern Etching Examples

Larger square patterns on GaAs were used to compare the effect of an increasing concentration of oxidizing agent at a constant volume of HF and DI. The oxidizing agent was increased three different ways: (1) by increasing the amount of KMnO4 with no K2S2O8 present (FIG. 2a-d), (2) increasing the amount of KMnO4 with 0.755±0.005 g K2S2O8 always present (FIG. 2e-h), and (3) increasing the amount of K2S2O8 with 0.265±0.005 g KMnO4 always present (FIG. 2i-l). The samples were measured on two parameters: (1) the vertical etch depth, and (2) the length of horizontal side etching.

As observed in FIGS. 2a-2l, in most of the examples, horizontal side etching of considerable length was observed, sometimes exceeding the length of the vertical etch. The vertical and side etches used for the plots in FIGS. 2d, 2h, and 2l were calculated by measuring multiple squares along the same sample and taking the standard mean. Both FIG. 2d and FIG. 2h examine how the vertical and side etching changes with increasing KMnO4 concentration. Without any persulfate present, the vertical etching depth peaks at around 4.2 μm at a concentration of 37.1 mM KMnO4 (FIG. 2b). This concentration also had the best aspect ratio. There is still some side etching even at low concentrations of 18.5 mM KMnO4 (FIG. 2a). This indicates that a low concentration over a long period of time may not provide the best structure. As the amount of permanganate increased, the vertical etching dropped to a depth near 2 μm consistently after peaking. However, the horizontal side etch continues to increase in what appears to be a linear relationship with oxidant concentration. At 85 mM KMnO4 (FIG. 2c) the horizontal etch seems to be primarily the result of excess holes produced during the MacEtch process. Had the GaAs been etched by the solution itself in a manner similar to H2SO4 and H2O2, the surface of the GaAs should show some deformation. However, the top of the GaAs square is undamaged, and the edge has the shape of an overhang. If this was due to etching from a solution this overhang should not occur because the edge itself should provide more surfaces for etching. However the area between the gold and the square is very rough with visible indents and crevices.

Similarly, the horizontal side etch was observed to increase linearly with increasing KMnO4 when K2S2O8 was kept constant at 62 mM K2S2O8. As shown in FIG. 2b, the vertical etch depth peaked at 49 mM KMnO4. However, at 49 mM KMnO4, the GaAs square became damaged and showed signs of being etched by the solution itself. For example, FIG. 2g shows the results of 73.7 mM KMnO4. The area to the left is actually the area that is covered with gold and the square area, on the right, had been severely etched. Much like the other example, the surface is extremely rough and has a rocky interface at high concentrations of KMnO4. The other two images of this example, FIG. 2e and FIG. 2f, are 17 mM and 26 mM KMnO4, respectively. In FIG. 2f, the area covered by the gold is at the same height as GaAs surface, but in FIG. 2e the gold covered surface is noticeably depleted. For FIG. 2f, metal assisted chemical etching appeared to have occurred only in the gold closest to the interface. As the etching continued, the gold rotated the etch around the edge. It is possible that with large gold patterns, the concentration of oxidizing agent can affect what regions of GaAs form holes, with areas near the interface being more favorable.

Increasing potassium persulfate resulted in a decrease in both vertical and side etching. At 103 mM K2S2O8 (FIG. 2k), the surface of the GaAs square showed signs of etching for all exposed GaAs. This is evident by the rough surface in FIG. 2k. This is not unusual since potassium persulfate has a higher oxidation potential than both potassium permanganate and H2O2. FIG. 2i and FIG. 2j (42 mM and 81 mM K2S2O8, respectively) both show signs of vacancy formation within the substrate. Along the tip of the GaAs square in FIG. 2i, there is a clearly defined row of vacancies. The vacancies formed at the higher concentration in FIG. 2j are smaller and closer packed. These defects are visually similar to the defects observed in hole formation in GaAs from H2O2 and H2SO4. However, since they only occur near the edge of the square near the gold, the source of these holes are from the MacEtch process and not the solution itself. While most of these vacancies are visible at the surface, a few can be observed below the surface in both FIG. 2i and FIG. 2j. It is possible that enough holes were created from MacEtch that as they diffused through the GaAs, and there was not enough surface area to dissolve into the solution. Therefore, it became more favorable to form a positive vacancy. When observing the square at higher magnitude, a ring of these defects can easily be noticed with undamaged GaAs in the middle. At higher concentrations, the width of the ring was larger and the amount of GaAs in the center decreased.

Similar surface defects occur in the other two examples as well. While none of them formed vacancies beneath the surface, there were similar surface morphologies evident only near the GaAs gold interface. Both FIG. 2a and FIG. 2e have slight ridges observable close to the edge of the square. It appears that GaAs was etched away at this interface similar to the etching along the sides. However, since most of the holes had already dissociated into the solution before then, only a small amount was able to diffuse that far, resulting in a very slight etch. At higher oxidizing concentration, a strip of rough surface deformation appears in FIG. 2b and along the edge of the square in FIG. 2f. This roughness was likely formed in the same manner as the vacancies in FIG. 2i and FIG. 2j. Additionally, vacancies could be responsible for rough surfaces noticed at high concentrations of KMnO4. The trials with the highest concentration of oxidizing agent will have the most holes diffusing through the substrate. It is possible that these vacancies are abundant enough for pieces to break off and form the facetted surfaces observed in FIG. 2c and FIG. 2g.

Nanowire Formation Examples

While silicon has already been able to form nanowires by metal assisted chemical etching with much success, it has yet to be proven for III-V materials. Using the perforated patterns mentioned above (such as in regard to FIG. 1) and the etching solutions mentioned above, nanowires were able to be etched in GaAs with varying degrees of success depending on etching parameters.

With a solution of only KMnO4 and HF, nanowires of different morphologies were observed at distinct KMnO4:HF concentrations (FIGS. 3a-3c). The concentrations of 54.8 mM, 55.7 mM, and 58.2 mM KMnO4 for FIGS. 3a-3c, respectively, refer to a solution of 15 mL HF and 0 mL DI with the etch occurring for 5 minutes. Small amounts of DI were added in an attempt to increase uniformity but did not show significant improvement. For solutions with DI, as long as mole ratio of HF to KMnO4 remained the same the nanowire morphology stayed consistent.

Also, these examples were done in a 30 mL Pyrex container with a 32 mm diameter. The HF reacted with the SiO2 and B2O3 to dilute the solution. However, the examples done in the Pyrex glass were more consistent than those done in the plastic container.

As observed in FIGS. 3a-3c, the molarities of the three wires were close to each other with a range of only 3.4 mM KMnO4. This corresponds to only 0.008 grams of KMnO4 in a 15 mL solution which is a small window. An interesting attribute of the nanowires formed form this solution is that they had a distinctive zigzag shape, as shown in FIG. 3b. When introduced to the solution, the gold initially etched the wire at an angle. However, after etching this way for a certain distance the wire began to etch in the opposite direction. The width of the zigzag from one turning point to the other varied with tiny changes in KMnO4 concentration.

However, some wires obtained were fairly smooth as observed in FIG. 3a. These wires still had zigzag properties, but much less so than FIG. 3b. It would appear that as concentration of KMnO4 decreases the shape becomes smoother while, at a higher concentration of 58.2 mM KMnO4 only small bumps were etched. The bumps appeared vertically straight and uniform. Even though these bumps do not have a large amount of tapering, the tops of them appear to be etched off completely.

Nanostructures were observed using other solutions as well. FIGS. 4a-4b show the results of nanowires formed by etching in a solution of 15 mL of HF, 15 mL of DI, 92 mM of K2S2O8 and 56 mM of KMnO4 for 5 minutes. The morphology of these wires is vastly different from the wires formed with only KMnO4. As shown FIG. 4a, these wires are somewhat tapered with diagonal facets on the top of each one. Also, there is a very thin strand of material that falls down above the wire. This thin strand used to be part of the wire, but due to excessive etching it was reduced to a very thin strand. This signifies the actual depth of the etch being much deeper than the nanowires themselves. This excessive etching could be due to etching from the solution itself, as observed in FIG. 2k, or as part of the MacEtch process. During etching, it is not uncommon for some connections of gold to tear or break. The etch rate is different along these areas because of the change in surface area. This can creates multiple levels of height along the surface, as seen in FIG. 4b. However, the wires observed were able to etch in multiple directions even though the crystal directions were not the same. FIG. 4b shows wires being etched in three different directions according to the angle of the surface beneath them.

A small chuck of gold was placed in the solution during the K2S2O8 and KMnO4 etch. By producing an additional surface for oxidation to occur, the small chunk of gold essentially reduced the effect of the oxidizing agent. Without the piece of gold, the side etch was too extensive and only miniature spikes were etched out of the GaAs substrate.

Even better nanowires were formed with sulfuric acid and potassium permanganate, as shown FIGS. 5a-5b. The wires in FIG. 5a exhibit very little side etching and retain a flat circular top. However, the wires varied somewhat over the sample and not all of the wires were this perfect. Some have more tapering or side etching than others, but over the sample, the wires are fairly uniform (FIG. 5b). Unfortunately, these wires are very sensitive to the kinetics of mixing the solution and are very difficult to repeat. The solution which produced the nanowires observed in FIGS. 5a-5b included 15 mL of HF, 30 mL of DI, and 1.06 g of KMnO4, which is about 150 mM KMnO4. With such a high amount of potassium permanganate, not all of it could dissolve into the solution and the undissolved solute remained on the bottom of the beaker during the etch. The GaAs sample was etched for 3 minutes with the temperature of the solution being between 42 and 45° C. The nanowires etched with sulfuric acid exhibited the best morphologies out of the above three different solutions, but were the least reproducible.

By adapting metal-assisted chemical etching methods to GaAs, nanoscale structures can be successfully etched into substrates. Similar methods can be used to etch through other heterostructure III-V material. By exploiting the effect different acids and oxidizing agents have on the etching process, different nanostructures can be formed for a variety of applications, including nanowires of multiple morphologies, with zigzag shapes and along angled interfaces.

Regardless of the type of the semiconductor, an ideal MacEtch solution is substantially inert without the presence of metal. Although H2O2 has been proven to be a suitable MacEtch agent for silicon, it has been shown to etch (100) GaAs in either acidic or base solution without the presence of metal catalyst. MacEtch of III-V material can be performed by using appropriate etching conditions resulting in the highest differential etch rate for the III-V semiconductors, where differential etch rate refers to the difference in the etch rate with and without metal present. Oxidizing agents with weaker oxidation potentials (e.g., KMnO4) can be used to prevent nonmetal-catalyzed etching, while maintaining a reasonable etch rate in the presence of metal.

Described below is additional discussion of how the parameters of the MacEtch process can be selected for different III-V materials. Also described are additional etching characteristics of n-type GaAs wafers patterned by gold using soft lithography and etched with KMnO4 as the oxidizing agent in acidic (H2SO4 or HF) solutions. Of interest is the influence of solution concentration and temperature on the etching characteristics.

DISCUSSION AND ADDITIONAL EXAMPLES

As described above and further below ordered arrays of high aspect ratio GaAs nanostructures have been formed using Au-MacEtch. In the below additional MacEtch examples, Epi-ready Si-doped (100) GaAs substrates acquired from AXT, Inc. with a doping concentration of 1×1018 to 4×1018 cm3 were used for MacEtch. Potassium permanganate (KMnO4), an oxidizing agent that has an oxidation potential lower than that of H2O2 (see Table I), was mixed with deionized water (DI) and either sulfuric acid (H2SO4) or hydrofluoric acid (HF). The overall etching of GaAs using KMnO4 can be described by the following chemical reaction: GaAs+MnO−+H+→Ga3++Asn++Mn2++H2O, with n equal to 3 or 5. In MacEtch, the metal catalyst acts as the cathode and the semiconductor acts as the anode. Table I lists relevant half reactions involving chemical species used for etching, as well as possible products and participating reactants in the overall reaction. Several possible products of the etching reaction with mass and charge balanced are listed in Table II. The etching was carried out at either room temperature or at 30 to 45′ C. for a period of 3 to 5 min, as indicated below. No stirring was done during etching.

TABLE H
Half-cell electrochemical potentials.
E°/V
Anode Reaction
Gallium
Ga → Ga3+ + 3e 0.549
Ga → Ga+ + e− 0.2
Ga + H2O → GaOH2+ + H+ + 3e− 0.498
Ga + 4OH− → H2GaO3− + H2O + 3e− 1.219
Arsenic
As + 3H+ + 3e− → AsH3 −0.608
2As + 3H2O → As2O3 + 6H+ + 6e− −0.234
As + 2H2O → HAsO2 + 3H′ + 3e −0.248
HAsO2 + 2H2O → H3AsO4 + 2H+ + 2e− −0.560
As + 4OH− → AsO2− + 2H2O + 3e− 0.68
AsO2− + 4OH− → AsO43− + 2H2O + 2e− 0.71
Silicon
Si + 6F− → SiF62− + 4e− 1.24
Si +H2O → SiO + 2H+ + 2e− 0.8
Si + 2H2O → SiO2 (quartz) + 4H+ + 4e− −0.857
Si + 6OH− → SiO32− + 3H2O + 4e− 1.697
Cathode Reaction
MnO4− + 8H+ + 5e− → Mn2+ + 4H2O 1.507
MnO4− + 4H− + 3e− → MnO2 + 2H2O 1.679
H2O2 + 2H+ + 2e− → 2H2O 1.776
S2O82− + 2H′ + 2e− → 2HSO4− 2.123
Gold
Au+ + e− → Au 1.692
Au3+ + 2e− → Au+ 1.401
Au3+ + 3e− → Au 1.498
Au2+ + e− → Au+ 1.8
Overall Reaction
GaAs + MnO4− + H+ → Ga3+ + As3+ + Mn2+ + H2O
Overall reaction with possible forms of the products (balanced)
GaAs + 2KMnO4 + H2O + 5HF → HAsO2 + GaF3•3H2O +
2MnO2 + 2KF
3GaAs + 8KMnO4 + 17HF + 5H2O → 3H3AsO4 + 3(GaF3•3H2O) +
8MnO2 + 8KF
10HaAs + 12KMnO4 + 33H2SO4 → 10HAsO2 + 12MnSO4 +
6K2SO4 + 5Ga2(SO4)3 + 28H2O
10HaAs + 16KMnO4 + 39H2SO4 → 10H3AsO4 + 16MnSO4 +
K2SO4 + 5Ga2(SO4)3 + 24H2O

Nanoscale gold mesh patterns, with hole size ranging between 500 and 1000 nm, were prepared using a soft lithography method. First, a layer of SiNx was deposited on top of the GaAs, followed by a spin-coated layer of SU8 resist. Using a poly-(methyl methacrylate) (PMMA) stamp, the pattern was imprinted onto the SU8. Next the depressed SU8 was removed using an oxygen plasma etch. The sample was then subject to a CHF4 etch to remove the exposed SiNx. Following this step, a 20 nm layer of Au was evaporated on the GaAs surface. Native oxide on GaAs was removed using (HCL: DI=1:1) solution just before evaporating Au. The remaining SiNx and SU8 were removed with sonication in a diluted HF solution. Also tested were micrometer square patterns of 300×300 μm2 separated by 125 μm wide strips of gold formed with standard optical lithography using AZ5214 photoresist. SEM images were obtained using a Hitachi 4800 microscope and photoluminescence (PL) spectra were measured using a Renishaw micro-PL system with a 633 nm pump laser and a CCD detector at room temperature.

As mentioned above, MacEtch begins when holes (h+) are generated from the oxidant on the metal surface and then diffuse to the semiconductor. The holes (h+) can then subsequently be consumed by oxidizing the semiconductor directly underneath the metal to form soluble product in the acidic solution. This leads to vertical etching. Alternatively, the holes can diffuse outside of the metal-semiconductor interface to areas around the metal to induce lateral etching. The aspect ratio of a produced structure is inherently related to the proportion of vertical to lateral etching, which is the essence of the MacEtch mechanism. Processing factors that affect the dynamics of MacEtch can be classified into three categories. (1) semiconductor type and doping; (2) metal type, feature size, and density; and (3) solution components, concentration, temperature, and local concentration fluctuation. The examples herein focused on parameters of the third factor that limits aspect ratios, e.g., the solution. In particular, the effect was explored of oxidizing agent potential and concentration, chemical end product, accessibility to solution as a result of metal pattern size, and temperature on the etching dynamics and aspect ratio of GaAs nanostructures produced by this method.

In order to produce high aspect ratio structures, lateral etching should be suppressed. FIGS. 6a-6b present the effect of the oxidant concentration on the etching direction by using large size gold mesh patterns (300×300 μm2 separated by 125 μm). For metal patterns of such a large size, etching takes place mostly around the edges of the metal pattern, while areas under the middle of the metal pads have limited access to solution which prevents product removal. Accumulated holes from the metal covered areas tend to diffuse laterally and side etch occurs. FIG. 6a is a schematic illustration of the typical topography produced from patterns of this size as well as the SEM image of FIG. 2b showing the trenched profiles. The trenched etching structures are measured on two parameters: vertical etch depth and side (lateral) etch length.

FIG. 6b is the plot of FIG. 2d which shows the effect of the concentration of oxidizing agent KMnO4 on the vertical versus side etch rate. The vertical and side etching depths are plotted using the average depth measured over multiple squares on the same sample, and the standard deviation is plotted as the error bar. It can be seen that as KMnO4 concentration increases, the vertical etch depth peaks at a concentration of 37 mM and then drops to a relatively stable value. This concentration also exhibits the best aspect ratio (vertical/side etch depth) of the examples. Further increase in concentration causes the side etch rate to surpass the vertical etch rate, as more holes are produced at higher concentrations of KMnO4. In order to form completely ordered structures with vertical sidewalls, the dissolution step of MacEtch reaction should to be uniform across the patterned area.

Note that patterns of hundreds of micrometers were used to evaluate side etch. If the side etch is larger than the radius of the nanostructure's lateral dimension, the etching will result in polishing with no discernible structure formation. Due to the difference in the supply of holes (h+) for oxidation and end product removal rate, the selection of the parameters of etching recipe varies as a function of metal pattern size and connectivity. MacEtch of GaAs at nanoscale dimensions was found to be sensitive to all etching parameters. For gold mesh patterns at submicrometer scales, most combinations of oxidant to acid ratio, dilution, and temperature resulted in either no etching or polishing from overetching. A suitable etching condition is determined by calibrating between the two extremes.

FIGS. 7a-7c are SEM micrographs of an array of highly vertical GaAs nanopillars produced from a gold mesh pattern with 600 nm diameter openings in a solution of H2SO4 oversaturated with KMnO4 at slightly elevated temperature for 5 min. The nanopillars formed are about 3.5 μm tall and about 600 nm in width. The gold mesh pattern descends to the bottom of the pillar structure and can be seen clearly in FIG. 7b, similar as is the case for silicon MacEtch. The tips of the nanopillars appear to be tapered, probably resulting from lateral etching at the initial stage. Slight nonuniformity in the pillar width can be seen in the cross-sectional SEM image near half height of the wire. However, the position of the narrow neck appears to be synchronized for all pillars, implying that this is due to local etchant concentration fluctuations in the solution. Nevertheless, large area periodic arrays of ordered GaAs nanopillars are produced using MacEtch in a matter of minutes. The solution was kept between 40 and 45° C. during etching. Note that using the same solution, no etching was observed at room temperature, while at temperatures higher than 45° C., the gold pattern delaminated from the substrate surface.

Without being bound by theory, it is hypothesized that at this temperature, the etching reaction is dissolution limited. The rate-determining step is the removal of the oxidized Ga3+ and Asn+ (n=3+ or 5+) into solution (e.g., Ga2(SO4)3 and HAsO2). As a result, the holes (h+) generated at the gold surface are not consumed in time and instead diffuse laterally to promote etching of the bare GaAs. Similar reverse MacEtch was reported for InP under photoirradiation. In that case, the above bandgap photons generate electrons and holes in the bare InP area; the electrons then diffuse and recombine with the holes generated from metal-catalyzed oxidant reduction in the metal-covered area causing holes to accumulate and etch the bare InP region. These results indicate that etching temperature can affect the dynamics of carrier diffusion, oxidation, and product removal, all of which effect the spatial profile of GaAs structures generated by patterned MacEtch.

Furthermore, striking zigzagging high aspect ratio nanowires are formed by MacEtch using a solution of KMnO4 and HF in a glass beaker at room temperature. Shown in FIGS. 8a-8b is an array of wires with zigzagging sidewalls formed from a 1.0 μm diameter mesh pattern etched using 55.7 mM of KMnO4 in HF for 5 min. Front the zoomed in side image of FIG. 8b, the zigzag pattern can be seen to be synchronized horizontally. Also, the twisting direction is close to <111> crystal orientation based on measured angles from the SEM images. MacEtch can propagate along different orientations with different etchant concentration, and high HF/oxidant ratio prefers etching along <111> directions for Si (100) substrate (Chem, W.; Hsu, K.; Chun, I. S.; de Azeredo, B. P.; Ahmed, N,; Kim, K. H.; Zuo, J. M.; Fang, N.; Ferreira, P; Li, X. L. Nano Lett. 2010, 10, 1582-1588). Without being bound by theory, it is believed that concentration modulation is the reason for the observed zigzagging GaAs nanowires which twist left and right from one <111> orientation to another, joined by the straight <100> segments.

It has been reported that zigzag silicon nanowires were formed using (111) Si wafers through MacEtch with solution-based gold catalyst AgNO3 (Chen, H.; Wang, H.; Zhang, X.-H.; Lee, C.-S.; Lee, S.-T. Nano Lett. 2010, 10, 864-868). Notably, an intentionally scratched rough surface led to zigzag, while polished smooth surface yielded straight wires. In another report (Kim, J.; Kim, Y. H.; Choi, S.-H.; Lee, W. ACS Nano 2011, 5, 5242-5248), an initial porous silicon layer was deemed important for the formation of zigzag Si nanowires for Si(100) surface using patterned gold mesh as catalyst at an elevated temperature (60° C.). The porous layer acted as a barrier to deter diffusion of MacEtch reactants in the unstirred solution, creating high and low concentrations as reactants were consumed because there was a delay in replenishing them. The zigzag morphology was also believed to be attributed to the concentration variations.

For GaAs, intentional surface roughening did not produce zigzagging structures. However, carrying out the reaction in a glass container with HF acid produced the zigzag morphology while other container materials did not, implying that the borosilicate glass container participated in the etching reaction. Without being bound by theory, it is hypothesized that the glass surrounding the solution is constantly turning HF into H2O, which creates a concentration gradient that drives the diffusion of HF directly above the semiconductor wafer piece toward the container walls. In competition with the outward diffusion, HF is consumed from reacting with GaAs during MacEtch, causing the diffusion to shift back toward the wafer piece to rebalance the concentration. The constant modulation of flux during etching creates a periodic concentration variation similar to the zigzagging silicon nanowire etching condition reported by Kim et al. Although the borosilicate container reaction replicated an extreme case of concentration variations during etching, the resulting nanowire morphology clearly demonstrates the susceptibility of GaAs MacEtch to local solution fluctuations.

FIG. 8c is a plot of the PL spectrum taken from the zigzagged nanowires along with an unetched area on the same sample. A distinct shift toward longer wavelength by about 9 nm relative to bulk GaAs is observed for the zigzagged nanowires, and smaller (about 3 nm) red shift (not shown) has also been observed for other nanowire structures formed. The red shift might be from some shallow surface states which become more prevalent for nanowires due to the increased surface area.

FIGS. 9a-9c are schematic illustrations of the formation mechanism of the GaAs nanostructures discussed above. Three processes labeled 1, 2, and 3 correspond to the three steps in MacEtch: hole formation, hole diffusion, and semiconductor oxidation and removal. FIG. 9a corresponds to MacEtch involving H2SO4 at high temperature (40 to 45° C.), where the holes are removed as soon as they reach the boundary of Au, GaAs, and solution. This scenario results in high aspect ratio vertical wall nanopillars, as shown in FIGS. 7a-7c. FIG. 9b represents MacEtch involving H2SO4 at mid-temperature range (30 to 35° C.), where there is an excess amount of holes accumulates in the bare GaAs area because the lower temperature severely reduces the rate of step 3. This mechanism leads to reverse MacEtch where metal acts as a mask. FIG. 9c illustrates the scenario of FIGS. 8a-8c, where MacEtch involves local concentration fluctuation induced by consumption and rebalance of HF/KMnO4 by the boroslicate glass. The concentration modulation forces the nanowires to exhibit a zigzag morphology.

By adapting the etching solution to GaAs, the MacEtch process, a wet but directional etching method, has been demonstrated to produce high aspect ratio semiconductor nanoscale structures beyond just silicon. In contrast to MacEtch of silicon, the process window for GaAs is more sensitive to the rate of oxidation with and without the gold catalyst and rate of dissolution for etching product removal, as well as to changes in the local concentration during etching. By exploiting the effect of etching parameters, different nanostructures can be formed for a variety of applications, including DBR or DFB lasers, photonic crystals, LEDs with periodic roughening surfaces, and solar cells with light trapping nanostructures. Since the etching takes place at a temperature near room temperature, no metal contaminants should be incorporated in the core of the nanopillars, and surface contamination can be removed. Because there is no high energy ions involved, as in the case of dry etching, surface damage should not be a concern. Because the aspect ratio is essentially limited by etching time, as long as unassisted etching mechanism such as side etching can be suppressed, extremely high aspect ratio vertical structures can be generated. Although only n-type GaAs is demonstrated here, using teachings disclosed herein, etching parameters can be selected for MacEtch to work for other III-V materials of various doping types and levels as well as heterostructures. The realization of high aspect ratio III-V nanostructure arrays by MacEtch can potentially transform the fabrication of a variety of optoelectronic device structures including DBR and DFB semiconductor lasers, where surface grating is currently fabricated by dry etching. It also brings affordability and possibly new device concepts for III-V nanostructure based photonic devices.

n-GaAs, SI-GaAs, p-GaAs Compositions and Devices

MacEtch was performed on GaAs (100) substrates with three different doping types: semi-insulating (SI), Si-doped (n=˜1−3×1018 cm−3), and Zn-doped (p−1×1018 cm−3). After native oxide removal in a dilute HCl solution, a 35 Å Au-layer was deposited on the GaAs substrates via electron-beam evaporation, followed by soft-lithography patterning of gold to pattern various devices. MacEtch was performed in a solution including deionized water (DI), 49% hydrofluoric acid (HF) as the etching agent, and potassium permanganate (KMnO4) as the oxidizing agent. Scanning electron microscopy (SEM) was performed using a Hitachi S-4800 microscope and photoluminescence (PL) spectra were obtained through the use of a Renishaw in Via μ-PL system at room temperature with excitation provided by laser emission centered at 633 nm.

FIG. 10a is a SEM micrograph of an array of n-type GaAs nanopillars showing a substantially uniform structure over a relatively large area. FIG. 10b is a SEM micrograph of one of the GaAs nanopillars of FIG. 10a showing no discernible porosity in the nanopillar. The GaAs nanopillars of FIGS. 10a-10b were produced from a gold pattern in a solution of 20 mL HF, 20 mL DI, 0.05 g of KMnO4 at room temperature for 10 min.

FIGS. 11a-11d are SEM micrographs of semi-insulating GaAs (SI-GaAs) that was etched with a solution of (a) 5 mL HF and 25 mL DI, (b) 10 mL HF and 20 mL DI, (c) 20 mL HF and 10 mL DI, and (d) 25 mL HF and 5 mL DI, respectively. All of the solutions also include 0.05 g of KMnO4. The molar concentrations and concentration ratios are provided in Table III below. Etching was conducted at a temperature of 22° C. for a duration of 10 minutes.

TABLE III
Molar Concentrations and Concentration Ratios
[HF] [KMnO4] [HF]/[KMnO4] [KMnO4]/[HF]
(a) 0.14M  7.9E−6M 17722 5.6E−5
(b) 0.28M 6.35E−6M 44094 2.3E−5
(c) 0.56M 3.17E−6M 176654 5.6E−6
(d)  0.7M 1.59E−6M 440257 2.2E−4

Samples of p-GaAs were also etched. FIGS. 12a-12b are SEM micrographs of p-GaAs that were etched in a solution of 20 mL HF and 10 mL DI for 10 minutes at a temperature of 22° C. The solution for the sample of FIG. 12a includes 0.025 g of KMnO4 while the solution for the sample of FIG. 12b includes 0.2 g KMnO4. A higher level of porosity was introduced in the sample produced with the higher concentration KMnO4, and higher concentration of KMnO4 resulted in some tapering of the pillars. Similar trends were found for samples of i-GaAs and n+ GaAs beyond 0.1 g KMnO4. Under this regime, the maximum molar concentration of KMnO4 before porosity occurs is approximate 9 μM ([HF]=0.55 M, [KMnO4]=9 μM).

FIG. 13 shows a 45°-tilted view of a p-type GaAs sample subjected to a MacEtch process at room temperature. Under optimized conditions, material dissociation can occur only along regions where a metal-semiconductor interface exists. The use of KMnO4 as an oxidant can allow for hole-injection at the Au—GaAs interface such that HF may subsequently etch the oxidized material. Thus, during GaAs MacEtch, the gold layer sinks as material is removed from the substrate directly below, thereby allowing exposed GaAs to remain intact along regions where no gold coverage exists. MacEtch of GaAs has been observed at temperatures between 0° C. to 60° C., regardless of doping type. Vertical etch rates were observed to increase with temperature, as a result of enhanced hole-injection. Similarly, increasing oxidant molar concentrations results in a linear increase of vertical etch rate. However, variation in the dilution levels of the MacEtch solution has demonstrated a possible maximum vertical etch rate under a fixed 6.33 μM concentration of KMnO4 and an HF:DI volumetric ratio of 2:1. Dilution beyond this ratio can reduce the effect of DI as a surfactant, thereby diminishing vertical etch rates. The vertical etch rates of SI- and n-type GaAs samples are comparable under all etching conditions tested. In contrast, p-type GaAs samples consistently etched at rate nearly twice as fast as SI- and n-type samples. This is attributed to the presence of excess holes in the p-type samples, reducing the barrier for oxidation. Based on the wide parameter space explored, MacEtch of GaAs of all doping types at room temperature can occur with the same solution. However, increasing, oxidant concentrations beyond a certain level can result in the formation of porous GaAs surfaces, which may adversely influence device performance.

Samples of p-i-n GaAs were also tested. The p-i-n GaAs samples were produced by forming an intrinsic or non-doped GaAs (i-GaAs) layer on an n-type GaAs (n+ GaAs) substrate. A p-type GaAs (p-GaAs) layer was formed on the n+ GaAs substrate such that the i-GaAs layer was sandwiched between the n+ GaAs substrate and the p-GaAs layer. The i-GaAs layer was about 300 nm thick and the p-GaAs layer was doped with Zn and was about 300 nm thick. All of the p-i-n GaAs samples were produced using a gold pattern.

A first sample of p-i-n GaAs was etched in a solution of 10 mL HF, 20 mL DI, 0.1 g of KMnO4 at room temperature for 30 minutes. FIGS. 14a-14c are SEM micrographs of the first p-i-n GaAs sample. Compared to the solution used for the sample of FIGS. 10a-10b, the competition between h+ injection and material etching favored higher degree of oxidation which caused a higher degree of lateral etching. As a result, the nanopillars are thinner.

The first sample of p-i-n GaAs was then etched in a solution that was the same for an additional 15 minutes. FIGS. 15a-15b are SEM micrographs of the further etched sample showing that the vertical etching proceeded at a constant rate leading to taller pillars. However, lateral etching was quenched at the tip of the pillars. Therefore, lateral etching only occurred within a finite distance from the gold layer.

A second sample of p-i-n GaAs was etched in a solution the same as the first sample for 10 minutes to see the early etch stages where lateral etching started. FIGS. 16a-16b are SEM micrographs of the second sample showing lateral etching. The difference in vertical and lateral etch rate can be taken advantage of to form pyramidal instead of pillar structures. The surface roughness is noted as being induced by irregular gold pattern edge profile that was transferred during sidewall etching.

The second sample was then further etched in a solution of solution of 20 mL HF, 10 mL DI, 0.1 g of KMnO4 at room temperature for 3.5 minutes. FIGS. 17a-17b are SEM micrographs of the further etched second sample. The solution that was used resulted in lower lateral etching compared to the solution used for the initial etching. The vertical etching dominated resulting in the base, square structure translating vertically. Thus, as show in FIGS. 17a-17b, pillars with a square base and a pyramidal tip can be formed. Therefore, the morphology of the etched structures can be controlled by varying the competition between vertical and lateral etching by tuning dilution of the solution.

The morphology of GaAs pillars may also be altered as a function of the MacEtch solution employed. While vertical etch rates are quenched under higher dilution levels, lateral etch rates may be enhanced. This allows for a variation of the nanostructure geometry. Shown in FIG. 18 are the room temperature PL spectra of periodic GaAs nanopillar arrays with various dimensions. The periodic pillar arrays show a clear increase of PL intensity as compared to the planar substrate, and the intensity increases with pillar height and width, indicating higher extraction efficiency. In addition to homogeneous GaAs pillars, InGaAs/GaAs superlattice and axial p-i-n junction GaAs pillar arrays have also been successfully created via MacEtch.

MacEtch can be used to form p-i-n GaAs or InGaAs/GaAs quantum well nanopillar arrays for use in LED and solar cell applications. FIG. 19a is a schematic of a p-i-n GaAs structure that was etched with an etchant solution including the following molar concentrations and ratios: [HF]=0.42 M, [KMnO4]=9.50E-6 M, [HF]/[KMnO4]=44234, and [KMnO4]/[HF]=2.3E-5. FIG. 19b is a plot of amount of KMnO4 in the etching solution as a function of vertical etch rate. FIG. 19c is a SEM micrograph of the p-i-n GaAs structure patterned with gold and etched with a single solution to form pillars including the p-i-n GaAs structure. The etch depth was about 850 nm.

In order to produce an LED, a sample similar to that of the p-i-n GaAs of FIG. 19c was encapsulated with a photopolymer SU-8-2. The sample was planarized and about 200 nm of the pillar tips exposed. FIGS. 20a-20c are SEM micrographs of the samples showing about 200 nm of the pillar tips exposed. ITO was sputtered onto pillar tips. Since only about 200 nm of the pillar tips were exposed, only the p-GaAs layer was exposed. Thus, the ITO contacted the p-GaAs and did not contact the i-GaAs and the n+ GaAs. The resulting structure can be used in an LED.

Superlattice heterostructured samples including six periods of alternating layers of GaAs and InxGa1-xAs (x=0.5) were grown via metalorganic chemical vapor depositions (MOCVD). FIG. 21a is a schematic of the GaAs and InGaAs structure. The thickness of the GaAs and InGaAs layers were 18.6 nm and 4 nm, respectively. Nanosphere lithography patterning was carried out by spin-coating polystyrene spheres of 750 nm diameter on the as-grown superlattice samples. After spin-coating, the diameter reduction of the polystyrene spheres was achieved through an oxygen plasma reactive ion etching (RIE) process for 90 seconds, allowing for the closely packed spheres to be separated by a spacing of approximately 100 nm. A gold layer with a thickness of 30 nm was next deposited on the samples by electron-beam evaporation. Subsequently, MacEtch was carried out in a solution composed of 15 mL of HF, 15 mL of deionized water (DI), and 0.1 g KMnO4, at room temperature for a period of 5 minutes. FIGS. 21b and 21c are SEM micrographs of the etched sample.

The etching methods described herein offer the potential to create high quality III-V photonic devices quickly and efficiently. For example, the realization of high aspect ratio III-V nanostructure arrays by wet etching can potentially transform the fabrication of a variety of optoelectronic device structures including distributed Bragg reflector (DBR) and distributed feedback (DFB) semiconductor lasers, where the surface grating is currently fabricated by dry etching. Because it can occur at room temperature, MacEtch is not likely to introduce metal contamination, in contrast to bottom-up high-temperature metal-catalyzed nanowire growth techniques, and since MacEtch is a wet etch process, MacEtch avoids ion-induced surface damage typically seen in dry etch processes. This can be crucial to III-V nanostructures for optoelectronic applications. For silicon, such surface damage can be repaired by thermal annealing. However, for compound semiconductors, such as GaAs, thermal repair is not completely effective mainly because of the difficulty of maintaining stoichiometry.

Such III-V nanostructures can be also used in other devices such as distributed feedback (DFB) and distributed Bragg reflector (DBR) lasers, photonic crystals, solar cells and light emitting diodes (LEDs) that involve surface relief structures for light trapping, and simply creating micron and nanometer scale mesa structures that is currently done by dry etching. Since MacEtch is a wet etch, the container holding the solution can be sized to fit essentially any desired device.

Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible without departing from the present invention. The spirit and scope of the appended claims should not be limited, therefore, to the description of the preferred embodiments contained herein. All embodiments that come within the meaning of the claims, either literally or by equivalence, are intended to be embraced therein.

Furthermore, the advantages described above are not necessarily the only advantages of the invention, and it is not necessarily expected that all of the described advantages will be achieved with every embodiment of the invention.

INVENTORS:

Li, Xiuling, Chern, Winston, Shin, Jae Cheol, Dejarld, Matthew T., Mohseni, Parsian Katal

THIS PATENT IS REFERENCED BY THESE PATENTS:
Patent Priority Assignee Title
THIS PATENT REFERENCES THESE PATENTS:
Patent Priority Assignee Title
6790785, Sep 15 2000 Board of Trustees of the University of Illinois, The Metal-assisted chemical etch porous silicon formation method
8334216, Mar 02 2010 NATIONAL TAIWAN UNIVERSITY Method for producing silicon nanostructures
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Apr 22 2013MOHSENI, PARSIAN KATALThe Board of Trustees of the University of IllinoisASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0537190344 pdf
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Jun 21 2013DEJARLD, MATTHEW T The Board of Trustees of the University of IllinoisASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0537190344 pdf
Jul 15 2013CHERN, WINSTONThe Board of Trustees of the University of IllinoisASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0537190344 pdf
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