To reduce adverse effect of variations in threshold voltage. A semiconductor device includes a transistor including a gate connected to one electrode of a capacitor and one terminal of a SW1, a source and a drain one of which is connected to one terminal of a SW2 and one terminal of a SW3 and the other of which is connected to the other terminal of the SW1 and one terminal of a SW4; a first wiring electrically connected to the other terminal of the SW2; a second wiring electrically connected to the other terminal of the SW4; a load including electrodes one of which is connected to one electrode of the capacitor and the other terminal of the SW3; and a third wiring connected to the other electrode of the load.
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9. A display module comprising:
a display panel comprising:
a semiconductor device pixel comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a capacitor; and
a load light-emitting element; and
a first line;
a second line; and
a third line; and
at least one of flexible printed circuit and printed circuit,
wherein:
one of a source and a drain of the first transistor is electrically connected to the first power supply line;
one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor;
the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor;
a gate of the second transistor is electrically connected to one a first electrode of the capacitor;
the other a second electrode of the capacitor is directly electrically connected to the other of the source and the drain of the fourth transistor and a first terminal of the load;
the second electrode of the capacitor is electrically connected to the light-emitting element;
the other electrode of the capacitor is not directly connected to any other transistor other than the fourth transistor;
the other of the source and the drain of the third transistor is electrically connected to the second signal line;
one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor;
the other of the source and the drain of the fifth transistor is electrically connected to the one of the source and the drain of the first transistor; and
a second terminal of the load is electrically connected to the third line; and
each of the first transistor, the second transistor, the third transistor and the fourth the fifth transistor includes comprises a channel formation region containing comprising an oxide semiconductor.
0. 17. A display module comprising:
a display panel comprising:
a pixel comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a first capacitor;
a second capacitor; and
a light-emitting element; and
at least one of flexible printed circuit and printed circuit,
wherein:
one of a source and a drain of the first transistor is electrically connected to a power supply line;
one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor;
the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor;
a gate of the second transistor is electrically connected to a first electrode of the first capacitor;
a second electrode of the first capacitor is electrically connected to the other of the source and the drain of the fourth transistor;
the second electrode of the first capacitor is electrically connected to the light-emitting element;
a first electrode of the second capacitor is electrically connected to the second electrode of the first capacitor,
the other of the source and the drain of the third transistor is electrically connected to a signal line;
one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor; and
the other of the source and the drain of the fifth transistor is electrically connected to the one of the source and the drain of the first transistor.
1. A display module comprising:
a display panel comprising:
a semiconductor device pixel comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a capacitor; and
a load light-emitting element; and
a first line;
a second line; and
a third line; and
at least one of flexible printed circuit and printed circuit,
wherein:
one of a source and a drain of the first transistor is electrically connected to the first a power supply line;
one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor;
the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor;
a gate of the second transistor is electrically connected to one a first electrode of the capacitor;
the other a second electrode of the capacitor is directly electrically connected to the other of the source and the drain of the fourth transistor and a first terminal of the load;
the second electrode of the capacitor is electrically connected to the light-emitting element;
the other electrode of the capacitor is not directly connected to any other transistor other than the fourth transistor;
the other of the source and the drain of the third transistor is electrically connected to the second line; and a signal line
a second terminal of the load is electrically connected to the third line
one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor;
the other of the source and the drain of the fifth transistor is electrically connected to the one of the source and the drain of the first transistor;
the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor each have a channel length direction defined as a direction of a shortest path between a source of the transistor and a drain of the transistor, and
the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are configured such that the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor have a same channel length direction.
0. 2. The display module according to
the one of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fifth transistor; and
the gate of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor.
0. 3. The display module according to
0. 4. The display module according to
0. 5. The display module according to
0. 6. The display module according to
0. 7. A display device comprising the display module according to
0. 10. The display module according to
the one of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fifth transistor; and
the gate of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor.
0. 11. The display module according to
0. 12. The display module according to
0. 13. The display module according to
0. 14. The display module according to
0. 15. A display device comprising the display module according to
0. 18. The display panel according to claim 17,
wherein a second electrode of the second capacitor is electrically connected to a cathode line.
0. 19. An electronic device comprising the display module according to claim 17.
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This application is a continuation of U.S. application Ser. No. 13/532,171, filed Jun. 25, 2012, now allowed, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2011-145262 on Jun. 30, 2011, both of which are incorporated by reference.
This application is a Reissue application of U.S. application Ser. No. 14/529,237, filed Oct. 31, 2014, now U.S. Pat. No. 9,508,759, issued Nov. 29, 2016, which is a continuation of U.S. application Ser. No. 13/532,171, filed Jun. 25, 2012, now U.S. Pat. No. 8,878,589, issued Nov. 4, 2014, and claims the benefit of a foreign priority application filed in Japan as Serial No. 2011-145262 on Jun. 30, 2011. This application claims priority to each of these prior applications, and the disclosures of the prior applications are considered part of (and are incorporated by reference in) the disclosure of this application.
1. Field of the Invention
The present invention relates to semiconductor devices, display devices, light-emitting devices, methods for manufacturing these devices, and method for driving these devices. In particular, the present invention relates to a display device including a current-driving-type light-emitting element which changes in luminance depending on current. The present invention relates to an electronic device including the display device.
2. Description of the Related Art
In recent years, flat panel displays such as liquid crystal displays (LCDs) are becoming widespread. Researches on the display (ELD) including an organic EL element, which is not an LCD are actively carried out (Patent Document 1). The organic EL is a current-driving-type light-emitting element changing in luminance depending on current and also referred to as an electroluminescent element, an organic light-emitting diode, an OLED, or the like. For example, methods for correcting variations in threshold voltage of transistors have been examined (see Patent Document 1).
It is an object of one embodiment of the present invention to provide a structure with which adverse effect of variations in threshold voltage of transistors can be reduced. Alternatively, it is an object of one embodiment of the present invention to provide a novel structure with which adverse effect of variations in mobility of transistors can be reduced. Alternatively, it is an object of one embodiment of the present invention to provide a novel structure with which adverse effect of deterioration of a transistor can be reduced. Alternatively, it is an object of one embodiment of the present invention to provide a novel structure with which adverse effect of deterioration of a display element can be reduced. Alternatively, it is an object of one embodiment of the present invention to provide a novel structure with which display unevenness can be reduced. Alternatively, it is an object of one embodiment of the present invention to provide a novel structure with which an image can be displayed with high display quality. Alternatively, it is an object of one embodiment of the present invention to provide a structure which can achieve a desired circuit with a small number of transistors. Alternatively, it is an object of one embodiment of the present invention to provide a structure which can achieve a desired circuit with a small number of wirings.
Note that the descriptions of these problems do not disturb the existence of other problems. Note that in one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.
One embodiment of the present invention is a semiconductor device which includes a transistor including a gate electrically connected to one of electrodes of a capacitor and one of terminals of a first switch, a source and a drain one of which is electrically connected to one of terminals of a second switch and one of terminals of a third switch and the other of which is electrically connected to the other of the terminals of the first switch and one of terminals of a fourth switch; a first wiring electrically connected to the other of the terminals of the second switch; a second wiring electrically connected to the other of the terminals of the fourth switch, a load including electrodes one of which is electrically connected to the one of the electrodes of the capacitor and the other of the terminals of the third switch; and a third wiring connected to the other of the electrodes of the load. The first wiring is electrically connected to a circuit having a function of supplying a first potential and a second potential. The second wiring is electrically connected to a circuit having a function of supplying a third potential. The third wiring is electrically connected to a circuit having a function of supplying a fourth potential. The first potential is lower than the fourth potential. The second potential is used for controlling the amount of current flowing between the second wiring supplied with the third potential and the third wiring supplied with the fourth potential by the transistor.
One embodiment of the present invention is a semiconductor device which includes a transistor including a gate electrically connected to one of electrodes of a capacitor and one of terminals of a first switch, a source and a drain one of which is electrically connected to one of terminals of a second switch and one of terminals of a third switch and the other of which is electrically connected to the other of the terminals of the first switch and one of terminals of a fourth switch; a first wiring electrically connected to the other of the terminals of the second switch; a second wiring electrically connected to the other of the terminals of the fourth switch, a load including electrodes one of which is electrically connected to the one of the electrodes of the capacitor and the other of the terminals of the third switch; and a third wiring connected to the other of the electrodes of the load. The first wiring is electrically connected to a circuit having a function of supplying a first potential. The second wiring is electrically connected to a circuit having a function of supplying a second potential and a third potential. The third wiring is electrically connected to a circuit having a function of supplying a fourth potential. The second potential is lower than the fourth potential. The first potential is used for controlling the amount of current flowing between the second wiring supplied with the third potential and the third wiring supplied with the fourth potential by the transistor.
One embodiment of the present invention is a semiconductor device which includes a transistor including a gate electrically connected to one of electrodes of a capacitor and one of terminals of a first switch, a source and a drain one of which is electrically connected to one of terminals of a second switch, one of terminals of a third switch, and one of terminals of a fourth switch and the other of which is electrically connected to the other of the terminals of the first switch and one of terminals of a fifth switch; a first wiring electrically connected to the other of the terminals of the second switch; a second wiring electrically connected to the other of the terminals of the fourth switch; a third wiring electrically connected to the other of the terminals of the fifth switch; a load including electrodes one of which is electrically connected to the one of the electrodes of the capacitor and the other of the terminals of the third switch; and a fourth wiring connected to the other of the electrodes of the load. The first wiring is electrically connected to a circuit having a function of supplying a first potential. The second wiring is electrically connected to a circuit having a function of supplying a second potential. The third wiring is electrically connected to a circuit having a function of supplying a third potential. The fourth wiring is electrically connected to a circuit having a function of supplying a fourth potential. The second potential is lower than the fourth potential. The first potential is used for controlling the amount of current flowing between the third wiring supplying the third potential and the fourth wiring supplying the fourth potential by the transistor.
In the semiconductor device according to one embodiment of the present invention, the switches are transistors.
In the semiconductor device according to one embodiment of the present invention, the switches are transistors and the transistors have the same polarity.
In the semiconductor device according to one embodiment of the present invention, the load is preferably the display element with a rectification property.
In one embodiment of the present invention, adverse effect of variations in threshold voltage of transistors can be reduced. Alternatively, according to one embodiment of the present invention, adverse effect of variations in mobility of transistors can be reduced. Alternatively, according to one embodiment of the present invention, adverse effect of deterioration of a transistor can be reduced. Alternatively, according to one embodiment of the present invention, adverse effect of deterioration of a display element can be reduced. Alternatively, according to one embodiment of the present invention, display unevenness can be reduced. Alternatively, according to one embodiment of the present invention, an image can be displayed with high display quality. Alternatively, according to one embodiment of the present invention, a desired circuit with a small number of transistors can be achieved. Alternatively, according to one embodiment of the present invention, a desired circuit with a small number of wirings can be achieved. Alternatively, one embodiment of the present invention can be manufactured through a small number of steps.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the description below, and it is easily understood by those skilled in the art that a variety of changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be limited to the descriptions of the embodiments below. Note that in the structures described below, the same portions or portions having similar functions are denoted by the same reference numerals in common in different drawings and repetitive description thereof will be omitted.
Note that what is described (or part thereof) in one embodiment can be applied to, combined with, or exchanged with another content in the same embodiment and/or what is described (or part thereof) in another embodiment or other embodiments.
Note that the structure of a diagram (or part of the diagram) illustrated in one embodiment can be combined with the structure of another part of the diagram, the structure of a different diagram (or part of the different diagram) illustrated in the embodiment, and/or the structure of a diagram (or part of the diagram) illustrated in one or more different embodiments.
Note that the size, the thickness, or regions in diagrams are sometimes exaggerated for simplicity. Thus, one aspect of one embodiment of the present invention is not limited to such scales. Alternatively, the drawings are perspective views of ideal examples. Thus, one aspect of one embodiment of the present invention is not limited to shapes and the like illustrated in the drawings. For example, the drawings can include variations in shape due to a manufacturing technique or dimensional deviation.
Note that an explicit description “X and Y are connected” indicates the case where X and Y are electrically connected, the case where X and Y are connected in terms of the function, the case where X and Y are directly connected, or the like. Here, each of X and Y denotes an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like). Accordingly, another connection relation shown in drawings and texts is included without being limited to a predetermined connection relation, for example, the connection relation shown in the drawings and the texts.
For example, in the case where X and Y are electrically connected, one or more elements which enable electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, and a load) can be connected between X and Y. Note that the switch is controlled to be turned on or off. That is, the switch has a function of determining whether current flows or not by being turning on or off (becoming an on state and an off state). Alternatively, the switch has a function of determining and changing a current path. For example, the switch has a function of determining whether current flows through a current path 1 or a current path 2 and switching the paths.
For example, in the case where X and Y are functionally connected, one or more circuits that enable functional connection between X and Y (e.g., a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; a signal converter circuit such as a DA converter circuit, an AD converter circuit, or a gamma correction circuit; a potential level converter circuit such as a power supply circuit (e.g., a dc-dc converter, a step-up dc-dc converter, or a step-down dc-dc converter) or a level shifter circuit for changing the potential level of a signal; a voltage source; a current source; a switching circuit; an amplifier circuit such as a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit; a signal generation circuit; a memory circuit; and/or a control circuit) can be connected between X and Y. Note that for example, in the case where a signal output from X is transmitted to Y even when another circuit is interposed between X and Y, X and Y are functionally connected.
Note that an explicit expression “X and Y are electrically connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. That is, when it is explicitly described that “A and B are electrically connected”, the description is the same as the case where it is explicitly only described that “A and B are connected”.
Note that even when independent components are electrically connected to each other in a circuit diagram, there is the case where one conductive layer has functions of a plurality of components (e.g., a wiring and an electrode), such as the case where part of a wiring functions as an electrode. The expression “electrically connected” in this specification also means that one conductive layer has functions of a plurality of components.
Note that it might be possible for those skilled in the art to constitute one embodiment of the invention even when portions to which all terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected are not specified. In particular, in the case where the number of portions to which the terminal is connected might be plural, it is not necessary to specify the portions to which the terminal is connected. Therefore, it might be possible to constitute one embodiment of the invention by specifying only portions to which some of terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected.
Note that it might be possible for those skilled in the art to specify the invention when at least a connection portion of a circuit is specified. Alternatively, it might be possible for those skilled in the art to specify the invention when at least a function of a circuit is specified. Therefore, when a connection portion of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a function is not specified, and one embodiment of the invention can be constituted. Alternatively, when a function of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a connection portion is not specified, and one embodiment of the invention can be constituted.
Note that various people can implement the present invention described in this specification and the like. However, different people may implement the present invention in a joint effort with each other. For example, when an invention relating to a transmission/reception system is impremented, Company A manufactures and sells transmitting devices, and Company B manufactures and sells receiving devices, in some cases. As another example, when an invention relating to a light emitting device including TFTs and light-emitting elements is impremented, Company A manufactures and sells semiconductor devices including TFTs and Company B buys the semiconductor devices, deposits light-emitting elements to the semiconductor devices, and completes light emitting devices, in some cases.
In such a case, with one embodiment of the present invention, a person can file a patent infringement suit against Company A and Company B. That is, one embodiment of the present invention with which a person can file a patent infringement suit against Company A and Company B is clear and regarded as being described in this specification or the like. For example, in the case of a transmission/reception system, one embodiment of the present invention can be constituted of only a transmitting device and can be constituted of only a receiving device. The embodiment of the present invention is clear and regarded as being described in this specification or the like. As another example, in the case of a light emitting device including a TFT and a light-emitting element, one embodiment of the present invention can be constituted of only a semiconductor device including a TFT and can be constituted of only a light emitting device including a TFT and a light-emitting element. The embodiment of the present invention is clear and regarded as being described in this specification or the like.
The invention excluding content which is not specified in the drawings and texts in this specification can be constituted. Alternatively, when the range of a value (e.g., the maximum and minimum values) is described, part of the range is arbitrarily shortened and part of the range is removed, so that an invention can be specified by a range part of which is removed from the number range. In this manner, it is possible to specify the scope of the present invention so that a conventional technology is excluded, for example.
As a specific example, a diagram of a circuit including a first transistor to a fifth transistor is illustrated. In that case, it can be specified that a circuit of an invention does not include a sixth transistor. Alternatively, it can be specified that a circuit of an invention does not include a capacitor. Further alternatively, it can be specified that a circuit of an invention does not include a sixth transistor with a particular connection relation. Still alternatively, it can be specified that a circuit of an invention does not include a capacitor with a particular connection relation. For example, it can be specified that a circuit of an invention does not include the sixth transistor whose gate is connected to a gate of the third transistor. Alternatively, it can be specified that a circuit of an invention does not include the capacitor whose first electrode is connected to the gate of the third transistor.
As another specific example, a description says that “a voltage is preferably higher than or equal to 3 V and lower than or equal to 10 V”. In that case, for example, it can be specified that an invention excludes the case where the voltage is higher than or equal to −2 V and lower than or equal to 1 V. Alternatively, for example, it can be specified that an invention excludes the case where the voltage is higher than or equal to 13 V. Note that for example, it can be specified that in an invention, the voltage is higher than or equal to 5 V and lower than or equal to 8 V. Note that for example, it can be specified that in an invention, the voltage is approximately 9 V. Note that for example, it can be specified that in an invention, the voltage is higher than or equal to 3 V and lower than 9 V and higher than 9V and lower than or equal to 10 V.
As another specific example, a description says that “a voltage is preferably 10 V”. In that case, for example, it can be specified that an invention excludes the case where the voltage is higher than or equal to −2 V and lower than or equal to 1 V. Alternatively, for example, it can be specified that an invention excludes the case where the voltage is higher than or equal to 13 V.
As another specific example, a description says about a property of a film that “the film is an insulating film”. In that case, for example, it can be specified that in an invention, the insulating film is not an organic insulating film. Alternatively, for example, it can be specified that in an invention, the insulating film is not an organic insulating film.
As another specific example, a description says about a stacked structure that “a film is provided between A and B”. In that case, for example, it can be specified that in an invention, the film is not a stacked film of four or more layers. Alternatively, for example, it can be specified that in an invention, a conductive film is not provided between A and the film.
An embodiment of the present invention can be used for not only a pixel including a light-emitting element but also a variety of analog circuits functioning as current sources. First, in this embodiment, examples of a basic principle of a circuit disclosed in the present invention is described.
First,
Note that there is a voltage source as a power source different from a current source. The voltage source has a function of supplying a constant voltage even when current flowing through a circuit connected to the voltage source is changed. Accordingly, the voltage source and the current source both have a similar function. However, the voltage source and the current source are different. Specifically, the voltage source and the current source are different in what they supply, which is voltage or current. Further, the voltage source and the current source are different. Specifically, the voltage source and the current source are different in parameter, change of which enables the voltage source or the current source to supply voltage or current. The current source has a function of supplying a constant current event when voltage between both ends is changed. The voltage source has a function of supplying a constant voltage even when current is changed.
The circuit configuration illustrated in
The semiconductor device 10 illustrated in
Next, a connection relation of components of the semiconductor device 10 is described.
A gate of the transistor 11 is connected to one of electrodes (terminals) of the capacitor 17 and one of terminals of the switch 13. A first terminal (one of a source and a drain) of the transistor 11 is connected to one of terminals of the switch 12 and one of terminals of the switch 14. A second terminal (the other of the source and the drain) of the transistor 11 is connected to the other of the terminals of the switch 13 and one of terminals of the switch 15. Note that one of terminals is also referred to as a first terminal and the other of the terminals is also referred to as a second terminal.
The other of the terminals of the switch 12 is connected to the wiring 18.
The other of the terminals of the switch 15 is connected to the wiring 20.
One of terminals of the load 16 is connected to the other of the terminals of the switch 14 and the other of the electrodes (terminals) of the capacitor 17. The other of the terminals of the load 16 is connected to the wiring 19.
Note that in this specification, a semiconductor device means any device which can function by utilizing semiconductor characteristics; a light emitting device, a display device, a semiconductor circuit, and an electronic device are included as examples of the semiconductor device in some cases.
Note that in this specification, a load means an object having a rectifying property, an object having a capacitive property, an object having a resistive property, a circuit including a switch, a pixel circuit, or the like. For example, the object having a rectifying property has current-voltage characteristics showing different resistance values based on the direction of an applied bias, and has an electric property which allows current to flow only in one direction. In the circuit configuration illustrated in
Alternatively, other examples of the load 16 are a display element (liquid crystal element), a light-emitting element (an EL element), and part of a display element or a light-emitting element (e.g., a pixel electrode, an anode electrode, and a cathode electrode).
Note that a transistor is an element having at least three terminals: a gate, a drain, and a source. In addition, the transistor has a channel region between a drain (drain terminal, a drain region, or a drain electrode) and a source (source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. Here, since the source and the drain of the transistor may change depending on the structure, the operating condition, and the like of the transistor, it is difficult to define which is a source or a drain. Therefore, in this document (the specification, the claims, the drawings, and the like), a region functioning as a source and a drain is not called the source or the drain in some cases. In such a case, for example, one of the source and the drain may be referred to as a first terminal and the other thereof may be referred to as a second terminal. Alternatively, one of the source and the drain may be referred to as a first electrode and the other thereof may be referred to as a second electrode. Further alternatively, one of the source and the drain may be referred to as a first region and the other thereof may be referred to as a second region. Still alternatively, one of the source and the drain may be referred to as a source region and the other thereof may be called a drain region.
Note that terms such as “first”, “second”, “third”, and the like are used for distinguishing various elements, members, regions, layers, and areas from others. Therefore, the terms such as “first”, “second”, “third”, and the like do not limit the number of the elements, members, regions, layers, areas, or the like. Further, for example, “first” can be replaced with “second”, “third”, or the like.
Note that the switch has a function of operating by bringing terminals into a conduction state (ON) or a non-conduction state (OFF) and a function of determining whether or not current flows. The switch can be an electrical switch, a mechanical switch, or the like. For example, the switch can be formed using a transistor, a diode, and a micro electro mechanical system (MEMS) technology similarly to a digital micromirror device (DMD). Alternatively, the switch may be a logic circuit in which transistors are combined. Note that in the case of using a transistor, a polarity (conductivity type) thereof is not particularly limited. Note that a transistor having a low off-state current is preferably used and a configuration in which the transistor has an appropriate polarity in accordance with an input potential is preferable.
Examples of a transistor with lower off-state current are a transistor provided with an LDD region, a transistor with a multi-gate structure, and a transistor including an oxide semiconductor in a semiconductor layer. Alternatively in the case where a combination of transistors functions as a switch, a complementary switch may be employed by using both re-channel and p-channel transistors. A complementary switch achieves an appropriate operation even when a potential input to the switch is relatively changed in comparison with an output potential.
Note that when a transistor is used as a switch, the switch includes an input terminal (one of a source and a drain), an output terminal (the other of the source and the drain), and a terminal for controlling conduction (gate) in some cases. On the other hand, when a diode is used as a switch, the switch does not have a terminal for controlling electrical conduction in some cases. Therefore, when a diode is used as a switch, the number of wirings for controlling terminals can be reduced as compared to the case of using a transistor.
Note that for example, a transistor with a structure where gate electrodes are formed above and below a channel can be used as a transistor. With the structure where the gate electrodes are formed above and below the channel, a circuit structure where a plurality of transistors are connected in parallel is provided. Thus, a channel region is increased, so that the amount of current can be increased. Alternatively, by employing the structure where gate electrodes are formed above and below the channel, a depletion layer is easily formed; thus, a subthreshold swing (an S value) can be reduced.
Note that for example, a transistor with a structure where a source electrode or a drain electrode overlaps with a channel region (or part of it) can be used as a transistor. By using the structure where the source electrode or the drain electrode may overlap with the channel region (or part of it), an unstable operation due to electric charge accumulated in part of the channel region can be prevented.
Note that the capacitor 17 may have a structure in which an insulating film is sandwiched between wirings, semiconductor layers, electrodes, or the like, for example. The capacitor 17 has a function of capable of holding voltage in accordance with characteristics of the transistor 11 (e.g., voltage in accordance with a threshold voltage and a voltage in accordance with mobility). Alternatively, the capacitor 17 has a function of capable of holding voltage (e.g., a video signal) in accordance with the amount of current supplied to the load 16.
Note that as illustrated in
The potential Vinit initializes the potential of each node in the semiconductor device, for example. For example, Vinit is supplied before Vsig which is a signal for making current flow to the load 16.
An example of Vsig is a signal for controlling the amount of current flowing to the load 16. Therefore, a potential to be supplied depends on the amount of current to be supplied to the load 16. For example, when current supplied to the load 16 is constant, Vsig is a signal with a constant potential. When current supplied to the load 16 is not constant, Vsig is a signal with a potential which changes over time depending on the amount of current to be supplied to the load 16.
Note that as illustrated in
The potential Vcat is set to make current flow from the first electrode side of the load 16 to the second electrode side of the load 16 in a period in which current flows to the load 16.
Note that as illustrated in
The potential VDD is set to make current flow from the first electrode side of the load 16 to the second electrode side of the load 16 through the transistor 11. Therefore, for example, VDD is higher than Vcat.
Note that each of the switch 12, the switch 13, the switch 14, and the switch 15 which are illustrated in
In
A gate of the transistor 12T is connected to a wiring 31. A first terminal of the transistor 12T is connected to the first terminal of the transistor 11 and a first terminal of the transistor 14T. A second terminal of the transistor 12T is connected to the wiring 18. Therefore, the transistor 12T is in a conduction state when the potential of the wiring 31 is at an H level, and the transistor 12T is in a non-conduction state when the potential of the wiring 31 is at an L level.
Further, a gate of the transistor 13T is connected to a wiring 32. A first terminal of the transistor 13T is connected to the gate of the transistor 11 and the one of the electrodes of the capacitor 17. A second terminal of the transistor 13T is connected to a first terminal of the transistor 15T and the second terminal of the transistor 11. Therefore, the transistor 13T is in a conduction state when the potential of the wiring 32 is at an H level, and the transistor 13T is in a non-conduction state when the potential of the wiring 32 is at an L level.
Furthermore, a gate of the transistor 14T is connected to a wiring 33. A first terminal of the transistor 14T is connected to the first terminal of the transistor 11 and the first terminal of the transistor 12T. A second terminal of the transistor 14T is connected to the first electrode of the load 16 and the other electrode of the capacitor 17. Therefore, the transistor 14T is in a conduction state when the potential of the wiring 33 is at an H level, and the transistor 14T is in a non-conduction state when the potential of the wiring 33 is at an L level.
In addition, a gate of the transistor 15T is connected to a wiring 34. The first terminal of the transistor 15T is connected to the second terminal of the transistor 11 and the second terminal of the transistor 13T. A second terminal of the transistor 15T is connected to the wiring 20. Therefore, the transistor 15T is in a conduction state when the potential of the wiring 34 is at an H level, and the transistor 15T is in a non-conduction state when the potential of the wiring 34 is at an L level.
Note that for example, the wiring 31 is connected to a circuit 24A, the wiring 32 is connected to a circuit 24B, the wiring 33 is connected to a circuit 24C, and the wiring 34 is connected to a circuit 24D. The circuits 24A to 24D each have a function of supplying a signal at an H level or an L level, for example. An example of each of the circuits 24A to 24D is a gate driver (scan line driver circuit) or the like. Accordingly, the wiring 31 has a function of capable of transmitting or supplying a signal at an H level or an L level. Alternatively, the wiring 31 has a function of capable of controlling a conduction state of the switch 12 or the transistor 12T. The wiring 32 has a function of capable of controlling a conduction state of the switch 13 or the transistor 13T. The wiring 33 has a function of capable of controlling a conduction state of the switch 14 or the transistor 14T. The wiring 34 has a function of capable of controlling a conduction state of the switch 15 or the transistor 15T.
Note that the wiring 31, the wiring 32, the wiring 33, and the wiring 34 can function as different wirings. However, one embodiment of the present invention is not limited thereto. The wirings 31 to 34 can be combined into one wiring; therefore, it is possible to form a circuit with a small number of wirings.
For example, the wiring 31 and the wiring 32 can be combined into one wiring. Therefore, the wiring 31 can be connected to the wiring 32 to be one wiring. At this time, the transistor 12T and the transistor 13T preferably have the same polarity.
For example, the wiring 33 and the wiring 34 can be combined into one wiring. Therefore, the wiring 33 can be connected to the wiring 34 to be one wiring. At this time, the transistor 14T and the transistor 15T preferably have the same polarity.
Note that the wiring 31 and the wiring 32 can be combined into one wiring and the wiring 33 and the wiring 34 can be combined into one wiring.
In many cases, the transistor 11 operates in a saturation region at the time of passing current. Therefore, the transistor 11 preferably has a longer channel length or gate length than the transistor 12T, the transistor 13T, the transistor 14T, or the transistor 15T. When the channel length or the gate length is longer, characteristics in a saturation region have a flat slope; accordingly, a kink effect can be reduced. Note that one embodiment of the present invention is not limited to these examples.
In many cases, the transistor 11 operates in a saturation region at the time of passing current. Therefore, the transistor 11 preferably has a larger channel width or gate width than the transistor 12T, the transistor 13T, the transistor 14T, or the transistor 15T. When the channel width or the gate width is larger, a large amount of current can flow even in a saturation region. Note that one embodiment of the present invention is not limited to these examples.
Next, the operation of the semiconductor device 10 illustrated in
Note that in order to explain the operation of the circuit configuration illustrated in
A nodeA, a nodeB, a nodeC, a nodeD, a nodeE, a nodeF, and a nodeG correspond to nodes and wirings illustrated in
First, the first operation is described with reference to
The first operation initializes the potential of each node. Specifically, the nodeA is set at Vinit, the nodeD is set at Vcat, and the nodeG is set at VDD. Then, the switch 12, the switch 13, the switch 14, and the switch 15 are turned on. Thus, the nodeB is set at Vinit, the nodeC is set at Vinit, the nodeE is set at VDD, and the nodeF is set at VDD. Further, Vgs becomes (VDD−Vinit), and Vc becomes (VDD−Vinit).
As described above, in the first operation, Vinit at the nodeB and the nodeC is equal to or lower than Vcat at the nodeD, for example. With this structure, current is prevented from flowing to the load 16 in the first operation. Accordingly, problems caused by current flowing to the load 16 can be reduced. Further, when Vinit is lower than Vcat, the load 16 can be reverse biased. In that case, deterioration of the load 16 can be reduced and the load 16 can be repaired.
In the first operation, VDD at the nodeE and the nodeF is higher than Vcat at the nodeD. With this structure, Vgs can be higher than the threshold voltage of the transistor 11 in the first operation. Alternatively, electric charge can be charged in the capacitor 17.
Next, the second operation is described with reference to
The second operation is the operation for obtaining the threshold voltage of the transistor 11 as Vgs by discharging the potential of the gate of the transistor 11 (or the electric charge charged in the capacitor 17). Specifically, the nodeA is set at Vsig, the nodeD is set at Vcat, and the nodeG is set at VDD. Then, the switch 12 and the switch 13 are turned on, and the switch 14 and the switch 15 are turned off. Accordingly, the potential of the nodeB becomes Vsig, the potential of the nodeC becomes (Vinit−Vx), the potential of the nodeE becomes (Vsig+Vth), and the potential of the nodeF becomes (Vsig+Vth). Further, Vgs becomes Vth and Vc becomes (Vsig+Vth−Vinit+Vx).
As described above, Vsig at the nodeB in the second operation is the potential used for controlling the amount of current flowing between the wiring 20 and the wiring 19 with the use of the transistor 11 in the third operation. By the second operation, the potential of the nodeE corresponding to the potential of the gate of the transistor 11 can be (Vsig+Vth) which includes the threshold voltage of the transistor 11.
In the second operation, Vx of the potential of the nodeC (Vinit−Vx) changes when the nodeC is set in an electrically floating state. In this case, the amount of changes in Vx depends on a ratio of parasitic capacitance of the load 16 to the capacitance of the capacitor 17. Note that Vx is preferably set to a low potential in advance. Specifically, the parasitic capacitance of the load 16 is set to be sufficiently larger than the capacitance of the capacitor 17, whereby Vx can be low. It is preferable that the parasitic capacitance of the load 16 be two times or more, more preferably four times or more the capacitance of the capacitor 17.
Further, VDD at the nodeD and the nodeE in the first operation is discharged by the second operation. By the discharging, Vgs is decreased to the threshold voltage Vth of the transistor 11 and is set in a steady state. Therefore, the discharging makes the nodeD and the nodeE are set in a steady state at (Vsig+Vth). In addition, at the time of terminating the second operation, (Vsig+Vth−Vinit+Vx) is held as Vc.
Note that in some cases, it takes a very long time until Vgs becomes equal to the threshold voltage Vth of the transistor 11. Accordingly, in many case, the semiconductor device is driven while Vgs is not completely decreased to the threshold voltage Vth. That is, in many cases, the second operation is terminated while Vgs is slightly higher than the threshold voltage Vth. In other words, at the time of terminating the second operation, Vgs is based on the threshold voltage.
Note that in the second operation, the switch 14 and the switch 15 are turned off and the potential of the nodeB is set to Vsig. These operations can be performed at the same time or at different timings.
It is preferable that, for example, the potential of the nodeB be changed from Vinit to Vsig at the same time as or after the switch 14 is turned off. This is because the potential of the nodeC can be easily held at an appropriate potential.
Alternatively, it is preferable that, for example, the potential of the nodeB be changed from Vinit to Vsig before or at the same time as the switch 15 is turned off. This is because the gate potential of the transistor 101 can be quickly lowered.
Next, the third operation is described with reference to
The third operation is the operation for outputting current to the load 16 with the use of the transistor 11 as part of a current source. Specifically, the nodeA is set at Vsig, for example, though it can be any potential, the nodeD is set at Vcat, and the nodeG is set at VDD. Then, the switch 14 and the switch 15 are turned on, and the switch 12 and the switch 13 are turned off. Accordingly, the nodeB and the nodeC become Vel, the nodeE becomes (Vsig+Vth−Vinit+Vx+Vel), and the nodeF becomes VDD. In addition, Vgs becomes (Vsig+Vth−Vinit+Vx) and Vc becomes (Vsig+Vth−Vinit+Vx).
Note that in the third operation, the potentials of the nodeB, the nodeC, and the nodeF are increased while the nodeE is kept in an electrically floating state. Accordingly, the potential of the nodeE is increased by capacitive coupling while (Vsig+Vth−Vinit+Vx) is held as Vc, thereby becoming (Vsig+Vth−Vinit+Vx+Vel). That is, an increase in the potential of the nodeC leads to an increase in the potential of the nodeE by bootstrap operation.
The semiconductor device can operate even when the potential of the nodeC is increased; therefore, adverse effect of deterioration in voltage current characteristics of the load (e.g., a display element and a light-emitting element) can be reduced even when the deterioration is caused.
The potential Vel which is the potentials of the nodeB and the nodeC is set when the potential of the nodeF is increased to VDD and current flows to the load 16 through the transistor 11 which allows the semiconductor device to operate as a current source by the third operation. Specifically, the potential ranges from VDD to Vcat.
In the third operation, Vgs of the transistor 11 becomes (Vsig+Vth−Vinit+Vx), which includes the threshold voltage of the transistor 11. The amount of current of the transistor 11 depends on (Vgs−Vth). Accordingly, through the above operations, adverse effect of variations in the threshold voltage of the transistor on the amount of current supplied to the load can be reduced. Alternatively, even when the threshold voltage is changed by deterioration of the transistor, adverse effect of the change can be reduced. Therefore, in the case of a display element, display unevenness can be reduced and display can be performed with high quality.
Note that in the third operation, the switch 12 and the switch 13 are turned off and the switch 14 and the switch 15 are turned on. These operations can be performed at the same time or at different timings.
For example, it is preferable that the switch 14 and the switch 15 be turned on after the switch 12 and the switch 13 are turned off. This is because Vc can be easily held at an appropriate potential.
Alternatively, for example, it is preferable that the switch 12 be turned off after the switch 13 is turned off. This is because Vc can be easily held at an appropriate potential.
Note that
For example, specifically, the switch 12, the switch 13, the switch 14, and the switch 15 can be provided at any place and the number of switches is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
Note that the operation for correcting the threshold voltage of the transistor is described with reference to
Note that a first operation illustrated in
Next, a third operation is described with reference to
In the third operation, the transistor 11 is turned on with the use of the potential held in the gate of the transistor 11 (electric charge stored in the capacitor 17), and the mobility of the transistor 11 is corrected with the use of the amount of current flowing therethrough. Specifically, the nodeA is set at Vsig though it can be any potential, the nodeD is set at Vcat, and the nodeG is set at VDD though it can be any potential. Then, the switch 13 and the switch 14 are turned on, and the switch 12 and the switch 15 are turned off. Then, the amount of change in potentials of the nodeB and the nodeC is −ΔVel, the nodeE and the nodeF become (Vsig+Vth−ΔVel). In addition, Vgs becomes (Vth+ΔVel) and Vc becomes (Vsig+Vth−Vinit+Vx−ΔVel).
Note that in the third operation, the potentials of the nodeB and the nodeC are changed by turning on the switch 14. The amount of changes in the potentials corresponds to −ΔVel. When the amount of change in the potentials of the nodeB and the nodeC becomes −ΔVel, Vgs becomes (Vth+ΔVel) and higher than the threshold voltage Vth; as a result, current flows through the transistor 11. When current flows through the transistor 11, each of the potentials of the nodeE and the nodeF is decreased to (Vsig+Vth−ΔVel) and Vc becomes (Vsig+Vth−Vinit+Vx−ΔVel).
The amount of current flowing to the transistor 11 changes depending on the mobility of the transistor 11. Accordingly, the potential of the nodeE corresponding to the gate of the transistor 11 can be set so as to include the amount of change in potential corresponding to the mobility of the transistor 11.
In the third operation, the potential of the gate of the transistor 11 becomes (Vsig+Vth−ΔVel) which is set in consideration of the mobility of the transistor 11. Accordingly, through the above operations, adverse effect of variations in the mobility of the transistor on the amount of current supplied to the load can be reduced. Alternatively, even when mobility is changed by deterioration of the transistor, adverse effect of the change can be reduced.
Next, a fourth operation is described with reference to
By the fourth operation, the nodeB and the nodeC are set at Vel, the nodeE is set at (Vsig+Vth−Vinit+Vx−ΔVel+Vel), and the nodeF is set at VDD. The potential Vgs becomes (Vsig+Vth−Vinit+Vx−ΔVel) and Vc becomes (Vsig+Vth−Vinit+Vx).
In the fourth operation, Vgs of the transistor 11 becomes (Vsig+Vth−Vinit+Vx+ΔVel), which can be set in consideration of the threshold voltage and the mobility of the transistor 11. Accordingly, through the above operations, adverse effect of variations in the threshold voltage and the mobility of the transistor on the amount of current supplied to the load can be reduced.
The location of the switch or the number of switches can be changed and appropriate voltage can be supplied so as to achieve the similar operation to the operation described in
For example, specifically, the switch 12, the switch 13, the switch 14, and the switch 15 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
Note that
For example, as in a semiconductor device 10A illustrated in
As another example, as in a semiconductor device 10B illustrated in
As another example, as in a semiconductor device 10C illustrated in
The channel width and/or the channel length of the transistor 11 can be changed by application of the structures illustrated in
Note that
Therefore, a circuit can be formed with a small number of transistors in the case where a transistor is not added.
Note that variations in the threshold voltage or the like of a transistor is corrected in this embodiment, but one embodiment of the present invention is not limited thereto. For example, current can be supplied to the load 16 and the semiconductor device can be driven without performing the operation for correcting variations in threshold voltage.
This embodiment shows an example of a basic principle. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, an example of a configuration different from the circuit configuration of the semiconductor device described in Embodiment 1 is described.
Next, the operation of the semiconductor device 10h illustrated in
Note that in order to explain the operation of the circuit configuration illustrated in
In the first operation, a potential for initialization is applied to some extent at each node before initialization of the potential of each node (initialization before initialization). Specifically, the nodeG is set at Vinit and the nodeD is set at Vcat. The nodeA can be set at any potential. In addition, the switch 14 and the switch 15 are turned on, and the switch 12 and the switch 13 are turned off. The nodeB and the nodeC are then set at Vinit or the potential ΔVinit which is close to Vinit. The nodeE is set at Vy and the nodeF is set at Vinit. Note that Vgs and Vc are omitted because the first operation uses Vy which is a signal of an operation before the first operation.
The potential Vy is input before the first operation. The case where Vy enables the transistor 11 to operate as part of a current source is explained. The potential Vy is set so that current flows between the first terminal and the second terminal of the transistor 11 in the first operation. Usually, Vinit is very low and accordingly the transistor 11 is turned on because of Vy in many cases.
Therefore, in the first operation, the nodeF is set at Vinit and current flows between the first terminal and the second terminal of the transistor 11; as a result, the nodeB and the nodeC are set at Vinit or the potential ΔVinit which is close to Vinit.
That is, the first operation decreases the potentials of the nodeB and the nodeC. By the decrease in the potentials of the nodeB and the nodeC in the first operation, the following second operation can initialize the potential of each node at high speed. In particular, when the load 16 has large capacitance, the following operation can be performed smoothly by the decrease in the potentials of the nodeB and the nodeC in advance. Note that even if the potentials of the nodeB and the nodeC cannot be sufficiently decreased, it is not a problem unless subsequent operations are adversely affected.
The second operation is the same as the first operation described with reference to
In the second operation, the switch 12 and the switch 13 are turned on and the potential of the nodeG is set to VDD, and these operations can be performed at the same time or at different timings.
It is preferable that, for example, the potential of the nodeG be changed from Vinit to VDD before or at the same time as the switch 13 is turned on. This is because the potential of the nodeE can be increased easily in that case.
Then, the third operation illustrated in
The location of the switch or the number of switches can be changed and appropriate voltage can be supplied so as to achieve the similar operation to the operation described in
For example, specifically, the switch 12, the switch 13, the switch 14, and the switch 15 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
Note that the operation for correcting the threshold voltage of the transistor is described with reference to
The operation for correcting the mobility of the transistor 11 is described with reference to
The operation for correcting the mobility of the transistor 11 is the same as the third operation described with reference to
In the operation for correcting the mobility of the transistor 11, the potential of the gate of the transistor 11 becomes (Vsig+Vth−ΔVel) which is set in consideration of the mobility of the transistor 11. Accordingly, through the above operation, adverse effect of variations in the mobility of the transistor on the amount of current supplied to the load can be reduced.
The location of the switch or the number of switches can be changed and appropriate voltage can be supplied so as to achieve the similar operation to the operation described in
For example, specifically, the switch 12, the switch 13, the switch 14, and the switch 15 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the operation for correcting the mobility of the transistor described with reference to
The potential of the wiring 20 is switched between Vinit and VDD in the circuit configuration illustrated in
As described above, in the circuit configuration described in this embodiment, initialization before initialization can be performed by switching of the potential of the wiring 20 between Vinit and VDD. Accordingly, the potential of each node can be initialized at high speed. In the fourth operation, Vgs of the transistor 11 becomes (Vsig+Vth−Vinit+Vx), which includes the threshold voltage of the transistor 11. Accordingly, with this structure, adverse effect of variations in the threshold voltage of the transistor on the amount of current supplied to the load can be reduced.
Note that
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, an example of a configuration different from the circuit configurations of the semiconductor devices described in Embodiments 1 and 2 is described.
In
Next, the operation of the semiconductor device 10h illustrated in
Note that in order to explain the operation of the circuit configuration illustrated in
A nodeA, a nodeB, a nodeC, a nodeD, a nodeE, a nodeF, a nodeG, and a nodeH correspond to nodes and wirings illustrated in
First, the first operation is described with reference to
The first operation initializes the potential of each node. Specifically, the nodeA is set at any potential, the nodeD is set at Vcat, the nodeG is set at VDD, and the nodeH is set at Vinit. Then, the switch 12p, the switch 13, the switch 14, and the switch 15 are turned on, and the switch 12 is turned off. Thus, the nodeB is set at Vinit, the nodeC is set at Vinit, the nodeE is set at VDD, and the nodeF is set at VDD. Further, Vgs becomes (VDD−Vinit), and Vc becomes (VDD−Vinit).
The first operation described with reference to
Next, the second operation is described with reference to
The second operation is the operation for obtaining the threshold voltage of the transistor 11 with the use of Vgs by discharging the potential of the gate of the transistor 11 (or the electric charge of the capacitor 17). Specifically, the nodeA is set at Vsig, the nodeD is set at Vcat, the nodeG is set at VDD, and the nodeH is set at Vinit though it can be any potential. Then, the switch 12 and the switch 13 are turned on, and the switch 14, the switch 12p, and the switch 15 are turned off. Thus, the potential of the nodeB becomes Vsig, the potential of the nodeC becomes (Vinit−Vx), the potential of the nodeE becomes (Vsig+Vth), and the potential of the nodeF becomes (Vsig+Vth). Further, Vgs becomes Vth and Vc becomes (Vsig+Vth−Vinit+Vx).
The second operation described with reference to
Note that in the second operation, the switch 14, the switch 15, and the switch 12p are turned off and the switch 12 is turned on, and these operations can be performed at the same time or at different timings.
For example, it is preferable that the switch 12 be turned on at the same time as or after the switch 12p is turned off. This is because a short circuit between the nodeA and the nodeH can be prevented easily.
Next, the third operation is described with reference to
The third operation is the operation for outputting current to the load 16 with the use of the transistor 11 as part of a current source. Specifically, the nodeA is set at Vsig though it can be any potential, the nodeD is set at Vcat, the nodeG is set at VDD, and the nodeH can be set at Vinit though it can be any potential. Then, the switch 14 and the switch 15 are turned on, and the switch 12, the switch 12p, and the switch 13 are turned off. Then, the nodeB and the nodeC become Vel, the nodeE becomes (Vsig+Vth−Vinit+Vx+Vel), and the nodeF becomes VDD. In addition, Vgs becomes (Vsig+Vth−Vinit+Vx) and Vc becomes (Vsig+Vth−Vinit+Vx).
The third operation described with reference to
Note that
For example, specifically, the switch 12, the switch 12p, the switch 13, the switch 14, and the switch 15 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
As described above, in the circuit configuration described in this embodiment, the wiring 18p is provided and the initialization can be performed with the use of Vinit supplied from the wiring 18p through the switch 12p. Accordingly, time for initializing the potential of each node can be long. Alternatively, the initialization with the use of Vinit is not necessarily performed by using the wiring 18, which can save time allowing time for the second operation to be longer. In the third operation, Vgs of the transistor 11 becomes (Vsig+Vth−Vinit+Vx), which includes the threshold voltage of the transistor 11. Accordingly, with this structure, adverse effect of variations in the threshold voltage of the transistor on the amount of current supplied to the load can be reduced.
Note that the operation for correcting mobility can be performed with the use of the circuits illustrated in
Note that
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
The operations of the circuit configurations are described in Embodiments 1 to 3 under the assumption that the parasitic capacitance of the load 16 is utilized; however, another configuration can be used. In this embodiment, a configuration in which a capacitor is electrically connected in parallel to the load 16 provided in the circuit configuration in any of the above embodiments.
The capacitor 17c is electrically connected to the load 16 as illustrated in
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, a configuration different from the circuit configurations of the semiconductor devices described in Embodiments 1 to 4 is described.
The potential Vup can be higher than Vcat. The potential Vup is high, so that Vinit is prevented from being too low.
Next, the operation of the semiconductor device 10hm illustrated in
Note that in order to explain the operation of the circuit configuration illustrated in
The first operation illustrated in
The potential Vup is higher than Vinit and Vsig. Alternatively, Vup is approximately equal to Vinit. Note that the potential is preferably set so as not to cause dielectric breakdown of the load 16.
The second operation illustrated in
Then, the third operation illustrated in
With the structure described with reference to
Note that the operation for correcting mobility can be performed with the use of the circuits illustrated in
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, the structure used for part of a signal line driver circuit of a display device including the semiconductor device described in any of the above embodiments is explained.
As illustrated in
Note that the number of the gate line driver circuits 43 and the signal line driver circuits 44 may be more than one.
The signal line driver circuit 44 can be divided into a plurality of portions in its configuration. As an example, it can be roughly divided into a shift register 45, a first latch circuit 46 (LAT1), a second latch circuit 47 (LAT2), and a digital to analog converter circuit 48. The digital to analog converter circuit 48 has a function of converting a voltage into a current, and it may also have a function of providing a gamma correction. That is, the digital to analog converter circuit 48 has a circuit which outputs a current (video signal) to a pixel, namely a current source circuit to which the semiconductor device described in any of the above embodiments can be applied.
In addition, a pixel has a display element such as an EL element. The pixel has a circuit which outputs a current (video signal) to the display element, namely a current source circuit to which the semiconductor device described in any of the above embodiments can also be applied.
Next, the operation of the signal line driver circuit 44 is described briefly. The shift register 45 is formed by using a plurality of columns of flip-flop circuits (FFs) and the like, and a clock signal (S-CLK), a start pulse (SP), and an inverted clock signal (S-CLKb) are input to the shift register 45. Sampling pulses are sequentially outputted in accordance with these signals.
The sampling pulse outputted from the shift register 45 is input to the first latch circuit 46 (LAT1). The first latch circuit 46 (LAT1) is input with a video signal (VS) from the video signal line and holds a video signal in each column in response to the timing at which the sampling pulses are input. Note that a video signal has a digital value in the case where the digital to analog converter circuit 48 is disposed. Further, a video signal in this stage is often a voltage.
However, in a case where the first latch circuit 46 and the second latch circuit 47 are circuits which can store analog values, the digital to analog converter circuit 48 can be omitted in many cases. In that case, a video signal is a current in many cases. Further, in a case where data output to the pixel region 42 has a binary value, that is a digital value, the digital to analog converter circuit 48 can be omitted in many cases.
When the retainment of the video signals up to the last column is completed in the first latch circuit 46 (LAT1), a latch pulse LP is input from a latch control line in a horizontal retrace period and the video signals held in the first latch circuit 46 (LAT1) are transferred to the second latch circuit 47 (LAT2) all at once. After that, the video signals of one row, which are held in the second latch circuit 47 (LAT2), are input to the digital to analog converter circuit 48 at once. Then, a signal output from the digital to analog converter circuit 48 is input to the pixel region 42.
While the video signal held in the second latch circuit 47 (LAT2) is input to the digital to analog converter circuit 48 and then inputted to the pixel region 42, a sampling pulse is outputted from the shift register 45 again. In other words, two operations are performed at the same time. Accordingly, a line sequential driving can be enabled. These operations are repeated thereafter.
When a current source circuit in the digital to analog converter circuit 48 is a circuit which performs the set operation and the output operation, a circuit to supply a current to the current source circuit is required. In that case, a reference current source circuit 49 is disposed.
Note that a part or all of the signal line driver circuit may be provided outside a substrate having the pixel region 42, and for example, it may be constructed of an external IC chip. In that case, the IC chip and the substrate are connected by using COG (Chip On Glass), TAB (Tape Auto Bonding), a printed substrate or the like.
Note that a configuration of the signal line driver circuit or the like is not limited to
For example, in a case where the first latch circuit 46 and the second latch circuit 47 can store analog values, a video signal VS (analog current) is input to the first latch circuit 46 (LAT1) from a reference current source circuit 50 as illustrated in
Next, a specific configuration where the semiconductor device described in any of the above embodiments is applied to the signal line driver circuit 44 is described.
First,
Supply of current in accordance with Vsig set in the semiconductor device 10_1 is controlled by the switching of a switch 60_1 provided between the semiconductor device 10_1 and the load 16. In that case, for example, the plurality of semiconductor devices 10_1 are provided and the amount of current flowing to the load can be controlled by the switches 60_1.
For example, the following structure illustrated in
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, an example of the case where the circuit configuration which is one embodiment of the present invention is applied to a pixel of a display device is described.
The circuit configuration illustrated in
The pixel 100 illustrated in
Next, a connection relation of components in the pixel 100 is described.
A gate of the transistor 101 is connected to one of electrodes of the capacitor 107 and one of terminals of the switch 103. A first terminal (one of a source and a drain) of the transistor 101 is connected to one of terminals of the switch 102 and one of terminals of the switch 104. A second terminal (the other of the source and the drain) of the transistor 101 is connected to the other of the terminals of the switch 103 and one of terminals of the switch 105. Note that one of terminals is also referred to as a first terminal and the other of the terminals is also referred to as a second terminal.
The other of the terminals of the switch 102 is connected to the wiring 108.
The other of the terminals of the switch 105 is connected to the wiring 110.
One of electrodes of the light-emitting element 106 is connected to the other of the terminals of the switch 104 and the other of the electrodes of the capacitor 107. The other of the electrodes of the light-emitting element 106 is connected to the wiring 109.
Note that in this embodiment, a pixel corresponds to a display unit controlling the luminance of one color component (e.g., any one of R (red), G (green), and B (blue)). Therefore, in a color display device, the minimum display unit of a color image is composed of three pixels of an R pixel, a G pixel and a B pixel. Note that the color of the color elements is not necessarily of three varieties and may be of three or more varieties or may include a color other than RGB.
An example of the light-emitting element is an EL element. Examples of an EL element are an element including an anode, a cathode, and an EL layer interposed between the anode and the cathode, and the like. Examples of an EL layer are a layer utilizing light emission (fluorescence) from a singlet exciton, a layer utilizing light emission (phosphorescence) from a triplet exciton, a layer utilizing light emission (fluorescence) from a singlet exciton and light emission (phosphorescence) from a triplet exciton, a layer formed using an organic material, a layer formed using an inorganic material, a layer formed using an organic material and an inorganic material, a layer including a high-molecular material, a layer including a low-molecular material, a layer including a high-molecular material and a low-molecular material, and the like. Note that the present invention is not limited thereto, and various types of EL elements can be used.
Note that as illustrated in
The potential Vinit initializes the potential of each node in the pixel before Vsig which is a video signal is supplied, for example. Note that Vinit may be different depending on pixels, rows, or columns. Alternatively, Vinit may be different depending on colors of pixels.
An example of Vsig is a video signal. Therefore, the potential to be supplied to pixels depends on an image to be displayed. When the image to be displayed is a moving image, the potential to be supplied varies over time in some cases. Further, when the image to be displayed is a still image, the fixed potential is supplied in some cases.
Note that as illustrated in
The potential Vcat is set to make current flow from the side of one of electrodes (an anode) of the light-emitting element 106 to the side of the other of the electrodes (cathode) of the light-emitting element 106 in a period in which the light-emitting element 106 emits light. If the cathodes of the light-emitting elements 106 in pixels are the same, the wiring of each pixel is supplied with Vcat. The potential Vcat may be different depending on pixels, rows, or columns. Alternatively, Vcat may be different depending on colors of pixels.
Note that as illustrated in
The potential VDD is set to make current flow from the side of the one of the electrodes of the light-emitting element 106 to the side of the other of the electrodes of the light-emitting element 106 through the transistor 101. Therefore, for example, VDD is higher than Vcat. When the characteristics of the light-emitting elements 106 in pixels are the same, the same VDD can be supplied to the wiring of each pixel. The potential VDD may be different depending on pixels, rows, or columns. Alternatively, VDD may be different depending on colors of pixels.
Note that each of the switch 102, the switch 103, the switch 104, and the switch 105 which are illustrated in FIG. 28A can be a transistor. Thus, as an example,
In
A gate of the transistor 102T is connected to a wiring 131. A first terminal of the transistor 102T is connected to the first terminal of the transistor 101 and a first terminal of the transistor 104T. A second terminal of the transistor 102T is connected to the wiring 108. Therefore, the transistor 102T is in a conduction state when the potential of the wiring 131 is at an H level, and the transistor 102T is in a non-conduction state when the potential of the wiring 131 is at an L level.
Further, a gate of the transistor 103T is connected to a wiring 132. A first terminal of the transistor 103T is connected to the gate of the transistor 101 and the one of the electrodes of the capacitor 107. A second terminal of the transistor 103T is connected to a first terminal of the transistor 105T and the second terminal of the transistor 101. Therefore, the transistor 103T is in a conduction state when the potential of the wiring 132 is at an H level, and the transistor 103T is in a non-conduction state when the potential of the wiring 132 is at an L level.
Furthermore, a gate of the transistor 104T is connected to a wiring 133. A first terminal of the transistor 104T is connected to the first terminal of the transistor 101 and the first terminal of the transistor 102T. A second terminal of the transistor 104T is connected to the first electrode of the light-emitting element 106 and the other electrode of the capacitor 107. Therefore, the transistor 104T is in a conduction state when the potential of the wiring 133 is at an H level, and the transistor 104T is in a non-conduction state when the potential of the wiring 133 is at an L level.
In addition, a gate of the transistor 105T is connected to a wiring 134. The first terminal of the transistor 105T is connected to the second terminal of the transistor 101 and the second terminal of the transistor 103T. A second terminal of the transistor 105T is connected to the wiring 110. Therefore, the transistor 105T is in a conduction state when the potential of the wiring 134 is at an H level, and the transistor 105T is in a non-conduction state when the potential of the wiring 134 is at an L level.
Note that the wiring 131, the wiring 132, the wiring 133, and the wiring 134 can function as different wirings. However, one embodiment of the present invention is not limited thereto. The wirings 131 to 134 can be combined into one wiring; therefore, it is possible to form a circuit with a small number of wirings.
For example, the wiring 131 and the wiring 132 can be combined into one wiring. Therefore, the wiring 131 can be connected to the wiring 132 to be one wiring. At this time, the transistor 102T and the transistor 103T preferably have the same polarity.
For example, the wiring 133 and the wiring 134 can be combined into one wiring. Therefore, the wiring 133 can be connected to the wiring 134 to be one wiring. At this time, the transistor 104T and the transistor 105T preferably have the same polarity.
Note that the wiring 131 and the wiring 132 can be combined into one wiring and the wiring 133 and the wiring 134 can be combined into one wiring.
In many cases, the transistor 101 operates in a saturation region at the time of passing current. Therefore, the transistor 101 preferably has a longer channel length or gate length than the transistor 102T, the transistor 103T, the transistor 104T, or the transistor 105T. When the channel length or the gate length is longer, characteristics in a saturation region have a flat slope; accordingly, a kink effect can be reduced. Note that one embodiment of the present invention is not limited to these examples.
In many cases, the transistor 101 operates in a saturation region at the time of passing current. Therefore, the transistor 101 preferably has a larger channel width or gate width than the transistor 102T, the transistor 103T, the transistor 104T, or the transistor 105T. When the channel width or the gate width is larger, a large amount of current can flow even in a saturation region. Note that one embodiment of the present invention is not limited to these examples.
Here, a display device including the pixel 100 is described with reference to a block diagram of
The display device includes a signal line driver circuit 201, a scan line driver circuit 202A, a scan line driver circuit 202B, a scan line driver circuit 202C, a scan line driver circuit 202D, and a pixel region 203. The pixel region 203 is provided with a plurality of signal lines S1 to Sn (n is a natural number) extended from the signal line driver circuit 201 in a column direction; a plurality of scan lines Ga1 to Gam (m is a natural number) extended from the scan line driver circuit 202A in a row direction; a plurality of scan lines Gb1 to Gbm extended from the scan line driver circuit 202B in a row direction; a plurality of scan lines Gc1 to Gcm extended from the scan line driver circuit 202C in a row direction; a plurality of scan lines Gd1 to Gdm extended from the scan line driver circuit 202D in a row direction; a plurality of pixels 100 provided in matrix, connected to respective signal lines S1 to Sn, and connected to respective scan lines Ga1 to Gam, Gb1 to Gbm, Gc1 to Gcm, and Gd1 to Gdm; and power supply lines P1 to Pn which are parallel to the signal lines S1 to Sn. The pixel 100 is connected to the signal line Sj (one of the signal lines S1 to Sn), the scan line Gai (one of the scan lines Ga1 to Gam), the scan line Gbi (one of the scan lines Gb1 to Gbm), the scan line Gci (one of the scan lines Gc1 to Gcm), the scan line Gdi (one of the scan lines Gd1 to Gdm), and the power supply line Pj (one of the power supply lines P1 to Pn). Note that i and j are natural numbers.
The scan line Gai corresponds to the wiring 131 in
A scan line is selected with the use of a signal output from the scan line driver circuits 202A to 202D. The potential of each node of the pixels 100 connected to the selected scan line is initialized (first operation). Then, a video signal is written to the initialized pixel 100 to obtain the threshold voltage of a transistor (second operation). After the threshold voltage of the transistor is obtained by writing of the video signal, the operation moves to light emission. The pixel emits light in accordance with the video signal written to the pixel (third operation). In this manner, the initialization of the pixel 100, obtaining of the threshold voltage, and light-emitting operation are sequentially performed.
Next, the operation of the pixel 100 illustrated in
Note that in order to explain the operation of the circuit configuration illustrated in
A nodeA, a nodeB, a nodeC, a nodeD, a nodeE, a nodeF, and a nodeG correspond to nodes and wirings illustrated in
First, the first operation is described with reference to
The first operation initializes the potential of each node in the pixel 100. Specifically, the nodeA is set at Vinit, the nodeD is set at Vcat, and the nodeG is set at VDD. Then, the switch 102, the switch 103, the switch 104, and the switch 105 are turned on. Thus, the nodeB is set at Vinit, the nodeC is set at Vinit, the nodeE is set at VDD, and the nodeF is set at VDD. Further, Vgs becomes (VDD−Vinit), and Vc becomes (VDD−Vinit).
As described above, in the first operation, Vinit at the nodeB and the nodeC is equal to or lower than Vcat at the nodeD, for example. With this structure, current is prevented from flowing to the light-emitting element 106 in the first operation. Accordingly, problems caused by current flowing to the light-emitting element 106 can be reduced. Further, when Vinit is lower than Vcat, the light-emitting element 106 can be reverse biased. In that case, deterioration of the light-emitting element 106 can be reduced and the light-emitting element 106 can be repaired.
In the first operation, VDD at the nodeE and the nodeF is higher than Vcat at the nodeD. With this structure, Vgs can be higher than the threshold voltage of the transistor 101 in the first operation. Alternatively, electric charge can be charged in the capacitor 107.
Next, the second operation is described with reference to
The second operation is the operation for obtaining the threshold voltage of the transistor 101 as Vgs by discharging the potential of the gate of the transistor 101 (or the electric charge charged in the capacitor 107). Specifically, the nodeA is set at Vsig, the nodeD is set at Vcat, and the nodeG is set at VDD. Then, the switch 102 and the switch 103 are turned on, and the switch 104 and the switch 105 are turned off. Accordingly, the potential of the nodeB becomes Vsig, the potential of the nodeC becomes (Vinit−Vx), the potential of the nodeE becomes (Vsig+Vth), and the potential of the nodeF becomes (Vsig+Vth). Further, Vgs becomes Vth and Vc becomes (Vsig+Vth−Vinit+Vx).
As described above, Vsig at the nodeB in the second operation is the potential used for controlling the amount of current flowing between the wiring 110 and the wiring 109 with the use of the transistor 101 in the third operation. By the second operation, the potential of the nodeE corresponding to the potential of the gate of the transistor 101 can be (Vsig+Vth) which includes the threshold voltage of the transistor 101.
In the second operation, Vx of the potential of the nodeC (Vinit−Vx) changes when the nodeC is set in an electrically floating state. In this case, the amount of changes in Vx depends on a ratio of capacitance of the light-emitting element 106 to the capacitance of the capacitor 107. Note that Vx is preferably set to a low potential in advance. Specifically, the capacitance of the light-emitting element 106 is set to be sufficiently larger than the capacitance of the capacitor 107, whereby Vx can be low. It is preferable that the capacitance of the light-emitting element 106 be two times or more, more preferably four times or more the capacitance of the capacitor 107.
Further, VDD at the nodeD and the nodeE in the first operation is discharged by the second operation. By the discharging, Vgs is decreased to the threshold voltage Vth of the transistor 101 and is set in a steady state. Therefore, the discharging makes the nodeD and the nodeE are set in a steady state at (Vsig+Vth). In addition, at the time of terminating the second operation, (Vsig+Vth−Vinit+Vx) is held as Vc.
Note that in some cases, it takes a very long time until Vgs becomes equal to the threshold voltage Vth of the transistor 101. Accordingly, in many case, the semiconductor device is driven while Vgs is not completely decreased to the threshold voltage Vth. That is, in many cases, the second operation is terminated while Vgs is slightly higher than the threshold voltage Vth. In other words, at the time of terminating the second operation, Vgs is based on the threshold voltage.
Note that in the second operation, the switch 104 and the switch 105 are turned off and the potential of the nodeB is set to Vsig. These operations can be performed at the same time or at different timings.
It is preferable that, for example, the potential of the nodeB be changed from Vinit to Vsig at the same time as or after the switch 104 is turned off. This is because the potential of the nodeC can be easily held at an appropriate potential.
Alternatively, it is preferable that, for example, the potential of the nodeB be changed from Vinit to Vsig before or at the same time as the switch 105 is turned off. This is because the gate potential of the transistor can be quickly lowered.
Next, the third operation is described with reference to
The third operation is the operation for outputting current to the light-emitting element 106 and emitting light with the use of the transistor 101 as part of a current source. Specifically, the nodeA is set at Vsig, for example, though it can be any potential, the nodeD is set at Vcat, and the nodeG is set at VDD. Then, the switch 104 and the switch 105 are turned on, and the switch 102 and the switch 103 are turned off. Accordingly, the nodeB and the nodeC become Vel, the nodeE becomes (Vsig+Vth−Vinit+Vx+Vel), and the nodeF becomes VDD. In addition, Vgs becomes (Vsig+Vth−Vinit+Vx) and Vc becomes (Vsig+Vth−Vinit+Vx).
Note that in the third operation, the potentials of the nodeB, the nodeC, and the nodeF are increased while the nodeE is kept in an electrically floating state. Accordingly, the potential of the nodeE is increased by capacitive coupling while (Vsig+Vth−Vinit+Vx) is held as Vc, thereby becoming (Vsig+Vth−Vinit+Vx+Vel). That is, an increase in the potential of the nodeC leads to an increase in the potential of the nodeE by bootstrap operation.
The semiconductor device can operate even when the potential of the nodeC is increased; therefore, adverse effect of deterioration in voltage current characteristics of the light-emitting element 106 can be reduced even when the deterioration is caused.
The potential Vel which is the potentials of the nodeB and the nodeC is set when the potential of the nodeF is increased to VDD and current flows to the light-emitting element 106 through the transistor 101 which allows the semiconductor device to operate as a current source by the third operation. Specifically, the potential ranges from VDD to Vcat.
In the third operation, Vgs of the transistor 101 becomes (Vsig+Vth−Vinit+Vx), which includes the threshold voltage of the transistor 101. The amount of current of the transistor 101 depends on (Vgs−Vth). Accordingly, through the above operations, adverse effect of variations in the threshold voltage of the transistor on the amount of current supplied to the light-emitting element can be reduced. Alternatively, even when the threshold voltage is changed by deterioration of the transistor, adverse effect of the change can be reduced. Therefore, display unevenness can be reduced and display can be performed with high quality.
Note that in the third operation, the switch 102 and the switch 103 are turned off and the switch 104 and the switch 105 are turned on. These operations can be performed at the same time or at different timings.
For example, it is preferable that the switch 104 and the switch 105 be turned on after the switch 102 and the switch 103 are turned off. This is because Vc can be easily held at an appropriate potential.
Alternatively, for example, it is preferable that the switch 102 be turned off after the switch 103 is turned off. This is because Vc can be easily held at an appropriate potential.
Note that
For example, specifically, the switch 102, the switch 103, the switch 104, and the switch 105 can be provided at any place and the number of switches is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
Note that the operation for correcting the threshold voltage of the transistor is described with reference to
Note that a first operation illustrated in
Next, a third operation is described with reference to
In the third operation, the transistor 101 is turned on with the use of the potential held in the gate of the transistor 101 (electric charge stored in the capacitor 107), and the mobility of the transistor 101 is corrected with the use of the amount of current flowing therethrough. Specifically, the nodeA is set at Vsig though it can be any potential, the nodeD is set at Vcat, and the nodeG is set at VDD. Then, the switch 103 and the switch 104 are turned on, and the switch 102 and the switch 105 are turned off. Then, the amount of change in potentials of the nodeB and the nodeC is −ΔVel, the nodeE and the nodeF become (Vsig+Vth−ΔVel). In addition, Vgs becomes (Vth+ΔVel) and Vc becomes (Vsig+Vth−Vinit+Vx−ΔVel).
Note that in the third operation, the potentials of the nodeB and the nodeC are changed by turning on the switch 104. The amount of changes in the potentials corresponds to −ΔVel. When the amount of change in the potentials of the nodeB and the nodeC becomes −ΔVel, Vgs becomes (Vth+ΔVel) and higher than the threshold voltage Vth; as a result, current flows through the transistor 101. When current flows through the transistor 101, each of the potentials of the nodeE and the nodeF is decreased to (Vsig+Vth−ΔVel) and Vc becomes (Vsig+Vth−Vinit+Vx−ΔVel).
The amount of current flowing to the transistor 101 changes depending on the mobility of the transistor 101. Accordingly, the potential of the nodeE corresponding to the gate of the transistor 101 can be set so as to include the amount of change in potential corresponding to the mobility of the transistor 101.
In the third operation, the potential of the gate of the transistor 101 becomes (Vsig+Vth−ΔVel) which is set in consideration of the mobility of the transistor 101. Accordingly, through the above operations, adverse effect of variations in the mobility of the transistor on the amount of current supplied to the light-emitting element can be reduced. Alternatively, even when mobility is changed by deterioration of the transistor, adverse effect of the change can be reduced.
Next, a fourth operation is described with reference to
By the fourth operation, the nodeB and the nodeC are set at Vel, the nodeE is set at (Vsig+Vth−Vinit+Vx−ΔVel+Vel), and the nodeF is set at VDD. The potential Vgs becomes (Vsig+Vth−Vinit+Vx−ΔVel) and Vc becomes (Vsig+Vth−Vinit+Vx).
In the fourth operation, Vgs of the transistor 101 becomes (Vsig+Vth−Vinit+Vx+ΔVel), which can be set in consideration of the threshold voltage and the mobility of the transistor 101. Accordingly, through the above operations, adverse effect of variations in the threshold voltage and the mobility of the transistor on the amount of current supplied to the light-emitting element can be reduced.
The location of the switch or the number of switches can be changed and appropriate voltage can be supplied so as to achieve the similar operation to the operation described in
For example, specifically, the switch 102, the switch 103, the switch 104, and the switch 105 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
Note that
For example, as in a pixel 100A illustrated in
As another example, as in a pixel 100B illustrated in
As another example, as in a pixel 100C illustrated in
The channel width and/or the channel length of the transistor 101 can be changed by application of the structures illustrated in
Note that
Therefore, a circuit can be formed with a small number of transistors in the case where a transistor is not added.
Note that variations in the threshold voltage or the like of a transistor is corrected in this embodiment, but one embodiment of the present invention is not limited thereto. For example, current can be supplied to the light-emitting element 106 and the semiconductor device can be driven without performing the operation for correcting variations in threshold voltage.
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, an example of a configuration different from the circuit configuration of the pixel described in Embodiment 7 is described.
Here, a display device including the pixel 100h is described with reference to a block diagram of
The display device includes a signal line driver circuit 201, a scan line driver circuit 202A, a scan line driver circuit 202B, a scan line driver circuit 202C, a scan line driver circuit 202D, a pixel region 203, and a power supply line control circuit 204. The pixel region 203 is provided with a plurality of signal lines S1 to Sn extended from the signal line driver circuit 201 in a column direction; a plurality of scan lines Ga1 to Gam extended from the scan line driver circuit 202A in a row direction; a plurality of scan lines Gb1 to Gbm extended from the scan line driver circuit 202B in a row direction; a plurality of scan lines Gc1 to Gcm extended from the scan line driver circuit 202C in a row direction; a plurality of scan lines Gd1 to Gdm extended from the scan line driver circuit 202D in a row direction; a plurality of pixels 100 provided in matrix, connected to respective signal lines S1 to Sn, and connected to respective scan lines Ga1 to Gam, Gb1 to Gbm, Gc1 to Gcm, and Gd1 to Gdm; and power supply lines P1 to Pm which are parallel to the scan lines Ga1 to Gam, Gb1 to Gbm, Gc1 to Gcm, and Gd1 to Gdm. The pixel 100h is connected to the signal line Sj (one of the signal lines S1 to Sn), the scan line Gai (one of the scan lines Ga1 to Gam), the scan line Gbi (one of the scan lines Gb1 to Gbm), the scan line Gci (one of the scan lines Gc1 to Gcm), the scan line Gdi (one of the scan lines Gd1 to Gdm), and the power supply line Pj (one of the power supply lines P1 to Pn).
The scan line Gai corresponds to the wiring 131 in
A scan line is selected with the use of a signal output from the scan line driver circuits 202A to 202D. An operation in which a potential for initialization is applied to some extent to each node of the pixels 100 connected to the selected scan line before initialization of the potential of each node (initialization before initialization) is performed (first operation). The potential of each node of the pixels 100 connected to the selected scan line is initialized (second operation). Then, a video signal is written to the initialized pixel 100 to obtain the threshold voltage of a transistor (third operation). After the threshold voltage of the transistor is obtained by writing of the video signal, the operation moves to light emission. The pixel emits light in accordance with the video signal written to the pixel (fourth operation). In this manner, the initialization before the initialization, the initialization of the pixel 100, obtaining of the threshold voltage, and a light-emitting operation are sequentially performed.
Next, the operation of the pixel 100h illustrated in
Note that in order to explain the operation of the circuit configuration illustrated in
First, the first operation is described with reference to
In the first operation, a potential for initialization is applied to some extent at each node before initialization of the potential of each node (initialization before initialization). Specifically, the nodeG is set at Vinit and the nodeD is set at Vcat. The nodeA can be set at any potential. In addition, the switch 104 and the switch 105 are turned on, and the switch 102 and the switch 103 are turned off. The nodeB and the nodeC are then set at Vinit or the potential ΔVinit which is close to Vinit. The nodeE is set at Vy and the nodeF is set at Vinit. Note that Vgs and Vc are omitted because the first operation uses Vy which is a signal of an operation before the first operation.
The potential Vy is input before the first operation. The case where Vy enables the transistor 101 to operate as part of a current source is explained. The potential Vy is set so that current flows between the first terminal and the second terminal of the transistor 101 in the first operation. Usually, Vinit is very low and accordingly the transistor 101 is turned on because of Vy in many cases.
Therefore, in the first operation, the nodeF is set at Vinit and current flows between the first terminal and the second terminal of the transistor 101; as a result, the nodeB and the nodeC are set at Vinit or the potential ΔVinit which is close to Vinit.
That is, the first operation decreases the potentials of the nodeB and the nodeC. By the decrease in the potentials of the nodeB and the nodeC in the first operation, the following second operation can initialize the potential of each node at high speed. In particular, when the light-emitting element 106 has large capacitance, the following operation can be performed smoothly by the decrease in the potentials of the nodeB and the nodeC in advance. Note that even if the potentials of the nodeB and the nodeC cannot be sufficiently decreased, it is not a problem unless subsequent operations are adversely affected.
The second operation described with reference to
In the second operation, the switch 102 and the switch 103 are turned on and the potential of the nodeG is set to VDD, and these operations can be performed at the same time or at different timings.
It is preferable that, for example, the potential of the nodeG be changed from Vinit to VDD before or at the same time as the switch 103 is turned on. This is because the potential of the nodeE can be increased easily in that case.
Then, the third operation illustrated in
The location of the switch or the number of switches can be changed and appropriate voltage can be supplied so as to achieve the similar operation to the operation described in
For example, specifically, the switch 102, the switch 103, the switch 104, and the switch 105 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
Note that the operation for correcting the threshold voltage of the transistor is described with reference to
The operation for correcting the mobility of the transistor 101 is described with reference to
The operation for correcting the mobility of the transistor 101 is the same as the third operation described with reference to
In the operation for correcting the mobility of the transistor 101, the potential of the gate of the transistor 101 becomes (Vsig+Vth−ΔVel) which is set in consideration of the mobility of the transistor 101. Accordingly, through the above operation, adverse effect of variations in the mobility of the transistor on the amount of current supplied to the light-emitting element can be reduced.
The location of the switch or the number of switches can be changed and appropriate voltage can be supplied so as to achieve the similar operation to the operation described in
For example, specifically, the switch 102, the switch 103, the switch 104, and the switch 105 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the operation for correcting the mobility of the transistor described with reference to
The potential of the wiring 110h is switched between Vinit and VDD in the circuit configuration illustrated in
The case of
The circuit 113A has a function of supplying Vinit and examples of the circuit 113A are a power supply circuit and a voltage follower circuit. The circuit 113B has a function of supplying VDD and an example of the circuit 113B is a power supply circuit. In addition, the switching of the switch 105A is controlled with a wiring 135A and the switching of the switch 105B is controlled with a wiring 135B. As an example, the wiring 135A and the wiring 135B are connected to a scan line driver circuit 202E and a scan line driver circuit 202F, respectively. The scan line driver circuit 202E and the scan line driver circuit 202F each have at least a function of supplying an H-level signal or an L-level signal.
In the case of the circuit configuration illustrated in
The wirings explained with reference to
As described above, in the circuit configuration described in this embodiment, initialization before initialization can be performed by switching of the potential of the wiring 110h between Vinit and VDD. Accordingly, the potential of each node can be initialized at high speed. In the fourth operation, Vgs of the transistor 101 becomes (Vsig+Vth−Vinit+Vx), which includes the threshold voltage of the transistor 101. Accordingly, with this structure, adverse effect of variations in the threshold voltage of the transistor on the amount of current supplied to the load can be reduced.
Note that
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, an example of a configuration different from the circuit configurations of the pixel of the display devices described in Embodiments 7 and 8 is described.
A transistor can be applied to each of the switch 102, the switch 102p, the switch 103, the switch 104, and the switch 105 in the pixel 100p illustrated in
In
Note that in order to explain the operation of the pixel 100p illustrated in
A nodeA, a nodeB, a nodeC, a nodeD, a nodeE, a nodeF, a nodeG, and a nodeH correspond to nodes and wirings illustrated in
Here, a display device including the pixel 100p is described with reference to a block diagram of
The display device includes a signal line driver circuit 201, a scan line driver circuit 202A, a scan line driver circuit 202B, a scan line driver circuit 202C, a scan line driver circuit 202D, a scan line driver circuit 202E, a pixel region 203, and an initialization signal line driver circuit 205. The pixel region 203 is provided with a plurality of signal lines S1 to Sn extended from the signal line driver circuit 201 in a column direction; a plurality of signal lines Sil to Sin extended from the initialization signal line driver circuit 205 in a column direction; a plurality of scan lines Ga1 to Gam extended from the scan line driver circuit 202A in a row direction; a plurality of scan lines Gb1 to Gbm extended from the scan line driver circuit 202B in a row direction; a plurality of scan lines Gc1 to Gcm extended from the scan line driver circuit 202C in a row direction; a plurality of scan lines Gd1 to Gdm extended from the scan line driver circuit 202D in a row direction; a plurality of scan lines Gel to Gem extended from the scan line driver circuit 202E in a row direction; a plurality of pixels 100p provided in matrix, connected to respective signal lines S1 to Sn, and connected to respective scan lines Ga1 to Gam, Gb1 to Gbm, Gc1 to Gcm, Gd1 to Gdm, and Gel to Gem; and power supply lines P1 to Pn which are parallel to the signal lines S1 to Sn. The pixel 100 is connected to the signal line Sj (one of the signal lines S1 to Sn), the initialization signal line Sij (one of the initialization signal lines S1 to Sn), the scan line Gai (one of the scan lines Ga1 to Gam), the scan line Gbi (one of the scan lines Gb1 to Gbm), the scan line Gci (one of the scan lines Gc1 to Gcm), the scan line Gdi (one of the scan lines Gd1 to Gdm), the scan line Gei (one of the scan lines Gel to Gem), and the power supply line Pj (one of the power supply lines P1 to Pn).
The scan line Gai corresponds to the wiring 131 in
A scan line is selected with the use of a signal output from the scan line driver circuits 202A to 202E. The potential of each node of the pixels 100 connected to the selected scan line is initialized (first operation). Then, a video signal is written to the initialized pixel 100 to obtain the threshold voltage of a transistor (second operation). After the threshold voltage of the transistor is obtained by writing of the video signal, the operation moves to light emission. The pixel emits light in accordance with the video signal written to the pixel (third operation). In this manner, the initialization of the pixel 100, obtaining of the threshold voltage, and a light-emitting operation are sequentially performed.
Next, the operation of the pixel 100h illustrated in
First, the first operation is described with reference to
The first operation initializes the potential of each node. Specifically, the nodeA is set at any potential, for example, Vsig, the nodeD is set at Vcat, the nodeG is set at VDD, and the nodeH is set at Vinit. Then, the switch 102p, the switch 103, the switch 104, and the switch 105 are turned on, and the switch 102 is turned off. Thus, the nodeB is set at Vinit, the nodeC is set at Vinit, the nodeE is set at VDD, and the nodeF is set at VDD. Further, Vgs becomes (VDD−Vinit), and Vc becomes (VDD−Vinit).
The first operation described with reference to
Next, the second operation is described with reference to
The second operation is the operation for obtaining the threshold voltage of the transistor 101 with the use of Vgs by discharging the potential of the gate of the transistor 101 (or the electric charge of the capacitor 107). Specifically, the nodeA is set at Vsig, the nodeD is set at Vcat, the nodeG is set at VDD, and the nodeH is set at Vinit though it can be any potential. Then, the switch 102 and the switch 103 are turned on, and the switch 104, the switch 102p, and the switch 105 are turned off. Thus, the potential of the nodeB becomes Vsig, the potential of the nodeC becomes (Vinit−Vx), the potential of the nodeE becomes (Vsig+Vth), and the potential of the nodeF becomes (Vsig+Vth). Further, Vgs becomes Vth and Vc becomes (Vsig+Vth−Vinit+Vx).
The second operation described with reference to
Note that in the second operation, the switch 104, the switch 105, and the switch 102p are turned off and the switch 102 is turned on, and these operations can be performed at the same time or at different timings.
For example, it is preferable that the switch 102 be turned on at the same time as or after the switch 102p is turned off. This is because a short circuit between the nodeA and the nodeH can be prevented easily.
Next, the third operation is described with reference to
The third operation is the operation for outputting current to the light-emitting element 106 with the use of the transistor 101 as part of a current source. Specifically, the nodeA is set at Vsig though it can be any potential, the nodeD is set at Vcat, the nodeG is set at VDD, and the nodeH can be set at Vinit though it can be any potential. Then, the switch 104 and the switch 105 are turned on, and the switch 102, the switch 102p, and the switch 103 are turned off. Then, the nodeB and the nodeC become Vel, the nodeE becomes (Vsig+Vth−Vinit+Vx+Vel), and the nodeF becomes VDD. In addition, Vgs becomes (Vsig+Vth−Vinit+Vx) and Vc becomes (Vsig+Vth−Vinit+Vx).
The third operation described with reference to
Note that
For example, specifically, the switch 102, the switch 102p, the switch 103, the switch 104, and the switch 105 can be provided any place and the numbers thereof is not limited as long as the switches can control a conduction state and a non-conduction state between nodes. In the case of the first operation described with reference to
As described above, in the circuit configuration described in this embodiment, the wiring 108p is provided and the initialization can be performed with the use of Vinit supplied from the wiring 108p through the switch 102p. Accordingly, time for initializing the potential of each node can be long. Alternatively, the initialization with the use of Vinit is not necessarily performed by using the wiring 108, which can save time allowing time for the second operation to be longer. In the third operation, Vgs of the transistor 101 becomes (Vsig+Vth−Vinit+Vx), which includes the threshold voltage of the transistor 101. Accordingly, with this structure, adverse effect of variations in the threshold voltage of the transistor on the amount of current supplied to the load can be reduced.
In the case of the circuit configuration illustrated in
The wirings explained with reference to
Note that the operation for correcting mobility can be performed with the use of the circuits illustrated in
Note that
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
The operations of the circuit configurations are described in Embodiments 7 to 9 under the assumption that the parasitic capacitance of the light-emitting element 106 is utilized; however, another configuration can be used. In this embodiment, a configuration in which a capacitor is electrically connected in parallel to the light-emitting element 106 provided in the circuit configuration in any of the above embodiments.
The capacitor 107C is electrically connected to the light-emitting element 106 as illustrated in
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, a configuration different from the circuit configurations of the pixels described in Embodiments 7 to 10 is described.
The potential Vup can be higher than Vcat. The potential Vup is high, so that Vinit is prevented from being too low.
Here, a display device including the pixel 100hm is described with reference to a block diagram of
The display device includes a signal line driver circuit 201, a scan line driver circuit 202A, a scan line driver circuit 202B, a scan line driver circuit 202C, a scan line driver circuit 202D, a pixel region 203, and a cathode line driver circuit 206. The pixel region 203 is provided with a plurality of signal lines S1 to Sn extended from the signal line driver circuit 201 in a column direction; a plurality of scan lines Ga1 to Gam extended from the scan line driver circuit 202A in a row direction; a plurality of scan lines Gb1 to Gbm extended from the scan line driver circuit 202B in a row direction; a plurality of scan lines Gc1 to Gcm extended from the scan line driver circuit 202C in a row direction; a plurality of scan lines Gd1 to Gdm extended from the scan line driver circuit 202D in a row direction; a plurality of cathode lines C1 to Cm extended from the cathode line driver circuit 206 in a row direction; a plurality of pixels 100hm provided in matrix, connected to respective signal lines S1 to Sn, and connected to respective scan lines Ga1 to Gam, Gb1 to Gbm, Gc1 to Gcm, and Gd1 to Gdm; and power supply lines P1 to Pn which are parallel to the signal lines S1 to Sn. The pixel 100 is connected to the signal line Sj (one of the signal lines S1 to Sn), the scan line Gai (one of the scan lines Ga1 to Gam), the scan line Gbi (one of the scan lines Gb1 to Gbm), the scan line Gci (one of the scan lines Gc1 to Gcm), the scan line Gdi (one of the scan lines Gd1 to Gdm), the cathode line Ci (one of cathode lines C1 to Cm) and the power supply line Pj (one of the power supply lines P1 to Pn).
The scan line Gai corresponds to the wiring 131 in
A scan line is selected with the use of a signal output from the scan line driver circuits 202A to 202D. The potential of each node of the pixels 100hm connected to the selected scan line is initialized (first operation). Then, a video signal is written to the initialized pixel 100hm to obtain the threshold voltage of a transistor (second operation). After the threshold voltage of the transistor is obtained by writing of the video signal, the operation moves to light emission. The pixel emits light in accordance with the video signal written to the pixel (third operation). In this manner, the initialization of the pixel 100hm, obtaining of the threshold voltage, and light-emitting operation are sequentially performed.
Next, the operation of the pixel 100hm illustrated in
Note that in order to explain the operation of the circuit configuration illustrated in
The first operation illustrated in
The potential Vup is higher than Vinit and Vsig. Alternatively, Vup is approximately equal to Vinit. Note that the potential is preferably set so as not to cause dielectric breakdown of the light-emitting element 106.
The second operation illustrated in
Then, the third operation illustrated in
With the structure described with reference to
Note that the operation for correcting mobility can be performed with the use of the circuits illustrated in
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, structures of a top view and a cross-sectional view corresponding to the circuit diagram of the pixel of the display device illustrated in
A top view of
As a structure corresponding to that in
The structure illustrated in
The conductive layer 851 has a region that functions as a gate electrode or a scan line. Note that the conductive layer 851 is formed over a substrate over which elements such as a transistor are provided. A base insulating layer may be sandwiched between the substrate and the conductive layer 851.
Although there is no particular limitation on a substrate used as the substrate, a glass substrate is preferably used. The base insulating layer has a function of preventing diffusion of an impurity element from the substrate, and can be formed to have a single-layer structure or a layered structure including any of a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, and a silicon oxynitride layer.
As the substrate, a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, a flexible substrate, an attachment film, paper including a fibrous material, a base material film, or the like can be used, for example. As an example of a glass substrate, a barium borosilicate glass substrate, an aluminoborosilicate glass substrate, soda lime glass substrate, and the like can be given. For a flexible substrate, a flexible synthetic resin such as plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES), or acrylic can be used, for example. For an attachment film, polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, or the like can be used, for example. For a base material film, polyester, polyamide, polyimide, an inorganic vapor deposition film, paper, or the like can be used, for example. Specifically, when a transistor is formed using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to form a transistor with few variations in characteristics, size, shape, or the like and with high current supply capability and a small size. By forming a circuit with the use of such a transistor, power consumption of the circuit can be reduced or the circuit can be highly integrated.
Note that the transistor may be formed using one substrate, and then, the transistor may be transferred to another substrate. In addition to the above substrates over which the transistor can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate, cupra, rayon, or regenerated polyester), or the like), a leather substrate, a rubber substrate, or the like can be used as a substrate to which the transistor is transferred. By using such a substrate, a transistor with excellent properties or a transistor with low power consumption can be formed, a device with high durability or high heat resistance can be formed, or reduction in weight or thickness can be achieved.
The conductive layer 851 can be formed to have a single-layer structure or a stacked-layer structure using a metal material such as molybdenum (Mo), titanium (Ti), chromium (Cr), tantalum (Ta), tungsten (W), aluminum (Al), copper (Cu), neodymium (Nd), or scandium (Sc), or an alloy material including any of these as a main component.
The semiconductor layer 852 has a region functioning as a semiconductor layer of the transistor.
The semiconductor layer 852 may include amorphous silicon. The semiconductor layer 852 may include polycrystalline silicon. Alternatively, The semiconductor layer 852 may include an organic semiconductor, an oxide semiconductor, or the like.
The conductive layer 853 has regions functioning as wirings and source and drain of the transistor.
The conductive layer 853 can be formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy including any of these elements as a main component, an alloy film including a combination of any of these elements, or the like. The conductive film may have a structure in which a high-melting-point metal layer of Ti, Mo, W, or the like is stacked over and/or below a metal layer of Al, Cu, or the like. When an Al material to which an element (e.g., Si, Nd, or Sc) which prevents generation of hillocks and whiskers in an Al film is added is used, heat resistance can be increased.
Alternatively, the conductive layer 853 may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide-tin oxide (In2O3—SaO2, abbreviated to ITO), indium oxide-zinc oxide (In2O3—ZnO), or any of these metal oxide materials containing silicon oxide can be used.
The conductive layer 854 has a region functioning as a wiring. Note that the conductive layer 854 is provided to improve the planarity of an insulating layer formed later to be in contact with a transparent conductive layer and is not necessarily provided.
The conductive layer 855 has a region functioning as one of the electrodes of the light-emitting element. The conductive layer 855 has a function of reflecting light in the case where light emitted from the light-emitting element is obtained from the counter substrate side. On the other hand, the conductive layer 855 has a function of transmitting light in the case where light emitted from the light-emitting element is obtained from the element substrate side.
The contact holes 856 each have a function of connecting the conductive layer 851 and the conductive layer 853. An insulating layer functioning as a gate insulating layer is sandwiched between the conductive layer 851 and the conductive layer 853. The insulating layer functioning as the gate insulating layer can be formed to have a single-layer structure or a layered structure of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer by plasma-enhanced CVD, sputtering, or the like.
The contact hole 857 has a function of connecting the conductive layer 853 and the conductive layer 854. An insulating layer functioning as a passivation layer is sandwiched between the conductive layer 853 and the conductive layer 854. For the passivation layer, an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film can be used.
The contact hole 858 has a function of connecting the conductive layer 854 and the conductive layer 855. An insulating layer providing the planarity of a surface is sandwiched between the conductive layer 854 and the conductive layer 855. For the insulating layer providing the planarity of the surface, an organic material such as polyimide, acrylic resin, or benzocyclobutene-based resin can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (low-k material) or the like.
Next, structures of a cross section (taken along the chain double-dashed line A-A′ in
The transistor functioning as the switch 105 in
The transistor functioning as the switch 105 illustrated in
The capacitor 107 illustrated in
Note that a top view of the pixel which can be applied to the display device illustrated in
As an example, a top view of the pixel described with reference to
The structure of a top view can also be a top view illustrated in
The structure of a top view can also be a top view illustrated in
The structure of a top view can also be a top view illustrated in
The structure of a top view can also be a top view illustrated in
Note that when the pixels described with reference to
Note that when the pixels each described with reference to
The above top view illustrates an inverted staggered transistor as each transistor, but the transistors may be top-gate transistors.
The contact holes 859 each have a function of connecting the semiconductor layer 852 and the conductive layer 853.
In the case where the transistor forming the pixel is a top-gate transistor as illustrated in
Next, structures of a cross section (taken along the chain double-dashed line A-A′ in
The transistor functioning as the switch 105 in
The transistor functioning as the switch 105 illustrated in
The capacitor 107 illustrated in
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In the above embodiment, a transistor forming the pixel of the display device is an re-channel transistor. On the other hand, in this embodiment, a circuit configuration in which a p-channel transistor is used for the pixel of the display device is described.
The transistor 101 of the pixel 100 in
As shown by comparison between
In
As described above, the transistor which allows the semiconductor device to function as a current source can be a p-channel transistor.
Note that each switch forming the pixel 100 in
Note that in
Note that the switches of the pixel have the same polarity in each of
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In the above embodiments, transistors forming the pixels of the display devices are re-channel transistors in many cases. In particular, the case where a transistor which includes a channel formation region in an oxide semiconductor layer is used in the circuit configuration of the pixel of the display device is described in this embodiment.
In
In the structure in
Each switch forming the pixel 600 can be a transistor which includes a channel formation region in an oxide semiconductor layer. Specifically, as illustrated in
Note that in this specification, the off-state current is current that flows between a source and a drain when a transistor is off. In the case of an n-channel transistor (whose threshold voltage is, for example, about 0 to 2 V), off-state current refers to current flowing between the source and the drain when negative voltage is applied between the gate and the source.
Next, a material of an oxide semiconductor layer in which a channel formation region is provided is described below. As described above, a structure in this embodiment may include a layer formed using an oxide semiconductor (an oxide semiconductor layer), for example.
Examples of an oxide semiconductor include a four-component metal oxide such as an In—Sn—Ga—Zn—O-based oxide semiconductor; three-component metal oxides such as an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, a Sn—Al—Zn—O-based oxide semiconductor, and a Hf—In—Zn—O-based oxide semiconductor; two-component metal oxides such as an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, an In—Mg—O-based oxide semiconductor, and an In—Ga—O-based oxide semiconductor; and the like. In addition, any of the above oxide semiconductors may contain an element other than In, Ga, Sn, and Zn, for example, SiO2.
For example, an In—Sn—Zn—O-based oxide semiconductor means an oxide semiconductor containing indium (In), tin (Sn), and zinc (Zn), and there is no limitation on the composition ratio. For example, an In—Ga—Zn—O-based oxide semiconductor means an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), and there is no limitation on the composition ratio. An In—Ga—Zn—O-based oxide semiconductor can be referred to as IGZO.
The oxide semiconductor layer can be formed using an oxide semiconductor film. In the case where an In—Sn—Zn—O-based oxide semiconductor film is formed by sputtering, a target which has a composition ratio of In:Sn:Zn=1:2:2, 2:1:3, 1:1:1, 20:45:35, or the like in an atomic ratio is used.
In the case where an In—Zn—O-based oxide semiconductor film is formed by sputtering, a target has a composition ratio of In:Zn=50:1 to 1:2 in an atomic ratio (In2O3:ZnO=25:1 to 1:4 in a molar ratio), preferably In:Zn=20:1 to 1:1 in an atomic ratio (In2O3:ZnO=10:1 to 1:2 in a molar ratio), more preferably In:Zn=1.5:1 to 15:1 in an atomic ratio (In2O3:ZnO=3:4 to 15:2 in a molar ratio). For example, in a target which has an atomic ratio of In:Zn:O=X:Y:Z, an inequality of Z>1.5X+Y is satisfied.
In the case where an In—Ga—Zn—O-based oxide semiconductor film is formed by sputtering, a target can have a composition ratio of In:Ga:Zn=1:1:0.5, 1:1:1, or 1:1:2 in an atomic ratio.
When the purity of the target is set to 99.99% or higher, alkali metal, hydrogen atoms, hydrogen molecules, water, a hydroxyl group, hydride, or the like mixed to the oxide semiconductor film can be reduced. In addition, when the target is used, the concentration of alkali metal such as lithium, sodium, or potassium can be reduced in the oxide semiconductor film.
Note that it has been pointed out that an oxide semiconductor is insensitive to impurities, there is no problem when a considerable amount of metal impurities is contained in the film, and therefore, soda-lime glass which contains a large amount of alkali metal such as sodium (Na) and is inexpensive can be used (Kamiya, Nomura, and Hosono, “Carrier Transport Properties and Electronic Structures of Amorphous Oxide Semiconductors: The present status”, KOTAI BUTSURI (SOLID STATE PHYSICS), 2009, Vol. 44, pp. 621-633). But such consideration is not appropriate. Alkali metal is not an element included in an oxide semiconductor, and therefore, is an impurity. Also, alkaline earth metal is impurity in the case where alkaline earth metal is not included in an oxide semiconductor. Alkali metal, in particular, Na becomes Na+ when an insulating film in contact with the oxide semiconductor layer is an oxide and Na diffuses into the insulating layer. Further, in the oxide semiconductor layer, Na cuts or enters a bond between metal and oxygen which are included in an oxide semiconductor. As a result, for example, deterioration of characteristics of the transistor, such as a normally-on state of the transistor due to shift of a threshold voltage in the negative direction, or reduction in mobility, occurs. In addition, variations in characteristics also occurs. Such deterioration of characteristics and variations in characteristics of the transistor due to the impurity remarkably appear when the concentration of hydrogen in the oxide semiconductor layer is extremely low. Therefore, when the hydrogen concentration in the oxide semiconductor layer is less than or equal to 1×1018/cm3, preferably less than or equal to 1×1017/cm3, the concentration of the above impurity is preferably reduced. Specifically, a measurement value of a Na concentration by secondary ion mass spectrometry is preferably less than or equal to 5×1016/cm3, more preferably less than or equal to 1×1016/cm3, still more preferably less than or equal to 1×1015/cm3. In a similar manner, a measurement value of a Li concentration is preferably less than or equal to 5×1015/cm3, more preferably less than or equal to 1×1015/cm3. In a similar manner, a measurement value of a K concentration is preferably less than or equal to 5×1015/cm3, more preferably less than or equal to 1×1015/cm3.
The oxide semiconductor film is in a single crystal state, a polycrystalline (also referred to as polycrystal) state, an amorphous state, or the like.
The oxide semiconductor layer is preferably a CAAC-OS (c-axis aligned crystalline oxide semiconductor) film.
The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts are included in an amorphous phase. Note that in most cases, the crystal part fits inside a cube whose one side is less than 100 nm From an observation image obtained with a transmission electron microscope (TEM), a boundary between an amorphous part and a crystal part in the CAAC-OS film is not clear. Further, with the TEM, a grain boundary in the CAAC-OS film is not found. Thus, in the CAAC-OS film, a reduction in electron mobility, due to the grain boundary, is prevented.
In each of the crystal parts included in the CAAC-OS film, a c-axis is aligned in a direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, triangular or hexagonal atomic arrangement which is seen from the direction perpendicular to the a-b plane is formed, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis. Note that, among crystal parts, the directions of the a-axis and the b-axis of one crystal part may be different from those of another crystal part. In this specification, a simple term “perpendicular” includes a range from 85° to 95°. In addition, a simple term “parallel” includes a range from −5° to 5°.
In the CAAC-OS film, distribution of crystal parts is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth occurs from a surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher than that in the vicinity of the surface where the oxide semiconductor film is formed in some cases. Further, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.
Since the c-axes of the crystal parts included in the CAAC-OS film are aligned in the direction parallel to a normal vector of a surface where the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, the directions of the c-axes may be different from each other depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface where the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film). Note that when the CAAC-OS film is formed, the direction of c-axis of the crystal part is the direction parallel to a normal vector of the surface where the CAAC-OS film is formed or a normal vector of the surface of the CAAC-OS film. The crystal part is formed by deposition or by performing treatment for crystallization such as heat treatment after deposition.
With use of the CAAC-OS film in a transistor, change in electric characteristics of the transistor due to irradiation with visible light or ultraviolet light can be reduced. Thus, the transistor has high reliability.
An example of a crystal structure of the CAAC-OS film is described in detail with reference to
Here, a plurality of small groups form a medium group, and a plurality of medium groups form a large group (also referred to as a unit cell).
Now, a rule of bonding between the small groups will be described. The three O atoms in the upper half with respect to the hexacoordinate In atom in
A metal atom whose coordination number is 4, 5, or 6 is bonded to another metal atom through a tetracoordinate O atom in the c-axis direction. In addition to the above, a medium group can be formed in a different manner by combining a plurality of small groups so that the total electric charge of the layered structure is 0.
In
In the medium group included in the layered structure of the In—Sn—Zn—O-based material in
Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively. For example, electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4, respectively. Accordingly, electric charge in a small group including a Sn atom is +1. Therefore, electric charge of −1, which cancels +1, is needed to form a layered structure including a Sn atom. As a structure having electric charge of −1, the small group including two Zn atoms as illustrated in
When the large group illustrated in
The above-described rule also applies to the following materials: a four-component metal oxide such as an In—Sn—Ga—Zn—O-based oxide; a three-component metal oxide such as an In—Ga—Zn—O-based oxide (also referred to as IGZO), an In—Al—Zn—O-based oxide, a Sn—Ga—Zn—O-based oxide, an Al—Ga—Zn—O-based oxide, a Sn—Al—Zn—O-based oxide, an In—Hf—Zn—O-based oxide, an In—La—Zn—O-based oxide, an In—Ce—Zn—O-based oxide, an In—Pr—Zn—O-based oxide, an In—Nd—Zn—O-based oxide, an In—Sm—Zn—O-based oxide, an In—Eu—Zn—O-based oxide, an In—Gd—Zn—O-based oxide, an In—Tb—Zn—O-based oxide oxide, an In—Dy—Zn—O-based oxide, an In—Ho—Zn—O-based oxide, an In—Er—Zn—O-based oxide, an In—Tm—Zn—O-based oxide, an In—Yb—Zn—O-based oxide, or an In—Lu—Zn—O-based oxide; a two-component metal oxide such as an In—Zn—O-based oxide, a Sn—Zn—O-based oxide, an Al—Zn—O-based oxide, a Zn—Mg—O-based oxide, a Sn—Mg—O-based oxide, an In—Mg—O-based oxide, or an In—Ga—O-based oxide; and the like.
As an example,
In the medium group included in the layered structure of the In—Ga—Zn—O-based material in
Here, since electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate) Ga atom are +3, +2, and +3, respectively, electric charge of a small group including any of an In atom, a Zn atom, and a Ga atom is 0. As a result, the total electric charge of a medium group having a combination of such small groups is always 0.
In order to form the layered structure of the In—Ga—Zn—O-based material, a large group can be formed using not only the medium group illustrated in
When the large group shown in
In the case where n=1 (InGaZnO4), a crystal structure illustrated in
In the case where n is 2 (InGaZn2O5), a crystal structure illustrated in
A CAAC-OS film can be formed by sputtering. The above material can be used as a target material. In the case where the CAAC-OS film is formed by a sputtering method, the proportion of an oxygen gas in an atmosphere is preferably high. In the case where sputtering is performed in a mixed gas of argon and oxygen, for example, the proportion of an oxygen gas is preferably 30% or higher, more preferably 40% or higher because supply of oxygen from the atmosphere promotes crystallization of the CAAC-OS film.
In the case where the CAAC-OS film is formed by a sputtering method, a substrate over which the CAAC-OS film is formed is heated preferably to 150° C. or higher, more preferably to 170° C. or higher. This is because the higher the substrate temperature becomes, the more crystallization of the CAAC-OS film is promoted.
After heat treatment is performed on the CAAC-OS film in a nitrogen atmosphere or in vacuum, heat treatment is preferably performed in an oxygen atmosphere or a mixed gas of oxygen and another gas. This is because oxygen deficiency due to the former heat treatment can be reduced by supply of oxygen from the atmosphere in the latter heat treatment.
A film surface on which the CAAC-OS film is formed (deposition surface) is preferably flat. This is because roughness of the deposition surface leads to generation of grain boundaries in the CAAC-OS film because the c-axis approximately perpendicular to the deposition surface exists in the CAAC-OS film. For this reason, the deposition surface is preferably subjected to planarization treatment such as chemical mechanical polishing (CMP) before the CAAC-OS film is deposited. The average roughness of the deposition surface is preferably 0.5 nm or less, more preferably 0.3 nm or less.
Note that an oxide semiconductor film (or an oxide semiconductor layer formed using an oxide semiconductor film) formed by a sputtering method or the like contains moisture or hydrogen (including a hydroxyl group) as impurities in some cases. In one embodiment of the present invention, in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film (the oxide semiconductor layer) (in order to perform dehydration or dehydrogenation), heat treatment is performed on the oxide semiconductor film (the oxide semiconductor layer) in a reduced-pressure atmosphere, an inert gas atmosphere of nitrogen, a rare gas, or the like, an oxygen gas atmosphere, or ultra dry air (the moisture amount is 20 ppm (−55° C. by conversion into a dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less, in the case where measurement is performed by a dew point meter in a cavity ring-down laser spectroscopy (CRDS) method).
Heat treatment can eliminate moisture or hydrogen in the oxide semiconductor film (the oxide semiconductor layer). Specifically, the heat treatment may be performed at temperature higher than or equal to 250° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of a substrate. For example, the heat treatment may be performed at 500° C. for 3 minutes or longer and 6 minutes or shorter. When RTA is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time; thus, treatment can be performed even at temperature higher than the strain point of a glass substrate.
After moisture or hydrogen in the oxide semiconductor film is eliminated in such a manner, oxygen is added to the oxide semiconductor film (the oxide semiconductor layer). Thus, oxygen defects in the oxide semiconductor film (oxide semiconductor layer), or the like is reduced, so that the oxide semiconductor layer can be an i-type or substantially i-type oxide semiconductor layer.
The addition of oxygen can be performed in such a manner that an insulating film including a region where the amount of oxygen is greater than that in the stoichiometric composition ratio is formed in contact with the oxide semiconductor film (or the oxide semiconductor layer), and then heated. In such a manner, excessive oxygen in the insulating film can be supplied to the oxide semiconductor film (oxide semiconductor layer). Thus, the oxide semiconductor film (oxide semiconductor layer) can contain oxygen excessively. Oxygen contained excessively exists, for example, between lattices of a crystal included in the oxide semiconductor film (oxide semiconductor layer).
Note that the insulating film including a region where the amount of oxygen is greater than that in the stoichiometric composition ratio may be used for either the insulating film positioned on the upper side of the oxide semiconductor film (oxide semiconductor layer) or the insulating film positioned on the lower side of the oxide semiconductor film (oxide semiconductor layer) of the insulating films in contact with the oxide semiconductor film (oxide semiconductor layer); however, it is preferable to use such an insulating film to both of the insulating films in contact with the oxide semiconductor film (oxide semiconductor layer). The above-described effect can be enhanced with a structure, in which the insulating films each including a region where the amount of oxygen is greater than that in the stoichiometric composition ratio are used as the insulating films in contact with the oxide semiconductor film (oxide semiconductor layer) and positioned on the upper side and the lower side of the oxide semiconductor film (oxide semiconductor layer) so that the oxide semiconductor film (oxide semiconductor layer) is provided between the insulating films.
Here, the insulating film including a region where the amount of oxygen is greater than that in the stoichiometric composition ratio may be a single-layer insulating film or a plurality of insulating films which are stacked. Note that it is preferable that the insulating film include impurities such as moisture and hydrogen as little as possible. When hydrogen is contained in the insulating film, entry of the hydrogen to the oxide semiconductor film (oxide semiconductor layer) or extraction of oxygen from the oxide semiconductor film (oxide semiconductor layer) by the hydrogen occurs, whereby the oxide semiconductor film has lower resistance (has n-type conductivity); thus, a parasitic channel might be formed. Therefore, it is important that a film formation method in which hydrogen is not used be employed in order to form the insulating film containing as little hydrogen as possible. In addition, a material having a high barrier property is preferably used for the insulating film. For example, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum oxide film, an aluminum nitride oxide film, or the like can be used as the insulating film having a high barrier property. In the case of using a plurality of insulating films which are stacked, an insulating film having a lower proportion of nitrogen such as a silicon oxide film or a silicon oxynitride film is formed to be closer to the oxide semiconductor film (oxide semiconductor layer) than the insulating film having high barrier property. Then, the insulating film having a high barrier property is formed to overlap with the oxide semiconductor film (oxide semiconductor layer) with the insulating film having a lower proportion of nitrogen provided therebetween. With the use of the insulating film having a high barrier property, impurities such as moisture or hydrogen can be prevented from entering the oxide semiconductor film (oxide semiconductor layer), the interface between the oxide semiconductor film and another insulating film, and the vicinity thereof. In addition, the insulating film having lower proportion of nitrogen such as a silicon oxide film or a silicon oxynitride film is formed to be in contact with the oxide semiconductor film (oxide semiconductor layer), so that the insulating film formed using a material having a high barrier property can be prevented from being in contact with the oxide semiconductor film (oxide semiconductor layer) directly.
Alternatively, the addition of oxygen after moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer) is eliminated may be performed by heat treatment on the oxide semiconductor film (oxide semiconductor layer) in an oxygen atmosphere. The heat treatment is performed at a temperature of, for example, higher than or equal to 100° C. and lower than 350° C., preferably higher than or equal to 150° C. and lower than 250° C. It is preferable that an oxygen gas used for the heat treatment under an oxygen atmosphere do not include water, hydrogen, or the like. Alternatively, the purity of the oxygen gas which is introduced into the heat treatment apparatus is preferably greater than or equal to 6N (99.9999%), further preferably greater than or equal to 7N (99.99999%) (that is, the impurity concentration in the oxygen gas is less than or equal to 1 ppm, preferably less than or equal to 0.1 ppm).
Further alternatively, the addition of oxygen after moisture or hydrogen in the oxide semiconductor film (oxide semiconductor layer) is eliminated may be performed by an ion implantation method or an ion doping method. For example, oxygen made to be plasma with a microwave of 2.45 GHz may be added to the oxide semiconductor film (oxide semiconductor layer).
The thus formed oxide semiconductor layer can be used as the semiconductor layer of the transistor 601. In this manner, the transistor 601 with extremely low off-state current can be obtained.
Alternatively, the semiconductor layer of the transistor 601 may include microcrystalline silicon. Note that microcrystalline silicon is a semiconductor having an intermediate structure between an amorphous structure and a crystalline structure (including single crystal and polycrystal). In the microcrystalline silicon, columnar or needle-like crystal grains having a grain size of 2 nm to 200 nm, preferably 10 nm to 80 nm, further preferably 20 nm to 50 nm, still further preferably 25 nm to 33 nm have grown in a direction normal to the substrate surface. Therefore, there are some cases in which a crystal grain boundary is formed at the interface between the columnar or needle-like crystal grains.
Alternatively, the semiconductor layer of the transistor 601 may include amorphous silicon. Alternatively, the semiconductor layer of the transistor 601 may include polycrystalline silicon. Alternatively, the semiconductor layer of the transistor 601 may include an organic semiconductor, a carbon nanotube, or the like.
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, the structures of a display panel cell having the pixel configuration described in Embodiments 7 to 14 are described with reference to
It is to be noted that
Note that a wire 6708 is a wire for transmitting a signal input to the first scan line driver circuit 6703, the second scan line driver circuit 6706, and the signal line driver circuit 6701 and receives a video signal, a clock signal, a start signal, and the like from a flexible printed circuit (FPC) 6709 functioning as an external input terminal. An IC chip (semiconductor chip including a memory circuit, a buffer circuit, and the like) 6719 is mounted over a connecting portion of the FPC 6709 and the display panel cell by chip on glass (COG) or the like. It is to be noted that only the FPC 6709 is shown here; however, a printed wire board (PWB) may be attached to the FPC 6709. The display device in this specification includes not only a main body of the display panel cell but also one with an FPC or a PWB attached thereto and one on which an IC chip or the like is mounted.
Next, description is made with reference to
Note that the signal line driver circuit 6701 is formed of a p-channel or n-channel transistor such as an n-channel transistor 6720 or an n-channel transistor 6721. As for a pixel configuration, a pixel can be formed of a p-channel or n-channel transistor by applying the pixel configuration of
Further, the pixel portion 6702 includes transistors 6711 and 6712. It is to be noted that a source electrode of the transistor 6712 is connected to a first electrode (pixel electrode) 6713. An insulator 6714 is formed so as to cover end portions of the first electrode 6713. Here, a positive photosensitive acrylic resin film is used for the insulator 6714.
In order to obtain excellent coverage, the insulator 6714 is formed to have a curved surface having a curvature at a top end portion or a bottom end portion of the insulator 6714. For example, in the case of using a positive photosensitive acrylic as a material for the insulator 6714, it is preferable that only the top end portion of the insulator 6714 has a curved surface having a curvature radius (0.2 to 3 μm). Moreover, either a negative photosensitive acrylic which becomes insoluble in etchant by light or a positive photosensitive acrylic which becomes soluble in etchant by light can be used as the insulator 6714.
A layer 6716 containing an organic compound and a second electrode (opposite electrode) 6717 are formed over the first electrode 6713. Here, it is preferable to use a material having a high work function as a material used for the first electrode 6713 which functions as an anode. For example, a single layer of an indium tin oxide film, an indium zinc oxide film, a titanium nitride film, a chromium film, a tungsten film, a Zn film, a Pt film, or the like, a stacked layer of a titanium nitride film and a film containing aluminum as a main component, a three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film, or the like can be used. It is to be noted that with a stacked layer structure, resistance as a wire is low, good ohmic contact can be obtained, and a function as an anode can be obtained.
The layer 6716 containing an organic compound is formed by an evaporation method using an evaporation mask, or ink-jet. A complex of a metal belonging to group 4 of the periodic table of the elements is used for a part of the layer 6716 containing an organic compound. Besides, a low molecular material or a high molecular material may be used in combination as well. Further, as a material used for the layer containing an organic compound, a single layer or a stacked layer of an organic compound is often used; however, in this example, an inorganic compound may be used in a part of a film formed of an organic compound. Moreover, a known triplet material can also be used.
Further, as a material used for the second electrode 6717 which functions as a cathode and is formed over the layer 6716 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF2, or Ca3N2) may be used. In the case where light generated from the layer 6716 containing an organic compound passes through the second electrode 6717, a stacked layer of a thin metal film with a thinner thickness and a transparent conductive layer (e.g., an indium tin oxide film, indium oxide zinc oxide (In2O3—ZnO), or zinc oxide (ZnO)) is preferably used as the second electrode 6717 (cathode).
Further, by attaching the sealing substrate 6704 to the substrate 6710 with the sealing material 6705, a light-emitting element 6718 is provided in the space 6707 surrounded by the substrate 6710, the sealing substrate 6704, and the sealing material 6705. It is to be noted that the space 6707 may be filled with the sealing material 6705, as well as with an inert gas (nitrogen, argon, or the like).
Note that an epoxy-based resin is preferably used for the sealing material 6705. Further, it is preferable that these materials should not transmit moisture or oxygen as much as possible. As a material for the sealing substrate 6704, a glass substrate, a quartz substrate, a plastic substrate formed of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinylfluoride), polyester, acrylic, or the like can be used.
In the above manner, the display panel cell with the pixel structures in Embodiments 7 to 14 can be obtained.
Next, a structural example of a display module which includes the display panel cell described with reference to
A display module 8000 has an upper cover 8001 and a lower cover 8002 with a touch panel cell 8004 connected to an FPC 8003, a display panel cell 8006 connected to an FPC 8005, a frame 8007, and a printed circuit 8008 provided therebetween.
The shapes and sizes of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel cell 8004 and the display panel cell 8006.
The touch panel cell 8004 can be a resistive touch panel cell or a capacitive touch panel cell and may be formed to overlap with the display panel cell 8006. A counter substrate (sealing substrate) of the display panel cell 8006 can have a touch panel function. A photosensor may be provided in each pixel of the display panel cell 8006 and the touch panel cell 8004 can be an optical touch panel.
The display panel cell illustrated in
The frame 8007 has a function of protecting the display panel cell 8006 and functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit 8008. The frame 8007 may function as a radiator plate.
The printed circuit 8008 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. A power source for supplying power to the power supply circuit can be an external commercial power source or a power source using a battery which is additionally provided.
The display module 8000 can be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet
This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part of or the whole of the other embodiment. Thus, part of or the whole of this embodiment can be freely combined with, applied to, or replaced with part of or the whole of another embodiment.
In this embodiment, examples of electronic devices are described.
The electronic devices illustrated in
The electronic devices in this embodiment each include a display portion for displaying some kind of information.
Next, application examples of semiconductor devices are described.
Note that although this embodiment describes the wall and the prefabricated bath unit as examples of the building structures, this embodiment is not limited thereto. The semiconductor devices can be provided in a variety of building structures.
Next, examples in which semiconductor devices are incorporated in moving objects are described.
Note that although bodies of a car and an airplane are illustrated as examples of moving objects in this embodiment, this embodiment is not limited to them. The semiconductor devices can be provided for a variety of objects such as two-wheeled vehicles, four-wheeled vehicles (including cars, buses, and the like), trains (including monorails, railroads, and the like), and vessels.
Note that in this specification and the like, in a diagram or a text described in one embodiment, part of the diagram or the text is taken out, and one embodiment of the invention can be constituted. Thus, in the case where a diagram or a text related to a certain portion is described, the context taken out from part of the diagram or the text is also disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. Therefore, for example, in a diagram or a text in which one or more active elements (e.g., transistors or diodes), wirings, passive elements (e.g., capacitors or resistors), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operating methods, manufacturing methods, or the like are described, part of the diagram or the text is taken out, and one embodiment of the invention can be constituted. For example, M circuit elements (e.g., transistors or capacitors) (M is an integer, where M<N) are taken out from a circuit diagram in which N circuit elements (e.g., transistors or capacitors) (N is an integer) are provided, and one embodiment of the invention can be constituted. As another example, M layers (M is an integer, where M<N) are taken out from a cross-sectional view in which N layers (N is an integer) are provided, and one embodiment of the invention can be constituted. As another example, M elements (M is an integer, where M<N) are taken out from a flow chart in which N elements (N is an integer) are provided, and one embodiment of the invention can be constituted.
Note that in this specification and the like, in a diagram or a text described in one embodiment, in the case where at least one specific example is described, it will be readily appreciated by those skilled in the art that a broader concept of the specific example can be derived. Thus, in the diagram or the text described in one embodiment, in the case where at least one specific example is described, a broader concept of the specific example is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted.
Note that in this specification and the like, a content described in at least a diagram (or may be part of the diagram) is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. Thus, when a certain content is described in a diagram, the content is disclosed as one embodiment of the invention even when the content is not described with a text, and one embodiment of the invention can be constituted. Similarly, part of a diagram that is taken out from the diagram is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted.
This application is based on Japanese Patent Application serial No. 2011-145262 filed with Japan Patent Office on Jun. 30, 2011, the entire contents of which are hereby incorporated by reference.
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