An integrated circuit includes a plurality of functional blocks. utilization information for the various functional blocks is generated. Based on that information, the power consumption and thus the performance levels of the functional blocks can be tuned. Thus, when a functional block is heavily loaded by an application, the performance level and thus power consumption of that particular functional block is increased. At the same time, other functional blocks that are not being heavily utilized and thus have lower performance requirements can be kept at a relatively low power consumption level. Thus, power consumption can be reduced overall without unduly impacting performance.
|
0. 38. An integrated circuit comprising:
a plurality of functional blocks; and
utilization circuits respectively coupled to the functional blocks to provide block utilization information of the functional blocks, wherein the integrated circuit, responsive to the block utilization information, independently adjusts power consumption levels of the functional blocks to match respective block utilization levels,
wherein a clock frequency and a power supply voltage of a selected functional block and a dispatch rate of a first set of operations dispatched to or within the selected functional block are increased in response to an increase in the block utilization level associated with the selected functional block, and
wherein the clock frequency and the power supply voltage of the selected functional block and the dispatch rate of a second set of operations dispatched to or within the selected functional block are decreased in response to a decrease in the block utilization level associated with the selected functional block.
0. 28. An integrated circuit comprising:
a plurality of functional blocks;
utilization circuits respectively coupled to the functional blocks to provide block utilization information of the functional blocks, the block utilization information indicating a utilization rate of a corresponding functional block, and wherein a block utilization level of the corresponding functional block is based at least in part on the utilization rate; and
wherein the integrated circuit, responsive to the block utilization information, independently adjusts power consumption levels of each of the functional blocks to match respective block utilization levels,
wherein a power consumption level of a selected functional block is increased in response to the utilization rate of the selected functional block being greater than a first threshold,
wherein the power consumption level of the selected functional block is decreased in response to the utilization rate of the selected functional block being less than a second threshold,
wherein the power consumption level of the selected functional block is adjusted by changing a power consumption parameter of the selected functional block, and
wherein the second threshold is different from the first threshold.
0. 32. An integrated circuit comprising:
a plurality of functional blocks;
utilization circuits respectively coupled to the functional blocks to provide block utilization information of the functional blocks, wherein the block utilization information represents activity in each of the functional blocks as measured over a period of time, and
wherein each of the utilization circuits comprises:
a utilization detection circuit to detect a utilization event;
a utilization counter to count a number of utilization events; and
a cycle counter to count to a value equal to the period of time;
wherein the integrated circuit, responsive to the block utilization information, independently adjusts power consumption levels of the of the functional blocks to match respective block utilization levels according to the block utilization information,
wherein one or more of the block utilization levels are based at least in part on the number of utilization events counted by the utilization counter over the period of time,
wherein, in response to an increase in a block utilization level for a respective functional block, a clock frequency of the respective functional block is increased to a first frequency value, and
wherein, in response to a decrease in the block utilization level for the respective functional block, the clock frequency of the respective functional block is decreased to a second frequency value, the first and second frequency values being different from one another and each greater than zero hertz.
0. 1. A method of controlling power consumption in an integrated circuit that includes a plurality of functional blocks, comprising:
generating respective block utilization information for the functional blocks included in the integrated circuit; and
independently managing power of the respective functional blocks to match respective block utilization levels according to the respective block utilization information.
0. 2. The method as recited in
0. 3. The method as recited in
0. 4. The method as recited in
0. 5. The method as recited in
0. 6. The method as recited in
0. 7. The method as recited in
0. 8. The method as recited in
0. 9. The method as recited in
0. 10. The method as recited in
0. 11. The method as recited in
reading utilization information from a utilization register associated with one of the functional blocks; and
adjusting power usage of the one functional block according to the utilization information read.
0. 12. The method as recited in
0. 13. The method as recited in
adjusting the frequency of a first clock being supplied to one of the functional blocks upward, when first utilization information for the one block is above a first threshold; and
adjusting the frequency of the first clock downward when the first utilization information for the one block is below a second threshold.
0. 14. The method as recited in
0. 15. The method as recited in
0. 16. An integrated circuit comprising:
a plurality of functional blocks;
utilization circuits respectively associated with the functional blocks coupled to provide block utilization information of the functional blocks; and wherein
the integrated circuit is responsive to the block utilization information to independently adjust power consumption levels of the functional blocks to match respective block utilization levels.
0. 17. The integrated circuit as recited in
0. 18. The integrated circuit as recited in
0. 19. The integrated circuit as recited in
a clock control circuit coupled to independently adjust the frequency of respective clocks being supplied to the functional blocks.
0. 20. The integrated circuit as recited in
0. 21. The integrated circuit as recited in
0. 22. The integrated circuit as recited in
0. 23. A computer system comprising:
an integrated circuit that includes a plurality of functional blocks;
utilization circuits respectively associated with the functional blocks and coupled to provide block utilization information of the functional blocks; and
a computer program including an instruction sequence executable by the integrated circuit to adjust power consumption levels of the functional blocks to match respective block utilization levels according to the block utilization information.
0. 24. The computer system as recited in
0. 25. The computer system as recited in
0. 26. An electronic system comprising:
an integrated circuit including a plurality of functional blocks;
means for determining respective block utilization information of the functional blocks; and
means for adjusting power consumption of the respective functional blocks to match respective block utilization levels according to the respective block utilization information.
0. 27. The method of
increasing power consumption levels for those functional blocks with utilization information that indicates increased utilization; and
decreasing power consumption levels for those functional blocks with utilization information that indicates decreased utilization.
0. 29. The integrated circuit of claim 28, wherein:
each of the utilization circuits comprises a timer to set a monitoring time period at which the block utilization level for a respective functional block is checked, and
the monitoring time period is different for one or more timers.
0. 30. The integrated circuit of claim 28, wherein the power consumption parameter comprises a clock frequency associated with the selected functional block, a voltage supplied to the selected functional block, a dispatch rate of operations associated with the selected functional block, or a combination thereof.
0. 31. The integrated circuit of claim 28, wherein the power consumption parameter comprises a clock frequency derived from a clock divider circuit operable to provide a base clock frequency or a fraction of the base clock frequency.
0. 33. The integrated circuit of claim 32, wherein the clock frequency increases or decreases in step adjustments.
0. 34. The integrated circuit of claim 32, wherein the clock frequency of the respective functional block is increased to the first frequency value or decreased to the second frequency value without changing a clock frequency of another functional block.
0. 35. The integrated circuit of claim 32, wherein:
the first frequency value matches a first block utilization level associated with a first load of the respective functional block; and
the second frequency matches a second block utilization level associated with a second load of the respective functional block, wherein the first load is greater than the second load.
0. 36. The integrated circuit of claim 32, wherein:
in response to the increase in the block utilization level for the respective functional block, a power supply voltage of the respective functional block is increased to a first voltage value, and
in response to the decrease in the block utilization level for the respective functional block, the power supply voltage of the respective functional block is decreased to a second voltage value, the first and second voltage values being different from one another and each greater than zero volts.
0. 37. The integrated circuit of claim 32, wherein:
in response to the increase in the block utilization level for the respective functional block, a dispatch rate of operations issued to the respective functional block is increased to a first dispatch rate value, and
in response to the decrease in the block utilization level for the respective functional block, the dispatch rate of operations issued to the respective functional block is decreased to a second dispatch rate value, the first and second dispatch rate values being different from one another and each greater than zero.
0. 39. The integrated circuit of claim 38, wherein the block utilization information represents activity in each of the functional blocks as measured over a period of time, and wherein each of the utilization circuits comprises:
a utilization detection circuit to detect a utilization event;
a utilization counter to count a number of utilization events; and
a cycle counter to count to a value equal to the period of time.
0. 40. The integrated circuit of claim 39, wherein the period of time is different for one or more functional blocks.
0. 41. The integrated circuit of claim 38, wherein the clock frequency of the selected functional block is increased or decreased without changing a clock frequency of another functional block.
0. 42. The integrated circuit of claim 38,
wherein, in response to the increase in the block utilization level associated with the selected functional block, the clock frequency is increased to a first frequency value and the power supply voltage is increased to a first voltage value,
wherein, in response to the decrease in the block utilization level associated with the selected functional block, the clock frequency is decreased to a second frequency value and the power supply voltage is decreased to a second voltage value, and wherein:
the first frequency value matches a first block utilization level associated with a first load of the selected functional block; and
the second frequency matches a second block utilization level associated with a second load of the selected functional block, wherein the first load is greater than the second load.
|
This application is a continuation of U.S. patent application Ser. No. 15/217,553, titled “Performance and Power Optimization via Block Oriented Performance Measurement and Control,” filed Jul. 22, 2016, and issued as U.S. Pat. No. RE47,420, which is a reissue of U.S. patent application Ser. No. 09/798,176, titled “Performance and Power Optimization via Block Oriented Performance Measurement and Control,” filed Mar. 2, 2001, and issued as U.S. Pat. No. 6,895,520, all of which are incorporated by reference herein in their entireties. This application is a re-issue of U.S. patent application Ser. No. 09/798,176, titled “Performance and Power Optimization via Block Oriented Performance Measurement and Control,” filed Mar. 2, 2001, and issued as U.S. Pat. No. 6,895,520, which is incorporated by reference herein in its entirety.
I. Field of the Invention
This invention relates to integrated circuits and more particularly to power management in integrated circuits.
2. Description of the Related Art
Large computational devices, e.g., current microprocessors, include many functional units such as one or more fixed point units, load/store units, floating point units (FPU), vector arithmetic units, barrel shifters, instruction and data cache memories, bridge or tunnel circuits, memory controllers, first in first out (FIFO) buffers, and various input/output interface units (e.g., interfaces for universal asynchronous receiver/transmitters (UART), serializer/deserializer (SERDES), HyperTransport™, Infiniband™, PCI bus). In a portable computing environment, where power conservation is particularly important, power management techniques have been implemented to conserve power based on when, e.g., a period of inactivity occurs. The power conservation typically includes stopping clocks for a period of time. However, the clocks are controlled globally, and thus in situations where one part of a processor is being heavily used but another part is being lightly utilized, all the functional blocks in the processor are configured for heavy use. Thus, power may be wasted in situations where, e.g., the fixed point unit is being used but the floating point unit is not being utilized heavily or at all.
In a prior art power savings approach, disclosed in U.S. Pat. No. Re 37,839, functional blocks are deactivated to save power. The activation and deactivation of the functional blocks is controlled by the flow of data within the integrated circuit. Thus, as data flows through the integrated circuit, those functional blocks are turned on and off as necessary to accommodate that data flow.
The amount of power consumed by a functional block is directly related to its performance. In order to allocate power resources more effectively, it would be desirable to be able to dynamically match performance and thus control power consumed by individual functional blocks according to the utilization requirements of the functional blocks. However, current designs generally do not provide information about utilization of the individual functional blocks, and power consumption is not tuned to match the loading of the individual functional blocks. A possible disadvantage to turning clocks on and off based on data flow is that inefficiencies may result due to the time it takes to turn clocks on and off to the various functional blocks. Accordingly, it would be desirable to dynamically adjust the power consumed by functional blocks of an integrated circuit according to the utilization or loading of those functional blocks and thus achieve power savings while maintaining performance.
The present invention monitors the utilization of the functional blocks in an integrated circuit. Based on that information, the power consumption and thus the performance levels of the functional blocks can be tuned. When a functional block is heavily loaded by an application, the performance level and power consumption of that particular functional block can be increased. At the same time, other blocks that may not be loaded by that application and have lower performance requirements can be kept at a relatively low power consumption level. Thus, power consumption can be reduced overall without unduly impacting performance.
In one embodiment, the invention provides a method for controlling power consumption in an integrated circuit that includes a plurality of functional blocks. The functional blocks generate block utilization information. The power consumption of the respective functional blocks is managed according to respective block utilization information. The power consumption can be managed by adjusting dispatch rate of operations through the particular functional block, adjusting the clock frequency of clocks being supplied to the functional circuit and/or adjusting the voltage along with the clock frequency. In an embodiment, utilization information may be kept on a task basis.
In another embodiment, the invention provides a computer system that includes an integrated circuit that has a plurality of functional blocks. Utilization circuits that are respectively associated with the functional blocks provide block utilization information of the functional blocks. A computer program includes an instruction sequence executable by the integrated circuit to adjust power consumption levels of the functional blocks according to the block utilization information.
In another embodiment an integrated circuit includes a plurality of functional blocks. Utilization circuits respectively associated with the functional blocks provide block utilization information of the functional blocks. The integrated circuit is responsive to the block utilization information to independently adjust power consumption levels of the functional blocks.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
Referring to
An exemplary functional block 200 is shown in
Thus, as shown in
In addition to counting the utilization events, a measure may be needed to indicate the period of time over which the counted utilizations occurred. In the exemplary embodiment shown in
Software, which may reside in the operating system or elsewhere in the electronic system can periodically read utilization counter 205 and cycle counter 207 and determine whether the power consumption and thus the performance of the functional unit matches the load of the functional unit, i.e., its utilization. The power consumption of a functional unit can be adjusted in a number of ways including increasing or decreasing a dispatch rate of instructions into an execution unit (or floating point operations into an FPU), adjusting clock frequency up or down as well as adjusting voltage up or down to match the clock rate. If the functional unit is set for low performance operations and thus has a low power consumption setting and the latest utilization information indicates that the functional unit is heavily loaded, the power consumption and thus performance of the functional unit can be increased to match the performance requirements indicated by the utilization information. In order to increase performance, clock frequency, voltage, and dispatch rate can all be increased. Note that voltage is typically changed only with clock frequency.
If on the other hand, the utilization information indicates that the functional unit is lightly loaded, the clock frequency and/or other power management parameters can be decreased to match the loading. If a particular functional unit is unused or very lightly used, its clocks may even be turned off for a period of time.
In an embodiment, thresholds are provided to determine whether a current power consumption and performance level is appropriate. In order to determine whether current performance levels are adequate as indicated by the utilization information in counter 205, the utilization level can be checked periodically at a predetermined time interval determined by counter 207. Thus, a timer may be provided for each functional unit that indicates how often the utilization counter should be read and the power usage adjusted according to loading factors. When the timer expires, appropriate power management software is notified. The timers could be set differently for different functional units so that each functional unit can be checked at a different time. Alternatively, the operating system or other power management software can read all of the utilization information periodically, with the period being determined by a single timer for all of the functional units.
Alternatively, the value in the utilization counter can be divided by the cycle counter to obtain a utilization per unit time. If that is done, then the utilization counter has to be read before the utilization counter 205 overflows. In either case, the utilization level is compared to upper threshold level 209. If the utilization level is above the upper threshold level 209, clock frequency and/or other performance parameters are increased to provide increased performance. The amount of that increase may be based upon the magnitude of the difference between the calculated utilization level and the upper threshold level. For example, a 10% difference may result in a 10% increase. Alternatively, the increase may occur in fixed steps, e.g., from ¼ of a base clock to ½ of a base clock frequency regardless of the difference between the calculated utilization level and the upper threshold level.
The utilization level may also be compared to the lower threshold value and if the calculated utilization is below the lower threshold level, the clock speed is adjusted downward. Again, the adjustment may be based on the magnitude of the difference between the calculated utilization value and the lower threshold value. Or the adjustment may be fixed between a current level and a next lower level, e.g., from full clock speed in the functional unit to ¾ clock speed. In addition, voltage can be adjusted up or down to match the clock speed for additional power savings.
The threshold registers can be implemented as registers in the functional units or integrated circuit (e.g., model specific registers), system memory, or any other suitable memory that can be used by the software performing the power management function. The values for the threshold registers may be supplied by BIOS, application software or some other initialization source. For example, the values for the threshold registers for each functional block may be calculated empirically by the operating system. Each functional unit would typically have associated with it unique threshold registers.
Once an appropriate utilization number is obtained, it is compared to the upper threshold value in 309. If the utilization number is greater than the upper threshold value then in 311, a control indication is provided to power management control logic 112 (see
In one embodiment, a non intrusive performance monitoring circuit can be utilized to determine a probability of a utilization event occurring. Such a circuit is shown in
A counter 401 provides a count value which is compared in comparator 403 with a random number generated in random number generator circuit 405. If the counter value is greater than or equal to the random number, a 1 is generated. The compare signal 404 output from the comparator is provided back to counter 401 as an up/down count signal. When the comparator indicates that the count is larger than the random number, the compare signal 404 configures the counter 401 as a down counter and when the count is less than the random number, the compare signal 404 configures counter to be an up counter.
The compare signal 404 is compared with the input data stream of interest conveyed on node 402. The input data stream is serially provided samples of the performance parameter being measured (e.g., the cache hit information) which are provided by utilization detect circuit 203. These two stochastic data streams (compare signal and input data stream) are compared to see which one has the highest probability of being 1. That is accomplished by XORing the two data streams together in XOR gate 407. When the data streams differ, there is a difference in probability. That probability information is fed back to increase or decrease the counter value according to the comparator output. The feedback in the illustrated embodiment is accomplished by ANDing together clock signal 409 and the output from XOR gate 407 to provide a gated clock signal 410 to the counter. Consequently, with each new comparison the counter is adjusted to produce a probability stream (from the comparator) which matches the input data stream.
TABLE 1
illustrates the action of the counter:
comparator
0
1
0
1
performance
0
0
1
1
parameter data
XOR output
0
1
1
0
count action
none
down
up
none
The adaptive adder circuit effectively integrates the probability stream. The probability stream of the parameter being measured is converted into a digital value which is held in the counter. The counter value represents the probability of the parameter which is being measured. Thus, software or hardware can read counter 401 periodically to determine a sliding window average of the parameter of interest. The size of the window can be adjusted to more closely or less closely track changes in utilization of the functional block.
In addition to monitoring block utilization on an overall basis, the operating system (or other power management software) can monitor block utilization on a software task basis. Thus, the operating system can compile utilization information of various functional blocks per task. In such an embodiment the operating system software creates a power management profile that matches a desired performance level for each functional block for a plurality of tasks. The performance level is indicated by desired power consumption parameters (e.g., clock rate, voltage, dispatch rate) for each of the functional blocks. When the operating system switches the processor to executing a task, the power management controller in conjunction with the operating system software sets the appropriate power management parameters to correspond to the particular task. The power management parameters of the functional blocks can be further adjusted during task execution to further improve power management. In addition, rather than operating system software performing task-based power management, application software may instead perform that function.
Selecting a clock frequency for the various functional units can be accomplished by selectively providing to each functional unit that clock selected by a power management controller. For example, the clocks provided to each functional unit may be a full speed clock, a half speed clock and a quarter speed clock. The granularity of the available clock speed will be design dependent. The ability to provide clocks of different speeds, e.g., by dividing down the full speed clock, is well known in the art and not described further herein.
As is also known in the art, it is advantageous from a power savings perspective to reduce voltage when possible because the power saved is proportional to the square of the voltage reduction, whereas the power savings is linear with respect to frequency reduction. In one embodiment, a plurality of voltages are supplied to the integrated circuit, e.g., one for each potential clock speed for the functional units. A suitable voltage is selected that corresponds to the clock speed. In order to avoid the possible unpredictable results, the voltage should not be adjusted downward until the clock speed has been reduced, and the clock speed should not be adjusted upward until the voltage has been increased. In other embodiments the correct voltage for a particular functional block may be a selectable off chip.
It is desirable to reduce any performance impact when adjusting power management parameters in an attempt save power. Thus, it is desirable that the granularity of checking utilization information be sufficiently high that performance degradation, particularly any degradation noticeable to a user, is minimized. From a user's perspective, checking block utilization every ten milliseconds may be sufficient for most tasks. However, given high clock speeds in current integrated circuits, more frequent checking may be desirable, particularly where performance is very important.
There are various other approaches to conserve power that may be utilized in addition to adjusting frequency and voltage. In one embodiment, dispatch rate of instructions can be reduced in order to reduce power consumption of an execution unit. Note also that utilization information may be generated for sub-blocks. Thus, in an embodiment having three execution pipelines that have a combined utilization of, e.g., 30%, several options are available. The clocks to all of the execution pipelines can be reduced, e.g. by one half, to match the load. In another embodiment, several of the pipelines might be shut down while one pipeline is kept operating at full speed. In another embodiment, the clocks can be turned off while operations directed to a particular functional unit accumulate. Once a sufficient number have accumulated, the clocks can be turned back on and the accumulated operations can be executed in a burst mode, and then the clocks can be turned off again.
Thus, a more finely grained power management technique has been described that allows particular sections of an integrated circuit to be controlled independently from other sections to provide both effective power savings along with good performance. The power management techniques can include adjusting such parameters as clock rates, voltages, and dispatch rates.
The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. For instance while operating system software has been described as performing aspects of the power management, any software, including application software, can incorporate the teachings herein. In addition, while the embodiments described herein have been described mostly with relation to a microprocessor, the power savings and performance approach described herein can be implemented in any integrated circuit or electronic device where both performance and power savings are considerations. Other variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.
Altmejd, Morrie, Menezes, Evandro, Tobias, Dave
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4544950, | Jan 03 1984 | WESTINGHOUSE ELECTRIC CORPORATION, A CORP OF PA | Technique for the transmission of video and audio signals over a digital transmission system |
4745402, | Feb 19 1987 | RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP OF DE | Input device for a display system using phase-encoded signals |
4821261, | Jul 30 1985 | ETAT FRANCAIS, REPRESENTE PAR LE SECRETARIAT D ETAT AUX POSTES ET TELECOMMUNICATIONS CENTRE NATIONAL D ETUDES DES TELECOMMUNICATIONS ; ETABLISSEMENT PUBLIC DE TELEDIFFUSION DIT TELEDIFFUSION DE FRANCE | Packet transmission of digital signals over a high capacity channel, particularly over a satellite broadcasting channel |
4833601, | May 28 1987 | Bull HN Information Systems Inc.; HONEYWELL BULL INC , 3800 WEST 80TH ST , MINNEAPOLIS, MN 55431 A CORP OF DE | Cache resiliency in processing a variety of address faults |
4843568, | Apr 11 1986 | Real time perception of and response to the actions of an unencumbered participant/user | |
4924428, | Dec 08 1987 | Nortel Networks Limited | Real time digital signal processor idle indicator |
4926353, | Apr 04 1987 | Sipra Patententwicklungs-und Beteiligungsgesellschaft GmbH | Measuring apparatus for determining the degree of utilization of a machine |
5142684, | Jun 23 1989 | HAND HELD PRODUCTS, INC | Power conservation in microprocessor controlled devices |
5146210, | Aug 22 1989 | Deutsche ITT Industries GmbH | Wireless remote control system for a television receiver |
5241428, | Mar 12 1991 | CITIGROUP GLOBAL MARKETS REALTY CORP | Variable-delay video recorder |
5280530, | Sep 07 1990 | U.S. Philips Corporation | Method and apparatus for tracking a moving object |
5307003, | Oct 19 1990 | Poqet Computer Corporation | Varying the supply voltage in response to the current supplied to a computer system |
5327160, | May 09 1991 | Touch sensitive user interface for television control | |
5333296, | Jun 29 1990 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Combined queue for invalidates and return data in multiprocessor system |
5396635, | Jun 01 1990 | ST CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC | Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system |
5418969, | Mar 30 1990 | Matsushita Electric Industrial Co., Ltd. | Low power consumption microprocessor |
5423045, | Apr 15 1992 | INTERNATIONAL BUSINESS MACHINES CORPORATION A CORP OF NY | System for distributed power management in portable computers |
5436639, | Mar 16 1993 | Hitachi, Ltd. | Information processing system |
5436676, | Jun 10 1994 | LG Electronics Inc | Remote control unit code translation |
5438372, | Sep 10 1991 | Sony Corporation | Picture-in-picture television receiver with menu displayed in second sub-screen |
5451892, | Oct 03 1994 | UNITED STATES OF AMERICA, THE, AS REPRESENTED BY THE SECRETARY OF COMMERCE | Clock control technique and system for a microprocessor including a thermal sensor |
5490059, | Sep 02 1994 | Advanced Micro Devices, Inc. | Heuristic clock speed optimizing mechanism and computer system employing the same |
5502838, | Apr 28 1994 | PDACO LTD | Temperature management for integrated circuits |
5511203, | Feb 02 1994 | Advanced Micro Devices; Advanced Micro Devices, INC | Power management system distinguishing between primary and secondary system activity |
5511205, | Apr 15 1992 | International Business Machines Corporation | System for distributed power management in portable computers |
5517250, | Feb 28 1995 | Google Technology Holdings LLC | Acquisition of desired data from a packetized data stream and synchronization thereto |
5517257, | Mar 28 1995 | Microsoft Technology Licensing, LLC | Video control user interface for interactive television systems and method for controlling display of a video movie |
5521922, | May 25 1993 | Sony Corporation | Data demultiplexer |
5528263, | Jun 15 1994 | Daniel M., Platzker | Interactive projected video image display system |
5528304, | Jul 22 1994 | LC ELECTRONICS INC | Picture-in-picture feedback for channel related features |
5528698, | Mar 27 1995 | Bendix Commercial Vehicle Systems LLC | Automotive occupant sensing device |
5532753, | Mar 22 1993 | Sony Deutschland GmbH | Remote-controlled on-screen audio/video receiver control apparatus |
5534917, | May 09 1991 | Qualcomm Incorporated | Video image based control system |
5545857, | Jul 27 1994 | SAMSUNG ELECTRONICS CO , LTD | Remote control method and apparatus thereof |
5563988, | Aug 01 1994 | Massachusetts Institute of Technology | Method and system for facilitating wireless, full-body, real-time user interaction with a digitally represented visual environment |
5570108, | Jun 27 1994 | AUTODESK, Inc | Method and apparatus for display calibration and control |
5589893, | Dec 01 1994 | Zenith Electronics Corporation | On-screen remote control of a television receiver |
5592679, | Nov 14 1994 | Oracle America, Inc | Apparatus and method for distributed control in a processor architecture |
5594469, | Feb 21 1995 | Mitsubishi Electric Research Laboratories, Inc | Hand gesture machine control system |
5613152, | Oct 19 1992 | U.S. Philips Corporation | Data processor with operation units executing dyadic and monadic operations sharing groups of register files with one of the units exclusively accessing one of the register files |
5621456, | Jun 22 1993 | Apple Inc | Methods and apparatus for audio-visual interface for the display of multiple program categories |
5654748, | May 05 1995 | Rovi Technologies Corporation | Interactive program identification system |
5675358, | Aug 04 1992 | International Business Machines Corporation | Digital image capture control |
5682511, | May 05 1995 | Microsoft Technology Licensing, LLC | Graphical viewer interface for an interactive network system |
5696985, | Jun 07 1995 | International Business Machines Corporation; International Business Machines Corp | Video processor |
5713030, | Oct 11 1995 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Thermal management device and method for a computer processor |
5719800, | Jun 30 1995 | Intel Corporation | Performance throttling to reduce IC power consumption |
5721829, | May 05 1995 | Microsoft Technology Licensing, LLC | System for automatic pause/resume of content delivered on a channel in response to switching to and from that channel and resuming so that a portion of the content is repeated |
5729280, | Aug 31 1994 | Sony Corporation | Near video-on-demand signal receiver having a memory which provides for VCR like functions |
5737029, | Nov 11 1994 | Sony Corporation | Image reception controller and method with ordered display of previously viewed channels |
5745375, | Sep 29 1995 | Intel Corporation | Apparatus and method for controlling power usage |
5751373, | Mar 31 1995 | Sony Corporation | Television function selection method, television receiver and remote commander for television receiver |
5754436, | Dec 22 1994 | Texas Instruments Incorporated | Adaptive power management processes, circuits and systems |
5754837, | Dec 22 1994 | Texas Instruments Incorporated | Clock control circuits, systems and methods |
5774591, | Dec 15 1995 | University of Maryland | Apparatus and method for recognizing facial expressions and facial gestures in a sequence of images |
5774704, | Jul 30 1996 | Hewlett Packard Enterprise Development LP | Apparatus and method for dynamic central processing unit clock adjustment |
5778237, | Jan 10 1995 | ADVANCED PROCESSOR TECHNOLOGIES, LLC | Data processor and single-chip microcomputer with changing clock frequency and operating voltage |
5781247, | Apr 05 1995 | Thomson Consumer Electronics, Inc | Customizable menu for a television receiver accessed via a remote control keyboard |
5781780, | Dec 22 1994 | Texas Instruments Incorporated | Power management supply interface circuitry, systems and methods |
5781783, | Jun 28 1996 | Intel Corporation | Method and apparatus for dynamically adjusting the power consumption of a circuit block within an integrated circuit |
5784628, | Mar 12 1996 | Microsoft Technology Licensing, LLC | Method and system for controlling power consumption in a computer system |
5784630, | Sep 07 1990 | Hitachi, Ltd. | Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory |
5790877, | Jul 06 1995 | Hitachi, Ltd. | Method for controlling a processor for power-saving in a computer for executing a program, compiler medium and processor system |
5793980, | Nov 30 1994 | Intel Corporation | Audio-on-demand communication system |
5798667, | May 16 1994 | TAIWAN SEMICONDUCTOR MANUFACTURING CO , LTD | Method and apparatus for regulation of power dissipation |
5808690, | Jun 10 1996 | Rambus Inc | Image generation system, methods and computer program products using distributed processing |
5812860, | Feb 12 1996 | Intel Corporation | Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption |
5828370, | Jul 01 1996 | OPEN TV, INC ; OPENTV, INC | Video delivery system and method for displaying indexing slider bar on the subscriber video screen |
5828895, | Sep 20 1995 | International Business Machines Corporation | Methods and system for predecoding instructions in a superscalar data processing system |
5832284, | Dec 23 1996 | CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD | Self regulating temperature/performance/voltage scheme for micros (X86) |
5838578, | Sep 21 1993 | Intel Corporation | Method and apparatus for programmable thermal sensor for an integrated circuit |
5845132, | Dec 22 1994 | Texas Instruments Incorporated | Computer system power management interconnection circuitry, system and methods |
5850218, | Feb 19 1997 | Time Warner Cable Enterprises LLC | Inter-active program guide with default selection control |
5850470, | Aug 30 1995 | Siemens Corporation | Neural network for locating and recognizing a deformable object |
5852737, | Apr 24 1995 | National Semiconductor Corporation | Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down |
5873000, | Jul 19 1996 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | System incorporating hot docking and undocking capabilities without requiring a standby or suspend mode by placing local arbiters of system and base into idle state |
5881245, | Sep 10 1996 | DIGITAL VIDEO SYSTEMS, INC | Method and apparatus for transmitting MPEG data at an adaptive data rate |
5881298, | Sep 05 1996 | Round Rock Research, LLC | Portable computer with selectively operable cooling unit |
5884049, | Dec 31 1996 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Increased processor performance comparable to a desktop computer from a docked portable computer |
5886690, | Oct 31 1996 | Uniden America Corporation | Program schedule user interface |
5887179, | Jun 11 1996 | Apple Inc | System power saving means and method |
5898849, | Apr 04 1997 | Advanced Micro Devices, Inc. | Microprocessor employing local caches for functional units to store memory operands used by the functional units |
5920572, | Jun 30 1995 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Transport stream decoder/demultiplexer for hierarchically organized audio-video streams |
5923755, | Dec 03 1993 | Cisco Technology, Inc | Multi-service data receiver architecture |
5925133, | Oct 19 1994 | GLOBALFOUNDRIES Inc | Integrated processor system adapted for portable personal information devices |
5930444, | Apr 23 1992 | DRAGON INTELLECTUAL PROPERTY, LLC | Simultaneous recording and playback apparatus |
5940785, | Apr 29 1996 | GLOBALFOUNDRIES Inc | Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit |
5958055, | Sep 20 1996 | VLSI Technology, Inc. | Power management system for a computer |
5958058, | Jul 18 1997 | Round Rock Research, LLC | User-selectable power management interface with application threshold warnings |
5968167, | Apr 03 1997 | Imagination Technologies Limited | Multi-threaded data processing management system |
5973704, | Oct 09 1995 | Nintendo Co., Ltd. | Three-dimensional image processing apparatus |
5974557, | Jun 20 1994 | Method and system for performing thermal and power management for a computer | |
5978864, | Jun 25 1997 | Oracle America, Inc | Method for thermal overload detection and prevention for an intergrated circuit processor |
5978923, | Aug 07 1997 | Toshiba America Information Systems, Inc. | Method and apparatus for a computer power management function including selective sleep states |
5987244, | Dec 22 1994 | Intel Corporation | Power management masked clock circuitry, systems and methods |
5996083, | Aug 11 1995 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Microprocessor having software controllable power consumption |
6014611, | May 30 1995 | Kabushiki Kaisha Toshiba | Cooling mode switching system for CPU |
6020912, | Jul 11 1995 | Koninklijke Philips Electronics N V | Video-on-demand system |
6026186, | Nov 17 1997 | Xerox Corporation | Line and curve detection using local information |
6047248, | Apr 29 1996 | GLOBALFOUNDRIES Inc | Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit |
6073244, | Dec 24 1997 | Mitsubishi Denki Kabushiki Kaisha | Power-saving clock control apparatus and method |
6076171, | Mar 28 1997 | Mitsubishi Denki Kabushiki Kaisha | Information processing apparatus with CPU-load-based clock frequency |
6105127, | Aug 27 1996 | Matsushita Electric Industrial Co., Ltd. | Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream |
6105142, | Feb 11 1997 | TUMBLEWEED HOLDINGS LLC | Intelligent power management interface for computer system hardware |
6108033, | May 31 1996 | Hitachi Denshi Kabushiki Kaisha | Method and system monitoring video image by updating template image |
6111517, | Dec 30 1996 | ROCKEFELLER UNIVERSITY, THE | Continuous video monitoring using face recognition for access control |
6111584, | Dec 18 1995 | RPX Corporation | Rendering system with mini-patch retrieval from local texture storage |
6119241, | Dec 23 1996 | MARVELL INTERNATIONAL LTD | Self regulating temperature/performance/voltage scheme for micros (X86) |
6122676, | Jan 07 1998 | National Semiconductor Corporation | Apparatus and method for transmitting and receiving data into and out of a universal serial bus device |
6128653, | Jan 30 1997 | Microsoft Technology Licensing, LLC | Method and apparatus for communication media commands and media data using the HTTP protocol |
6128745, | May 28 1998 | KINGLITE HOLDINGS INC | Power management inactivity monitoring using software threads |
6141003, | Mar 18 1997 | Rovi Technologies Corporation | Channel bar user interface for an entertainment system |
6141762, | Aug 03 1998 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Power reduction in a multiprocessor digital signal processor based on processor load |
6147714, | Jul 21 1995 | Sony Corporation | Control apparatus and control method for displaying electronic program guide |
6151059, | Aug 06 1996 | Rovi Guides, Inc | Electronic program guide with interactive areas |
6151681, | Jun 25 1997 | Texas Instruments Incorporated | Dynamic device power management |
6184877, | Dec 11 1996 | TIVO SOLUTIONS INC | System and method for interactively accessing program information on a television |
6185314, | Jun 19 1997 | FLIR COMMERCIAL SYSTEMS, INC | System and method for matching image information to object model information |
6185641, | May 01 1997 | Microchip Technology Incorporated | Dynamically allocating space in RAM shared between multiple USB endpoints and USB host |
6191773, | Apr 28 1995 | Panasonic Intellectual Property Corporation of America | Interface apparatus |
6195753, | Jun 09 1997 | Renesas Electronics Corporation | Information processing apparatus with reduced power consumption |
6208361, | Jun 15 1998 | Hewlett Packard Enterprise Development LP | Method and system for efficient context switching in a computer graphics system |
6219723, | Jun 25 1997 | Sun Microsystems, Inc. | Method and apparatus for moderating current demand in an integrated circuit processor |
6226447, | Sep 11 1995 | Panasonic Corporation | Video signal recording and reproducing apparatus |
6233389, | Jul 30 1998 | TIVO SOLUTIONS INC | Multimedia time warping system |
6239810, | Dec 12 1997 | RPX Corporation | High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing |
6252598, | Jul 03 1997 | WSOU Investments, LLC | Video hand image computer interface |
6252878, | Oct 30 1997 | ITT Manufacturing Enterprises, Inc | Switched architecture access server |
6256743, | Mar 31 1992 | SAMSUNG ELECTRONICS CO , LTD | Selective power-down for high performance CPU/system |
6266715, | Jun 01 1998 | Advanced Micro Devices, INC | Universal serial bus controller with a direct memory access mode |
6275782, | May 05 1998 | GLOBALFOUNDRIES Inc | Non-intrusive performance monitoring |
6295321, | Dec 29 1997 | LG Electronics Inc. | Video decoding method, video decoder and digital TV system using the video decoding method and video decoder |
6311287, | Oct 11 1994 | Hewlett Packard Enterprise Development LP | Variable frequency clock control for microprocessor-based computer systems |
6323911, | Oct 02 1995 | Rovi Guides, Inc | System and method for using television schedule information |
6327418, | Apr 03 1998 | TIVO SOLUTIONS INC | Method and apparatus implementing random access and time-based functions on a continuous stream of formatted digital data |
6345362, | Apr 06 1999 | GLOBALFOUNDRIES Inc | Managing Vt for reduced power using a status table |
6353628, | Dec 15 1998 | RPX CLEARINGHOUSE LLC | Apparatus, method and system having reduced power consumption in a multi-carrier wireline environment |
6363490, | Mar 30 1999 | Intel Corporation | Method and apparatus for monitoring the temperature of a processor |
6397000, | Sep 09 1997 | MAXELL, LTD | Digital signal recording devices, digital signal recording/ playback devices, and digital signal receiving/recording/playback devices |
6407595, | Apr 04 2000 | Silicon Integrated Systems Corp | Digital clock throttling means |
6421463, | Apr 01 1998 | Massachusetts Institute of Technology | Trainable system to search for objects in images |
6425086, | Apr 30 1999 | Intel Corp | Method and apparatus for dynamic power control of a low power processor |
6442700, | Aug 10 1999 | Intel Corporation | Thermal control within systems having multiple CPU performance states |
6470290, | Aug 31 1999 | ANPA INC | Device having an improved apparatus and method for setting power management mode |
6490000, | Dec 24 1997 | DISH TECHNOLOGIES L L C | Method and apparatus for time shifting and controlling broadcast audio and video signals |
6510400, | Mar 31 1999 | NEC PERSONAL COMPUTERS, LTD | Temperature control circuit for central processing unit |
6513124, | May 20 1998 | International Business Machines Corporation | Method and apparatus for controlling operating speed of processor in computer |
6535798, | Dec 03 1998 | Intel Corporation | Thermal management in a system |
6535905, | Apr 29 1999 | Intel Corporation | Method and apparatus for thread switching within a multithreaded processor |
6542621, | Aug 31 1998 | Texas Instruments Incorporated | Method of dealing with occlusion when tracking multiple objects and people in video sequences |
6545683, | Apr 19 1999 | Microsoft Technology Licensing, LLC | Apparatus and method for increasing the bandwidth to a graphics subsystem |
6564328, | Dec 23 1999 | Intel Corporation | Microprocessor with digital power throttle |
6564329, | Mar 16 1999 | HANGER SOLUTIONS, LLC | System and method for dynamic clock generation |
6573900, | Dec 06 1999 | Nvidia Corporation | Method, apparatus and article of manufacture for a sequencer in a transform/lighting module capable of processing multiple independent execution threads |
6591058, | Dec 23 1997 | Intel Corporation | Time shifting by concurrently recording and playing a data stream |
6608476, | Sep 26 2000 | Oracle America, Inc | Method and apparatus for reducing power consumption |
6630935, | Apr 21 2000 | ADVANCED SILICON TECHNOLOGIES, LLC | Geometric engine including a computational module for use in a video graphics controller |
6636635, | Nov 01 1995 | Canon Kabushiki Kaisha | Object extraction method, and image sensing apparatus using the method |
6636976, | Jun 30 2000 | Intel Corporation | Mechanism to control di/dt for a microprocessor |
6639998, | Jan 11 1999 | LG Electronics Inc. | Method of detecting a specific object in an image signal |
6647502, | Jul 13 1999 | Sony Corporation | Method and apparatus for providing power based on the amount of data stored in buffers |
6650327, | Jun 16 1998 | RPX Corporation | Display system having floating point rasterization and floating point framebuffering |
6711447, | Jan 22 2003 | UNM Rainforest Innovations | Modulating CPU frequency and voltage in a multi-core CPU architecture |
6717599, | Jun 29 2000 | Microsoft Technology Licensing, LLC | Method, system, and computer program product for implementing derivative operators with graphics hardware |
6724825, | Sep 22 2000 | Google Technology Holdings LLC | Regeneration of program clock reference data for MPEG transport streams |
6724915, | Mar 13 1998 | Siemens Aktiengesellschaft | Method for tracking a video object in a time-ordered sequence of image frames |
6728862, | May 22 2000 | LIBERTY PATENTS LLC | Processor array and parallel data processing methods |
6731289, | May 12 2000 | Microsoft Technology Licensing, LLC | Extended range pixel display system and method |
6762797, | Apr 14 1999 | Koninklijke Philips Electronics N V | Method and apparatus for catch-up video viewing |
6784879, | Jul 14 1997 | ATI Technologies ULC | Method and apparatus for providing control of background video |
6788710, | Mar 19 1998 | Thomson Licensing S.A. | Auxiliary data insertion in a transport datastream |
6789037, | Mar 30 1999 | Sony Corporation of America | Methods and apparatus for thermal management of an integrated circuit die |
6804632, | Dec 06 2001 | Intel Corporation | Distribution of processing activity across processing hardware based on power consumption considerations |
6825843, | Jul 18 2002 | Nvidia Corporation | Method and apparatus for loop and branch instructions in a programmable graphics pipeline |
6829713, | Dec 30 2000 | Intel Corporation | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
6845456, | May 01 2001 | AMD TECHNOLOGIES HOLDINGS, INC ; GLOBALFOUNDRIES Inc | CPU utilization measurement techniques for use in power management |
6859882, | Jun 01 1990 | Huron IP LLC | System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment |
6889332, | Dec 11 2001 | Advanced Micro Devices, Inc. | Variable maximum die temperature based on performance state |
6897871, | Nov 20 2003 | ATI Technologies ULC | Graphics processing architecture employing a unified shader |
6901522, | Jun 07 2001 | Intel Corporation | System and method for reducing power consumption in multiprocessor system |
6922783, | Jan 16 2002 | HEWLETT-PACKARD DEVELOPMENT COMPANY L P | Method and apparatus for conserving power on a multiprocessor integrated circuit |
6928559, | Jun 27 1997 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Battery powered device with dynamic power and performance management |
6952520, | Sep 06 1999 | RPX Corporation | Picture recorder/reproducer and method thereof |
6954204, | Jul 18 2002 | Nvidia Corporation | Programmable graphics system and method using flexible, high-precision data formats |
6976182, | Feb 01 2002 | ADVANCED SILICON TECHNOLOGIES, LLC | Apparatus and method for decreasing power consumption in an integrated circuit |
6978389, | Dec 20 2001 | Texas Instruments Incorporated | Variable clocking in an embedded symmetric multiprocessor system |
7015913, | Jun 27 2003 | Nvidia Corporation | Method and apparatus for multithreaded processing of data in a programmable graphics processor |
7024100, | Mar 26 1999 | Panasonic Intellectual Property Corporation of America | Video storage and retrieval apparatus |
7028196, | Dec 13 2002 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | System, method and apparatus for conserving power consumed by a system having a processor integrated circuit |
7038685, | Jun 30 2003 | Nvidia Corporation | Programmable graphics processor for multithreaded execution of programs |
7039755, | May 31 2000 | MEDIATEK INC | Method and apparatus for powering down the CPU/memory controller complex while preserving the self refresh state of memory in the system |
7051306, | May 07 2003 | Mosaid Technologies Incorporated | Managing power on integrated circuits using power islands |
7081895, | Jul 18 2002 | Nvidia Corporation | Systems and methods of multi-pass data processing |
7085945, | Jan 24 2003 | Intel Corporation | Using multiple thermal points to enable component level power and thermal management |
7095945, | Nov 06 2000 | ATI Technologies ULC | System for digital time shifting and method thereof |
7100056, | Aug 12 2002 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | System and method for managing processor voltage in a multi-processor computer system for optimized performance |
7100060, | Jun 26 2002 | Intel Corporation | Techniques for utilization of asymmetric secondary processing resources |
7100061, | Jan 18 2000 | SEMCON IP INC | Adaptive power control |
7134031, | Aug 04 2003 | ARM Limited | Performance control within a multi-processor system |
7144152, | Aug 23 2002 | Sony Corporation of America | Apparatus for thermal management of multiple core microprocessors |
7174194, | Oct 24 2000 | Texas Instruments Incorporated | Temperature field controlled scheduling for processing systems |
7174467, | Jul 18 2001 | Advanced Micro Devices, INC | Message based power management in a multi-processor system |
7197229, | Sep 09 1997 | MAXELL, LTD | Digital signal recording devices, digital signal recording/playback devices, and digital signal receiving/recording/playback devices |
7206966, | Oct 22 2003 | Hewlett-Packard Development Company, L.P.; HEWELTT-PACKARD DEVELOPMENT COMPANY, L P | Fault-tolerant multi-core microprocessing |
7216064, | Sep 21 1993 | Intel Corporation | Method and apparatus for programmable thermal sensor for an integrated circuit |
7233335, | Apr 21 2003 | NIVIDIA Corporation | System and method for reserving and managing memory spaces in a memory resource |
7249268, | Jun 29 2004 | Intel Corporation | Method for performing performance optimization operations for a processor having a plurality of processor cores in response to a stall condition |
7272298, | May 06 1998 | TIVO INC | System and method for time-shifted program viewing |
7313706, | Sep 17 2002 | Mosaid Technologies Incorporated | System and method for managing power consumption for a plurality of processors based on a supply voltage to each processor, temperature, total power consumption and individual processor power consumption |
7321369, | Aug 30 2002 | Intel Corporation | Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device |
7327369, | Nov 20 2003 | ATI Technologies ULC | Graphics processing architecture employing a unified shader |
7363472, | Apr 07 2000 | Rambus Inc | Memory access consolidation for SIMD processing elements having access indicators |
7366407, | Dec 16 1999 | Sharp Kabushiki Kaisha | Method and apparatus for storing MPEG-2 transport streams using a conventional digital video recorder |
7376848, | Jun 26 1997 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Battery powered device with dynamic power and performance management |
7428645, | Dec 29 2003 | CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD | Methods and apparatus to selectively power functional units |
7437581, | Sep 28 2004 | Meta Platforms, Inc | Method and apparatus for varying energy per instruction according to the amount of available parallelism |
7475175, | Mar 17 2003 | Hewlett-Packard Development Company, LP | Multi-processor module |
7502948, | Dec 30 2004 | Intel Corporation | Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores |
7516334, | Mar 22 2001 | SONY NETWORK ENTERTAINMENT PLATFORM INC ; Sony Computer Entertainment Inc | Power management for processing modules |
7529465, | Jul 30 1998 | TIVO SOLUTIONS INC | System for time shifting multimedia content streams |
7587262, | Sep 21 1993 | Intel Corporation | Temperature averaging thermal sensor apparatus and method |
7636863, | Jan 13 2004 | LG Electronics Inc. | Apparatus for controlling power of processor having a plurality of cores and control method of the same |
7664971, | Jun 10 2005 | LG Electronics Inc | Controlling power supply in a multi-core processor |
7673304, | Feb 18 2003 | Microsoft Technology Licensing, LLC | Multithreaded kernel for graphics processing unit |
7742053, | Sep 29 2003 | ATI Technologies ULC | Multi-thread graphics processing system |
7966511, | Jul 27 2004 | TAHOE RESEARCH, LTD | Power management coordination in multi-core processors |
8285109, | Sep 11 1995 | Panasonic Corporation | Video signal recording and reproducing apparatus |
8463110, | Dec 23 1997 | Intel Corporation | Storage of video stream multiplexed with random access playback after variable time delay |
20010003206, | |||
20020054146, | |||
20020112193, | |||
20030030326, | |||
20030110012, | |||
20030122429, | |||
20030188208, | |||
20030188212, | |||
20040003301, | |||
20040117678, | |||
20040260958, | |||
20050046400, | |||
CN1154629, | |||
EP594240, | |||
EP632360, | |||
EP737006, | |||
EP737007, | |||
EP762769, | |||
EP840504, | |||
EP1039750, | |||
JP200010673, | |||
JP5252439, | |||
JP6153017, | |||
JP6217271, | |||
JP7154626, | |||
JP7222027, | |||
JP7281666, | |||
JP8106421, | |||
JP8328698, | |||
JP8331415, | |||
JP9006947, | |||
JP9167260, | |||
KR100185947, | |||
KR100191731, | |||
KR100301826, | |||
RE36839, | Feb 14 1995 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | Method and apparatus for reducing power consumption in digital electronic circuits |
RE43184, | Jul 22 1997 | LG Electronics Inc. | Method of application menu selection and activation using image cognition |
RE47420, | Mar 02 2001 | Advanced Micro Devices, Inc. | Performance and power optimization via block oriented performance measurement and control |
WO9719560, | |||
WO9919805, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 06 2018 | Advanced Micro Devices, Inc. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Jul 06 2018 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Date | Maintenance Schedule |
Nov 16 2024 | 4 years fee payment window open |
May 16 2025 | 6 months grace period start (w surcharge) |
Nov 16 2025 | patent expiry (for year 4) |
Nov 16 2027 | 2 years to revive unintentionally abandoned end. (for year 4) |
Nov 16 2028 | 8 years fee payment window open |
May 16 2029 | 6 months grace period start (w surcharge) |
Nov 16 2029 | patent expiry (for year 8) |
Nov 16 2031 | 2 years to revive unintentionally abandoned end. (for year 8) |
Nov 16 2032 | 12 years fee payment window open |
May 16 2033 | 6 months grace period start (w surcharge) |
Nov 16 2033 | patent expiry (for year 12) |
Nov 16 2035 | 2 years to revive unintentionally abandoned end. (for year 12) |