A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
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0. 21. A semiconductor integrated circuit, comprising:
a branch line that extends along a first direction, a switch cell is wired directly to the branch line;
a first main line that extends along the first direction in parallel to the branch line, the switch cell is wired directly to the first main line;
a second main line that extends along a second direction so as to cross the branch line and the first main line, the first main line is wired directly to the second main line; and
an auxiliary interconnect that extends along the second direction in parallel to the second main line, the branch line is wired directly to the auxiliary interconnect,
wherein the switch cell configured to receive a signal that controls the switch cell to:
electrically connect, when the branch line is electrically disconnected from the first main line, the first main line to the branch line, and
electrically disconnect, when the first main line is electrically connected to the branch line, the branch line from the first main line.
0. 1. A semiconductor integrated circuit, comprising:
a plurality of circuit cells;
a plurality of sub wiring lines disposed in a first direction and individually shared by predetermined ones of the plural circuit cells, a plurality of the predetermined ones of the plural circuit cells being juxtaposed in the first direction;
a plurality of power supply switch cells for controlling connection and disconnection between individual sub wiring lines and said main wiring line in response to a control signal inputted thereto; and
an auxiliary wiring line for connecting the plural sub wiring lines to each other, the auxiliary wiring line extending in a second direction that is perpendicular to the first direction,
wherein the predetermined ones of the plural circuit cells include a first circuit cell that is located at a left side of one of the sub wiring lines and a second circuit cell that is located at a right side of said one of the sub wiring lines.
0. 2. A semiconductor integrated circuit as set forth in
0. 3. A semiconductor integrated circuit as set forth in
0. 4. A semiconductor integrated circuit as set forth in
0. 5. A semiconductor integrated circuit as set forth in
0. 6. A semiconductor integrated circuit as set forth in
0. 7. A semiconductor integrated circuit as set forth in
0. 8. A semiconductor integrated circuit as set forth in
a contact directly electrically connecting said main line to one of the branch lines, said one of the branch lines being directly electrically connected to said one of the power supply switch cells.
0. 9. A semiconductor integrated circuit as set forth in
0. 10. A semiconductor integrated circuit as set forth in
an auxiliary line directly electrically connected to a second one of the branch lines, said auxiliary line extending along said first direction.
0. 11. A semiconductor integrated circuit as set forth in
0. 12. A semiconductor integrated circuit as set forth in
0. 13. A semiconductor integrated circuit as set forth in
a circuit cell directly electrically connected said one of the branch lines and another of the branch lines, said auxiliary wiring line being between said main line and said circuit cell.
0. 14. A semiconductor integrated circuit as set forth in
0. 15. A semiconductor integrated circuit as set forth in
0. 16. A semiconductor integrated circuit as set forth in
0. 17. A semiconductor integrated circuit as set forth in
a third one of the power supply switch cells directly electrically connected to said control line, said third one of the power supply switch cells being controllable to provide electrical connection and disconnection between said main line and another of the branch lines.
0. 18. A semiconductor integrated circuit as set forth in
0. 19. A semiconductor integrated circuit as set forth in
a different control line extending along said first direction, a different one of the power supply switch cells being directly electrically connected to said different control line.
0. 20. A semiconductor integrated circuit comprising:
an interconnect layer of the semiconductor integrated circuit between a substrate region of the semiconductor integrated circuit and an upper layer of the semiconductor integrated circuit;
a main line in said upper layer, said main line extending along a first direction;
branch lines in said interconnect layer, said branch lines extending along a second direction;
a row of power supply switch cells in said substrate region, said row of the power supply switch cells extending along said first direction;
a control line extending along said first direction, one of the power supply switch cells and a second one of the power supply switch cells being directly electrically connected to said control line.
0. 22. A semiconductor integrated circuit as set forth in claim 21, wherein the auxiliary interconnect crosses the first main line and the branch line.
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This application is a Continuation Reissue application of application Ser. No. 15/583,125, filed May 1, 2017, which is a Reissue application of application Ser. No. 14/224,910, filed Mar. 25, 2014, now U.S. Pat. No. 9,024,662, issued on May 5, 2015, which is a Continuation of application Ser. No. 13/551,353, filed on Jul. 17, 2012, now U.S. Pat. No. 8,742,793, issued on Jun. 3, 2014, which is a Continuation of application Ser. No. 13/064,731, filed Apr. 12, 2011, now U.S. Pat. No. 8,299,818, issued on Oct. 30, 2012, which is a Continuation of application Ser. No. 12/656,219, filed Jan. 21, 2010, now U.S. Pat. No. 7,944,243, issued on May 17, 2011, which is a Continuation of application Ser. No. 12/285,375, filed Oct. 2, 2008, now U.S. Pat. No. 7,750,681, issued on Jul. 6, 2010, which claims priority from Japanese Application Number 2007-289250, filed on Nov. 7, 2007, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a power supply switch cell that controls supplying of supply voltage or reference voltage to a circuit cell and blocking of the voltage supplying.
2. Description of Related Art
To control supplying of supply voltage or reference voltage to a circuit cell and blocking of the voltage supplying is known as, for example, a circuit technique called multi-threshold complementary metal oxide semiconductor (MTCMOS). In the MTCMOS, for example, for each circuit block having a specific function, a power supply switch transistor with threshold voltage higher than that of a transistor in a functional circuit is connected to the path of the supplying of the supply voltage or the reference voltage (e.g. GND voltage). When the circuit block enters the unused state, the power supply switch transistor is set to the off-state, so that the leakage current that flows through the respective transistors in the circuit block is blocked. This can significantly reduce the leakage current that flows through the circuit block in the unused state.
For the purpose of eliminating a troublesome task of arranging power supply switch transistors based on man-power in design of a semiconductor integrated circuit including a circuit block to which the MTCMOS technique is applied, the inventors of the present application have already proposed a semiconductor integrated circuit in which power supply switch transistors are included as cells and the power supply switch cells are properly disposed in the area in which circuit cells are arranged (refer to Japanese Patent Laid-open No. 2005-259879 (hereinafter referred to as Patent Document1)).
There is a need for the present invention to add improvement to the semiconductor integrated circuit with the structure in which the power supply switch cells are disposed as proposed in Patent Document 1 so that power supply noise can be further suppressed.
According to an embodiment of the present invention, there is provided a semiconductor integrated circuit including a main-interconnect to which supply voltage or reference voltage is applied, a plurality of sub-interconnects, a plurality of circuit cells configured to be connected to the plurality of sub-interconnects, and a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects. The semiconductor integrated circuit further includes an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
In the embodiment of the present invention, it is preferable that a plurality of the power supply switch cells be disposed on a line along a direction in parallel to or perpendicular to the direction along which the main-interconnect is disposed and be connected to a plurality of control lines in accordance with a predetermined connection rule.
In the above-described configuration, before the power supply switch cell is turned on, equalization of the amount of accumulated charges among the plurality of sub-interconnects connected to the plurality of circuit cells is carried out via the auxiliary interconnect. Thus, compared with the case of providing no auxiliary interconnect, the peak of power supply noise arising in the main-interconnect when the power supply switch is turned on first is sufficiently suppressed.
The embodiment of the present invention offers an advantage that power supply noise can be suppressed effectively and sufficiently in a semiconductor integrated circuit in which power supply switch transistors are included as cells and the power supply switch cells are properly disposed in the area in which circuit cells are arranged. Furthermore, the embodiment of the present invention offers advantages of reduction in leakage, reduction in the area of the power supply switch cell, and shortening of the design period in defining of the switch cells that should be turned on.
An embodiment of the present invention will be described below with reference to the accompanying drawings.
<Entire Configuration>
The semiconductor integrated circuit shown in
The pairs of power supply lines PL1 extend along the column direction, and are disposed in parallel to each other with the intermediary of a predetermined distance therebetween along the row direction.
The pairs of power supply lines PL2 extend along the row direction perpendicular to the pairs of power supply lines PL1, and are disposed in parallel to each other with the intermediary of a predetermined distance therebetween along the column direction.
In
In each of the pairs of power supply lines PL1 and PL2, one supply voltage main line VDD and one reference voltage main line VSS are disposed in parallel to each other so as to form one pair. At the intersections in this lattice power supply line pattern, the supply voltage main lines VDD are connected to each other via a contact and the reference voltage main lines VSS are connected to each other via a contact.
In the lattice power supply line pattern, the power supply input cells 41 and 42 are connected to each of the pairs of power supply lines PL1 and PL2 on four outer frames of the power supply line pattern. The reference voltage main line VSS is connected to the power supply input cell 41, and the supply voltage main line VDD is connected to the power supply input cell 42.
Reference voltage Vss is supplied from the external of the semiconductor integrated circuit via the power supply input cell 41. Supply voltage Vdd is supplied from the external of the semiconductor integrated circuit via the power supply input cell 42.
The branch line groups BL1 and BL2 arise from branching from the pair of power supply lines PL1 as the “main-interconnect”, and provide power to the circuit cells 10 as the basic unit of the circuit in the semiconductor integrated circuit.
Each of the branch line groups BL1 and BL2 is so formed as to extend along the row direction from the pair of power supply lines PL1 as the “main-interconnect” extending along the column direction.
A plurality of such branch line groups arise from one pair of power supply lines PL1, and the plural circuit cells 10 are connected to each branch line group.
The circuit cell 10 included in the semiconductor integrated circuit receives power supplying from two branch lines connected to this circuit cell 10, i.e., from the branch line to which the supply voltage Vdd is applied and the branch line to which the reference voltage Vss is applied.
On the other hand, a circuit for which blocking of the power supply line is unnecessary, such as a continuous operating circuit, receives power supplying not via a branch line group but directly from a pair of power supply lines, like, for example, the circuit block 30 shown in
The branch line group BL1 includes a supply voltage branch line VDDA and a reference voltage branch line VSSA as the above-described two branch lines for power supplying to the circuit cells 10. The supply voltage branch line VDDA is connected to the supply voltage main line VDD, and the reference voltage branch line VSSA is connected to the reference voltage main line VSS.
The branch line group BL2 includes a supply voltage branch line VDDB and a reference voltage branch line VSSB as the above-described two branch lines. The supply voltage branch line VDDB is connected to the supply voltage main line VDD, and the reference voltage branch line VSSB is connected to the reference voltage main line VSS.
The difference between the branch line groups BL1 and BL2 is the presence and absence of provision of the power supply switch cell 20. Specifically, the power supply switch cell 20 is provided between the branch line group BL2 and the pair of power supply lines PL1, while the power supply switch cell 20 is not provided between the branch line group BL1 and the pair of power supply lines PL1. Of the branch line groups BL1 and BL2, the branch line group BL2 is equivalent to one example of the “sub-interconnect” because the connection of the branch line group BL2 to the pair of power supply lines PL1 is controlled by the power supply switch cell 20.
A control signal (not shown) is input to the power supply switch cell 20. In response to this signal input, the power supply switch cell 20 can block at least one of the supply voltage and the reference voltage between the pair of power supply lines PL1 and the branch line group BL2. For example, the power supply switch cell 20 includes a power supply switch transistor, and turns off the power supply switch transistor in accordance with the logic level of the input control signal to thereby block the power supply current path to the circuit cell 10 connected to the branch line group BL2.
In the case of a semiconductor integrated circuit of the MTCMOS type, a MOS transistor with threshold voltage higher than that of a transistor of the same conductivity type in the circuit cell 10 is used as the power supply switch transistor. For example, in the case of electrically disconnecting the reference voltage branch line VSSB from the reference voltage main line VSS in accordance with the control signal, an n-type MOS transistor having high threshold voltage is used as the power supply switch transistor. In the case of electrically disconnecting the supply voltage branch line VDDB from the supply voltage main line VDD in accordance with the control signal, a p-type MOS transistor having high threshold voltage is used as the power supply switch transistor.
In
For a rectangular semiconductor chip in which the semiconductor integrated circuit is formed, plural IO cells 40 arranged on a line are disposed on the peripheral part of the semiconductor chip along four sides thereof. In the area surrounded by these IO cells 40, the above-described lattice power supply line pattern is formed.
Referring to
The ranges of the areas A1 and A2 shown in
<Connection Structure of Control Lines>
In
As shown in
As shown in
A buffer circuit BUF is provided in a proper intermediate position of each of the first control line CL1 and the second control line CL2. The provision of the buffer circuit BUF is to rectify a control signal attenuated in the middle of its transmission into a waveform having the amplitude between the supply voltage Vdd and the reference voltage Vss. The buffer circuit BUF is disposed at least in the IO cells 40 of
Although the above-described example is a connection example of two control lines, three or more control lines may be provided.
In any case, the control lines are connected to the control nodes (the gates of the power supply switch transistors) of the respective power supply switch cells 20 arranged on a line, in accordance with a predetermined connection rule. Although the predetermined connection rule in the above-described example is that “the power supply switch cells 20 are connected at a ratio of one to three”, any rule may be optionally employed.
The reason why the plural power supply switch cells 20 are controlled by the plural control lines is as follows.
In the MTCMOS technique, as the way of the provision of the power supply switch transistor (the power supply switch cell 20), the following three ways are available: it is provided between the supply voltage branch line VDDB and the supply voltage main line VDD connected to the circuit cell 10 whose activation and stop are repeated; it is provided between the reference voltage branch line VSSB and the supply voltage main line VDD connected to this circuit cell 10; and it is provided at both of these positions. In the present embodiment, the former two ways can be employed. Moreover, because the drive capability of an n-type MOS transistor is higher than that of a p-type MOS transistor, it is desirable that the power supply switch cell 20 be provided between the reference voltage branch line VSSB and the supply voltage main line VDD connected to the circuit cell 10. In the following, the description will be continued on the premise of this desirable case.
In the area A1 (see
In contrast, if plural control lines are provided as shown in
The position at which the row of the power supply switch cells 20 is provided may be overlapped with the pair of power supply lines PL1 as shown in
Various forms are available regarding the multilevel use form, connection, and interconnect pattern of the multilayer interconnect in the overlapping part between the power supply switch cells 20 and the pair of power supply lines PL1. Regarding these points, various forms described in the previous application (Japanese Patent Laid-open No. 2005-259879) by the inventors of the present application can be employed.
In
FIG. 3B1 shows the case in which each of the supply voltage branch line VDDB and the reference voltage branch line VSSB is shared by two circuit cells 10 adjacent to each other along the column direction like three circuit cells given numeral “10” in
In
If the circuit cell group shown in
On the assumption that the circuit to be formed is the same and the input/output node is positioned at the center of the cell height (along the column direction, i.e. the vertical direction of
FIG. 3B2 shows the interconnect structure called the “three-line system” in the above-mentioned previous application (Japanese Patent Laid-open No. 2005-259879). In the three-line system, for example, three reference voltage branch lines VSSB are disposed in proximity to each other, while one supply voltage branch line VDDB is disposed in an isolated manner.
A reference voltage branch line VSSB(0) as the center line of three adjacent branch lines is shared by two cells adjacent to each other, and the supply voltage branch line VDDB is also shared by two cells adjacent to each other. Thus, for one cell, for example, a circuit cell 10A (10B), the three-line system based on the following three lines is formed: an interconnect segment having the width half of the width of the reference voltage branch line VSSB(0), an interconnect segment having the width half of the width of the supply voltage branch line VDDB, and another reference voltage branch line VSSB(A) (or VSSB(B)) between these interconnect segments.
The purpose of forming the branch line group based on three adjacent reference voltage branch lines VSSB is to allow the circuit cell for which power supply is always necessary (in
In the circuit cell 10A shown in
On the assumption that the circuit to be formed is the same and the input/output node is positioned at the center of the cell height (along the column direction, i.e. the vertical direction of
Even when the reference voltage branch lines VSSB look as one line or two lines as the planar pattern, the interconnect structure is encompassed in the category of the “three-line system” if the reference voltage branch lines VSSB having the function as three lines as described above are formed in the multilayer interconnect structure.
Either the “two-line system” of FIG. 3B1 or the “three-line system” of FIG. 3B2 may be employed optionally. Furthermore, interconnect structures of the different systems may be mounted on different areas of the same semiconductor integrated circuit in a mixed manner.
As specific forms regarding the multilevel use form, connection, and interconnect pattern of the multilayer interconnect in the “two-line system” and the “three-line system”, various forms described in the previous application (Japanese Patent Laid-open No. 2005-259879) by the inventors of the present application can be employed.
The following advantages are achieved by the above-described structure in which the interconnect for supplying the supply voltage Vdd or the reference voltage Vss is composed of the main-interconnect (the supply voltage main line VDD or the reference voltage main line VSS) and the sub-interconnect (the supply voltage branch line VDDB or the reference voltage branch line VSSB) and the power supply switch cell 20 is provided between the necessary main-interconnect and sub-interconnect.
Specifically, it is possible to widely disperse the power supply switch cells 20 in the area in which the circuit cell 10 can be disposed and finely carry out blocking of power supplying by the power supply switch cell 20 for each circuit cell group including a comparatively-small number of circuit cells.
Thus, compared with a method of providing a power supply switch for each circuit block, the supply current that flows through the power supply switch cell 20 is reduced, and thus a supply voltage drop is decreased. This can alleviate the influence of the voltage drop arising in the power supply switch cell 20 on signal delay.
Furthermore, compared with a method of disposing a power supply switch outside a circuit block, the flexibility of the arrangement of the power supply switch cell 20 is enhanced, and thus the area A1, for which blocking of power supplying is carried out, can be flexibly defined. This makes it possible to easily realize automatic design of the layout including the power supply switch cell 20. In particular, in the “three-line system”, the area A1, for which blocking of power supplying is carried out, and the area A2, for which blocking of power supplying is not carried out, can be formed in one area in a mixed manner without being separated from each other.
This can reduce the burden of the design task, which is tackled based on manpower in a related art, and thus can shorten the development time.
If, of the plural power supply switch cells 20, different cell groups each including a predetermined number of power supply switch cells 20 are separately controlled by plural different control lines, the above-described advantage that the peak value of power supply noise can be suppressed is achieved.
In the present embodiment, in addition to the above-described configuration, an auxiliary interconnect 50 is provided as shown in
In
If the auxiliary interconnect 50 is not provided, when the potential of a certain reference voltage branch line VSSB is the highest, charges accumulated in the reference voltage branch line VSSB with this potential are discharged to the reference voltage main line VSS at a burst, and thus the peak of power supply noise arising in the reference voltage main line VSS becomes high.
In contrast, if the auxiliary interconnect 50 is provided, the amount of accumulated charges is equalized among the plural reference voltage branch lines VSSB before this discharging. Thus, providing the auxiliary interconnect 50 connecting the plural reference voltage branch lines VSSB to each other offers an effect to suppress the peak of power supply noise.
The suppression of the peak value of power supply noise can be achieved not only by providing the auxiliary interconnect 50 to thereby equalize the amount of accumulated charges before discharging but also by increasing the connection impedance at the time of power supply switching. That is, this is equivalent to a method of decreasing the size of the outlet of discharged charges.
In the case of controlling the power supply switch cells 20 by plural control lines, the connection impedance at the time of the first power supply switching, which determines the peak value of power supply noise, can be increased compared with the case of simultaneously turning on all of the power supply switch cells 20. Thus, the effect to suppress the power supply noise is achieved.
Employing both the auxiliary interconnect 50 and power supply switching by plural control lines offers the following advantages. Specifically, due to the power supply switching by plural control lines, the amount of charges discharged per unit time from the reference voltage branch line VSSB to the reference voltage main line VSS (the amount of charges that lead to power supply noise) decreases as described above, and thus the effect to suppress the peak of power supply noise is achieved as described above. In addition, due to the equalization of accumulated charges via the auxiliary interconnect 50 before power supply switching, the peak of the power supply noise can be further suppressed.
Consequently, if the auxiliary interconnect 50 is provided, power supply noise can be effectively suppressed attributed to both the provision of the auxiliary interconnect 50 and the power supply switching by plural control lines.
The above-described rule that determines the control of the power supply switch cells 20, such as the ratio of the number of power supply switch cells 20 that are switched on first to the number of power supply switch cells 20 that are switched on subsequently, is determined in consideration of the interconnect resistance, interconnect capacitance, and so on of the auxiliary interconnect 50.
Inversely, in matching with the number of switch transistors that are controlled at one time, the interconnect resistance of the auxiliary interconnect 50 and the layer level used for the auxiliary interconnect 50 may be so determined that the peak of power supply noise can be sufficiently suppressed. However, because the limit regarding the process is imposed on the interconnect resistance of the auxiliary interconnect 50 and the layer level used therefor, the former method, in which the number of power supply switch cells 20 that are switched on at one time is adjusted in matching with the specification of the auxiliary interconnect 50, is easier.
If the power supply switch cells 20 that are connected to the first control line CL1 and are switched on first are uniformly arranged with the intermediary of an equal distance therebetween as shown in
Furthermore, if the auxiliary interconnect 50 is provided, the following advantages are achieved due to the equalization of the current that starts to flow from the reference voltage branch line VSSB to the reference voltage main line VSS when the circuit cell 10 is returned from the state in which power supplying thereto is blocked: the transistor size can be decreased; the design is facilitated and thus the design period can be shortened; and leakage current can be reduced. Details of these advantages will be described below.
In the present example, the above-described reference voltage main line VSS (
On both the sides of the first reference voltage main line VSS1 along the width direction thereof, two reference voltage branch lines VSSB are disposed. The reference voltage branch lines VSSB are connected to each other via contacts CN1 and the auxiliary interconnect 50. These first reference voltage main line VSS1 and two reference voltage branch lines VSSB may be formed of an interconnect layer of the same layer level, such as a metal interconnect layer as the second layer.
The first reference voltage main line VSS1 is connected to the second reference voltage main line VSS2 of the upper layer via contacts CN2. In a substrate region below the interconnect layer level of the first reference voltage main line VSS1, power supply switch transistors SW1 and SW2 are formed. The power supply switch transistor SW1 is connected between one reference voltage branch line VSSB and the first reference voltage main line VSS1, and the power supply switch transistor SW2 is connected between the other reference voltage branch line VSSB and the first reference voltage main line VSS1.
The above-described configuration is repeated along the column direction.
In the configuration shown in
Another specific example is shown in
In this example, the reference voltage branch line VSSB and the supply voltage main line VDD are alternately disposed. This arrangement corresponds to the “two-line system” similar to that of FIG. 3B1. However, in
Furthermore, the power supply switch cell 20 including the power supply switch transistor SW1 of
In order to achieve the effect to suppress power supply noise similar to the above-described effect, the reference voltage branch lines VSSB are connected to each other by the auxiliary interconnect 50.
The circuit cells 10 are arranged at random as shown in
In the present embodiment, these disadvantages are eliminated because the auxiliary interconnect 50 is provided. Specifically, the movement of charges via the auxiliary interconnect 50 eliminates variation in the current among the reference voltage branch lines VSSB. Therefore, no matter which of the switches SW0 to SW3 is switched on, the equalized current will flow through the selected and turned-on switch.
Consequently, the provision of the auxiliary interconnect 50 facilitates the selection of the power supply switch cell 20. As a result, the power supply switch cells 20 can be formed by the switches SW0 to SW3 having the minimum necessary size. This results in achievement of an effect to reduce leakage current, an effect to decrease the area of the power supply switch cell 20, and an effect to shorten the design period.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alternations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalent thereof.
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