An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.
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0. 23. An integrated circuit, comprising:
an addressable memory;
a serial peripheral interface coupled to the memory, the serial peripheral interface including a plurality of pins; and
circuitry performing a first transfer of data bits on a first pin of the serial peripheral interface of a read operation addressed to the addressable memory responsive to a command received on a second pin of the serial peripheral interface, simultaneously with a second transfer of address bits of a write operation addressed to the addressable memory on the second pin of the serial peripheral interface.
0. 28. A method for operating an integrated circuit having a serial peripheral interface, comprising:
performing a first transfer of data bits on a first pin of the serial peripheral interface of a read operation for data stored in an addressable memory responsive to a command received on a second pin of the serial peripheral interface, while performing a second transfer of address bits of a memory address of a location in the addressable memory through the second pin of the serial peripheral interface; and
triggering a bit transfer on a falling edge and a bit transfer on a rising edge of a clock signal in one or both of the first and second transfers.
0. 20. An integrated circuit, comprising:
a memory array having a plurality of addressable locations with associated memory addresses at which to store data;
a serial peripheral interface, the serial peripheral interface including a plurality of pins; and
circuitry performing a first transfer of data bits through the serial peripheral interface on a first pin in the plurality of pins, the data bits of the first transfer responsive to address bits for access to addressable locations in the memory array received on a second pin in the plurality of pins, while performing a second transfer of memory address bits of a memory address of an addressable location in the plurality of addressable locations in the memory array on said second pin of the plurality of pins concurrently with the data bits of the first transfer on the first pin through the serial peripheral interface.
0. 1. An integrated circuit, comprising:
a memory array having a plurality of memory addresses at which to store data;
a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and
circuitry performing a first transfer of the data through the plurality of pins of the serial peripheral interface, while performing a second transfer of one of the plurality of memory addresses through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.
0. 2. The integrated circuit of
0. 3. The integrated circuit of
0. 4. The integrated circuit of
0. 5. An integrated circuit, comprising:
a memory array;
a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and
circuitry performing a first transfer of read operation bits through the plurality of pins of the serial peripheral interface, simultaneously with a second transfer of write operation bits through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.
0. 6. The integrated circuit of
0. 7. The integrated circuit of
0. 8. The integrated circuit of
0. 9. The integrated circuit of
0. 10. An integrated circuit, comprising:
a memory array;
a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and
circuitry performing a first transfer of read operation bits through the plurality of pins of the serial peripheral interface, simultaneously with a second transfer of erase operation bits through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.
0. 11. The integrated circuit of
0. 12. The integrated circuit of
0. 13. The integrated circuit of
0. 14. The integrated circuit of
0. 15. An integrated circuit, comprising:
a memory array;
a serial peripheral interface coupled to the memory array, the serial peripheral interface including a plurality of pins; and
circuitry performing a first transfer of read operation bits of a first read operation through the plurality of pins of the serial peripheral interface, simultaneously with a second transfer of read operation bits of a second read operation through the plurality of pins of the serial peripheral interface, wherein at least one of the first transfer and the second transfer is performed concurrently through multiple pins of the plurality of pins of the serial peripheral interface.
0. 16. The integrated circuit of
0. 17. The integrated circuit of
0. 18. The integrated circuit of
0. 19. The integrated circuit of
0. 21. The integrated circuit of claim 20, wherein the circuitry performs the first transfer and the second transfer as part of a read/write operation.
0. 22. The integrated circuit of claim 20, wherein the circuitry triggers bit transfers through the plurality of pins on both falling and rising edges of a clock signal.
0. 24. The integrated circuit of claim 23, wherein the write operation includes transfer of program instruction bits, program address bits of a program address in the memory array, and data bits to be written to the memory array at the program address.
0. 25. The integrated circuit of claim 23, wherein the read operation includes transfer of data bits read from the memory.
0. 26. The integrated circuit of claim 23, wherein the first transfer is performed simultaneously with the second transfer, in that at least one bit of the first transfer is performed at a same time as at least one bit of the second transfer is performed.
0. 27. The integrated circuit of claim 23, wherein the operation circuitry triggers bit transfers through the plurality of pins on both falling and rising edges of a clock signal.
0. 29. The method of claim 28, wherein the first transfer and second transfer are part of a read/write operation.
0. 30. The method of claim 28, wherein the first transfer is performed while the second transfer is performed, in that at least one data bit of the first transfer is performed at a same time as at least one address bit of the second transfer is performed.
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This application is a continuation reissue of application Ser. No. 14/995,059 filed on 13 Jan. 2016, and is an application for reissue of U.S. Pat. No. 8,630,128, issued from U.S. application Ser. No. 13/523,060, filed 14 Jun. 2012, which is a continuation of U.S. patent application Ser. No. 13/282,116, filed 26 Oct. 2011, which is a divisional of U.S. Pat. No. 8,064,268, which is a continuation of U.S. Pat. No. 7,613,049, which claims the benefit of U.S. Provisional Patent Application No. 60/884,000, titled “METHOD AND SYSTEM FOR A SERIAL PERIPHERAL INTERFACE PROTOCOL”, filing date Jan. 8, 2007, all of which are incorporated by reference herein.
The present invention is directed to integrated circuits and their operation. More particularly, this invention provides a method and system for serial peripheral interface protocol for an integrated circuit which include memory device. Merely by way of example, the invention has been applied to serial memory devices for fast data transfer rate and for enabling simultaneously read/write operations. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other stand-alone or embedded memory devices such DRAM, SRAM, parallel flash, or other non-volatile memories.
Flash memories are used in a variety of applications in electronics. These memory devices often include a large number of input and output pins to accommodate data and addresses required to access the memory cells. In response to increasing space and wiring demands, serial flash memories have been developed to provide reduced pin counts, often requiring only one or two data pins. These serial flash memories provide a storage solution for systems with limited space, pin connections, and power supplies. Serial flash memories can be used for code download applications, as well as for storage of voice, video, text, and data, etc. However, conventional serial flash memory devices have many limitations. For example, a conventional serial peripheral interface flash memory device transfers data or address bits in a sequential and serial fashion, limiting the speed of the memory device.
From the above, it is seen that an improved technique for design of semiconductor memory devices is desired.
The present invention is directed to integrated circuit memory devices and their operation. More particularly, this invention provides a method and system for serial peripheral interface protocol for integrated circuits which include memory devices. Merely by way of example, the invention has been applied to serial flash memory devices for improved data transfer rate and for enabling simultaneously read and write operations. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other stand-alone or embedded memory devices such DRAM, SRAM, parallel flash, or other non-volatile memories.
According to an embodiment of the present invention, a method is provided for dual I/O data read in an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a flash memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a serial peripheral interface pin out configuration and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The serial peripheral interface pin out configuration typically includes pin #1 (CS#), pin #2 (SO/SIO1), pin #3 (WP#), pin #4 (GND), pin #5 (SI/SIO0), pin #6 (SCLK), pin #7 (HOLD#), and pin #8 (VCC). The method includes applying a chip select signal coupled to pin #1 and transferring a dual I/O read instruction to the memory device using pin #5. The method includes transferring a read address to the memory device using pin #5 and pin #2 concurrently. The read address is associated with a location in the memory and includes at least a first address bit and a second address bit. The first address bit is transmitted using pin #5, and the second address bit is transmitted using pin #2. In a specific embodiment, the method uses a same clock edge to transmit the first address bit and the second address bit. The method also includes accessing data associated with the read address and waiting for a predetermined number of clock cycles. In an embodiment, the predetermined number of clock cycles is associated with the wait cycle count. The method includes transferring the data from the memory device using pin #5 and pin #2 concurrently. The data is associated with the read address and includes at least a first data bit and a second data bit. The first data bit is transmitted using pin #5, and the second data bit is transmitted using pin #2. According to embodiments of the invention, the transferring of the read address concurrently reduces address transfer clock cycles by one half. In an embodiment, the method also includes using a falling edge or a rising edge or both edges of a clock signal from pin #6 to trigger data transfer. In another embodiment, the method uses a falling edge or a rising edge or both edges of a first clock signal from pin #6 to trigger address transfer. In yet another embodiment, the method uses a falling edge or a rising edge or both edges of a first clock signal from pin #6 to trigger address transfer; and uses a falling edge or a rising edge or both edges of a second clock signal from pin #6 to trigger data transfer.
According to another embodiment, the present invention provides a method for quadruple I/O data read an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a flash memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a serial peripheral interface pin out configuration and a configuration register. The configuration register includes a wait cycle count. The serial peripheral interface pin out configuration including pin #1 (CS#), pin #2 (SO/SIO1), pin #3 (WP#/SIO2), pin #4 (GND), pin #5 (SI/SIO0), pin #6 (SCLK), pin #7 (HOLD#/SIO3), and pin #8 (VCC). The method includes applying a chip select signal coupled to pin #1, and transferring a quadruple I/O read instruction to the memory device using pin #5. The method also includes transmitting a read address to the memory device using pin #5, pin #2, pin #3, and pin #7 concurrently. The read address is associated with a location in the memory and includes at least a first address bit, a second address bit, a third address bit, and a fourth address bit. The first address bit is transmitted using pin #5, the second address bit is transmitted using pin #2, the third address bit is transmitted using pin #3, and the fourth address bit is transmitted using pin #7. In an embodiment, the transferring of the read address concurrently further includes using a same clock edge to transmit the first, second, third, and fourth address bits. In a specific embodiment, the transferring of the read address concurrently reduces address transfer clock cycles by ¾. The method then accesses data bits associated with the address in the memory device, and waits for a predetermined number of clock cycles, which is associated with the wait cycle count, and then transfers the data bits from the memory device using pin #5, pin #2, pin #3, and pin #7, concurrently. In a specific embodiment, the method uses a falling edge of a clock signal from pin #6 to trigger address transfer. In another embodiment, the method uses a falling edge or a rising edge or both edges of a first clock signal from pin #6 to trigger address transfer. In yet another embodiment, the method uses a falling edge or a rising edge or both edges of a first clock signal from pin #6 to trigger address transfer, and uses a falling edge or a rising edge or both edges of a second clock signal from pin #6 to trigger data transfer.
According to an alternative embodiment, the invention provides a method for dual I/O page read in an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a flash memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a serial peripheral interface pin out configuration and a configuration register. The configuration register includes a wait cycle count. The serial peripheral interface pin out configuration includes pin #1 (CS#), pin #2 (SO/SO1), pin #3 (WP#/SI0), pin #4 (GND), pin #5 (SI/SI1), pin #6 (SCLK), pin #7 (HOLD#/SO0), and pin #8 (VCC). The method includes applying a chip select signal coupled to pin #1 and transferring a dual I/O page read instruction to the memory device using pin #5. The method includes transferring a page address to the memory device using pin #5 and pin #3 concurrently. The page addresses includes a first part and a second part. The first part is associated with a page of data in the memory device, whereas the second part includes a plurality of byte addresses, each of which pointing to a corresponding byte in the page of data. The method includes accessing data associated with the page address in the memory device and waiting for a predetermined number of clock cycles, which is determined by the wait cycle count. The method then transfers the data in page mode from the memory device using pin #7 and pin #2 concurrently. In an embodiment, in one or more clock cycles, pin #5 and pin #3 are transferring address into the memory and pin #7 and pin #2 are transferring data out of the memory. In a specific embodiment, in one or more clock cycles, the method uses a falling edge or a rising edge or both edges of clock signal from pin #6 to trigger address transfer and data transfer.
According to another alternative embodiment, the inventions provides a method for dual I/O simultaneous read/write operation an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a serial peripheral interface pin out configuration and a configuration register. The configuration register includes a wait cycle count, a burst read length, and a wrap around indicator, and the serial peripheral interface pin out configuration includes pin #1 (CS#), pin #2 (SO/SO1), pin #3 (WP#/SI0), pin #4 (GND), pin #5 (SI/SI1), pin #6 (SCLK), pin #7 (HOLD#/SO0), and pin #8 (VCC). The method includes applying a chip select signal coupled to pin #1, and performing a read operation. The read operation including the following processes.
In yet another embodiment, the invention provides a method for dual I/O data read an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a clock signal, a plurality of pins, and a configuration register. The configuration register includes a wait cycle count, among other parameters. The method includes transmitting a read address to the memory device using a first pin and a second pin concurrently. The read address is associated with a location in the memory and includes at least a first address bit and a second address bit. In an embodiment, the first address bit is transmitted using the first pin, the second address bit is transmitted using the second pin. In a specific embodiment, the transferring of the read address concurrently further includes using a same clock edge to transmit the first address bit and the second bit. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles. The predetermined number is associated with the wait cycle count. The method also includes transferring the data from the memory device using the first pin and the second pin concurrently. In an embodiment, the method uses a falling edge or a rising edge or both edges of the clock signal to trigger data transfer. In a specific embodiment, method uses a falling edge or a rising edge or both edges of the clock signal to trigger address transfer. In some embodiments, the method uses a first falling edge or a first rising edge or first both edges of the clock signal to trigger address transfer, and using a second falling edge or a second rising edge or second both edges of the clock signal to trigger data transfer.
In still another embodiment, the invention provides a method for quadruple I/O data read in an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a clock signal, a plurality of pins, and a configuration register. The configuration register includes a wait cycle count, among other parameters. The method includes transmitting a read address to the memory device using a first pin, a second pin, a third pin, and a fourth pin concurrently. The read address is associated with a location in the memory device, and includes at least a first address bit, a second address bit, a third address bit, and a fourth address bit. These address bits are transmitted concurrently, e.g., the first address bit being transmitted using the first pin, the second address bit being transmitted using the second pin, the third address bit being transmitted using the third pin, and the fourth address bit being transmitted using the fourth pin. The method includes accessing data associated with the read address in the memory device and waiting a predetermined number of clock cycles which is associated with the wait cycle count. The method includes transferring the data from the memory device using the first pin, the second pin, the third pin, and the fourth pin concurrently. In an embodiment, the transferring of the read address concurrently includes using a same clock edge to transmit the first, second, third, and fourth address bits. In a specific embodiment, the method uses a falling edge or a rising edge or both edges of the clock signal to trigger data transfer. In an embodiment, the method uses a falling edge or a rising edge or both edges of the clock signal to trigger address transfer. In some embodiments, the method uses a first falling edge or a first rising edge or first both edges of the clock signal to trigger address transfer, and using a second falling edge or a second rising edge or second both edges of the clock signal to trigger data bit transfer.
According to an alternative embodiment of the invention, a method is provided for dual I/O page read an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a clock signal and a plurality of pins. The method includes transmitting a first page read address to the memory device using a first pin and a second pin concurrently. The first page read address is associated with a location in the memory device. The method includes transferring data from the memory device using a third pin and a fourth pin concurrently. The data is associated with the first page read address in the memory device. The method includes transmitting a second page read address to the memory device using the first pin and the second pin concurrently, while continuing to transfer the data associated with the first page read address from the memory device using the third pin and the fourth pin concurrently. The method includes transferring data associated with the second page read address from the memory device using the third pin and the fourth pin concurrently.
In a specific embodiment of the method for page read, the first page read address includes a first part and a second part. The first part is associated with a page of data in the memory device, and the second part includes a plurality of byte addresses. Each of the byte addresses is associated with a corresponding byte in the page of data. In an embodiment, the first page read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first pin, the second address bit being transmitted using the second pin. In a specific embodiment, the integrated circuit memory device includes a configuration register which includes a wait cycle count, and the method includes waiting for a predetermined number of clock cycles before transferring data from the memory device. The predetermined number of clock cycles is associated with the wait cycle count. In an embodiment, the method uses a falling edge or a rising edge or both edges of the clock signal to trigger address transfer. In a specific embodiment, method uses a falling edge or a rising edge or both edges of the clock signal to trigger data transfer. In some embodiments, the method uses a falling edge or a rising edge or both edges of a clock signal to trigger address transfer and data transfer.
In still another embodiment, the invention provides a method for dual I/O simultaneous read/write operation an integrated circuit which includes a memory device. In a specific embodiment, the integrated circuit includes a memory device. In other embodiments, the method can be applied to integrated circuits which include other types of memory devices. In an embodiment, the integrated circuit includes a clock signal, a plurality of pins, and a configuration register. The configuration register includes a wait cycle count, a burst read length, and a wrap around indicator. The method includes entering a read command into the memory device using a first pin and transmitting a read address to the memory device using the first pin and a second pin concurrently. The read address is associated with a location in the memory device, and includes at least a first address bit and a second address bit. The first address bit is transmitted using the first pin, and the second address bit is transmitted using the second pin. The method includes accessing read data associated with the read address in the memory device. The method includes transferring the read data in burst mode from the memory device using a third pin and a fourth pin concurrently. The length of the read data is provided in the burst read length field of the configuration register. The method includes performing a write operation in the memory using the first pin and second pin while continuing to transfer the read data in burst mode using the third pin and the fourth pin. The write operation includes at least one of the following processes:
In a specific embodiment of the method for simultaneous read/write operation, the method includes repeating the transferring of the read data associated with the location in the memory if the wrap around indicator is set. In an embodiment, the method includes waiting for a predetermined number of cycles before transferring the read data in from the memory device. In an example, the predetermined number of cycles is associated with the wait cycle count. In specific embodiments, the method uses a falling edge or a rising edge or both edges of a clock signal to trigger address transfer and data transfer.
Many benefits can be achieved by way of the present invention over conventional techniques. For example, in an embodiment, the present technique provides an easy to use method that relies upon conventional serial peripheral interface pin out technology. In certain embodiments, the data and address transfer rates are increased. In some embodiments, the method provides high speed and random read operation, for example, the page read method accessing individual bytes in a page. In certain embodiments, the invention provides methods for simultaneously read and program or erase operation. Depending upon the embodiment, one or more of these benefits may be achieved. These and other benefits will be described in more detail throughout the present specification and more particularly below.
Various additional objects, features and advantages of the present invention can be more fully appreciated with reference to the detailed description and accompanying drawings that follow.
The present invention is directed to integrated circuits and their operation. More particularly, this invention provides a method and system for serial peripheral interface protocol for integrated circuits which include memory devices. Merely by way of example, the invention has been applied to serial flash memory devices for improved data transfer rate and for enabling simultaneously read/write operations. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to other stand-alone or embedded memory devices such as DRAM, SRAM, parallel flash, or other non-volatile memories.
Depending upon the embodiment, the present invention includes various features, which may be used. These features include the following:
As shown, the above features may be in one or more of the embodiments to follow. These features are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
TABLE I
Read
03 Hex
Fast Read
0B Hex
Dual I/O read
BB Hex
Quad I/O read
32 Hex
Dual I/O DDR read
BA hex
Quad I/O DDR read
33 Hex
Dual I/O page read
BC Hex
Dual I/O DDR page read
BD Hex
Dual I/O read with SRW
AE Hex
Dual I/O program with SRW
CE Hex
Dual I/O sector erase with SRW
CD Hex
Configuration register write
D1 Hex
It is noted that SRW is used here to mean simultaneous read and write. Of course, there can be other variations, modifications, and alternatives. Various features will be discussed below.
SI/SIO0 pin coupled to SI/SIO0 block 211;
SO/SIO1 pin coupled to SO/SIO1 block 212,
WP#/ACC pin coupled to WP#/ACC block 213,
HOLD# pin coupled to HOLD# block 214,
CS# pin coupled to CS# block 215, and
SCLK pin coupled to SCLK block 216.
As shown in
Memory Array 230,
X-Decoder 231,
Page Buffer 232,
Y-decoder 233,
Sense Amplifier 234, and
Output Buffer 236.
Device 200 also includes the following control and support circuit blocks.
Address Generator 221,
Data Register 222,
SRAM Buffer 223,
Mode Logic 224,
Clock Generator 225,
State Machine 226, and
HV Generator 227.
Merely as examples, certain operations of device 200 are now discussed according to a specific embodiment of the present invention. System clock signal SCLK on input terminal 216 is coupled to Clock Generator 225, which in turn is coupled to Mode Logic 224. Mode Logic 224 is operably coupled to receive a chip select signal CS# on CS# input terminal 215. Commands or instructions may be input through input SI/SIO0 block 211 and then transferred to Data Register 222 and Mode Logic 224. Mode Logic 224, in combination with State Machine 226, interprets and executes the command such as a read, erase, or program operation. In an embodiment, Mode Logic 224 also receives a signal from WP#/ACC block 213 to perform a write protect function, and a signal from HOLD# block 214 to keep a clock signal from entering the State Machine 226.
According to a specific embodiment, data may be input through SI/SIO0 block 211, SO/SIO1 block 212, WP#/ACC block 213, and HOLD# block 214, which are coupled to Data Register 222. Data Register 222 is coupled to SRAM Buffer 223 for temporary storage. Data may be output through SI/SIO0 block 211, SO/SIO1 block 212, WP#/ACC block 213, and HOLD# block 214, which are coupled the Output Buffer 236. An address corresponding to a location in memory array 230 may be supplied from Data Register 222 to Address Generator 221. The address is then decoded by X-decoder 231 and Y-decoder 233. Page Buffer 232 is coupled to memory array 230 to provide temporary storage for memory operation. In a read operation, the data is transferred from memory array 230 through Sense Amplifier 234 to the Output Buffer 236. For write operation, data is transferred from Data Register to Page Buffer 232 and then written into Memory Array 230. For high voltage operation, e.g., for a write operation, High Voltage Generator 227 is activated.
Although the above has been shown using a selected group of components for the integrated circuit device, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification and more particularly below.
1. (Process 310) Provide an integrated circuit memory device;
2. (Process 320) Transmit a read address to the memory device using a first pin and a second pin concurrently;
3. (Process 330) Access the memory device for data associated with the address;
4. (Process 340) Wait a predetermined number of clock cycles; and
5. (Process 350) Transfer the data from the memory device using the first pin and the second pin concurrently.
The above sequence of processes provides a dual I/O read method for a memory device according to an embodiment of the present invention. As shown, the method uses a combination of processes including a way of transmitting address information using two pins concurrently, and transferring data using two pins concurrently. Other alternatives can also be provided where processes are added, one or more processes are removed, or one or more processes are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification and more particularly below with reference to
Many benefits can be achieved by the embodiment shown in
In an embodiment, a configurable wait period is provided after the transfer of address information. As an example, a wait cycle is shown as clock cycles 20-27 in
In an embodiment, a number of configurable wait cycles are provided. The number of wait cycles is specified in a configuration register and can be selected according to the application. In
1. (Process 810) Provide an integrated circuit memory device;
2. (Process 820) Transmit a read address to the memory device using a first pin, a second pin, a third pin, and a fourth pin concurrently;
3. (Process 830) Access data associated with the read address in the memory device;
4. (Process 840) Wait a predetermined number of clock cycles; and
5. (Process 850) Transfer the data from the memory device using the first pin, the second pin, the third pin, and the fourth pin concurrently.
The above sequence of processes provides a quadruple I/O page read method for a memory device according to an embodiment of the present invention. As shown, the method uses a combination of processes including a way of transmitting address information using four pins concurrently, and transferring data using four pins concurrently. Other alternatives can also be provided where processes are added, one or more processes are removed, or one or more processes are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification and more particularly below with reference to
1. (Process 1310) Provide an integrated circuit memory device, the memory device including a clock signal and a plurality of pins;
2. (Process 1320) Transmit a first page read address to the memory device using a first pin and a second pin concurrently;
3. (Process 1330) Transfer data from the memory device using a third pin and a fourth pin concurrently;
4. (Process 1340) Transmit a second page read address to the memory device using the first pin and the second pin concurrently, while continuing to transfer the data associated with the first page read address from the memory device using the third pin and the fourth pin concurrently; and
5. (Process 1350) Transfer data associated with the second page read address from the memory device using the third pin and the fourth pin concurrently.
The above sequence of processes provides a dual I/O page read method for a memory device according to an embodiment of the present invention. As shown, the method uses a combination of processes including a way of transmitting page address information using two pins concurrently, while transmitting page data using two different pins concurrently. Other alternatives can also be provided where processes are added, one or more processes are removed, or one or more processes are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification and more particularly below with reference to
TABLE II
Bit
Purpose
Description
7-4
Dummy
0001: 1 dummy cycle,
cycle count
0010: 2 dummy cycles,
0011: 3 dummy cycles,
0100: 4 dummy cycles,
0101: 5 dummy cycles,
0110: 6 dummy cycles,
0111: 7 dummy cycles,
1000: 8 dummy cycles (default)
3-1
Burst length
000: 4-byte burst,
001: 8-byte burst,
010: 16-byte burst,
100: 32-byte burst,
111: continuous burst
0
Wrap around
0: Wrap around,
1: No wrap around (default)
In a specific embodiment, bits 4-7 provide the number of dummy cycles used in, for example, configurable wait cycles included in the embodiments discussed above. In the specific embodiment shown in
1. (Process 1710) Provide an integrated circuit memory device;
2. (Process 1720) Enter a read command into the memory device;
3. (Process 1730) Transmit a read address to the memory device using a first pin and a second pin concurrently;
4. (Process 1740) Access read data associated with the read address;
5. (Process 1750) Transfer the read data from the memory device using a third pin and a fourth pin concurrently; and
5. (Process 1760) Perform a write operation in the memory using the first pin and second pin while continuing to transfer the read data using the third pin and the fourth pin. The write operation including at least one of the following processes:
The above sequence of processes provides a method dual I/O burst read with simultaneous read/write (SRW) for a memory device according to an embodiment of the present invention. As shown, the method uses a combination of processes including a way of transferring burst read data while writing program data using different pins. Other alternatives can also be provided where processes are added, one or more processes are removed, or one or more processes are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification and more particularly below with reference to
Referring to
As shown in
x1 mode:
Pin#2 SO
Pin#3 WP#
Pin#5 SI
Pin#7 HOLD#
x2 read mode:
Pin#2 SO/SIO1
Pin#3 WP#
Pin#5 SI/SIO0
Pin#7 HOLD#
x4 read mode:
Pin#2 SO/SIO1
Pin#3 WP#/SIO2
Pin#5 SI/SIO0
Pin#7 HOLD#/SIO3
Page/Burst read mode:
Pin#2 SO/SO1
Pin#3 WP#/SI0
Pin#5 SI/SI1
Pin#7 HOLD#/SO0
Although the above has been shown using a selected group of components, pin configuration, and timing sequences for the serial peripheral interface methods for memory device according to embodiments of the present invention, there can be many alternatives, modifications, and variations. For example, some of the pin assignments and functions can be interchanged or modified. Depending upon the embodiment, the arrangement of timing sequence may be altered. As another example, the use of falling and rising clock edges may be interchanged and modified. Many other variations, modifications, and alternatives can be implemented by one skilled in the art in view of this disclosure. For example, the invention can be applied to other memory devices such DRAM, SRAM, parallel flash, or other non-volatile memories, etc.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Hung, Chun-Hsiung, Chang, Kuen-Long, Liu, Chia-He
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