On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

Abstract

A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex concave sidewall portions.

Description

RELATED APPLICATIONS

This application convex concave sidewall portions 72C. In one embodiment, each of the pair of lengthwise sidewalls includes a laterally alternating sequence of vertical planar sidewall portions 72P and vertical convex concave sidewall portions 72C. Each of the convex concave sidewall portions is equidistant from a sidewall of a respective most proximal one of the drain select level assemblies 115 by the lateral thickness of the sacrificial spacers 274.

Referring to FIGS. 16A-16E, a photoresist layer (not shown) can be applied over the sacrificial matrix material layer 272, the drain select level isolation strips 72, and the drain select level assemblies 115. The photoresist layer is lithographically patterned to form openings in areas between clusters of drain select level assemblies 115, as shown in FIG. 16D. Each vertical stack of a memory opening fill structure 58 and a drain select level assembly 115 constitutes a vertical transistor stack structure 358, which includes a vertical semiconductor channel (60, 260) that includes a memory level channel portion 60 and a drain select level channel portion 260, charge storage elements, and various dielectric material layers that prevent electrical shorts from various control gates to be subsequently formed. Each vertical stack of a support opening fill structure 20 (which is a first support pillar structure) and a drain select level assembly 115 (which is a second support pillar structure) constitutes a support pillar stack 320. Thus, the photoresist layer includes openings between arrays of the vertical transistor stack structures 358, each of which can be a two-dimensional periodic array having an inter-row pitch p along the second horizontal direction hd2.

The pattern in the photoresist layer can be transferred through the sacrificial matrix material layer 272, the isolation spacer layer 270, the insulating cap layer 70, the alternating stack (32, 42) and/or the retro-stepped dielectric material portion 65 employing an anisotropic etch to form the backside trenches 79. The backside trenches 79 vertically extend at least to the top surface of the substrate (9, 10), and laterally extend in the first horizontal direction hd1 through the memory array region 100 and the contact region 300. In one embodiment, the backside trenches 79 can include a source contact opening in which a source contact via structure can be subsequently formed.

The photoresist layer can be removed, for example, by ashing. The backside trenches 79 can extend along the first horizontal direction hd1, which is parallel to the word line direction which is the lengthwise direction of the drain select level isolation strips 72. At least one backside trench 79 can be located between a set of at least two drain select level isolation strips 72, and a set of at least one drain select level isolation strip 72 can be located between a neighboring pair of backside trenches 79. For example, as shown in FIG. 16E, a set of three drain select level isolation strip 72 is located between a neighboring pair of backside trenches 79.

Referring to FIGS. 17A-17D, an isotropic etchant can be applied to the first exemplary structure in an isotropic etch process. The isotropic etchant is an etchant that etches the second material of the sacrificial material layers 42, the material of the sacrificial matrix material layer 272, and the material of the sacrificial spacers 274 selective to the first material of the insulating layers 32, selective to the material of the drain select level isolation strips 72, selective to the semiconductor materials of the array of drain select level assemblies 115, and selective to the material of the outermost layer of the memory films 50. The sacrificial material layers 42 can be removed selective to the insulating layers 32 and the memory stack structures 55. Backside recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The sacrificial matrix material layer 272 and the sacrificial spacers 274 can be removed from around the drain select level assemblies 115 and the drain select level isolation strips 72 above the top surface of the isolation spacer layer 270.

In one embodiment, the sacrificial material layers 42, the sacrificial matrix material layer 272, and the sacrificial spacers 274 can include silicon nitride, and the materials of the insulating layers 32, the isolation spacer layer 270, the drain select level isolation strips 72, and the retro-stepped dielectric material portion 65 can be selected from silicon oxide and dielectric metal oxides.

The etch process that removes the second material selective to the first material and the outermost layer of the memory films 50 can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches 79. For example, if the sacrificial material layers 42 include silicon nitride, the etch process can be a wet etch process in which the exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure 20, the retro-stepped dielectric material portion 65, and the memory stack structures 55 provide structural support while the backside recesses 43 are present within volumes previously occupied by the sacrificial material layers 42. Void volumes 279 remain in regions previously occupied by the removed sacrificial matrix material layer 272 and the sacrificial spacers 274.

Each backside recess 43 can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 can be greater than the height of the backside recess 43. A plurality of backside recesses 43 can be formed in the volumes from which the second material of the sacrificial material layers 42 is removed. The memory openings in which the memory stack structures 55 are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses 43. In one embodiment, the memory array region 100 comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9, 10). In this case, each backside recess 43 can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses 43 can extend substantially parallel to the top surface of the substrate (9, 10). A backside recess 43 can be vertically bounded by a top surface of an underlying insulating layer 32 and a bottom surface of an overlying insulating layer 32. In one embodiment, each backside recess 43 can have a uniform height throughout.

Physically exposed surface portions of the optional epitaxial channel portions 11 and the semiconductor material layer 10 can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each epitaxial channel portion 11 into a tubular dielectric spacer 116, and to convert each physically exposed surface portion of the semiconductor material layer 10 into a planar dielectric portion 616. In one embodiment, each tubular dielectric spacer 116 can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The tubular dielectric spacers 116 include a dielectric material that includes the same semiconductor element as the epitaxial channel portions 11 and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the tubular dielectric spacers 116 is a dielectric material. In one embodiment, the tubular dielectric spacers 116 can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the epitaxial channel portions 11. Likewise, each planar dielectric portion 616 includes a dielectric material that includes the same semiconductor element as the semiconductor material layer and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the planar dielectric portions 616 is a dielectric material. In one embodiment, the planar dielectric portions 616 can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the semiconductor material layer 10. Planar oxide portions (not shown) can be collaterally formed on the top surfaces of the drain regions 263 by conversion of the surface portions of the drain regions 263 into silicon oxide portions. Such planar oxide portions are sacrificial structures that are removed in subsequent processing steps.

Referring to FIGS. 18A-18C, a backside blocking dielectric layer 44 (shown in the inset of FIG. 18B) can be optionally formed by a conformal deposition process. The backside blocking dielectric layer 44, if present, comprises a dielectric material that functions as a portion of a control gate dielectric for the control gates to be subsequently formed in the backside recesses 43. In case the blocking dielectric layer 52 is present within each memory opening, the backside blocking dielectric layer 44 is optional. In case the blocking dielectric layer 52 is omitted, the backside blocking dielectric layer 44 is present.

The backside blocking dielectric layer 44 can be formed in the backside recesses 43 and on a sidewall of the backside trench 79. The backside blocking dielectric layer 44 can be formed directly on horizontal surfaces of the insulating layers 32 and sidewalls of the memory stack structures 55 within the backside recesses 43. If the backside blocking dielectric layer 44 is formed, formation of the tubular dielectric spacers 116 and the planar dielectric portion 616 prior to formation of the backside blocking dielectric layer 44 is optional. In one embodiment, the backside blocking dielectric layer 44 can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer 44 can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer 44 can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.

The dielectric material of the backside blocking dielectric layer 44 can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer can include a silicon oxide layer. The backside blocking dielectric layer can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The thickness of the backside blocking dielectric layer can be in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed. The backside blocking dielectric layer is formed on the sidewalls of the backside trenches 79, horizontal surfaces and sidewalls of the insulating layers 32, the portions of the sidewall surfaces of the memory stack structures 55 that are physically exposed to the backside recesses 43, and a top surface of the planar dielectric portion 616. A backside cavity 79′ is present within the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer.

At least one conductive material can be subsequently deposited by a conformal deposition method. In one embodiment, the at least one conductive material can include a metallic liner layer and a metallic fill material layer. In this case, the metallic liner layer can include an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic liner layer can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic liner layer can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic liner layer can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic liner layer can consist essentially of a conductive metal nitride such as TiN.

The metallic fill material layer can be subsequently deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer can be deposited employing a fluorine-containing precursor gas such as WF₆. In one embodiment, the metallic fill material layer can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer is spaced from the insulating layers 32 and the memory stack structures 55 by the metallic liner layer, which can be a metallic barrier layer that blocks diffusion of fluorine atoms therethrough. The thickness of the metallic fill material layer can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed.

The thicknesses of the metallic liner layer and the metallic fill material layer can be selected such that each backside recess 43 is completely filled with the metallic liner layer and the metallic fill material layer, while a backside cavity 79′ is present within each backside trench 79.

Each portion of the combination of the metallic liner layer and the metallic fill material layer that fills a backside recess constitutes an electrically conductive layer 46. Each portion of the combination of the metallic liner layer and the metallic fill material layer that is deposited below the horizontal plane including the bottom surfaces of the drain regions 263, and within void volumes 279 from which the sacrificial matrix material layer 272 and the sacrificial spacers 274 are removed, constitutes a drain select gate electrode 146. A continuous conductive material layer 46L is formed at peripheral portions of each backside trench 79, over each of the drain select gate electrodes 146, and over regions of the isolation spacer layer 270 that do not underlie arrays of the drain select level assemblies 115.

Referring to FIGS. 19A-19C, the at least one conductive material of the continuous conductive material layer 46L can be isotropically recessed by an isotropic etch process. Specifically, horizontal portions of the at least one conductive material can be removed from above the array of drain select level assemblies 115 and from around upper portions of the array of drain select level assemblies 115. The unetched remaining portions of the at least one conductive material overlying the isolation spacer layer 270 constitute the drain select gate electrodes 146, which are laterally spaced among one another by the drain select level dielectric strips 72. Further, the vertical portions of the at least one conductive material can be removed from inside the backside trenches 79 by the isotropic etch process. The duration of the isotropic etch process can be controlled to avoid removal of the drain select gate electrodes 146 and the electrically conductive layers 46.

The drain select gate electrodes 146 can be formed on the array of drain select level assemblies 115 and the drain select level isolation strips 72. Each of the drain select gate electrodes 146 can laterally encircle each of the drain select level assemblies 115 located between a neighboring pair of drain select level isolation strips 72. In one embodiment, each of the drain select gate electrodes 146 can include a pair of lengthwise sidewalls that generally extend along the first horizontal direction hd1 and contact a respective sidewall of the drain select level isolation strips 72. Each of the lengthwise sidewalls of the drain select gate electrode 146 can include a laterally alternating sequence of planar sidewall portions 146P and convex sidewall portions 146C. In one embodiment, each of the lengthwise sidewalls of the drain select gate electrode 146 can include a laterally alternating sequence of vertical planar sidewall portions 146P and vertical convex sidewall portions 146C. Each of the drain select gate electrodes 146 laterally surrounds respective rows of the drain select level assemblies 115. Each row of the drain select level assemblies 115 can be arranged along the first horizontal direction hd1. The top surface of each drain select gate electrode 146 can be located below the horizontal plane including the bottom surfaces of the drain regions 263 to avoid electrical shorts between the drain select gate electrodes 146 and the drain regions 263.

Referring to FIGS. 20A-20E, a dielectric fill material layer 78 is formed on the top surface of the drain select gate electrodes 146 and in the backside trenches 79. The dielectric fill material layer 78 can include a planarizable dielectric material such as silicon oxide. The dielectric fill material layer 78 can be planarized to remove to provide a top surface that is coplanar with the top surfaces of the drain regions 263. For example, chemical mechanical planarization or a recess etch can be employed. The top surfaces of the drain select level isolation strips 72 and the dielectric fill material layer 78 can be within a same horizontal plane as the top surfaces of the drain regions 263. The dielectric fill material layer 78 can be formed over the drain select gate electrodes 146. In one embodiment, portions of the dielectric fill material layer 78 may be laterally spaced apart among one another by the drain select level isolation strips 72.

Alternatively, the planarized top surface of the dielectric fill material layer 78 can be formed over the horizontal plane including the top surfaces of the drain regions 163 and the drain select level isolation strips 72. In this case, the dielectric fill material layer 78 can be formed as a single continuous material layer.

Each portion of the dielectric fill material layer 78 that fills one of the backside trenches 79 is herein referred to as a dielectric wall structure 78T, which provides electrical isolation between laterally neighboring pairs of electrically conductive layers 46 that are located at the same level, i.e., at the same vertical distance from the top surface of the substrate (9, 10).

Each volume located underneath horizontal interfaces between the dielectric fill material layer 78 and the drain select gate electrodes 146 and located above bottom surfaces of the drain select gate electrodes 146, and located within peripheries defined by sidewalls of the drain select gate electrodes 146 can be filled entirely with a respective one of the drain select gate electrodes 146. In other words, the drain select gate electrodes can have a uniform horizontal cross-sectional shape that is invariant between the top surface thereof and the bottom surface thereof.

Referring to FIGS. 21A-21C, an alternative embodiment of the first exemplary structure can be derived from the first exemplary structure of FIGS. 15A-15C by applying and patterning a photoresist layer in the same manner as in the processing steps of FIGS. 16A-16E, and subsequently performing an isotropic etch such that the depth of the line trenches thereby formed does not extend below the isolation spacer layer 270. The line trenches thereby formed are herein referred to as upper backside trenches 179, which extend through the sacrificial matrix material layer 272 and stops on, or extends only through an upper portion of, the isolation spacer layer 270. The duration of the anisotropic etch process can be controlled to limit the depth of the upper backside trenches 179.

Referring to FIGS. 22A-22C, an isotropic etch can be performed to remove the materials of the sacrificial matrix material layer 272 and the spacer layers 274 selective to the materials of the semiconductor materials of the drain select level assemblies 115 and the dielectric material of the drain select level isolation strips 72 to form the void volumes 279. For example, if the sacrificial matrix material layer 272 and the spacer layers 274 include silicon nitride, a wet etch employing hot phosphoric acid can be performed to remove the sacrificial matrix material layer 272 and the spacer layers 274.

Referring to FIGS. 23A to 23C, at least one conductive material can be conformally deposited to fill the void volumes 279 (i.e., gaps) between each set of drain select level assemblies 115 between neighboring pairs of drain select level isolation strips 72. The at least one conductive material can include a metallic liner layer and a metallic fill material layer. For example, the materials employed to form the drain select gate electrodes 146 at the processing steps of FIGS. 18A-18C can be employed. Each portion of the at least one conductive material that is deposited below the horizontal plane including the bottom surfaces of the drain regions 263, and within void volumes 279 from which the sacrificial matrix material layer 272 and the sacrificial spacers 274 are removed, constitutes a drain select gate electrode 146. A continuous conductive material layer 46M is formed over each of the drain select gate electrodes 146 and over regions of the isolation spacer layer 270 that do not underlie arrays of the drain select level assemblies 115.

Referring to FIGS. 24A-24C, the at least one conductive material of the continuous conductive material layer 46M can be selectively recessed by an anisotropic or isotropic etch process. Specifically, horizontal portions of the at least one conductive material can be removed from above the array of drain select level assemblies 115 and from around upper portions of the array of drain select level assemblies 115. The unetched remaining portions of the at least one conductive material overlying the isolation spacer layer 270 constitute the drain select gate electrodes 146, which are laterally spaced among one another by the drain select level dielectric strips 72.

The drain select gate electrodes 146 can be formed on the array of drain select level assemblies 115 and the drain select level isolation strips 72. Each of the drain select gate electrodes 146 can laterally encircle each of the drain select level assemblies 115 located between a neighboring pair of drain select level isolation strips 72. In one embodiment, each of the drain select gate electrodes 146 can include a pair of lengthwise sidewalls that generally extend along the first horizontal direction hd1. Each of the lengthwise sidewalls of the drain select gate electrode 146 can include a laterally alternating sequence of planar sidewall portions and convex sidewall portions. In one embodiment, each of the lengthwise sidewalls of the drain select gate electrode 146 can include a laterally alternating sequence of vertical planar sidewall portions and vertical convex sidewall portions. Each of the drain select gate electrodes laterally surrounds respective rows of the drain select level assemblies 115. Each row of the drain select level assemblies 115 can be arranged along the first horizontal direction hd1. The top surface of each drain select gate electrode 146 can be located below the horizontal plane including the bottom surfaces of the drain regions 263 to avoid electrical shorts between the drain select gate electrodes 146 and the drain regions 263.

Referring to FIGS. 25A-25C, a dielectric fill material layer 78 is formed on the top surface of the drain select gate electrodes 146. The dielectric fill material layer 78 can include a planarizable dielectric material such as silicon oxide. The dielectric fill material layer 78 can be planarized to remove to provide a top surface that is coplanar with the top surfaces of the drain regions 263. For example, chemical mechanical planarization or a recess etch can be employed. The top surfaces of the drain select level isolation strips 72 and the dielectric fill material layer 78 can be within a same horizontal plane as the top surfaces of the drain regions 263. In one embodiment, portions of the dielectric fill material layer 78 may be laterally spaced apart among one another by the drain select level isolation strips 72.

Alternatively, the planarized top surface of the dielectric fill material layer 78 can be formed over the horizontal plane including the top surfaces of the drain regions 163 and the drain select level isolation strips 72. In this case, the dielectric fill material layer 78 can be formed as a single continuous material layer.

Each volume located underneath horizontal interfaces between the dielectric fill material layer 78 and the drain select gate electrodes 146 and located above bottom surfaces of the drain select gate electrodes 146, and located within peripheries defined by sidewalls of the drain select gate electrodes 146 can be filled entirely with a respective one of the drain select gate electrodes 146. In other words, the drain select gate electrodes can have a uniform horizontal cross-sectional shape that is invariant between the top surface thereof and the bottom surface thereof.

Referring to FIGS. 26A-26C, a photoresist layer (not shown) can be applied over the dielectric fill material layer 78, and can be lithographically patterned to form openings in areas between clusters of drain select level assemblies 115. The pattern of the openings in the photoresist layer can be the same as in the processing steps of FIGS. 16A-16E. Further, the pattern of the opening in the photoresist layer can be the same as the pattern of the upper backside trenches 179 as formed at the processing steps of FIGS. 21A-21C.

The pattern in the photoresist layer can be transferred through the dielectric fill material layer 78, the isolation spacer layer 270, the insulating cap layer 70, the alternating stack (32, 42) and/or the retro-stepped dielectric material portion 65 employing an anisotropic etch to form the backside trenches 79. The backside trenches 79 vertically extend at least to the top surface of the substrate (9, 10), and laterally extend in the first horizontal direction hd1 through the memory array region 100 and the contact region 300. In one embodiment, the backside trenches 79 can include a source contact opening in which a source contact via structure can be subsequently formed.

The photoresist layer can be removed, for example, by ashing. The backside trenches 79 can extend along the first horizontal direction hd1, which is parallel to the lengthwise direction of the drain select level isolation strips 72. Each backside trench 79 can be located between a set of at least one drain select level isolation strip 72, and each set of at least one drain select level isolation strip 72 can be located between a neighboring pair of backside trenches 79.

Referring to FIGS. 27A-27C, the processing steps of FIGS. 17A-17D can be performed to introduce an isotropic etchant into the backside trenches 79 in an isotropic etch process. The isotropic etchant is an etchant that etches the second material of the sacrificial material layers 42 selective to the first material of the insulating layers 32, selective to the dielectric materials of the dielectric fill material layer 78 and the drain select level isolation strips 72, and selective to the outermost layers of the memory films 50. The sacrificial material layers 42 can be removed selective to the insulating layers 32 and the memory stack structures 55. Backside recesses are formed in volumes from which the sacrificial material layers 42 are removed.

A backside blocking dielectric layer (shown in the inset of FIG. 27B) can be optionally formed by a conformal deposition process as in the processing steps of FIGS. 18A-18C. At least one conductive material can be subsequently deposited by at least one conformal deposition method as in the processing steps of FIGS. 18A-18C. Excess portions of the conductive material can be removed from inside the backside trenches 79 and from above the dielectric fill material layer 78 by an isotropic etch to form electrically conductive layers 46 in the backside recesses.

A dielectric fill material can be subsequently deposited in the backside trenches 79 to form dielectric material portions therein, which are herein referred to as dielectric wall structure 278. The dielectric wall structures 278 provides electrical isolation between laterally neighboring pairs of electrically conductive layers 46 that are located at the same level, i.e., at the same vertical distance from the top surface of the substrate (9, 10). The dielectric fill material layer 78 and the dielectric wall structures 278 can include the same dielectric material or different dielectric materials. For example, the dielectric fill material layer 78 and the dielectric wall structures 278 can include an undoped silicate glass or doped silicate glasses having the same dopant species at the same dopant concentration(s) or having different dopant species and/or different dopant concentrations.

Referring to FIGS. 28A-28C, a second exemplary structure according to a second embodiment of the present disclosure can be derived from the first exemplary structure of FIGS. 6A, 6B, and 7A-7C by forming an isolation spacer layer 270 as in the first embodiment, and by subsequently forming a layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132 in lieu of a single sacrificial matrix material layer 272. In this case, the at least one sacrificial matrix material layer 142 formed over the alternating stack (32, 42) includes a plurality of sacrificial matrix material layers 142 that are spaced among one another by one or more insulating spacer layers 132.

Each of the sacrificial matrix material layers 142 of the second embodiment can include the same material as the sacrificial matrix material layer 272 of the first embodiment. Each of the one or more insulating spacer layers 132 can include the same material as the material of the insulating layers 32 or the material of the isolation spacer layer 270. In one embodiment, the sacrificial matrix material layers 142 can include silicon nitride, and the insulating spacer layers 132 can include silicon oxide. Each of the sacrificial matrix material layers 142 and the insulating spacer layers 132 can have a thickness in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed. In one embodiment, an alternating stack of at least three sacrificial matrix material layers 142 and at least two insulating spacer layers 132 can be formed.

Referring to FIGS. 29A-29C, an array of cylindrical openings can be formed through layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132 and through the isolation spacer layer 270. The processing steps of FIGS. 9A-9C can be employed to form a patterned photoresist layer, which can have the same pattern as in the first embodiment. The anisotropic etch process that forms the cylindrical openings through the sacrificial matrix material layer 272 and the isolation spacer layer 270 can be modified to form an array of cylindrical openings through the layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132. Top surfaces of the enhanced doping regions 63 and the memory level channel portions 60 can be physically exposed at the bottom of each of the cylindrical openings through the layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132. Subsequent processing steps of FIGS. 9A-9C can be performed to form gate dielectrics 250, the conformal semiconductor material layer 260L, and the drain select level dielectric core layer 262L in the array of cylindrical openings and over the layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132.

Referring to FIGS. 30A-30C, the processing steps of FIGS. 10A-10C can be performed to form the drain select level channel portions 260 and the drain select level dielectric cores 262. Recessed regions can be formed above each drain select level dielectric core 262 in the same manner as in the first embodiment.

Referring to FIGS. 31A-31C, drain regions 263 can be formed in each of the recessed regions in the same manner as in the first embodiment. Arrays of drain select level assemblies 115 having the same periodicity as the underlying array of memory stack structures 55 can be formed as in the first embodiment.

Referring to FIGS. 32A-32C, a photoresist layer 277 is applied and lithographically patterned in the same manner as in the processing steps of FIGS. 12A-12C. An anisotropic etch process is performed to etch through the layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132 employing the combination of the patterned photoresist layer 277 and the drain regions 263 as an etch mask. The isolation spacer layer 270 can be employed as an etch stop layer. Laterally extending trenches 273 are formed through the layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132. The laterally extending trenches 273 can have the same pattern as in the first embodiment. Each of the sacrificial matrix material layers 142 can be patterned into sacrificial material strips, i.e., strips of the sacrificial material, that are laterally spaced apart by the laterally extending trenches 273. Further, each of the one or more insulating spacer layers 132 can be patterned into insulating material strips, i.e., strips of the insulating material.

Each laterally extending trench 273 can laterally extend along the first horizontal direction hd1. Each laterally extending trench 273 is laterally bounded by two lengthwise sidewalls that generally extend along the first horizontal direction hd1. For each laterally extending trench 273 located between a neighboring pair of rows of the drain select level assemblies 115, each of the two lengthwise sidewalls can include a respective alternating sequence of planar sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132 and convex sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132. In one embodiment, for each laterally extending trench 273 located between a neighboring pair of rows of the drain select level assemblies 115, each of the two lengthwise sidewalls can include a respective alternating sequence of vertical planar sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132 and vertical convex sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132.

For each laterally extending trench 273 located around an outermost row of the drain select level assemblies 115, one of the two lengthwise sidewalls can include a respective alternating sequence of planar sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132 and convex sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132, and the other of the two lengthwise sidewalls can consist of a single straight vertical sidewall. In one embodiment, for each laterally extending trench 273 located between a neighboring pair of rows of the drain select level assemblies 115, one of the two lengthwise sidewalls can include a respective alternating sequence of vertical planar sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132 and vertical convex sidewall segments of the layer stack of the sacrificial matrix material layers 142 and one or more insulating spacer layers 132. The photoresist layer 277 can be subsequently removed, for example, by ashing.

Referring to FIGS. 33A-33C, the processing steps of FIGS. 13A-13C can be performed to form a sacrificial spacer material layer 274L.

Referring to FIGS. 34A-34C, the processing steps of FIGS. 14A-14C can be performed to form sacrificial spacers 274 within each of the laterally extending trenches.

Referring to FIGS. 35A-35C, the processing steps of FIGS. 15A-15C can be performed to form a drain select level isolation strip 72 within each unfilled volume of the laterally extending trenches.

Referring to FIGS. 36A-36C, the processing steps of FIGS. 16A-16E can be performed to form backside trenches 79. The anisotropic etch process can be appropriately modified to etch through the layer stack including multiple sacrificial matrix material layers 142 spaced among one another by insulating spacer layers 132, the isolation spacer layer 270, the insulating cap layer 70, and the alternating stack (32, 42).

Referring to FIGS. 37A-37C, the processing steps of FIGS. 17A-17D can be performed. Specifically, an isotropic etchant can be applied to the second exemplary structure in an isotropic etch process. The isotropic etchant is an etchant that etches the second material of the sacrificial material layers 42, the material of the sacrificial matrix material layers 142, and the material of the sacrificial spacers 274 selective to the first material of the insulating layers 32, selective to the material of the one or more insulating spacer layers 132, selective to the material of the drain select level isolation strips 72, selective to the semiconductor materials of the array of drain select level assemblies 115, and selective to the material of the outermost layer of the memory films 50. The sacrificial material layers 42 can be removed selective to the insulating layers 32 and the memory stack structures 55. Backside recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The sacrificial matrix material layer 142 and the sacrificial spacers 274 can be removed from around the drain select level assemblies 115 and the drain select level isolation strips 72 above the top surface of the isolation spacer layer 270.

Strips of each insulating spacer layer 132 that are supported by a respective set of drain select level assemblies 115 between a neighboring pair of drain select level isolation strips 72 remain attached to the respective set of drain select level assemblies 115. Strips of each insulating spacer layer 132 that are not supported by a respective set of drain select level assemblies 115 are removed during the isotropic etch process. The regions from which the strips of each insulating spacer layer 132 are removed are located adjacent to the backside trenches 79, and are herein referred to as insulating spacer removal regions IRR.

Drain select level lateral recesses 243 can be formed between the isolation spacer layer 270 and each remaining strip portion of a bottommost one of the insulating spacer layers 132. If two or more insulating spacer layers 132 are present, additional drain select level lateral recesses 243 can be formed between each vertically neighboring pair of the insulating spacer layers 132.

As in the first embodiment, each backside recess 43 can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 can be greater than the height of the backside recess 43. A plurality of backside recesses 43 can be formed in the volumes from which the second material of the sacrificial material layers 42 is removed. The memory openings in which the memory stack structures 55 are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses 43. In one embodiment, the memory array region 100 comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9, 10). In this case, each backside recess 43 can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses 43 can extend substantially parallel to the top surface of the substrate (9, 10). A backside recess 43 can be vertically bounded by a top surface of an underlying insulating layer 32 and a bottom surface of an overlying insulating layer 32. In one embodiment, each backside recess 43 can have a uniform height throughout.

Physically exposed surface portions of the optional epitaxial channel portions 11 and the semiconductor material layer 10 can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each epitaxial channel portion 11 into a tubular dielectric spacer 116, and to convert each physically exposed surface portion of the semiconductor material layer 10 into a planar dielectric portion 616 as illustrated in FIG. 17D.

Referring to FIGS. 38A-38C, a backside blocking dielectric layer 44 can be deposited as in the first embodiment. The processing steps of FIGS. 18A-18C can be performed to deposit the backside blocking dielectric layer 44. At least one conductive material can be subsequently deposited by a conformal deposition method in the same manner as in the first embodiment. In one embodiment, the at least one conductive material can include a metallic liner layer and a metallic fill material layer. The thicknesses of the metallic liner layer and the metallic fill material layer can be selected such that each backside recess 43 is completely filled with the metallic liner layer and the metallic fill material layer, while a backside cavity 79′ is present within each backside trench 79. The processing steps of FIGS. 18A-18C can be performed to deposit the at least one conductive material.

Each portion of the combination of the metallic liner layer and the metallic fill material layer that fills a backside recess constitutes an electrically conductive layer 46. Each portion of the combination of the metallic liner layer and the metallic fill material layer that is deposited below the horizontal plane including the bottom surfaces of the drain regions 263, and within volumes from which the sacrificial matrix material layers 142 and the sacrificial spacers 274 are removed, constitutes a drain select gate electrode 246. A continuous conductive material layer 46L is formed at peripheral portions of each backside trench 79, over each of the drain select gate electrodes 246, and over regions of the isolation spacer layer 270 that do not underlie arrays of the drain select level assemblies 115, i.e., within insulating spacer removal regions IRR shown in FIG. 37C.

Referring to FIGS. 39A-39C, the at least one conductive material of the continuous conductive material layer 46L can be selectively recessed by an etch process as in the first embodiment. Specifically, horizontal portions of the at least one conductive material can be removed from above the array of drain select level assemblies 115 and from around upper portions of the array of drain select level assemblies 115. The unetched remaining portions of the at least one conductive material overlying the isolation spacer layer 270 constitute the drain select gate electrodes 246, which are laterally spaced among one another by the drain select level dielectric strips 72. Further, the vertical portions of the at least one conductive material can be removed from inside the backside trenches 79 by the etch process. The duration of the isotropic etch process can be controlled to avoid removal of the drain select gate electrodes 246 and the electrically conductive layers 46.

The drain select gate electrodes 246 can be formed on the array of drain select level assemblies 115 and the drain select level isolation strips 72. Each of the drain select gate electrodes 246 can laterally encircle each of the drain select level assemblies 115 located between a neighboring pair of drain select level isolation strips 72. In one embodiment, each of the drain select gate electrodes 246 can include a pair of lengthwise sidewalls that generally extend along the first horizontal direction hd1 and contact a respective sidewall of the drain select level isolation strips 72. Each of the lengthwise sidewalls of the drain select gate electrode 246 can include a laterally alternating sequence of planar sidewall portions and convex sidewall portions. In one embodiment, each of the lengthwise sidewalls of the drain select gate electrode 246 can include a laterally alternating sequence of vertical planar sidewall portions and vertical convex sidewall portions. Each of the drain select gate electrodes 246 laterally surrounds respective rows of the drain select level assemblies 115. Each row of the drain select level assemblies 115 can be arranged along the first horizontal direction hd1. The top surface of each drain select gate electrode 246 can be located below the horizontal plane including the bottom surfaces of the drain regions 263 to avoid electrical shorts between the drain select gate electrodes 246 and the drain regions 263.

Each of the drain select gate electrodes 246 includes multiple horizontal portions that are located at different levels and vertical portions that are located adjacent to the lengthwise sidewalls of a neighboring pair of drain select level isolation strips 72. Specifically, each of the drain select level gate electrodes can include a top horizontal drain select gate electrode portion overlying the at least one insulating material strip (as embodied as a discrete portions of each of the insulating spacer layers 132), a bottom horizontal drain select gate electrode portion underlying the at least one insulating material strip, and vertically extending portions that connect the top horizontal drain select gate electrode portion and the bottom horizontal drain select gate electrode portion. If a plurality of insulating spacer layers 132 is present, at least one intermediate level horizontal drain select gate electrode portions can be adjoined to the vertically extending portions.

In one embodiment, each of the drain select gate electrodes 246 can have the same width along the second horizontal direction hd2 (e.g., bit line direction). In this case, each of the drain select gate electrodes 246 can have substantially the same resistance, which can be measured along the first horizontal direction hd1 (e.g., word line direction) between two end portions of each drain select gate electrode 246.

Referring to FIGS. 40A-40C, a dielectric fill material layer 78 is formed over the drain select gate electrodes 246 and in the backside trenches 79. The dielectric fill material layer 78 can include a planarizable dielectric material such as silicon oxide. The dielectric fill material layer 78 can be planarized to remove to provide a top surface that is coplanar with the top surfaces of the drain regions 263. For example, chemical mechanical planarization or a recess etch can be employed. The top surfaces of the drain select level isolation strips 72 and the dielectric fill material layer 78 can be within a same horizontal plane as the top surfaces of the drain regions 263. The dielectric fill material layer 78 can be formed over the drain select gate electrodes 246. In one embodiment, portions of the dielectric fill material layer 78 may be laterally spaced apart among one another by the drain select level isolation strips 72.

Alternatively, the planarized top surface of the dielectric fill material layer 78 can be formed over the horizontal plane including the top surfaces of the drain regions 163 and the drain select level isolation strips 72. In this case, the dielectric fill material layer 78 can be formed as a single continuous material layer.

Each portion of the dielectric fill material layer 78 that fills one of the backside trenches 79 is herein referred to as a dielectric wall structure 78T, which provides electrical isolation between laterally neighboring pairs of electrically conductive layers 46 that are located at the same level, i.e., at the same vertical distance from the top surface of the substrate (9, 10).

A discrete strip portion of each of the one or more insulating spacer layers 132 can be embedded within, and encapsulated within, the drain select gate electrodes 246. Multiple horizontal drain select gate electrodes 246 can be vertically spaced among one another by the discrete strip portions of the one or more insulating spacer layers 132, and can be continuously connected among one another by vertically extending portions 246A that contact the lengthwise sidewalls of a pair of drain select level isolation strips 72 located at peripheries of the respective drain select gate electrodes 246. Thus, the horizontal drain select gate electrodes 246 are electrically shorted to each other by the vertically extending portions 246A.

Referring to FIGS. 41A-41C, an alternative embodiment of the second exemplary structure can be derived from the second exemplary structure by modifying the pattern of the openings in the photoresist layer at the processing steps of FIGS. 32A-32C. Specifically, linear openings in the photoresist layer 277 are formed only over neighboring pairs of rows of drain select level assemblies 115, and are not formed over peripheral rows of the drain select level assemblies 115. In other words, each peripheral row (i.e., outermost row) of drain select level assemblies 115 is entirely covered with the photoresist layer 277 after lithographic patterning.

Subsequently, the anisotropic etch process of FIGS. 32A-32C can be performed to form laterally extending trenches 273. The number of the laterally extending trenches 273 in this alternate embodiment may be less than the number of the laterally extending trenches 273 in the second exemplary structure of FIGS. 32A-32C because the laterally extending trenches 273 are not formed in regions proximate to areas in which backside trenches are to be subsequently formed. The photoresist layer 277 can be subsequently removed, for example, by ashing.

Referring to FIGS. 42A-42C, the processing steps of FIGS. 13A-13C can be performed to form a sacrificial spacer material layer 274L.

Referring to FIGS. 43A-43C, the processing steps of FIGS. 14A-14C can be performed to form sacrificial spacers 274 within each of the laterally extending trenches.

Referring to FIGS. 44A-44C, the processing steps of FIGS. 15A-15C can be performed to form a drain select level isolation strip 72 within each unfilled volume of the laterally extending trenches.

Referring to FIGS. 45A-45C, the processing steps of FIGS. 36A-36C can be performed to form backside trenches 79.

Referring to FIGS. 46A-46C, the processing steps of FIGS. 37A-37C can be performed. The sacrificial material layers 42 can be removed selective to the insulating layers 32 and the memory stack structures 55. Backside recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The sacrificial matrix material layer 142 and the sacrificial spacers 274 can be removed from around the drain select level assemblies 115 and the drain select level isolation strips 72 above the top surface of the isolation spacer layer 270.

Drain select level lateral recesses 243 can be formed between the isolation spacer layer 270 and each remaining strip portion of a bottommost one of the insulating spacer layers 132. If two or more insulating spacer layers 132 are present, additional drain select level lateral recesses 243 can be formed between each vertically neighboring pair of the insulating spacer layers 132. Physically exposed surface portions of the optional epitaxial channel portions 11 and the semiconductor material layer 10 can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials as in previously described embodiments.

Referring to FIGS. 47A-47C, a backside blocking dielectric layer 44 can be deposited, for example, employing the processing steps of FIGS. 18A-18C. At least one conductive material can be subsequently deposited by a conformal deposition method as in the previously described embodiments. The at least one conductive material can include a metallic liner layer and a metallic fill material layer. The thicknesses of the metallic liner layer and the metallic fill material layer can be selected such that each backside recess 43 is completely filled with the metallic liner layer and the metallic fill material layer, while a backside cavity 79′ is present within each backside trench 79. The processing steps of FIGS. 18A-18C can be performed to deposit the at least one conductive material.

Each portion of the combination of the metallic liner layer and the metallic fill material layer that fills a backside recess constitutes an electrically conductive layer 46. Each portion of the combination of the metallic liner layer and the metallic fill material layer that is deposited below the horizontal plane including the bottom surfaces of the drain regions 263, and within volumes from which the sacrificial matrix material layer 272 and the sacrificial spacers 274 are removed, constitutes a drain select gate electrode 246. A continuous conductive material layer 46L is formed at peripheral portions of each backside trench 79, over each of the drain select gate electrodes 246.

Referring to FIGS. 48A-48C, the at least one conductive material of the continuous conductive material layer 46L can be selectively recessed by an etch process as in the first embodiment. Specifically, horizontal portions of the at least one conductive material can be removed from above the array of drain select level assemblies 115 and from around upper portions of the array of drain select level assemblies 115. The unetched remaining portions of the at least one conductive material overlying the isolation spacer layer 270 constitute the drain select gate electrodes 246, which are laterally spaced among one another by the drain select level dielectric strips 72. Further, the vertical portions of the at least one conductive material can be removed from inside the backside trenches 79 by the etch process. The duration of the etch process can be controlled to avoid removal of the drain select gate electrodes 246 and the electrically conductive layers 46.

The drain select gate electrodes 246 can be formed on the array of drain select level assemblies 115 and the drain select level isolation strips 72. Each of the drain select gate electrodes 246 can laterally encircle each of the drain select level assemblies 115 located between a neighboring pair of drain select level isolation strips 72. In one embodiment, each of the drain select gate electrodes 246 located between a neighboring pair of drain select level isolation strips 72 can include a pair of lengthwise sidewalls that generally extend along the first horizontal direction hd1 and contact a respective sidewall of the drain select level isolation strips 72. Each of the lengthwise sidewalls of the drain select gate electrode 246 can include a laterally alternating sequence of planar sidewall portions and convex sidewall portions. In one embodiment, each of the lengthwise sidewalls of the drain select gate electrode 246 can include a laterally alternating sequence of vertical planar sidewall portions and vertical convex sidewall portions.

In one embodiment, each of the drain select gate electrodes 246 located between a drain select level isolation strip 72 and a backside trench 79 can include a lengthwise sidewall that generally extends along the first horizontal direction hd1 and contacts a respective sidewall of the drain select level isolation strips 72. The lengthwise sidewall of the drain select gate electrode 246 can include a laterally alternating sequence of planar sidewall portions and convex sidewall portions. In one embodiment, the lengthwise sidewall of the drain select gate electrode 246 can include a laterally alternating sequence of vertical planar sidewall portions and vertical convex sidewall portions. Further, each of the drain select gate electrodes 246 located between a drain select level isolation strip 72 and a backside trench 79 can include a set of vertically coincident straight sidewalls that laterally extend along the first horizontal direction hd2, and is a portion of a sidewall of the backside trench 79.

Each of the drain select gate electrodes 246 laterally surrounds respective rows of the drain select level assemblies 115. Each row of the drain select level assemblies 115 can be arranged along the first horizontal direction hd1. The top surface of each drain select gate electrode 246 can be located below the horizontal plane including the bottom surfaces of the drain regions 263 to avoid electrical shorts between the drain select gate electrodes 246 and the drain regions 263.

In one embodiment, the drain select gate electrodes 246 bordering the backside trenches 79 can have a lower resistance than drain select gate electrodes 246 that do not border the backside trenches 79. A drain select gate electrode 246 bordering a backside trench 79 can have a greater width along the second horizontal direction hd2 than a drain select gate electrode 246 located between a neighboring pair of drain select level isolation strips 72. In this case, a drain select gate electrode 246 bordering a backside trench 79 can have a lower electrical resistance than a drain select gate electrode 246 formed between neighboring pair of drain select level isolation strips 72.

Referring to FIGS. 49A-49C, a dielectric fill material layer 78 is formed on the top surface of the drain select gate electrodes 246 and in the backside trenches 79. The dielectric fill material layer 78 can include a planarizable dielectric material such as silicon oxide. The dielectric fill material layer 78 can be planarized to remove to provide a top surface that is coplanar with the top surfaces of the drain regions 263. For example, chemical mechanical planarization or a recess etch can be employed. The top surfaces of the drain select level isolation strips 72 and the dielectric fill material layer 78 can be within a same horizontal plane as the top surfaces of the drain regions 263.

The dielectric fill material layer 78 can be formed over the drain select gate electrodes 246. In one embodiment, portions of the dielectric fill material layer 78 may be laterally spaced apart among one another by the drain select level isolation strips 72.

Alternatively, the planarized top surface of the dielectric fill material layer 78 can be formed over the horizontal plane including the top surfaces of the drain regions 163 and the drain select level isolation strips 72. In this case, the dielectric fill material layer 78 can be formed as a single continuous material layer.

Each portion of the dielectric fill material layer 78 that fills one of the backside trenches 79 is herein referred to as a dielectric wall structure 78T, which provides electrical isolation between laterally neighboring pairs of electrically conductive layers 46 that are located at the same level, i.e., at the same vertical distance from the top surface of the substrate (9, 10).

In an alternative embodiment, the drain select gate electrodes 246 can be formed separately from the other electrically conductive layers 46 (e.g., word lines and source select gate electrodes) using the separate processing steps shown in FIGS. 21A to 27C and described above. If desired the drain select gate electrodes 246 can be formed by selective metal deposition, while the other electrically conductive layers 46 are subsequently formed by non-selective metal deposition followed by etching the metal layer from the backside trenches as described above.

The various embodiments of the present disclosure can provide a three-dimensional memory device. The three-dimensional memory device can include: an alternating stack of insulating layers 32 and electrically conductive layers 46 located over a substrate (9, 10); an array of memory stack structures 55 extending through the alternating stack (32, 42) and arranged as rows that extend along a first horizontal direction hd1 and spaced apart along a second horizontal direction hd2. Each of the memory stack structures 55 comprises a memory film 50 and a memory level channel portion 60 contacting an inner sidewall of the memory film 50; an array of drain select level assemblies 115 overlying the alternating stack (32, 46) and having a same periodicity as the array of memory stack structures 55 along the first horizontal direction hd1 and the second horizontal direction hd2; drain select gate electrodes (146 or 246) laterally surrounding respective rows of the drain select level assemblies 115; and a first drain select level isolation strip 72 comprising a dielectric material and located between a neighboring pair of drain select gate electrodes (146 or 246) and including a pair of lengthwise sidewalls, wherein each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex concave sidewall portions, and wherein each of the convex concave sidewall portions is equidistant from a sidewall of a respective most proximal one of the drain select level assemblies 115. The distance from the respective most proximal one of the drain select level assemblies 115 can be the same as the thickness of a sacrificial spacer 274 that is employed during formation of the three-dimensional memory device.

In one embodiment, each of the drain select level assemblies 115 comprises a drain select level channel portion (160 or 260) contacting a respective memory level channel portion 60 and a gate dielectric (150 or 250) laterally surrounding the drain select level channel portion (160 or 260). In one embodiment, each of the gate dielectrics (150 or 250) has a cylindrical configuration, and top surfaces of the drain select gate electrodes (146 or 246) are adjoined to a respective subset of outer sidewalls of the gate dielectrics (150 or 250).

In one embodiment, each of the drain select level assemblies 115 comprises a drain region 263 contacting top surfaces of the drain select level channel portion (160 or 260) and optionally the gate dielectrics (150, 250). In one embodiment, a peripheral portion of the drain region 263 protrudes outward from an outer sidewall of the gate dielectric (150 or 250) and overhangs the gate dielectric (150 or 250) due to lateral recessing of a sacrificial matrix material layer 272 or a topmost sacrificial matrix material layer 142.

In one embodiment, the memory film 50 comprises a stack, from outside to inside, of a blocking dielectric 52, charge storage elements as embodied as portions of a charge storage layer 54 located at levels of the electrically conductive layers 46, and a tunneling dielectric 56; and the gate dielectric (150 or 250) comprises a material that is different from a material of the charge storage elements. A dielectric fill material layer 78 can contact, and laterally surround, each of the drain regions 263, and can contact top surfaces of the drain select gate electrodes (146 or 246).

The three-dimensional memory device can further include a second drain select level isolation strip 72. In one embodiment, each of the pair of lengthwise sidewalls of the first drain select level isolation strip 72 contacts a respective one of the drain select gate electrodes (146 or 246) as illustrated in FIGS. 20A, 27A, and 40A; the second drain select level isolation strip 72 comprises a first lengthwise sidewall and a second lengthwise sidewall; the first lengthwise sidewall contacts a respective one of the drain select gate electrodes (146 or 246); and an entirety of the second lengthwise sidewall contacts a sidewall of a portion of the dielectric fill material layer 78 as illustrated in FIGS. 20B, 27B, and 40B.

In one embodiment, each respective drain select level assembly 115 is laterally surrounded by only one drain select gate electrode 146. In another embodiment, insulating spacer strip is 132 located between a first horizontal drain select gate electrode 246 and a second horizontal drain select gate electrode 246 which is electrically connected to the first horizontal drain select gate electrode by a vertically extending portion 246A.

In one embodiment, each of the gate dielectrics 250 contacts, and is laterally encircled by, a respective one of the vertically extending portions of the drain select gate electrodes 246. In one embodiment, each drain select level channel portion (160, 260) contacts a top surface of a respective enhanced doping region 63 that contacts a sidewall of, and embedded within, a respective memory level channel portion 60.

In one embodiment, each laterally alternating sequence of planar sidewall portions and convex concave sidewall portions vertically extend from a bottom surface of the first drain select level isolation strip 72 to a top surface of the first drain select level isolation strip 72.

Each of exemplary structures of the present disclosure can include a three-dimensional memory device. In one embodiment, the three-dimensional memory device comprises a vertical NAND memory device. The electrically conductive layers 46 can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. The substrate (9, 10) can comprise a silicon substrate. The vertical NAND memory device can comprise an array of monolithic three-dimensional NAND strings over the silicon substrate. At least one memory cell (as embodied as a portion of a charge storage layer 54 at a level of an electrically conductive layer 46) in a first device level of the array of monolithic three-dimensional NAND strings can be located over another memory cell (as embodied as another portion of the charge storage layer 54 at a level of another electrically conductive layer 46) in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate can contain an integrated circuit comprising a driver circuit for the memory device located thereon. The electrically conductive layers 46 can comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate (9, 10), e.g., between a pair of backside trenches 79. The plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. The array of monolithic three-dimensional NAND strings can comprise: a plurality of semiconductor channels (11, 60, 63, 160 or 260). The plurality of semiconductor channels can additionally include a horizontal surface portion of the semiconductor material layer 10 between the pedestal channel portions 11 and a source region (not shown), which has a doping of the second conductivity type and is contacted by a source contact via structure. At least one end portion (60, 63, 160 or 260) of each of the plurality of semiconductor channels (11, 60, 63, 160 or 260) extends substantially perpendicular to a top surface of the substrate (9, 10); and a plurality of charge storage elements (as embodied as charge trapping material portions). Each charge storage element can be located adjacent to a respective one of the plurality of semiconductor channels (11, 60, 63, 160 or 260).

According to another aspect of the present disclosure, methods for formation of a spaceless drain select level isolation structure is provided, which provides on-pitch drain select gate electrode architecture in which memory stack structures are aligned to the drain select gate electrodes with no additional space allocated for the drain select level isolation structure, thereby providing a smaller array size. This feature can be advantageously employed to provide scaling of three-dimensional memory devices.

In one embodiment, one or more silicon nitride layers (272, 142) can be employed as sacrificial drain select level layers, which are subsequently selectively removed by a wet etch process either during word line sacrificial silicon nitride removal process or during a separate removal process.

In the first embodiment, single-level thick drain select gate electrodes can be employed. The drain select gate RC difference between the edge strings and the center strings of the drain select gate electrode is small. Single replacement process to form the drain select gate electrodes 246 together with the other electrically conductive layers 46, or a dual replacement process to form the drain select gate electrodes 246 separately from the other electrically conductive layers 46, may be employed.

In the second embodiment, multi-level drain select gate electrodes can be employed. Uniform drain select gate isolation structure flow provides more uniform drain select gate RC for each string of the drain select gate electrodes. Unbalanced string flow gives relatively small RC for edge strings of the drain select gate electrodes. Selective metal deposition may used in this process. Dual replacement may be employed in the second embodiment. For example, the word line electrically conductive layers can employ non-selective metal deposition, and the drain select gate electrodes can employ a selective metal deposition process.

Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

an array of memory stack structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and spaced apart along a second horizontal direction, wherein each of the memory stack structures comprises a memory film and a memory level channel portion contacting an inner sidewall of the memory film;

an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures along the first horizontal direction and the second horizontal direction;

drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies; and

a first drain select level isolation strip comprising a dielectric material located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls, wherein each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex concave sidewall portions.

2. The three-dimensional memory device of claim 1, wherein each of the drain select level assemblies comprises a drain select level channel portion contacting a respective memory level channel portion and a gate dielectric laterally surrounding the drain select level channel portion.

3. The three-dimensional memory device of claim 2, wherein:

each of the gate dielectrics has a cylindrical configuration;

top surfaces of the drain select gate electrodes are adjoined to a respective subset of outer sidewalls of the gate dielectrics; and

each of the convex concave sidewall portions is equidistant from a sidewall of a respective most proximal one of the drain select level assemblies.

4. The three-dimensional memory device of claim 2, wherein each of the drain select level assemblies comprises a drain region contacting top surfaces of the drain select level channel portion.

5. The three-dimensional memory device of claim 4, wherein a peripheral portion of the drain region protrudes outward from an outer sidewall of the gate dielectric and overhangs the gate dielectric.

6. The three-dimensional memory device of claim 4, wherein:

the memory film comprises a stack, from outside to inside, of a blocking dielectric, charge storage elements, and a tunneling dielectric; and

the gate dielectric comprises a material that is different from a material of the charge storage elements.

7. The three-dimensional memory device of claim 4, further comprising a dielectric fill material layer contacting, and laterally surrounding, each of the drain regions, and contacting top surfaces of the drain select gate electrodes.

8. The three-dimensional memory device of claim 7, further comprising a second drain select level isolation strip, wherein:

each of the pair of lengthwise sidewalls of the first drain select level isolation strip contacts a respective one of the drain select gate electrodes;

the second drain select level isolation strip comprises a first lengthwise sidewall and a second lengthwise sidewall;

the first lengthwise sidewall contacts a respective one of the drain select gate electrodes; and

an entirety of the second lengthwise sidewall contacts a sidewall of a portion of the dielectric fill material layer.

9. The three-dimensional memory device of claim 7, wherein each respective drain select level assembly is laterally surrounded by only one drain select gate electrode.

10. The three-dimensional memory device of claim 7, wherein an insulating spacer strip is located between a first horizontal drain select gate electrode and a second horizontal drain select gate electrode which is electrically connected to the first horizontal drain select gate electrode by a vertically extending portion.

11. The three-dimensional memory device of claim 7, wherein each of the gate dielectrics contacts, and is laterally encircled by, a respective one of the vertically extending portions of the drain select gate electrodes.

12. The three-dimensional memory device of claim 1, wherein each drain select level channel portion contacts a top surface of a respective enhanced doping region that contacts a respective vertical semiconductor channel.

13. The three-dimensional memory device of claim 1, wherein each laterally alternating sequence of planar sidewall portions and convex concave sidewall portions vertically extend from a bottom surface of the first drain select level isolation strip to a top surface of the first drain select level isolation strip.