Semiconductor device including three voltage generator circuits and two transistors configured to short-circuit respective different combinations of the voltage generator circuits

Abstract

According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first mos transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first mos transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first mos transistor. The controller controls a period in which the first mos transistor is kept in an on state based on time.

Description

thetime during operation that, this is true in applies to all of the disclosed embodiments.

<Before Time t0>

As shown in FIG. 7, signal TG is set to the ‘L’ level before time t0. Therefore, the MOS transistor 23 is turned off. Further, enable signal EN is set at the ‘L’ level. Therefore, the MOS transistor 71 is also turned off. As a result, the potentials of the nodes 1′2 N2, N3 are respectively maintained at voltage VREAD and voltage VREADLA.

(Time t0>

Next, enable signal EN is set to the ‘H’ level by means of the control unit 60 at time to. Thus, the local pump 61 outputs a signal of ‘H’ level to the gate of the MOS transistor 71. As a result, the MOS transistor 71 is turned on. In other words, the nodes N2 and N3 are short-circuited. Then, signal TG output from the block decoder 20 of the row decoder 2 is set to the ‘H’ level to turn on the MOS transistor 23. Therefore, loads (parasitic capacitors of the word lines WL) are applied to the output terminals of the first voltage generator circuit 41 and second voltage generator circuit 42. At this time, signal TG maintains the ‘H’ level after time t0. Therefore, the potentials of the nodes N2, N3 are temporarily set to 0 [V] from respective voltage VREAD and voltage VREADLA generated from the first, second voltage generator circuits 41, 42.

Then, after time t0, the potentials of the nodes N2, N3 rise at the same rate in a period in which enable signal EN is kept at the ‘H’ level or in a period in which the MOS transistor 71 is kept in the on s=ate. Likewise, the potentials of the word lines WL connected to the nodes N2, N3 also rise at the same rate.

<Time t1>

When time t1 is reached, the potentials of the nodes N2, N3 and the unselected word lines WL are reached voltage VREAD. Then, the controller 6 switches enable signal EN to the ‘L’ level. That is, an output of the local pump 61 is set to the ‘L’ level. As a result, the MOS transistor 71 is turned off.

Therefore, the nodes N2 and N3 are electrically isolated. Therefore, the potential of the node N2 is set to voltage VREAD and the potential of the unselected word line WL is maintained at voltage VREAD.

<After Time t1>

After time t1, the potential of the node N3 rises to voltage VREADLA. This is because the second voltage generator circuit 42 generates voltage VREADLA. That is, the potential of the unselected word line WL to which voltage VREADLA is transferred rises to voltage VREADLA after time t1.

Voltage Transfer Operation at Read Operation Time (Second Case)>

Next, the voltage transfer operation of the NAND flash memory is explained with reference to FIG. 8. FIG. 8 shows a case wherein voltage VREAD generated from the first voltage generator circuit 41 is higher than voltage VREADLA. That is, voltage VREADLA=voltage (VREAD-α). Further, the explanation for the same operation as of the read operation(first case) explained above, as in the above explanation of FIG. 7, is omitted.

As shown in FIG. 8, the potential of the node N3 rises at the same rising rate as the potential of the node N2 after time t0 like the case of the above operation (first case). As described above, voltage VREAD>voltage VREADLA. Therefore, the controller 6 switches enable signal EN to the ‘L’ level at time t1 at which the potentials of the nodes N2, N3 reach voltage VREADLA. That is, an output of the local pump 61 is set to the ‘L’ level. As a result, the MOS transistor 71 is turned off and the nodes N2 and N3 are electrically isolated. Therefore, the potential of the node N3 is maintained at voltage VREADLA. In other words, the potential of the unselected word line WL electrically connected via the node N3 is also maintained at voltage VREADLA.

After time t1, the potential of the node N2 rises to voltage VREAD. This is because the first voltage generator circuit 41 generates voltage VREAD. That is, the potential of the unselected word line WL to which voltage VREAD is transferred rises to voltage VREAD after time t1.

<Effect of this the First Embodiment>

In a semiconductor device and the control method for the semiconductor device according to this embodiment, the following effect (1) can be attained.

(1) Operation Reliability can be Enhanced:

The effect of this the first embodiment is explained below. In the semiconductor device and the control method for the semiconductor device according to this embodiment, the short circuit 7 that short-circuits the output terminal (node N2) of the first voltage generator circuit 41 and the output terminal (node N3) of the second voltage generator circuit 42 and the controller 6 that has a function of controlling the above circuit based on time are provided as shown in FIG. 5. When explaining the effect, for example, a case wherein the word line WL31 is used as the selected word line WL is considered like the above case.

According to this embodiment, the controller 6 short-circuits the output terminals of the first voltage generator circuit 41 and second voltage generator circuit 42 as required. In the case of short-circuiting, the parasitic capacitors of the word lines WL0 to WL30 and word lines WL33 to WL63 are applied as loads to the first voltage generator circuit 41 and second voltage generator circuit 42. That is, the load of the first voltage generator circuit 41 is alleviated.

Further, it a case can be prevented that in which only the word line WL32 is dealt with as the load (parasitic capacitor) as viewed from the second voltage generator circuit 42 that outputs voltageVREADLA.

Therefore, for example, the rising rate of voltage VREADLA transferred to the word line WL32 can be suppressed from becoming higher than the rising rate of voltage VREAD transferred to the word lines WL0 to WL30 and word lines WL33 to WL63.

That is, in this embodiment, the controller 6 snort-circuits short-circuits the output terminal of the first voltage generator circuit 41 that generates voltage VREAD and the output terminal of the second voltage generator circuit 42 that generates voltage VREADLA in a period of (t1-t0). That is, as shown in FIG. 7 and FIG. 8, the potentials of the nodes N2 and N3 that are the output terminals thereof are set to the same potential in the period (t1-t0). If the selected word line WLN is WL31, the potentials of the word lines WL0 to WL30 and word lines WL32 to WL63 are set to the same potential. As a result, the potentials of the word lines WL0 to WL30 and word lines WL32 to WL63 rise at the same rising rate and then the potentials of the word lines WL0 to WL30 and word lines WL33 to WL63 are set to voltage VREAD after time t1.

That is, the controller 6 short-circuits the output terminal of the first voltage generator circuit 41 and the output terminal of the second voltage generator circuit 42 in a period of (t1-t0). Therefore, although the potential of the word line WL32 is set to voltage VREADLA at a certain time t, the potentials of the word lines WL0 to WL30 and word lines WL33 to WL63 are still kept at 0 [V] and occurrence of a potential difference between the word lines WL can be prevented. This is would be the same even if the number of word lines WL for each block BLK unit becomes larger. Therefore, it is possible to solve a problem that, for example, only the potential of the word line WL32 is set to voltage VREADLA and, as a result, the potential of the n⁺-type impurity diffusion layer 103 in the memory cell transistor MT whose control gate 107 is connected to the word line WL32 is boosted and an abrupt potential difference occurs between the n⁺-type impurity diffusion layer 103 and the control gate 107 of the memory cell transistor MT corresponding to the word line WL33.

Thus, a voltage approximately equal to voltage VREADLA will not be applied between the n⁺-type impurity diffusion layer 103 whose potential rises to a value near voltage VREADLA, for example, and the control gate 107 functioning as the word line WL33. As a result, as shown in FIG. 9, a leakage current (GIDL) will not occur due to band-to-band tunneling in a portion in which the drain region and the control gate 107 functioning as the word line WL32 overlap.

As a result, the GIDL current will not occur and the operation reliability can be enhanced because the above voltages are transferred to the word lines WL.

Further, voltages are transferred to the word lines WL0 to WL30 and word lines WL32 to WL63 of the selected block BLK by means of the first, second voltage generator circuits 41, 42 in the period (t1-t0). That is, the voltage driving ability (pumping ability) for loads of the word lines WL0 to WL30 and word lines WL32 to WL63 can be enhanced by providing the second voltage generator circuit 42 in addition to the first voltage generator circuit 41. Therefore, a time required for reaching voltage VREAD can be reduced in comparison with a case wherein the potentials of the word lines WL0 to WL30 and word lines WL33 to WL63 are charged to voltage VREAD only by means of the first voltage generator circuit 41. That is, as shown in FIG. 7 and FIG. 8, the time is reduced from t′1 to (t1-t0), and therefore, the time required for shifting the operation to the data read operation (sense) by the sense amplifier 5 in the next operation can be reduced.

In this case, t′1 indicates a time required for the potentials of the word lines WL0 to WL30 and word lines WL33 to WL63 to reach voltage VREAD after the potential of the word line WL32 has reached voltage VREADLA in a case where the output terminals are not short-circuited. Further, it is supposed assumed that the relationship of t′1>(t1-t0) is set. Thus, the operation speed of the whole circuit can be enhanced.

<Modification>

Next, a semiconductor device and the control method for the semiconductor device according to a modification of the first embodiment is explained with reference to FIG. 10. FIG. 10 is a time chart for illustrating a voltage transfer operation at a read operation time in a NAND flash memory according to the modification.

FIG. 10 is a time chart showing enable signal EN supplied to the local pump 61, a potential applied to the gate of the MOS transistor 71, signal TG, the on·off state of the MOS transistor 23, potentials of the nodes N2, N3 and potentials of the word lines WL.

In the modification, a case of voltage VREAD>voltage VREAD > voltage VREADLA is explained. That is, the relationship of voltage VREADLA=voltage (VREAD-α) is set. The timing of the voltage transfer operation is controlled by the controller 6. The same operation as the read operation explained in with respect to the first embodiment is emitted omitted. Further, the selected word line WLN is set to WL31. That is, voltage VREADLA is transferred to the unselected word line WL32 and voltage VREAD is transferred to the other unselected word lines WL0 to WL30 and unselected word lines WL33 to WL63.

<Time t0 to t1>

As shown in FIG. 10, a signal supplied to the gate of the MOS transistor 71 is set to the ‘L’ level by means of the controller 6 at time t1 before the potentials of the nodes N2, N3 and word line WL reach voltage VREADLA. That is, enable signal EN supplied to the local pump 61 is set to the ‘L’ level by means of the control unit 60 at time t1. As a result, the MOS transistor 71 is turned off and the nodes N2 and N3 are electrically isolated.

Then, since the load for the second voltage venerator generator circuit 42 is set to the unselected word line WL32, the rising rate of voltage VREADLA generated from the second voltage generator circuit 42 is increased at time t1. That is, a voltage inclination of voltage VREADLA is made abrupt.

<Time t2 to t3>

The potentials of the node N3 and unselected word line WL32 reach voltage VREADLA at time t2. Then, the potentials of the unselected word lines WL0 to WL30 and unselected word lines WL33 to WL63 reach voltage VREAD at time t3.

<Effect of Modification>

In the semiconductor device and the control method for the semiconductor device according to the modification, the following effect (2) can be obtained in the case of voltage VREAD >voltage > voltage VREADLA.

(2) Operation Speed can be Enhanced:

In the semiconductor device and the control method for the semiconductor device according to the modification, the controller 6 turns off the MOS transistor 71 at time t1 before the potential of the node N3 reaches voltage VREADLA. As a result, the voltage transfer operation with respect to the word line WL can be smoothly performed. This is because the MOS transistor 71 is not turned off immediately after the potential of the node N3 has reached voltage VREADLA.

Therefore, it becomes possible to prevent the potentials of the node N3 and word line WL32 from overshooting from voltage VREADLA immediately after the MOS transistor 71 is turned off, that is, the nodes N2 and N3 are electrically isolated.

Based on the above explanation, in the semiconductor device and the control method for the semiconductor device according to the modification of this embodiment, the time required for a voltage overshooting from voltage VREADLA to return to voltage VREADLA can be prevented from being increased. Thus, the operation speed can be enhanced and the operation speed of the whole chip can be enhanced according to the semiconductor device of this embodiment.

[Second Embodiment]

Next, a semiconductor device and the control method for the semiconductor device according to a second embodiment is explained. The semiconductor device according to the second embodiment further includes a sixth voltage generator circuit 46 that generates and outputs voltage VREADK. The explanation for the same configuration as that of the first embodiment is omitted.

FIG. 11 is a block diagram of a voltage generator circuit 4 provided in the semiconductor device according to this the second embodiment. In FIG. 11, the third voltage generator circuit 43, fourth voltage generator circuit 44 and fifth voltage generator circuit 45 are emitted omitted.

The voltage generator circuit 4 further includes the sixth voltage generator circuit 46 and short circuit 9 as shown in FIG. 11. A MOS transistor 91 functions as a short circuit. One end of the current path of the MOS transistor 91 is connected to a node N3, the other end thereof is connected to a node N4 and the gate thereof is supplied with a signal from the controller 6. Therefore, the nodes N2, N3 and N4 are short-circuited by causing the controller 6 to supply a signal of ‘H’ level to the MOS transistor 91 in response to enable signal EN.

Further, the output terminal of the sixth voltage venerator generator circuit 46 is connected to the node N4. The timing at which the ‘H’ level signal is supplied to the gate of the MOS transistor 91 is set at the same timing as in the case of the MOS transistor 71. As a result, the potentials of the nodes N2 to N4 are set to the same potential while the MOS transistors 71 and 91 are kept in the on state.

Further, the sixth voltage generator circuit 46 has the same configuration as that of FIG. 4 in the first embodiment. That is, it the sixth voltage generator circuit 46 generates voltage VREADK by controlling a value of the limiter 50. Voltage VREADK is a voltage that turns on the memory cell transistor MT and the magnitude thereof can be changed based on the threshold distribution of the memory cell transistor MT like voltage VREADLA.

That is, voltage VREADK is set to voltage (VREAD+β) or voltage (VREAD-β) (voltages (VREAD-β) and voltage (VREAD+β) are hereinafter respectively referred to as voltages VREADK₋ and VREADK₊ as required). Values of α and β may be set to the same value or set to satisfy the relationship of α>β or α<β. Further, voltage VREADK₋ may be set to voltage (VREAD+β) as required. That is, in this case, voltage VREADK is always set higher than voltage VREAD.

If the selected word line WL is set to an Nth word line in FIG. 1, voltage VREADK is a voltage to be transferred to the (N−1)th word line WL or (N−1)th word line WL and (N+1)th word line WL.

The local pump 61 may use the potential of the node N4 as a reference voltage in addition to the potential of the node N3. That is, if the threshold voltage of the MOS transistor 91 is set to the same voltage as threshold voltage Vth₇₁ of the MOS transistor 71, the local pump 61 may use the potential of the node N3 or N4 as a reference voltage and apply the potential of the sum of the reference voltage and Vth₇₁ to the gates of the MOS transistors 71 and 91.

In a case where the threshold voltage of the MOS transistor 91 is set to Vth₉₁, the local pump 61 may apply a voltage (potential of the node N3 or N4+voltage Vth₉₁) to the gates of the MOS transistors 71 and 91 if voltage Vth₉₁>voltage Vth₇₁. Further, if voltage Vth₇₁>voltage Vth₉₁, the local pump 61 may apply a voltage (potential of the node N3 or N4+voltage Vth₇₁) to the gates of the MOS transistors 71 and 91.

If voltages Vth₇₁, Vth₉₁ are different from each other, the local pump 61 may separately supply ‘H’ level signals to the gates of the MOS transistors 71 and 91. That is, the local pump 61 may apply a voltage (potential of the node N3 or N4+voltage Vth₉₁) to the gate of the MOS transistor 91 while applying a voltage (potential of the node N3 or N4+voltage Vth₇₁) to the gate of the MOS transistor 71.

<Read Operation of NAND Flash Memory>

Next, first and second cases of the read operation by use of voltages VCGR, VREAD, VREADLA and VREADK in the NAND flash memory are explained with reference to FIG. 12A, FIG. 12B and FIG. 13.

<First Case of Read Operation>

First, the first case of the read operation is explained with reference FIG. 12A, FIG. 12B. In the first case of the read operation, a case where voltage VREADK is transferred only to the word line WL(N−1) when voltage VCGR is transferred to the selected word line WLN is explained. In this case, voltage VREADLA is transferred to the word line WL(N+1). Since the read method for the selected word line WLN and unselected word line WL(N+1) is the same as that in the first embodiment, the explanation thereof is omitted.

<Step 1>

As shown in FIG. 12A, the first voltage generator circuit 41 transfers voltage VREAD to the word line WL(N−3) to word line WLN, word line WL(N+2) and word line WL(N+3). Further, the sixth voltage generator circuit 46 transfers voltage VREAD to the word line WL(N−1).

<Step 2>

As shown in FIG. 12B, the sixth voltage generator circuit 46 transfers voltage VREADK to the word line WL(N−1). As a result, the memory cell transistors MT connected to the word lines WL(N−3) to WL(N+3) are turned on to permit the sense amplifier 5 to perform the data read operation via a bit line BL (not shown).

<Second Case of Read Operation>

Next, a case wherein voltage VREADK is transferred to the word line WL(N−1) and word line WL(N+1) is explained with reference to FIG. 13. FIG. 13 shows a state in which data is read from the memory cell corresponding to the selected word line WLN after step 1 of FIG. 12. That is, the third voltage generator circuit 43 transistors voltage VCGR to the word line WLN.

As shown in FIG. 13, voltage VREADK is transferred to the word lines WL(N−1) and WL(N+1). As described before, voltage VREADK is set to either voltage VREADK₋ or voltage VREADK₊. That is, voltage VREADK is transferred to the word line WL(N−1) and word line WL(N+1) by the number of times corresponding to the number of cases.

The memory cell transistors MT whose control gates 107 are applied with voltages VREADK, VREAD and VCGR are turned on. As a result, channels are formed directly below the memory cell transistors MT connected to the word lines WL(N−3) to WL(N+3) and the sense amplifier 5 performs the data read operation via the bit line BL (not shown).

<Magnitude Relationship between Voltage VREAD, Voltage VREADLA and Voltage VREADK>

Next, the magnitude relationship between voltages generated from the first voltage generator circuit 41, second voltage generator circuit 42 and sixth voltage generator circuit 46 is explained. The magnitude relationship between voltages generated from the first voltage generator circuit 41, second voltage generator circuit 42 and sixth voltage generator circuit 46 is divided into the following five patterns (I) to (V). In this case, the relationships at the data read operation times in FIG. 12A and FIG. 12B are set to (I) to (V) and the data read voltage relationships in FIG. 13 are set to (VI) and (VII).

(I) Voltage VREAD≤voltage VREADLA≤voltage VREADK

(II) Voltage VREADK≤voltage VREAD≤voltage VREADLA

(III) Voltage VREADLA23 voltage VREAD≤voltage VREADK

(IV) Voltage VREADK≤voltage VREADLA≤voltage VREAD

(V) Voltage VREAD≤voltage VREADK≤voltage VREADLA

(VI) Voltage VREADK₋<voltage VREAD <voltage VREADK₊

(VII) Voltage VREAD≤voltage VREADK₋≤voltage VREADK₊

<Voltage Transfer Operation at Read Operation Time (Third Case)>

Next, the voltage transfer operation at the time of a read operation time in the NAND flash memory explained above is explained with reference to FIG. 14. FIG. 14 is a time chart of enable signal EN supplied to the local pump 61, a potential applied to the gate of the MOS transistor 71, potentials of the nodes N2, N3 and potentials of the word lines WL. The timings of the voltage transfer operations are controlled by the controller 6. In this case one example, the potentials of the nodes N2, N3 in the case (I) are raised as one example. Further, the explanation for the same operation as the read operation (first and second cases) explained above is omitted.

<Before Time t0>

As shown in FIG. 14, signal TG is set to the ‘L’ level to turn off the MOS transistor 23 before time t0 and the potentials of the nodes N2 to N4 are respectively set to voltages VREAD, VREADLA and VREADK.

(Time t0 to t1>

After time t0, the MOS transistors 71, 91 are turned on to short-circuit the nodes N2 to N4. Further, since signal TG is set at the ‘H’ level, the MOS transistor 23 is turned on, that is, the load (parasitic capacitor of the word line WL) and the nodes N2 to N4 are electrically connected. Therefore, output voltages of the first, second and sixth voltage generator circuits 41, 42 and 46 are temporarily reduced and then the potentials of the nodes N2 to N4 rise at the same rising rate.

When time t1 is reached, the controller 6 switches enable signal EN to the ‘L’ level. That is, an output of the local pump 61 is set to the ‘L’ level. At this time t1, since the relationship of voltage VREAD voltage VREADLA <voltage < voltage VREADK is set, the controller 6 controls time to set the potentials of the nodes N2 to N4 to voltage VREAD at time t1. Further, at this time t1, the potential of the word line WL is set to voltage VREAD.

Since the MOS transistors 71, 91 are simultaneously turned off at time t1, the nodes N2 to N4 are electrically isolated.

<Time t1 to t3>

The potential of the node N3 reaches voltage VREADLA at time t2. For example, if the selected word line WLN is set to WL31, the potential of a word line WL32 adjacent to the selected word line WL31 reaches voltage VREADLA.

Further, the potential of a word line WL30 and the potential of the node N4 reach voltage VREADK at time t3.

The voltage transfer operation in the case (I) is explained above, but the same operation is performed in the cases (II) to (V). That is, the controller 6 maintains the on state of the MOS transistors 71 and 91 to short-circuit the nodes N2 to N4 until the potential one of the nodes N2 to N4 reaches one of voltages VREAD, VREADLA and VREADK.

After this, when the potential of one of the nodes N2 to N4 reaches one of the above voltages, the MOS transistors 71, 91 are turned off. Then, the potential of the node whose potential does not reach a desired voltage rises to a voltage generated from the voltage generator circuit 4.

<Effect of this Embodiment>

In the semiconductor device and the control method for the semiconductor device according to this the second embodiment, the following effect (1) can be attained. That is, the operation reliability of the semiconductor device can be enhanced. In the semiconductor device and the control method for the semiconductor device according to this embodiment, the potentials of the word lines WL to which voltages VREADLA, VREADK and VREAD are transferred rise at the same rising rate even when voltage VREADK is transferred to the word line WL in addition to voltage VREADLA explained in the first embodiment. Therefore, there occurs no problem that a time lag occurs in the potential rising operation of the word line WL as in the conventional case explained in the first embodiment. That is, in the semiconductor device according to this embodiment, a GIDL current can be suppressed and the operation reliability can be enhanced.

If one of voltages VREADLA and VREADK is higher than voltage VREAD, the controller 6 performs the operation explained in the modification to attain the effect (2). That is, also, in this the second embodiment, enable signal EN is switched to the ‘L’ level to turn off the MOS transistors 71, 91 before the potentials of the nodes N2 to N4 reach one of voltages VREADLA and VREADK in the cases (II), (III) and (IV). As a result, the voltage transfer operation with respect to the word line WL can be smoothly performed and a problem that an operation delay occurs due to overshooting from a desired voltage can be avoided.

Further, in the semiconductor device according to this the second embodiment, the controller 6 transfers the sum of the threshold voltages of the MOS transistors 71, 91 and a second voltage to the gates of the MOS transistors 71 and 91 while monitoring the second potential of the second node.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A semiconductor device comprising:

a first voltage generator circuit which outputs a first voltage to a first node;

a second voltage generator circuit which outputs a second voltage to a second node;

a first mos transistor capable of short-circuiting the first node and second node; and

a controller which performs a control operation to short-circuit the first node and second node by turning on the first mos transistor, controlling a period in which the first mos transistor is kept in an on state based on time.

2. The device according to claim 1, wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node,

when a potential of the first load reaches the second voltage in a case where the first voltage is higher than the second voltage at a read time, the controller turns off the first mos transistor.

3. The device according to claim 1, wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node,

in a case where the second voltage is higher than the first voltage at a read time, the controller turns off the first mos transistor before a potential of the second load reaches the first voltage.

4. The device according to claim 1, wherein the first mos transistor is one of an n-type intrinsic mos transistor, depression-type mos transistor, and enhancement-type mos transistor.

5. The device according to claim 1, wherein the controller

senses a potential of the second node, and

transfers a voltage equal to the sum of the above potential and a threshold voltage of the first mos transistor to the gate of the first mos transistor.

6. The device according to claim 1, further comprising:

a third voltage generator circuit which outputs a third voltage to a third node; and

a second mos transistor capable of short-circuiting the second node and the third node,

wherein the controller simultaneously performs on and off switching operations of the first mos transistor and second mos transistor.

7. The device according to claim 6, wherein the controller

senses a potential of one of the second node and the third node, and

transfers one of a first voltage equal to the sum of the above potential and a first threshold voltage of the first mos transistor and a second voltage equal to the sum of the above potential and a second threshold voltage of the second mos transistor to the gates of the first and second mos transistors.

8. The device according to claim 1, further comprising:

a memory cell array including plural memory cells whose current paths are serially connected and each of which includes a charge storage layer and control gate; and

word lines connected to the control gates of the memory cells and each used as one of the first and second loads;

wherein the first and second voltage generator circuits transfer one of the first and second voltages to the word lines.

9. A semiconductor device comprising:

a memory cell array including i memory cells (i is an integral number larger than 2) capable of holding data each of which includes a charge storage layer and control gate and the i memory cells are serially connected along a current path; and

a voltage generator circuit which generates a first voltage and second voltage, transferring the first and second voltages to word lines connected to the control gates of the memory cells,

wherein the voltage generator circuit

transfers the first voltage to the word line connected to the control gate of the ith memory cell, and

transfers the second voltage to the word lines connected to the control gates of the (i+1)th and (i+2)th memory cells which are arranged on a drain side of the ith memory cell.

10. The device according to claim 9, wherein the first voltage is a voltage corresponding to data held by the ith memory cell.

11. The device according to claim 9, further comprising:

a mos transistor capable of short-circuiting a first node and second node; and

a controller which performs a control operation to turn on the mos transistor to short-circuit the first node and second node,

wherein the voltage generator circuit includes

a first voltage generator circuit which generates the first voltage and outputs the first voltage to the first node, and

a second voltage generator circuit which generates the second voltage and outputs the second voltage to the second node, and

the controller controls a period in which the mos transistor is maintained in an on state based on time.

12. The device according to claim 11, wherein the controller

senses a potential of the second node, and

transfers a voltage equal to the sum of the above

potential and a threshold voltage of the mos transistor to the gate of the mos transistor.

13. The device according to claim 9, wherein the mos transistor is one of an n-type intrinsic mos transistor, depression-type mos transistor, and enhancement-type mos transistor.

14. The device according to claim 11, wherein a word line used as a first load is connected to the first node, and a word line used as a second load larger than the first load is connected to the second node, and

in a case where the second voltage is higher than the first voltage, the controller turns off the first mos transistor before a potential of the second load reaches the first voltage.

15. A control method of a semiconductor device comprising:

causing a first voltage generator circuit to generate a first voltage and output the first voltage to a first node;

causing a second voltage generator circuit to generate a second voltage and output the second voltage to a second node;

causing a controller to set a first mos transistor in an on state and short-circuit the first node and second node; and

causing the controller to control a period in which the first mos transistor is maintained in the on state based on time.

16. The method according to claim 15, further comprising:

causing the first voltage generator circuit to transfer the first voltage to a first load via the first node;

causing the second voltage generator circuit to transfer the second voltage higher than the first voltage to a second load larger than the first load via the second node; and

causing the controller to turn off the first mos transistor before a potential of the second load reaches the first voltage.

17. The method according to claim 15, further comprising:

causing the first voltage generator circuit to transfer the first voltage to a first load via the first node;

causing the second voltage generator circuit to transfer the second voltage to a second load larger than the first load via the second node; and

if the first voltage is higher than the second voltage at a read time, causing the controller to turn off the first mos transistor at the timing of a potential of the first load reaching the second voltage.

18. The method according to claim 15, further comprising:

causing the controller to sense a potential of the second node; and

causing the controller to transfer a voltage equal to the sum of the above potential and a threshold voltage of the first mos transistor to the gate of the first mos transistor.

19. The method according to claim 15, further comprising:

causing a third voltage generator circuit to generate a third voltage and output the third voltage to a third node;

causing the controller to turn on the first and second mos transistors and short-circuit the first to third nodes; and

causing the controller to simultaneously perform on and off switching operations of the first and second mos transistors.

20. The method according to claim 16, further comprising:

transferring the first voltage to a control gate of an ith memory cell among plural memory cells whose current paths are serially connected via the first node at a data read time; and

transferring the second voltage to a control gate of an (i+1)th memory cell arranged on a drain side of the ith memory cell via the second node.

21. A semiconductor device comprising:

a memory cell array including a plurality of memory cells each configured to store data;

a plurality of word lines connected to gates of the memory cells, respectively;

a first node to which a first voltage is supplied;

a second node to which a second voltage is applied;

a third node to which a third voltage is applied;

a first mos transistor connected between the first node and the second node and configured to equalize a voltage level of the first node and a voltage level of the second node by being turned on and short-circuiting the first node and the second node;

a second mos transistor connected between the second node and the third node and configured to equalize the voltage level of the second node and a voltage level of the third node by being turned on and short-circuiting the second node and the third node;

a controller which performs a control operation to short circuit the first node and the second node by turning on the first mos transistor, controlling a period in which the first mos transistor is kept in an on state based on time, wherein

a first period during which the first mos transistor is turned on to short-circuit the first node and the second node and a second period during which the second mos transistor is turned on to short-circuit the second node and the third node are changed,

the voltage level of the first node is transferred to at least a first one of the word lines,

the voltage level of the second node is transferred to at least a second one of the word lines, and

the voltage level of the third node is transferred to at least a third one of the word lines.

22. The device according to claim 21, further comprising:

a first voltage generator circuitry including a first charge pump, and configured to output the first voltage to the first node;

a second voltage generator circuitry including a second charge pump, and configured to output the second voltage to the second node; and

a third voltage generator circuitry including a third charge pump, and configured to output the third voltage to the third node, wherein

the second voltage is higher than the first voltage, and

the first mos transistor is turned on during the first period in which at least one of first voltage generator circuit and the second voltage generator circuit controls the voltage level of the first node and the voltage level of the second node toward the first voltage, and the first mos transistor is turned off during a third period after the first period in which the second voltage generator circuit controls the voltage level of the second node toward the second voltage.

23. The device according to claim 22, wherein

the second mos transistor is turned on during the second period, and the second mos transistor is turned off during a fourth period after the second period in which the third voltage generator circuit controls the voltage level of the third node toward the third voltage.

24. The device according to claim 21, wherein

the first mos transistor is one of an n-type intrinsic mos transistor, a depression-type mos transistor, and an enhancement-type mos transistor.

25. The device according to claim 21, wherein

a voltage equal to a sum of the voltage level of the second node and a threshold voltage of the first mos transistor is applied to a gate of the first mos transistor.

26. The device according to claim 21, wherein

a voltage applied to gates of the first and second mos transistors is one of

a voltage equal to a sum of the voltage level of the one of the second node and the third node and a threshold voltage of the first mos transistor, and

a voltage equal to a sum of the voltage level of the one of the second node and the third node and a threshold voltage of the second mos transistor.

27. The device according to claim 21, wherein

a signal is applied to a gate of the first mos transistor and a gate of the second mos transistor.

28. The device according to claim 21, wherein

the first mos transistor is one of an n-type depletion mos transistor with high withstand voltage or an n-type enhancement mos transistor with high withstand voltage.