A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

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Patent
   RE49195
Priority
May 23 2014
Filed
Mar 06 2019
Issued
Aug 30 2022
Expiry
May 21 2035
Inventors
Uchida, Ma…
Assg.orig
PANASONIC …
Assg.curr
PANASONIC …
Entity
Large
Referenced by
0
References
10
Maint.:
currently ok
1. A silicon carbide semiconductor device comprising, a laminated structure that includes a first conductive type:
a semiconductor substrate, of first conductive type;
a first conductive type first silicon carbide semiconductor layer of the first conductive type located on a main surface of the semiconductor substrate,; and
a first ohmic electrode located on a back surface of the semiconductor substrate, wherein:
the laminated structure including silicon carbide semiconductor device includes a transistor region, a termination region, and a diode region, each region including a part of the semiconductor substrate, a part of the first silicon carbide semiconductor layer, and a part of the first ohmic electrode, wherein
the termination region surrounds the transistor region, and the diode region is located between the transistor region and the termination region when viewed in a direction perpendicular to the main surface of the semiconductor substrate,
wherein the silicon carbide semiconductor device comprises, in the transistor region includes, a plurality of unit cell regions,
the silicon carbide semiconductor device comprises:
in each of the plurality of unit cell regions, includes:
a second conductive type first well region located in a part of the first silicon carbide semiconductor layer of second conductive type;
a first conductive type source region located in the first well region of the first conductive type;
a second silicon carbide semiconductor layer formed on a part of the first silicon carbide semiconductor layer so as to be in contact with at least a part of the first well region and a part of the source region, the second silicon carbide semiconductor layer including a first conductive type layer having a lower higher impurity concentration than an impurity concentration of at least the first silicon carbide semiconductor layer;
a gate insulating film on the second silicon carbide semiconductor layer; and
a gate electrode located on the gate insulating film;
a second ohmic electrode electrically connected to the source region; and,
an upper electrode electrically connected to the second ohmic electrode,
the silicon carbide semiconductor device comprises, in the diode region:
a second conductive type second well region located in a part of the first silicon carbide semiconductor layer of the second conductive type;
a contact region located in the second well region and having a higher impurity concentration than an impurity concentration of the second well region;
a the second silicon carbide semiconductor layer formed on a part of the first silicon carbide semiconductor layer so as to be in contact with at least a part of the contact region;
an insulating film formed on the second silicon carbide semiconductor layer and having a thickness substantially same as a thickness of the gate insulating film;
a gate electrode formed on at least a part of the insulating film;
a gate line located on the contact region and electrically connected to the gate electrode;
a gate pad located on the contact region and electrically connected to the gate line for establishing external connection; and
an inner third ohmic electrode at least two third ohmic electrodes, one of the at least two third ohmic electrodes being electrically connected to at least a region located between the gate line and the transistor region in the contact region, and an outer third ohmic electrode, and another one of the at least two third ohmic electrodes being electrically connected to at least a region located between the gate line and the termination region in the contact region; and,
a source line electrically connected to the inner third ohmic electrode and the upper electrode on each of the unit cell regions, and
the silicon carbide semiconductor device comprises, in the termination region,
a second conductive type an impurity region located in a part of the first silicon carbide semiconductor layer of the second conductive type,
wherein the gate electrode is located between the inner third ohmic electrode and the outer third ohmic electrode when viewed in a direction perpendicular to the main surface of the semiconductor substrate at least two third ohmic electrodes,
the silicon carbide semiconductor device comprises a plurality of third ohmic electrodes between the gate line in the diode region and the transistor region, the at least two third ohmic electrodes being included in the plurality of third ohmic electrodes,
each of the plurality of third ohmic electrodes has a rectangular or a circular shape as viewed in a direction perpendicular to the main surface of the semiconductor substrate, and
a third ohmic electrode closest to a corner of the second well region, out of the plurality of third ohmic electrodes, has an area larger than an area of a third ohmic electrode, out of the plurality of third ohmic electrodes, adjacent to the third ohmic electrode closest to the corner of the second well region.
2. The silicon carbide semiconductor device according to claim 1, further comprising, between the gate line in the diode region and the termination region, at least one unit cell having a structure same as a structure of each of the plurality of unit cell regions in the transistor region.
3. The silicon carbide semiconductor device according to claim 1 or 2 A silicon carbide semiconductor device comprising:
a semiconductor substrate of first conductive type,
a first silicon carbide semiconductor layer of first conductive type located on a main surface of the semiconductor substrate, and
a first ohmic electrode located on a back surface of the semiconductor substrate, wherein
the silicon carbide semiconductor device includes a transistor region, a termination region, and a diode region,
the termination region surrounds the transistor region, and the diode region is located between the transistor region and the termination region,
the silicon carbide semiconductor device comprises, in the transistor region, a plurality of unit cell regions, each of the plurality of unit cell regions includes:
a first well region of second conductive type;
a source region of first conductive type;
a second silicon carbide semiconductor layer including a first conductive type layer having a higher impurity concentration than an impurity concentration of the first silicon carbide semiconductor layer;
a gate insulating film; and
a second ohmic electrode electrically connected to the source region,
the silicon carbide semiconductor device comprises, in the diode region:
a second well region of second conductive type;
a contact region having a higher impurity concentration than an impurity concentration of the second well region;
the second silicon carbide semiconductor layer;
an insulating film;
a gate electrode;
a gate line electrically connected to the gate electrode;
a gate pad electrically connected to the gate line; and
at least two third ohmic electrodes, one of the at least two third ohmic electrodes being electrically connected to a region located between the gate line and the transistor region, another one of the at least two third ohmic electrodes being electrically connected to a region located between the gate line and the termination region,
the silicon carbide semiconductor device comprises, in the termination region, an impurity region of second conductive type,
the gate electrode is located between the at least two third ohmic electrodes, wherein
the silicon carbide semiconductor device includes a laminated structure has having a shape of a substantially rectangle as viewed in the a direction perpendicular to the main surface of the semiconductor substrate, and
a breakdown voltage of the termination region on two corners closer to the gate pad out of four corners of the rectangle is higher than a breakdown voltage of the termination region on at least one of the other two corners.
4. The silicon carbide semiconductor device according to claim 3, wherein:
the impurity region constitutes a field limiting ring (FLR) structure in the termination region, and
a radius of the impurity region on the two corners closer to the gate pad is larger than a radius of the impurity region on at least one of the other two corners.
5. The silicon carbide semiconductor device according to claim 3, wherein:
the impurity region constitutes a field limiting ring (FLR) structure in the termination region, and
a width of the impurity region on the two corners closer to the gate pad is larger than a width of the impurity region on at least one of the other two corners.
0. 6. The silicon carbide semiconductor device according to claim 1, comprising a plurality of the third ohmic electrodes between the gate line in the diode region and the transistor region,
wherein the plurality of the third ohmic electrodes has a rectangular or a circular shape as viewed in the direction, and
a third ohmic electrode closest to a corner of the second well region, out of the plurality of the third ohmic electrodes, has an area larger than an area of a third ohmic electrode adjacent to the third ohmic electrode closest to the corner of the second well region.
7. The A silicon carbide semiconductor device comprising:
a semiconductor substrate of first conductive type,
a first silicon carbide semiconductor layer of first conductive type located on a main surface of the semiconductor substrate, and
a first ohmic electrode located on a back surface of the semiconductor substrate, wherein
the silicon carbide semiconductor device includes a transistor region, a termination region, and a diode region,
the termination region surrounds the transistor region, and the diode region is located between the transistor region and the termination region,
the silicon carbide semiconductor device comprises, in the transistor region, a plurality of unit cell regions, each of the plurality of unit cell regions includes:
a first well region of second conductive type;
a source region of first conductive type;
a second silicon carbide semiconductor layer including a first conductive type layer having a higher impurity concentration than an impurity concentration of the first silicon carbide semiconductor layer;
a gate insulating film; and
a second ohmic electrode electrically connected to the source region,
the silicon carbide semiconductor device comprises, in the diode region:
a second well region of second conductive type;
a contact region having a higher impurity concentration than an impurity concentration of the second well region;
the second silicon carbide semiconductor layer;
an insulating film;
a gate electrode;
a gate line electrically connected to the gate electrode;
a gate pad electrically connected to the gate line; and
at least two third ohmic electrodes, one of the at least two third ohmic electrodes being electrically connected to a region located between the gate line and the transistor region, another one of the at least two third ohmic electrodes being electrically connected to a region located between the gate line and the termination region,
the silicon carbide semiconductor device comprises, in the termination region, an impurity region of second conductive type,
the gate electrode is located between the at least two third ohmic electrodes,
the silicon carbide semiconductor device according to claim 1, comprising further comprises a plurality of the third ohmic electrodes between the gate line in the diode region and the transistor region, the at least two third ohmic electrodes being included in the plurality of third ohmic electrodes,
wherein each of the plurality of the third ohmic electrodes has a stripe shape as viewed in the a direction perpendicular to the main surface of the semiconductor substrate, and
a width of the stripe is maximized at a corner of the second well region.
8. The silicon carbide semiconductor device according to claim 1, wherein:
the second well region is constituted by a plurality of second well regions divided into multiple regions in the diode region, and
a space between the divided multiple plurality of second well regions is equal to or less than a space between the divided multiple the first well region and the plurality of second well regions and the first well region.
0. 9. The silicon carbide semiconductor device according to claim 1, wherein the insulating film has a thickness substantially same as a thickness of the gate insulating film.
lower
d=30 nm

Then, after dry etching of a predetermined portion of silicon carbide semiconductor layer 106A, gate insulating film 107 and insulating film 117 are simultaneously formed on the surface of silicon carbide semiconductor layer 106A, which is left after the etching, by thermal oxidization as illustrated in FIG. 5B, for example. Gate insulating film 107 is located on transistor region 100T, and insulating film 117 is located on diode region 100D. In the case where gate insulating film 107 and insulating film 117 are formed by thermal oxidization, a part of silicon carbide semiconductor layer 106A may become gate insulating film 107 and insulating film 117. Therefore, in consideration of the thickness lost by the thermal oxidization, the thickness of silicon carbide semiconductor layer 106A to be formed is adjusted such that thickness d described above is obtained after the formation of gate insulating film 107 and insulating film 117. For example, silicon carbide semiconductor layer 106A is formed to have a thickness larger than d by about 50 nm. Silicon carbide semiconductor layer 106A after the formation of gate insulating film 107 and insulating film 117 through the process for cleaning silicon carbide semiconductor layer 106A before the formation of the gate insulating film and the process for forming the gate insulating film has thickness d.

Thereafter, a polycrystalline silicon film to which phosphor is doped in an amount of about 7×1020 cm−3 is deposited on the surface of gate insulating film 107. The thickness of the polycrystalline silicon film is about 500 nm, for example.

Next, as illustrated in FIG. 5C, the polycrystalline silicon film is dry etched using a mask (not illustrated), whereby gate electrode 108 is formed on a desired region. Then, interlayer insulating film 111 contained of SiO2, for example, is deposited to cover the surface of gate electrode 108 and the surface of drift layer 102 by a chemical vapor deposition (CVD) method. The thickness of interlayer insulating film 111 is 1 μm, for example.

Next, as illustrated in FIG. 5D, interlayer insulating film 111, gate insulating film 107, and insulating film 117 on the surface of first contact region 105 and on a part of the surface of impurity region 104 are removed by dry etching using a photoresist mask (not illustrated) to form contact holes 111c and 111d.

Thereafter, an Ni film with a thickness of about 100 nm is formed on interlayer insulating film 111 having contact holes 111c and 111d. With a heat treatment at a temperature of 950° C. for 1 minute under an inert atmosphere, the Ni film is reacted with drift layer 102 to form an ohmic electrode contained of Ni silicide. Then, the Ni film on interlayer insulating film 111 is removed by etching, whereby source electrode 109 and base electrode 119 illustrated in FIG. 6A are formed.

Next, Ni is also deposited on the entire back surface of SiC semiconductor substrate 101, and the Ni is similarly reacted with the back surface of SiC semiconductor substrate 101 with the heat treatment to form drain electrode 110 contained of Ni silicide as illustrated in FIG. 6B.

Then, after the formation of a photoresist mask (not illustrated), a part of interlayer insulating film 111 is etched to expose a part of gate electrode 108 on gate line region 100GL, whereby gate contact hole 111g is formed as illustrated in FIG. 6C.

Next, an aluminum film with a thickness of about 4 μm is deposited on the surface, and the resultant is etched into a desired pattern. With this, as illustrated in FIG. 6D, upper electrode 112, gate line 114L, gate pad, and upper source line 112L are formed. Further, Ti/Ni/Ag is deposited on the back surface of drain electrode 110 as back line electrode 113 for die bond, for example. (The Ti side is in contact with drain electrode 110). In this way, SiC-MOSFET 100 illustrated in FIGS. 1A to 3 is obtained.

Although not particularly illustrated in the present exemplary embodiment, it is to be noted that a passivation film having an opening on a part of upper electrode 112 or a part of gate pad 114 may further be deposited on interlayer insulating film 111, gate line 114L, or upper electrode 112.

First Modification

A first modification of the semiconductor device according to the present exemplary embodiment will be described with reference to FIG. 9.

Since a high current such as a displacement current or avalanche current flows through the source line in diode region 100Db as described in the above exemplary embodiment, the width of the source line is preferably set as wide as possible. However, when only diode region 100Db is formed below an upper source line, the region other than the transistor is increased in the entire chip, so that an amount of current per chip area is decreased and on resistance is increased. Specifically, area efficiency is deteriorated. The first modification is characterized in that a transistor cell is also disposed below the source line. With this configuration, the reduction in an amount of current per chip area when the width of the source line is increased can be reduced.

FIG. 9 illustrates a schematic sectional diagram of the first modification of the present exemplary embodiment. SiC-MOSFET semiconductor device 800 according to the first modification includes transistor region 100TA in diode region 100D between diode region 100Db and termination region 100E. SiC-MOSFET semiconductor device 800 also includes diode region 100Dc between transistor region 100TA and termination region 100E. Transistor region 100TA includes at least one unit cell region 100u. For example, unit cell region 100u in transistor region 100TA has the same structure as that of unit cell region 100u in transistor region 100T.

This configuration can implement an increase in the width of upper source line 112L without reducing a current through the transistor. Particularly upon avalanche breakdown, a high current is likely to flow through the source line due to the reason described below, and therefore, the upper source line has to be configured to be sufficiently wide.

The breakdown voltage of the transistor cell formed in transistor region 100T is determined by the breakdown voltage of the PN junction formed by first well region 103 and drift layer 102. The breakdown voltage of the termination structure of FLR on termination region 100E is determined by the width of the ring, the number of rings, and a curvature of the ring at the corner of the chip. In the case where the breakdown voltage of the transistor cell is designed to be lower than the breakdown voltage of the termination structure, an avalanche current dispersively flows into all unit cells in the chip, and flows out to the outside through upper electrode 112 serving as a source pad for applying a source voltage from the outside and through an unillustrated wire bonded to the source pad. Upper electrode 112 serving as the source pad is wider than source line 112L.

However, in the case where the breakdown voltage of the transistor cell is designed to be higher than the breakdown voltage of the termination structure, avalanche breakdown occurs first at the termination structure, and an avalanche current flows only through the termination structure. Further, electric field concentration is likely to occur on the portion of the termination structure located at the corners of the chip, and the avalanche current may locally flow through this portion. In FIG. 1A, the avalanche current flowing through the left termination structure of the chip has to pass through source line 112L which is thinner than the source pad before flowing into the source pad. In view of this, it is necessary that the width of the upper source line is designed to prevent the upper source line from being broken even if all of the avalanche current flows therethrough.

For example, when upper source line 112L is formed from aluminum having a thickness of 3 μm, allowable instantaneous current is about 5×106 A/cm2. If the avalanche current is 30 A, a width of 200 μm is required for upper source line 112L. If the chip size is 1 mm×1 mm, the area of the upper source line occupies about 40% of the entire chip. If the diode region is present entirely below the source line, on current does not flow through this region. Thus, the region where the on current flows is only about 60% of the entire chip, so that the current per area is extremely low. In view of this, if transistor region 100TA is also formed below upper source line 112L as in the first modification, the reduction in an amount of current per chip area can be prevented while the source line is ensured to be wide.

SiC-MOSFET 800 according to the first modification can be manufactured by the similar manufacturing method only by changing a mask layout of SiC-MOSFET 100 according to the exemplary embodiment described above.

Second Modification

A second modification of the semiconductor device according to the present exemplary embodiment will be described with reference to FIG. 10. Upper source line 112L has a thinner region in comparison with the upper electrode, and thus, it is preferable to prevent a high current from flowing through upper source line 112L as much as possible. Particularly upon avalanche breakdown, it is likely that a current equivalent to a rated current flows toward the outside from the corners through the upper source line. In SiC-MOSFET 900 according to the second modification of the present exemplary embodiment, laminated structure 200 has substantially a rectangular shape as viewed in the direction perpendicular to the main surface of SiC semiconductor substrate 101. The breakdown voltage of termination region 100E at corners 200a, 200b which are located closer to gate pad 114 out of four corners 200a, 200b, 200c, 200d is higher than the breakdown voltage of termination region 100E on at least one of the other two corners 200c, 200d. In other words, the breakdown voltage of termination region 100E on at least one of corners 200c, 200d is lower than the breakdown voltage of termination region 100E on corners 200a, 200b.

With this structure, an avalanche current can be flown out to the outside through a wire bonded to gate pad 114 without passing through thin source line 112L.

As described above, the breakdown voltage of the transistor cell is determined by the breakdown voltage of the PN junction formed by first well region 103 and drift layer 102. The breakdown voltage of the termination structure of FLR is determined by the width of the ring, the number of rings, and a curvature of the ring at the corner of the chip. In the case where the breakdown voltage of the transistor cell is designed to be lower than the breakdown voltage of the termination structure, an avalanche current dispersively flows into all unit cells in the chip, and flows out to the outside through wide upper electrode 112 and through an unillustrated wire bonded to upper electrode 112.

However, in the case where the breakdown voltage of the transistor cell is designed to be higher than the breakdown voltage of the termination structure, avalanche breakdown occurs first at the termination structure, and an avalanche current flows only through the termination structure. Further, electric field concentration is likely to occur on the portion of the termination structure located at the corners of the chip, and the avalanche current may locally flow through this portion. In FIG. 1A, the avalanche current flowing through the left termination structure of the chip has to pass through source line 112L which is thinner than upper electrode 112 before flowing into upper electrode 112. In order to allow the avalanche current to flow out to the outside through the bonded wire without passing through thin source line 112L, it is necessary to make it difficult to cause avalanche breakdown on the termination structure at corners 200a, 200b of the chip in FIG. 10.

For example, when termination region 100E has the FLR structure, the radius of the ring in the FLR at corners 200a, 200b may be set larger than the radius of the ring in the FLR at corners 200c, 200d as viewed in the direction perpendicular to the main surface of SiC semiconductor substrate 101. More specifically, the radius of ring region 120 which is the innermost ring of the FLR at corners 200a, 200b is set to be 100 μm, and the radius of ring region 120 which is the innermost ring of the FLR at corners 200c, 200d is set to be 16 μm. FIG. 11A illustrates dependency of normalized breakdown voltage (BVD) on the radius of innermost ring region 120 of the FLR. The vertical axis is normalized with values when the radius of innermost ring region 120 of the FLR is 8 μm. When the radius is changed as described above, an avalanche breakdown voltage can be changed by about ±5%. Therefore, avalanche breakdown occurs in the FLR on corners 200c, 200d which are distant from gate pad 114 (which are close to upper electrode 112), whereby the avalanche current can be released to upper electrode 112 without passing through upper source line 112L. Accordingly, it is not necessary to consider the avalanche current for the determination of the width of source line 112L, whereby the width of the upper source line can be decreased. Thus, the region where the transistor cell can be disposed is increased, whereby an amount of current per unit area can be increased.

Further, the width of ring region 120 that is the ring in the FLR at corners 200a, 200b may be set larger than the width of ring region 120 that is the ring in the FLR at corners 200c, 200d as viewed in the direction perpendicular to the main surface of SiC semiconductor substrate 101. For example, the width of ring region 120 in the FLR at corners 200a, 200b may be 1.0 μm, and the width of ring region 120 in the FLR at corners 200c, 200d may be 0.9 μm. FIG. 11B illustrates dependency of normalized BVD on the width of the impurity region in the FLR. This result is brought by changing the region to which p type is implanted with the interval of the arrangement of rings being constant. In this case, the implantation width of ring region 120 is varied with the interval being set as 2 μm. The vertical axis is normalized with the values when the width of the ring region in the FLR is 0.8 μm. When the width of the ring region in the FLR is changed as described above, an avalanche breakdown voltage can be changed by about ±10%. Accordingly, the operation and effect similar to those obtained by changing the radius of curvature of the FLR can be obtained.

SiC-MOSFET 900 according to the second modification can be manufactured by the similar manufacturing method only by changing a mask layout of SiC-MOSFET 100 according to the exemplary embodiment described above.

Third Modification

A third modification of the semiconductor device according to the present exemplary embodiment will be described with reference to FIG. 12.

In gate pad region 1100GP for external connection, the second well region is wide in comparison with gate line region 100GL. Therefore, a high displacement current flows through gate pad region 1100GP, and thus, the gate pad region does not preferably have a region where a thin insulating film is present alone. SiC-MOSFET 1100 according to the third modification does not have gate electrode 108 in gate pad region 1100GP. With this, an interlayer insulating film is present directly on a thin insulating film with a gate electrode being not formed in the gate pad region. According to this structure, an electric field applied to the insulating film is relaxed when a high displacement current flows, and this can prevent insulating film 117 in gate pad region 1100GP from being broken down.

FIG. 12 illustrates a sectional schematic diagram illustrating the cross-section along line II-II in FIGS. 1A and 1B (gate pad region) according to the third modification. The structure of gate line region 100GL (cross-section along line I-I in FIGS. 1A and 1B) in the third modification is the same as that illustrated in FIG. 2. SiC-MOSFET 1100 according to the third modification of the present exemplary embodiment includes transistor region 100T, termination region 100E, gate pad region 1100GP, diode region 100Da, and diode region 100Db on the cross-section along line II-II in FIGS. 1A and 1B. Gate pad region 1100GP is disposed to be sandwiched between diode region 100Da and transistor region 100T. Further, diode region 100Db is disposed to be adjacent to termination region 100E. The structures of transistor region 100T, diode regions 100Da, 100Db, and termination region 100E are the same as those illustrated in FIG. 3. Gate pad region 1100GP includes drift layer 102 formed on the main surface of SiC semiconductor substrate 101, epitaxial layer 118 formed on drift layer 102, and insulating film 117, interlayer insulating film 111, and gate pad 114 which are formed on epitaxial layer 118. Drift layer 102 in gate pad region 1100GP has second well region 115 having a conductive type different from the conductive type of SiC semiconductor substrate 101 (here, second well region 115 is of p type). p+ type second contact region 116 containing p type impurities at a higher concentration than that in second well region 115 is formed in second well region 115. The p type impurity profile in the vertical direction is substantially the same between second well region 115 and first well region 103 and between second contact region 116 and first contact region 105. In addition, insulating film 117 is a thermally oxidized (SiO2) film formed by thermally oxidizing the surface of epitaxial layer 118, and has a thickness substantially same as the thickness of gate insulating film 107. Considering that the MOSFET is switched to the off state from the on state, a displacement current flows into the well through the drain-source capacitance generated between the drift layer and the well region due to the rapid change in the drain-source voltage. Particularly, gate pad region 1100GP needs to be relatively wide for connection to the outside. Therefore, the second well region is much larger in comparison with the gate line portion, and extremely large displacement current flows therein through drain-source capacitance generated in this region. In the third modification, base electrodes are present on both sides of second well region 115. However, the second well region in gate pad region is extremely wide, and therefore, the path of the displacement current is inevitably long. Thus, a considerable potential rise occurs in second well region 115 below the gate pad. It is configured such that interlayer insulating film 111 is thoroughly formed on insulating film 117 in the gate pad as in the third modification. With this configuration, even if a considerable potential rise occurs in second well region 115 below the gate pad, a voltage is distributed to the portion above insulating film 117 and interlayer insulating film 111, whereby an electric field applied to insulating film 117 can be relaxed. Consequently, breakdown of insulating film 117 below the gate pad can be prevented.

SiC-MOSFET 1100 according to the third modification can be manufactured by the similar manufacturing method only by changing a mask layout of SiC-MOSFET 100 according to the exemplary embodiment described above.

Fourth Modification

A fourth modification of the semiconductor device according to the present exemplary embodiment will be described with reference to FIG. 13. In gate pad region 100GP for external connection, second well region 115 is wide in comparison with gate line region 100GL. A displacement current flows according to the area of second well region 115. Therefore, when a thin insulating film is present alone on second well region 115, it is preferable that second well region 115 is narrow. SiC-MOSFET 1200 according to the present fourth modification is characterized in that second well region 1215 of gate pad region 1200GP is divided in gate pad region 1200GP. With this structure, the area of the second well region where only a thin insulating film is present can be decreased, whereby breakdown of insulating film 117 in gate pad region 1200GP can be prevented.

In SiC-MOSFET 1200 according to the fourth modification, the structure of gate line region 100GL (cross-section along line I-I in FIGS. 1A and 1B) is the same as that of SiC-MOSFET 100. SiC-MOSFET 1200 according to the fourth modification includes transistor region 100T, termination region 100E, gate pad region 1200GP, diode region 100Da, and diode region 100Db on the cross-section along line II-II in FIGS. 1A and 1B. Gate pad region 1200GP is disposed to be sandwiched between diode regions 100Da, 100Db. Diode region 100Db is disposed to be adjacent to termination region 100E. The structures of transistor region 100T, diode regions 100Da, 100Db, and termination region 100E are the same as those in the present exemplary embodiment.

Gate pad region 1200GP includes drift layer 102 formed on the main surface of SiC semiconductor substrate 101, epitaxial layer 118 formed on drift layer 102, and insulating film 117, interlayer insulating film 111, and gate pad 114 which are formed on epitaxial layer 118.

Drift layer 102 in gate pad region 1200GP has second well regions 1215a and 1215b having a conductive type different from the conductive type of SiC semiconductor substrate 101 (here, second well regions 1215a and 1215b are of p type). p+ type second contact regions 1216a and 1216b containing p type impurities at a higher concentration than that in second well regions 1215a and 1215b are formed in second well region 115.

Further, the impurity concentration profile in the vertical direction is substantially the same between second well regions 1215a and 1215b and first well region 103 and between second contact regions 1216a and 1216b and first contact region 105. In addition, insulating film 117 is a thermally oxidized (SiO2) film formed by thermally oxidizing the surface of epitaxial layer 118, and is formed simultaneously with gate insulating film 107.

In this case, space L1 between second well region 1215a and second well region 1215b is equal to or less than space L2 (illustrated in FIG. 2) between first well regions 103 of transistor region 100T. Since space L1 between second well region 1215a and second well region 1215b is equal to or less than space L2 between first well regions 103, application of a voltage equal to that of the drain on the surface of drift layer 102 can be prevented due to the depletion layers, when a voltage is applied between the drain and source. Further, the distance from base electrode 119 on diode region 100Da to the farthest end of second well region 1215a is shorter than the distance from base electrode 119 on diode region 100Db to the farthest end of second well region 1215b. With the configuration in which the distance from base electrode 119 on diode region 100Da to the farthest end of second well region 1215a is decreased, the displacement current flowing through second well region 1215b can be suppressed.

Considering that the MOSFET is switched to the off state from the on state, a displacement current flows into the well through the drain-source capacitance generated between the drift layer and the well region due to the rapid change in the drain-source voltage. Particularly, gate pad region 1200GP needs to be relatively wide for connection to the outside. Therefore, second well regions 1215a and 1215b are much larger in comparison with the gate line portion, and extremely large displacement current flows therein through drain-source capacitance generated in this region. In the fourth modification, base electrodes are present at both sides of second well regions 1215a and 1215b, and each of second well regions 1215a and 1215b is electrically connected to corresponding one of the base electrodes. A displacement current can be suppressed with the configuration as in the present fourth modification in which the second well region is divided in the gate pad, and the distance to the base electrode from the end of second well region 1215a on which the gate electrode is present is decreased. Further, a potential rise can be suppressed by decreasing the distance of a path through which the displacement current flows. Consequently, breakdown of insulating film 117 below the gate pad can be prevented.

SiC-MOSFET 1200 according to the fourth modification can be manufactured by the similar manufacturing method only by changing a mask layout of SiC-MOSFET 100 according to the exemplary embodiment described above.

Fifth Modification

A fifth modification of the semiconductor device according to the present exemplary embodiment will be described with reference to FIGS. 14A, 14B, 15A, and 15B.

A displacement current or an avalanche current always flows out to upper source line 112L and upper electrode 112 through base electrode 119. Therefore, it is desirable to reduce a potential rise on base electrode 119 due to contact resistance simultaneously with the reduction in a potential rise in the second well region. SiC-MOSFETs 1300 and 1400 according to the fifth modification are characterized in that the contact area of base electrode 119 located near the corner of second well region 115, in particular, out of base electrodes 119 on the diode region formed between gate line 112 and transistor region 100T is large. With this structure, the potential rise due to contact resistance on the base region where current is particularly concentrated can be reduced. Consequently, breakdown of the insulating film on the second well can be prevented.

FIGS. 14A to 15B illustrate plan views in the fifth modification. FIGS. 14A and 15A are plan views of the entire semiconductor device, and FIGS. 14B and 15B illustrate enlarged views of portions enclosed by a broken line.

For example, in the case where base electrode 119 has a rectangular shape as viewed in the direction perpendicular to the main surface of SiC-MOSFET semiconductor substrate 101 as illustrated in FIG. 14B, the area of base electrode 119A located at the shortest distance from the corner of second well region 115 is larger than the area of base electrode 119 adjacent to base electrode 119A. Further, in the case where base electrode 119 has a stripe shape as viewed in the direction perpendicular to the main surface of SiC-MOSFET semiconductor substrate 101 as illustrated in FIG. 15B, the width of the stripe is maximized at the corner of second well region 115. With this structure, the potential rise on base electrode 119 can be suppressed, and further, this structure can prevent base electrode 119 from being broken when a current more than the maximum allowable current flows therein.

Further, arrows in FIGS. 14B and 15B schematically show the flow of a displacement current in a plan view. Considering that the MOSFET is switched to the off state from the on state, a displacement current flows into the well through the drain-source capacitance generated between the drift layer and the well region due to the rapid change in the drain-source voltage. In a plan view, the displacement current doesn't flow into base electrode 119, which is not located at the corner of second well region 115, in only one direction. On the other hand, the current flows into base electrode 119A near the corner of second well region 115 in two directions (from left to right and from bottom to top in the figures). When the area of base electrode 119A is larger than the area of adjacent base electrode 119, a potential rise on base electrode 119A can be suppressed even if a high displacement current flows therein. Second well region 115 and base electrode 119 are disposed in series with respect to the path of the displacement current. Therefore, the potential rise on any position of second well region 115 is a total of the potential rise due to the resistance of second well region 115 and the potential rise on the base electrode due to the contact resistance. Accordingly, the suppression of the potential rise on base electrode 119 leads to the suppression of the potential rise in second well region 115, whereby breakdown of the insulating film on second well region 115 can be prevented. Further, since the amount of allowable current of base electrode 119 also increases in proportion to an area, breaking of the base electrode can be prevented.

Further, as illustrated in FIG. 15B, the similar effect can be obtained even when the base electrode has a stripe shape.

Although the modifications describe the base electrode sandwiched between the gate line and the transistor cell, it is obvious that the similar effect can be obtained with the base electrode formed between the gate line and the termination portion, between the gate pad and the transistor cell, and between the gate pad and the transistor cell.

The SiC-MOSFET according to the present disclosure is widely applicable to semiconductor devices for various uses, and various control devices or drive devices provided with the semiconductor devices, such as inverter circuits.

INVENTORS:

Uchida, Masao, Hayashi, Masashi, Horikawa, Nobuyuki, Kusumoto, Osamu

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