Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method

Abstract

Disclosed is a method for transmitting a broadcast signal. The method comprises formatting input streams with multiple data transmission channels, and the formatting step comprises adding a header indicating a format of a payload of the BBF.

Description

This application

The LDPC code parameters for PLS1 and PLS2 are as following table 4.

TABLE 4
Signaling				Kldpc
Type	Ksig	Kbch	Nbch_parity	(=Nbch)
PLS1	342	1020	60	1080
PLS2	<1021
	>1020	2100		2160
Signaling			code
Type	Nldpc	Nldpc_parity	rate	Qldpc
PLS1	4320	3240	1/4	36
PLS2
	7200	5040	3/10	56

The LDPC parity puncturing block can perform puncturing on the PLS1 data and PLS 2 data.

When shortening is applied to the PLS1 data protection, some LDPC parity bits are punctured after LDPC encoding. Also, for the PLS2 data protection, the LDPC parity bits of PLS2 are punctured after LDPC encoding. These punctured bits are not transmitted.

The bit interleaver 6010 can interleave the each shortened and punctured PLS1 data and PLS2 data.

The constellation mapper 6020 can map the bit interleaved PLS1 data and PLS2 data onto constellations.

The time interleaver 6030 can interleave the mapped PLS1 data and PLS2 data.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 7 illustrates a frame building block according to one embodiment of the present invention.

The frame building block illustrated in FIG. 7 corresponds to an embodiment of the frame building block 1020 described with reference to FIG. 1.

Referring to FIG. 7, the frame building block can include a delay compensation block 7000, a cell mapper 7010 and a frequency interleaver 7020. Description will be given of each block of the frame building block.

The delay compensation block 7000 can adjust the timing between the data pipes and the corresponding PLS data to ensure that they are co-timed at the transmitter end. The PLS data is delayed by the same amount as data pipes are by addressing the delays of data pipes caused by the Input Formatting block and BICM block. The delay of the BICM block is mainly due to the time interleaver 5050. In-band signaling data carries information of the next TI group so that they are carried one frame ahead of the DPs to be signaled. The Delay Compensating block delays in-band signaling data accordingly.

The cell mapper 7010 can map PLS, EAC, FIC, DPs, auxiliary streams and dummy cells into the active carriers of the OFDM symbols in the frame. The basic function of the cell mapper 7010 is to map data cells produced by the TIs for each of the DPs, PLS cells, and EAC/FIC cells, if any, into arrays of active OFDM cells corresponding to each of the OFDM symbols within a frame. Service signaling data (such as PSI (program specific information)/SI) can be separately gathered and sent by a data pipe. The Cell Mapper operates according to the dynamic information produced by the scheduler and the configuration of the frame structure. Details of the frame will be described later.

The frequency interleaver 7020 can randomly interleave data cells received from the cell mapper 7010 to provide frequency diversity. Also, the frequency interleaver 7020 can operate on very OFDM symbol pair comprised of two sequential OFDM symbols using a different interleaving-seed order to get maximum interleaving gain in a single frame. Details of operations of the frequency interleaver 7020 will be described later.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions.

FIG. 8 illustrates an OFMD generation block according to an embodiment of the present invention.

The OFMD generation block illustrated in FIG. 8 corresponds to an embodiment of the OFMD generation block 1030 described with reference to FIG. 1.

The OFDM generation block modulates the OFDM carriers by the cells produced by the Frame Building block, inserts the pilots, and produces the time domain signal for transmission. Also, this block subsequently inserts guard intervals, and applies PAPR (Peak-to-Average Power Radio) reduction processing to produce the final RF signal.

Referring to FIG. 8, the frame building block can include a pilot and reserved tone insertion block 8000, a 2D-eSFN encoding block 8010, an IFFT (Inverse Fast Fourier Transform) block 8020, a PAPR reduction block 8030, a guard interval insertion block 8040, a preamble insertion block 8050, other system insertion block 8060 and a DAC block 8070. Description will be given of each block of the frame building block.

The pilot and reserved tone insertion block 8000 can insert pilots and the reserved tone.

Various cells within the OFDM symbol are modulated with reference information, known as pilots, which have transmitted values known a priori in the receiver. The information of pilot cells is made up of scattered pilots, continual pilots, edge pilots, FSS (frame signaling symbol) pilots and FES (frame edge symbol) pilots. Each pilot is transmitted at a particular boosted power level according to pilot type and pilot pattern. The value of the pilot information is derived from a reference sequence, which is a series of values, one for each transmitted carrier on any given symbol. The pilots can be used for frame synchronization, frequency synchronization, time synchronization, channel estimation, and transmission mode identification, and also can be used to follow the phase noise.

Reference information, taken from the reference sequence, is transmitted in scattered pilot cells in every symbol except the preamble, FSS and FES of the frame. Continual pilots are inserted in every symbol of the frame. The number and location of continual pilots depends on both the FFT size and the scattered pilot pattern. The edge carriers are edge pilots in every symbol except for the preamble symbol. They are inserted in order to allow frequency interpolation up to the edge of the spectrum. FSS pilots are inserted in FSS(s) and FES pilots are inserted in FES. They are inserted in order to allow time interpolation up to the edge of the frame.

The system according to an embodiment of the present invention supports the SFN network, where distributed MISO scheme is optionally used to support very robust transmission mode. The 2D-eSFN is a distributed MISO scheme that uses multiple TX antennas, each of which is located in the different transmitter site in the SFN network.

The 2D-eSFN encoding block 8010 can process a 2D-eSFN processing to distorts the phase of the signals transmitted from multiple transmitters, in order to create both time and frequency diversity in the SFN configuration. Hence, burst errors due to low flat fading or deep-fading for a long time can be mitigated.

The IFFT block 8020 can modulate the output from the 2D-eSFN encoding block 8010 using OFDM modulation scheme. Any cell in the data symbols which has not been designated as a pilot (or as a reserved tone) carries one of the data cells from the frequency interleaver. The cells are mapped to OFDM carriers.

The PAPR reduction block 8030 can perform a PAPR reduction on input signal using various PAPR reduction algorithm in the time domain.

The guard interval insertion block 8040 can insert guard intervals and the preamble insertion block 8050 can insert preamble in front of the signal. Details of a structure of the preamble will be described later. The other system insertion block 8060 can multiplex signals of a plurality of broadcast transmission/reception systems in the time domain such that data of two or more different broadcast transmission/reception systems providing broadcast services can be simultaneously transmitted in the same RF signal bandwidth. In this case, the two or more different broadcast transmission/reception systems refer to systems providing different broadcast services. The different broadcast services may refer to a terrestrial broadcast service, mobile broadcast service, etc. Data related to respective broadcast services can be transmitted through different frames.

The DAC block 8070 can convert an input digital signal into an analog signal and output the analog signal. The signal output from the DAC block 7800 can be transmitted through multiple output antennas according to the physical layer profiles. A Tx antenna according to an embodiment of the present invention can have vertical or horizontal polarity.

The above-described blocks may be omitted or replaced by blocks having similar or identical functions according to design.

FIG. 9 illustrates a structure of an apparatus for receiving broadcast signals for future broadcast services according to an embodiment of the present invention.

The apparatus for receiving broadcast signals for future broadcast services according to an embodiment of the present invention can correspond to the apparatus for transmitting broadcast signals for future broadcast services, described with reference to FIG. 1.

The apparatus for receiving broadcast signals for future broadcast services according to an embodiment of the present invention can include a synchronization & demodulation module 9000, a frame parsing module 9010, a demapping & decoding module 9020, an output processor 9030 and a signaling decoding module 9040. A description will be given of operation of each module of the apparatus for receiving broadcast signals.

The synchronization & demodulation module 9000 can be represented to a receiver and an OFDM demodulator.

The frame parsing module 9010 can be represented to a frame parser.

The demapping & decoding module 9020 can be represented to a converter and a decoder.

The synchronization & demodulation module 9000 can receive input signals through m Rx antennas, perform signal detection and synchronization with respect to a system corresponding to the apparatus for receiving broadcast signals and carry out demodulation corresponding to a reverse procedure of the procedure performed by the apparatus for transmitting broadcast signals.

The frame parsing module 9100 can parse input signal frames and extract data through which a service selected by a user is transmitted. If the apparatus for transmitting broadcast signals performs interleaving, the frame parsing module 9100 can carry out deinterleaving corresponding to a reverse procedure of interleaving. In this case, the positions of a signal and data that need to be extracted can be obtained by decoding data output from the signaling decoding module 9400 to restore scheduling information generated by the apparatus for transmitting broadcast signals.

The demapping & decoding module 9200 can convert the input signals into bit domain data and then deinterleave the same as necessary. The demapping & decoding module 9200 can perform demapping for mapping applied for transmission efficiency and correct an error generated on a transmission channel through decoding. In this case, the demapping & decoding module 9200 can obtain transmission parameters necessary for demapping and decoding by decoding the data output from the signaling decoding module 9400.

The output processor 9300 can perform reverse procedures of various compression/signal processing procedures which are applied by the apparatus for transmitting broadcast signals to improve transmission efficiency. In this case, the output processor 9300 can acquire necessary control information from data output from the signaling decoding module 9400. The output of the output processor 8300 corresponds to a signal input to the apparatus for transmitting broadcast signals and may be MPEG-TSs, IP streams (v4 or v6) and generic streams.

The signaling decoding module 9400 can obtain PLS information from the signal demodulated by the synchronization & demodulation module 9000. As described above, the frame parsing module 9100, demapping & decoding module 9200 and output processor 9300 can execute functions thereof using the data output from the signaling decoding module 9400.

The Output Processor of FIG. 9 implements functions, processes, and/or methods proposed in FIGS. 50, 51, and 53 to be described below.

FIG. 10 illustrates a frame structure according to an embodiment of the present invention.

FIG. 10 shows an example configuration of the frame types and FRUs in a super-frame. (a) shows a super frame according to an embodiment of the present invention, (b) shows FRU (Frame Repetition Unit) according to an embodiment of the present invention, (c) shows frames of variable PHY profiles in the FRU and (d) shows a structure of a frame.

A super-frame may be composed of eight FRUs. The FRU is a basic multiplexing unit for TDM of the frames, and is repeated eight times in a super-frame.

Each frame in the FRU belongs to one of the PHY profiles, (base, handheld, advanced) or FEF. The maximum allowed number of the frames in the FRU is four and a given PHY profile can appear any number of times from zero times to four times in the FRU (e.g., base, base, handheld, advanced). PHY profile definitions can be extended using reserved values of the PHY_PROFILE in the preamble, if required.

The FEF part is inserted at the end of the FRU, if included. When the FEF is included in the FRU, the minimum number of FEFs is 8 in a super-frame. It is not recommended that FEF parts be adjacent to each other.

One frame is further divided into a number of OFDM symbols and a preamble. As shown in (d), the frame comprises a preamble, one or more frame signaling symbols (FSS), normal data symbols and a frame edge symbol (FES).

The preamble is a special symbol that enables fast Futurecast UTB system signal detection and provides a set of basic transmission parameters for efficient transmission and reception of the signal. The detailed description of the preamble will be will be described later.

The main purpose of the FSS(s) is to carry the PLS data. For fast synchronization and channel estimation, and hence fast decoding of PLS data, the FSS has more dense pilot pattern than the normal data symbol. The FES has exactly the same pilots as the FSS, which enables frequency-only interpolation within the FES and temporal interpolation, without extrapolation, for symbols immediately preceding the FES.

FIG. 11 illustrates a signaling hierarchy structure of the frame according to an embodiment of the present invention.

FIG. 11 illustrates the signaling hierarchy structure, which is split into three main parts: the preamble signaling data 11000, the PLS1 data 11010 and the PLS2 data 11020. The purpose of the preamble, which is carried by the preamble symbol in every frame, is to indicate the transmission type and basic transmission parameters of that frame. The PLS1 enables the receiver to access and decode the PLS2 data, which contains the parameters to access the DP of interest. The PLS2 is carried in every frame and split into two main parts: PLS2-STAT data and PLS2-DYN data. The static and dynamic portion of PLS2 data is followed by padding, if necessary.

FIG. 12 illustrates preamble signaling data according to an embodiment of the present invention.

Preamble signaling data carries 21 bits of information that are needed to enable the receiver to access PLS data and trace DPs within the frame structure. Details of the preamble signaling data are as follows:

PHY_PROFILE: This 3-bit field indicates the PHY profile type of the current frame. The mapping of different PHY profile types is given in below table 5.

TABLE 5

Value   PHY profile

000     Base profile
001     Handheld profile
010     Advanced profiled
011~110 Reserved
111     FEF

FFT_SIZE: This 2 bit field indicates the FFT size of the current frame within a frame-group, as described in below table 6.

TABLE 6

Value FFT size

00    8K FFT
01    16K FFT
10    32K FFT
11    Reserved

GI_FRACTION: This 3 bit field indicates the guard interval fraction value in the current super-frame, as described in below table 7.

TABLE 7

Value   GI_FRACTION

000     ⅕
001     1/10
010     1/20
011     1/40
100     1/80
101     1/160
110~111 Reserved

EAC_FLAG: This 1 bit field indicates whether the EAC is provided in the current frame. If this field is set to ‘1’, emergency alert service (EAS) is provided in the current frame. If this field set to ‘0’, EAS is not carried in the current frame. This field can be switched dynamically within a super-frame.

PILOT_MODE: This 1-bit field indicates whether the pilot mode is mobile mode or fixed mode for the current frame in the current frame-group. If this field is set to ‘0’, mobile pilot mode is used. If the field is set to ‘1’, the fixed pilot mode is used.

PAPR_FLAG: This 1-bit field indicates whether PAPR reduction is used for the current frame in the current frame-group. If this field is set to value ‘1’, tone reservation is used for PAPR reduction. If this field is set to ‘0’, PAPR reduction is not used.

FRU_CONFIGURE: This 3-bit field indicates the PHY profile type configurations of the frame repetition units (FRU) that are present in the current super-frame. All profile types conveyed in the current super-frame are identified in this field in all preambles in the current super-frame. The 3-bit field has a different definition for each profile, as show in below table 8.

TABLE 8
	Current	Current	Current	Current
	PHY_PROFILE =	PHY_PROFILE =	PHY_PROFILE =	PHY_PROFILE =
	‘000’ (base)	‘001’ (handheld)	‘010’ (advanced)	‘111’ (FEF)
FRU_CONFIG-	Only base	Only handheld	Only advanced	Only FEF
URE = 000	profile present	profile present	profile present	present
FRU_CONFIG-	Handheld	Base	Base	Base
URE = 1XX	profile present	profile present	profile present	profile present
FRU_CONFIG-	Advanced	Advanced	Handheld	Handheld
URE = X1X	profile present	profile present	profile present	profile present
FRU_CONFIG-	FEF	FEF	FEF	Advanced
URE = XX1	present	present	present	profile present

RESERVED: This 7-bit field is reserved for future use.

FIG. 13 illustrates PLS1 data according to an embodiment of the present invention.

PLS1 data provides basic transmission parameters including parameters required to enable the reception and decoding of the PLS2. As above mentioned, the PLS1 data remain unchanged for the entire duration of one frame-group. The detailed definition of the signaling fields of the PLS1 data are as follows:

PREAMBLE_DATA: This 20-bit field is a copy of the preamble signaling data excluding the EAC_FLAG.

NUM_FRAME_FRU: This 2-bit field indicates the number of the frames per FRU.

PAYLOAD_TYPE: This 3-bit field indicates the format of the payload data carried in the frame-group. PAYLOAD_TYPE is signaled as shown in table 9.

TABLE 9

Value Payload type

1XX   TS stream is transmitted
X1X   IP stream is transmitted
XX1   GS stream is transmitted

NUM_FSS: This 2-bit field indicates the number of FSS symbols in the current frame.

SYSTEM_VERSION: This 8-bit field indicates the version of the transmitted signal format. The SYSTEM_VERSION is divided into two 4-bit fields, which are a major version and a minor version.

Major version: The MSB four bits of SYSTEM_VERSION field indicate major version information. A change in the major version field indicates a non-backward-compatible change. The default value is ‘0000’. For the version described in this standard, the value is set to ‘0000’.

Minor version: The LSB four bits of SYSTEM_VERSION field indicate minor version information. A change in the minor version field is backward-compatible.

CELL_ID: This is a 16-bit field which uniquely identifies a geographic cell in an ATSC network. An ATSC cell coverage area may consist of one or more frequencies, depending on the number of frequencies used per Futurecast UTB system. If the value of the CELL_ID is not known or unspecified, this field is set to ‘0’.

NETWORK_ID: This is a 16-bit field which uniquely identifies the current ATSC network.

SYSTEM_ID: This 16-bit field uniquely identifies the Futurecast UTB system within the ATSC network. The Futurecast UTB system is the terrestrial broadcast system whose input is one or more input streams (TS, IP, GS) and whose output is an RF signal. The Futurecast UTB system carries one or more PHY profiles and FEF, if any. The same Futurecast UTB system may carry different input streams and use different RF frequencies in different geographical areas, allowing local service insertion. The frame structure and scheduling is controlled in one place and is identical for all transmissions within a Futurecast UTB system. One or more Futurecast UTB systems may have the same SYSTEM_ID meaning that they all have the same physical layer structure and configuration.

The following loop consists of FRU_PHY_PROFILE, FRU_FRAME_LENGTH, FRU_GI_FRACTION, and RESERVED which are used to indicate the FRU configuration and the length of each frame type. The loop size is fixed so that four PHY profiles (including a FEF) are signaled within the FRU. If NUM_FRAME_FRU is less than 4, the unused fields are filled with zeros.

FRU_PHY_PROFILE: This 3-bit field indicates the PHY profile type of the (i+1)th (i is the loop index) frame of the associated FRU. This field uses the same signaling format as shown in the table 8.

FRU_FRAME_LENGTH: This 2-bit field indicates the length of the (i+1)th frame of the associated FRU. Using FRU_FRAME_LENGTH together with FRU_GI_FRACTION, the exact value of the frame duration can be obtained.

FRU_GI_FRACTION: This 3-bit field indicates the guard interval fraction value of the (i+1)th frame of the associated FRU. FRU_GI_FRACTION is signaled according to the table 7.

RESERVED: This 4-bit field is reserved for future use.

The following fields provide parameters for decoding the PLS2 data.

PLS2_FEC_TYPE: This 2-bit field indicates the FEC type used by the PLS2 protection. The FEC type is signaled according to table 10. The details of the LDPC codes will be described later.

TABLE 10

Contents PLS2 FEC type

00       4K-1/4 and 7K-3/10 LDPC codes
01~11    Reserved

PLS2_MOD: This 3-bit field indicates the modulation type used by the PLS2. The modulation type is signaled according to table 11.

TABLE 11

Value   PLS2_MODE

000     BPSK
001     QPSK
010     QAM-16
011     NUQ-64
100~111 Reserved

PLS2_SIZE_CELL: This 15-bit field indicates Ctotal_partial_block, the size (specified as the number of QAM cells) of the collection of full coded blocks for PLS2 that is carried in the current frame-group. This value is constant during the entire duration of the current frame-group.

PLS2_STAT_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-STAT for the current frame-group. This value is constant during the entire duration of the current frame-group.

PLS2_DYN_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-DYN for the current frame-group. This value is constant during the entire duration of the current frame-group.

PLS2_REP_FLAG: This 1-bit flag indicates whether the PLS2 repetition mode is used in the current frame-group. When this field is set to value ‘1’, the PLS2 repetition mode is activated. When this field is set to value ‘0’, the PLS2 repetition mode is deactivated.

PLS2_REP SIZE_CELL: This 15-bit field indicates Ctotal_partial_block, the size (specified as the number of QAM cells) of the collection of partial coded blocks for PLS2 carried in every frame of the current frame-group, when PLS2 repetition is used. If repetition is not used, the value of this field is equal to 0. This value is constant during the entire duration of the current frame-group.

PLS2_NEXT_FEC_TYPE: This 2-bit field indicates the FEC type used for PLS2 that is carried in every frame of the next frame-group. The FEC type is signaled according to the table 10.

PLS2_NEXT_MOD: This 3-bit field indicates the modulation type used for PLS2 that is carried in every frame of the next frame-group. The modulation type is signaled according to the table 11.

PLS2_NEXT_REP_FLAG: This 1-bit flag indicates whether the PLS2 repetition mode is used in the next frame-group. When this field is set to value ‘1’, the PLS2 repetition mode is activated. When this field is set to value ‘0’, the PLS2 repetition mode is deactivated.

PLS2_NEXT_REP_SIZE_CELL: This 15-bit field indicates Ctotal_full_block, The size (specified as the number of QAM cells) of the collection of full coded blocks for PLS2 that is carried in every frame of the next frame-group, when PLS2 repetition is used. If repetition is not used in the next frame-group, the value of this field is equal to 0. This value is constant during the entire duration of the current frame-group.

PLS2_NEXT_REP_STAT_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-STAT for the next frame-group. This value is constant in the current frame-group.

PLS2 NEXT_REP_DYN_SIZE_BIT: This 14-bit field indicates the size, in bits, of the PLS2-DYN for the next frame-group. This value is constant in the current frame-group.

PLS2_AP_MODE: This 2-bit field indicates whether additional parity is provided for PLS2 in the current frame-group. This value is constant during the entire duration of the current frame-group. The below table 12 gives the values of this field. When this field is set to ‘00’, additional parity is not used for the PLS2 in the current frame-group.

TABLE 12

Value PLS2-AP mode

00    AP is not provided
01    AP1 mode
10~11 Reserved

PLS2_AP_SIZE_CELL: This 15-bit field indicates the size (specified as the number of QAM cells) of the additional parity bits of the PLS2. This value is constant during the entire duration of the current frame-group.

PLS2_NEXT_AP_MODE: This 2-bit field indicates whether additional parity is provided for PLS2 signaling in every frame of next frame-group. This value is constant during the entire duration of the current frame-group. The table 12 defines the values of this field

PLS2_NEXT_AP_SIZE_CELL: This 15-bit field indicates the size (specified as the number of QAM cells) of the additional parity bits of the PLS2 in every frame of the next frame-group. This value is constant during the entire duration of the current frame-group.

RESERVED: This 32-bit field is reserved for future use.

CRC_32: A 32-bit error detection code, which is applied to the entire PLS1 signaling.

FIG. 14 illustrates PLS2 data according to an embodiment of the present invention.

FIG. 14 illustrates PLS2-STAT data of the PLS2 data. The PLS2-STAT data are the same within a frame-group, while the PLS2-DYN data provide information that is specific for the current frame.

The details of fields of the PLS2-STAT data are as follows:

FIC_FLAG: This 1-bit field indicates whether the FIC is used in the current frame-group. If this field is set to ‘1’, the FIC is provided in the current frame. If this field set to ‘0’, the FIC is not carried in the current frame. This value is constant during the entire duration of the current frame-group.

AUX_FLAG: This 1-bit field indicates whether the auxiliary stream(s) is used in the current frame-group. If this field is set to ‘1’, the auxiliary stream is provided in the current frame. If this field set to ‘0’, the auxiliary stream is not carried in the current frame. This value is constant during the entire duration of current frame-group.

NUM_DP: This 6-bit field indicates the number of DPs carried within the current frame. The value of this field ranges from 1 to 64, and the number of DPs is NUM_DP+1.

DP_ID: This 6-bit field identifies uniquely a DP within a PHY profile.

DP_TYPE: This 3-bit field indicates the type of the DP. This is signaled according to the below table 13.

TABLE 13

Value   DP Type

000     DP Type 1
001     DP Type 2
010~111 reserved

DP_GROUP_ID: This 8-bit field identifies the DP group with which the current DP is associated. This can be used by a receiver to access the DPs of the service components associated with a particular service, which will have the same DP_GROUP_ID.

BASE_DP_ID: This 6-bit field indicates the DP carrying service signaling data (such as PSI/SI) used in the Management layer. The DP indicated by BASE_DP_ID may be either a normal DP carrying the service signaling data along with the service data or a dedicated DP carrying only the service signaling data

DP_FEC_TYPE: This 2-bit field indicates the FEC type used by the associated DP. The FEC type is signaled according to the below table 14.

TABLE 14

Value FEC_TYPE

00    16K LDPC
01    64K LDPC
10~11 Reserved

DP_COD: This 4-bit field indicates the code rate used by the associated DP. The code rate is signaled according to the below table 15.

TABLE 15

Value     Code rate

0000      5/15
0001      6/15
0010      7/15
0011      8/15
0100      9/15
0101      10/15
0110      11/15
0111      12/15
1000      13/15
1001~1111 Reserved

DP_MOD: This 4-bit field indicates the modulation used by the associated DP. The modulation is signaled according to the below table 16.

TABLE 16

Value     Modulation

0000      QPSK
0001      QAM-16
0010      NUQ-64
0011      NUQ-256
0100      NUQ-1024
0101      NUC-16
0110      NUC-64
0111      NUC-256
1000      NUC-1024
1001~1111 reserved

DP_SSD_FLAG: This 1-bit field indicates whether the SSD mode is used in the associated DP. If this field is set to value ‘1’, SSD is used. If this field is set to value ‘0’, SSD is not used.

The following field appears only if PHY_PROFILE is equal to ‘010’, which indicates the advanced profile:

DP_MIMO: This 3-bit field indicates which type of MIMO encoding process is applied to the associated DP. The type of MIMO encoding process is signaled according to the table 17.

TABLE 17

Value   MIMO encoding

000     FR-SM
001     FRFD-SM
010~111 reserved

DP_TI_TYPE: This 1-bit field indicates the type of time-interleaving. A value of ‘0’ indicates that one TI group corresponds to one frame and contains one or more TI-blocks. A value of ‘1’ indicates that one TI group is carried in more than one frame and contains only one TI-block.

DP_TI_LENGTH: The use of this 2-bit field (the allowed values are only 1, 2, 4, 8) is determined by the values set within the DP_TI_TYPE field as follows:

If the DP_TI_TYPE is set to the value ‘1’, this field indicates PI, the number of the frames to which each TI group is mapped, and there is one TI-block per TI group (NTI=1). The allowed PI values with 2-bit field are defined in the below table 18.

If the DP_TI_TYPE is set to the value ‘0’, this field indicates the number of TI-blocks NTI per TI group, and there is one TI group per frame (PI=1). The allowed PI values with 2-bit field are defined in the below table 18.

TABLE 18
2-bit field	PI	NTI
00	1	1
01	2	2
10	4	3
11	8	4

DP_FRAME_INTERVAL: This 2-bit field indicates the frame interval (IJUMP) within the frame-group for the associated DP and the allowed values are 1, 2, 4, 8 (the corresponding 2-bit field is ‘00’, ‘01’, ‘10’, or ‘11’, respectively). For DPs that do not appear every frame of the frame-group, the value of this field is equal to the interval between successive frames. For example, if a DP appears on the frames 1, 5, 9, 13, etc., this field is set to ‘4’. For DPs that appear in every frame, this field is set to ‘1’.

DP_TI_BYPASS: This 1-bit field determines the availability of time interleaver 5050. If time interleaving is not used for a DP, it is set to ‘1’. Whereas if time interleaving is used it is set to ‘0’.

DP_FIRST_FRAME_IDX: This 5-bit field indicates the index of the first frame of the super-frame in which the current DP occurs. The value of DP_FIRST_FRAME_IDX ranges from 0 to 31

DP_NUM_BLOCK_MAX: This 10-bit field indicates the maximum value of DP_NUM_BLOCKS for this DP. The value of this field has the same range as DP_NUM_BLOCKS.

DP_PAYLOAD_TYPE: This 2-bit field indicates the type of the payload data carried by the given DP. DP_PAYLOAD_TYPE is signaled according to the below table 19.

TABLE 19

Value Payload Type

00    TS.
01    IP
10    GS
11    reserved

DP_INBAND_MODE: This 2-bit field indicates whether the current DP carries in-band signaling information. The in-band signaling type is signaled according to the below table 20.

TABLE 20

Value In-band mode

00    In-band signaling is not carried.
01    INBAND-PLS is carried only
10    INBAND-ISSY is carried only
11    INBAND-PLS and INBAND-ISSY are carried

DP_PROTOCOL_TYPE: This 2-bit field indicates the protocol type of the payload carried by the given DP. It is signaled according to the below table 21 when input payload types are selected.

TABLE 21
		If	If	If
		DP_PAY-	DP_PAY-	DP_PAY-
		LOAD_TYPE	LOAD_TYPE	LOAD_TYPE
	Value	Is TS	Is IP	Is GS
	00	MPEG2-TS	IPv4	(Note)
	01	Reserved	IPv6	Reserved
	10	Reserved	Reserved	Reserved
	11	Reserved	Reserved	Reserved

DP_CRC_MODE: This 2-bit field indicates whether CRC encoding is used in the Input Formatting block. The CRC mode is signaled according to the below table 22.

TABLE 22

Value CRC mode

00    Not used
01    CRC-8
10    CRC-16
11    CRC-32

DNP_MODE: This 2-bit field indicates the null-packet deletion mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS (‘00’). DNP_MODE is signaled according to the below table 23. If DP_PAYLOAD_TYPE is not TS (‘00’), DNP_MODE is set to the value ‘00’.

TABLE 23

Value Null-packet deletion mode

00    Not used
01    DNP-NORMAL
10    DNP-OFFSET
11    reserved

ISSY_MODE: This 2-bit field indicates the ISSY mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS (‘00’). The ISSY_MODE is signaled according to the below table 24 If DP_PAYLOAD_TYPE is not TS (‘00’), ISSY_MODE is set to the value ‘00’.

TABLE 24

Value ISSY mode

00    Not used
01    ISSY-UP
10    ISSY-BBF
11    reserved

HC_MODE_TS: This 2-bit field indicates the TS header compression mode used by the associated DP when DP_PAYLOAD_TYPE is set to TS (‘00’). The HC_MODE_TS is signaled according to the below table 25.

TABLE 25

Value Header compression mode

00    HC_MODE_TS 1
01    HC_MODE_TS 2
10    HC_MODE_TS 3
11    HC_MODE_TS 4

HC_MODE_IP: This 2-bit field indicates the IP header compression mode when DP_PAYLOAD_TYPE is set to IP (‘01’). The HC_MODE_IP is signaled according to the below table 26.

TABLE 26

Value Header compression mode

00    No compression
01    HC_MODE_IP 1
10~11 reserved

PID: This 13-bit field indicates the PID number for TS header compression when DP_PAYLOAD_TYPE is set to TS (‘00’) and HC_MODE_TS is set to ‘01’ or ‘10’.

RESERVED: This 8-bit field is reserved for future use.

The following field appears only if FIC_FLAG is equal to ‘1’:

FIC_VERSION: This 8-bit field indicates the version number of the FIC.

FIC_LENGTH_BYTE: This 13-bit field indicates the length, in bytes, of the FIC.

RESERVED: This 8-bit field is reserved for future use.

The following field appears only if AUX_FLAG is equal to ‘1’:

NUM_AUX: This 4-bit field indicates the number of auxiliary streams. Zero means no auxiliary streams are used.

AUX_CONFIG_RFU: This 8-bit field is reserved for future use.

AUX_STREAM_TYPE: This 4-bit is reserved for future use for indicating the type of the current auxiliary stream.

AUX_PRIVATE_CONFIG: This 28-bit field is reserved for future use for signaling auxiliary streams.

FIG. 15 illustrates PLS2 data according to another embodiment of the present invention.

FIG. 15 illustrates PLS2-DYN data of the PLS2 data. The values of the PLS2-DYN data may change during the duration of one frame-group, while the size of fields remains constant.

The details of fields of the PLS2-DYN data are as follows:

FRAME_INDEX: This 5-bit field indicates the frame index of the current frame within the super-frame. The index of the first frame of the super-frame is set to ‘0’.

PLS_CHANGE_COUNTER: This 4-bit field indicates the number of super-frames ahead where the configuration will change. The next super-frame with changes in the configuration is indicated by the value signaled within this field. If this field is set to the value ‘0000’, it means that no scheduled change is foreseen: e.g., value ‘1’ indicates that there is a change in the next super-frame.

FIC_CHANGE_COUNTER: This 4-bit field indicates the number of super-frames ahead where the configuration (i.e., the contents of the FIC) will change. The next super-frame with changes in the configuration is indicated by the value signaled within this field. If this field is set to the value ‘0000’, it means that no scheduled change is foreseen: e.g. value ‘0001’ indicates that there is a change in the next super-frame.

RESERVED: This 16-bit field is reserved for future use.

The following fields appear in the loop over NUM_DP, which describe the parameters associated with the DP carried in the current frame.

DP_ID: This 6-bit field indicates uniquely the DP within a PHY profile.

DP_START: This 15-bit (or 13-bit) field indicates the start position of the first of the DPs using the DPU addressing scheme. The DP_START field has differing length according to the PHY profile and FFT size as shown in the below table 27.

TABLE 27
	DP_START field size
	PHY profile	64K	16K
	Base	13 bits	15 bits
	Handheld	—	13 bits
	Advanced	13 bits	15 bits

DP_NUM_BLOCK: This 10-bit field indicates the number of FEC blocks in the current TI group for the current DP. The value of DP_NUM_BLOCK ranges from 0 to 1023

RESERVED: This 8-bit field is reserved for future use.

The following fields indicate the FIC parameters associated with the EAC.

EAC_FLAG: This 1-bit field indicates the existence of the EAC in the current frame. This bit is the same value as the EAC_FLAG in the preamble.

EAS_WAKE_UP_VERSION_NUM: This 8-bit field indicates the version number of a wake-up indication.

If the EAC_FLAG field is equal to ‘1’, the following 12 bits are allocated for EAC_LENGTH_BYTE field. If the EAC_FLAG field is equal to ‘0’, the following 12 bits are allocated for EAC_COUNTER.

EAC_LENGTH_BYTE: This 12-bit field indicates the length, in byte, of the EAC.

EAC_COUNTER: This 12-bit field indicates the number of the frames before the frame where the EAC arrives.

The following field appears only if the AUX_FLAG field is equal to ‘1’:

AUX_PRIVATE_DYN: This 48-bit field is reserved for future use for signaling auxiliary streams. The meaning of this field depends on the value of AUX_STREAM_TYPE in the configurable PLS2-STAT.

CRC_32: A 32-bit error detection code, which is applied to the entire PLS2.

FIG. 16 illustrates a logical structure of a frame according to an embodiment of the present invention.

As above mentioned, the PLS, EAC, FIC, DPs, auxiliary streams and dummy cells are mapped into the active carriers of the OFDM symbols in the frame. The PLS1 and PLS2 are first mapped into one or more FSS(s). After that, EAC cells, if any, are mapped immediately following the PLS field, followed next by FIC cells, if any. The DPs are mapped next after the PLS or EAC, FIC, if any. Type 1 DPs follows first, and Type 2 DPs next. The details of a type of the DP will be described later. In some case, DPs may carry some special data for EAS or service signaling data. The auxiliary stream or streams, if any, follow the DPs, which in turn are followed by dummy cells. Mapping them all together in the above mentioned order, i.e. PLS, EAC, FIC, DPs, auxiliary streams and dummy data cells exactly fill the cell capacity in the frame.

FIG. 17 illustrates PLS mapping according to an embodiment of the present invention.

PLS cells are mapped to the active carriers of FSS(s). Depending on the number of cells occupied by PLS, one or more symbols are designated as FSS(s), and the number of FSS(s) NFSS is signaled by NUM_FSS in PLS1. The FSS is a special symbol for carrying PLS cells. Since robustness and latency are critical issues in the PLS, the FSS(s) has higher density of pilots allowing fast synchronization and frequency-only interpolation within the FSS.

PLS cells are mapped to active carriers of the NFSS FSS(s) in a top-down manner as shown in an example in FIG. 17. The PLS1 cells are mapped first from the first cell of the first FSS in an increasing order of the cell index. The PLS2 cells follow immediately after the last cell of the PLS1 and mapping continues downward until the last cell index of the first FSS. If the total number of required PLS cells exceeds the number of active carriers of one FSS, mapping proceeds to the next FSS and continues in exactly the same manner as the first FSS.

After PLS mapping is completed, DPs are carried next. If EAC, FIC or both are present in the current frame, they are placed between PLS and “normal” DPs.

FIG. 18 illustrates EAC mapping according to an embodiment of the present invention.

EAC is a dedicated channel for carrying EAS messages and links to the DPs for EAS. EAS support is provided but EAC itself may or may not be present in every frame. EAC, if any, is mapped immediately after the PLS2 cells. EAC is not preceded by any of the FIC, DPs, auxiliary streams or dummy cells other than the PLS cells. The procedure of mapping the EAC cells is exactly the same as that of the PLS.

The EAC cells are mapped from the next cell of the PLS2 in increasing order of the cell index as shown in the example in FIG. 18. Depending on the EAS message size, EAC cells may occupy a few symbols, as shown in FIG. 18.

EAC cells follow immediately after the last cell of the PLS2, and mapping continues downward until the last cell index of the last FSS. If the total number of required EAC cells exceeds the number of remaining active carriers of the last FSS mapping proceeds to the next symbol and continues in exactly the same manner as FSS(s). The next symbol for mapping in this case is the normal data symbol, which has more active carriers than a FSS.

After EAC mapping is completed, the FIC is carried next, if any exists. If FIC is not transmitted (as signaled in the PLS2 field), DPs follow immediately after the last cell of the EAC.

FIG. 19 illustrates FIC mapping according to an embodiment of the present invention.

shows an example mapping of FIC cell without EAC and (b) shows an example mapping of FIC cell with EAC.

FIC is a dedicated channel for carrying cross-layer information to enable fast service acquisition and channel scanning. This information primarily includes channel binding information between DPs and the services of each broadcaster. For fast scan, a receiver can decode FIC and obtain information such as broadcaster ID, number of services, and BASE_DP_ID. For fast service acquisition, in addition to FIC, base DP can be decoded using BASE_DP_ID. Other than the content it carries, a base DP is encoded and mapped to a frame in exactly the same way as a normal DP. Therefore, no additional description is required for a base DP. The FIC data is generated and consumed in the Management Layer. The content of FIC data is as described in the Management Layer specification.

The FIC data is optional and the use of FIC is signaled by the FIC_FLAG parameter in the static part of the PLS2. If FIC is used, FIC_FLAG is set to ‘1’ and the signaling field for FIC is defined in the static part of PLS2. Signaled in this field are FIC_VERSION, and FIC_LENGTH_BYTE. FIC uses the same modulation, coding and time interleaving parameters as PLS2. FIC shares the same signaling parameters such as PLS2_MOD and PLS2_FEC. FIC data, if any, is mapped immediately after PLS2 or EAC if any. FIC is not preceded by any normal DPs, auxiliary streams or dummy cells. The method of mapping FIC cells is exactly the same as that of EAC which is again the same as PLS.

Without EAC after PLS, FIC cells are mapped from the next cell of the PLS2 in an increasing order of the cell index as shown in an example in (a). Depending on the FIC data size, FIC cells may be mapped over a few symbols, as shown in (b).

FIC cells follow immediately after the last cell of the PLS2, and mapping continues downward until the last cell index of the last FSS. If the total number of required FIC cells exceeds the number of remaining active carriers of the last FSS, mapping proceeds to the next symbol and continues in exactly the same manner as FSS(s). The next symbol for mapping in this case is the normal data symbol which has more active carriers than a FSS.

If EAS messages are transmitted in the current frame, EAC precedes FIC, and FIC cells are mapped from the next cell of the EAC in an increasing order of the cell index as shown in (b).

After FIC mapping is completed, one or more DPs are mapped, followed by auxiliary streams, if any, and dummy cells.

FIG. 20 illustrates a type of DP according to an embodiment of the present invention.

shows type 1 DP and (b) shows type 2 DP.

After the preceding channels, i.e., PLS, EAC and FIC, are mapped, cells of the DPs are mapped. A DP is categorized into one of two types according to mapping method:

Type 1 DP: DP is mapped by TDM

Type 2 DP: DP is mapped by FDM

The type of DP is indicated by DP_TYPE field in the static part of PLS2. FIG. 20 illustrates the mapping orders of Type 1 DPs and Type 2 DPs. Type 1 DPs are first mapped in the increasing order of cell index, and then after reaching the last cell index, the symbol index is increased by one. Within the next symbol, the DP continues to be mapped in the increasing order of cell index starting from p=0. With a number of DPs mapped together in one frame, each of the Type 1 DPs are grouped in time, similar to TDM multiplexing of DPs.

Type 2 DPs are first mapped in the increasing order of symbol index, and then after reaching the last OFDM symbol of the frame, the cell index increases by one and the symbol index rolls back to the first available symbol and then increases from that symbol index. After mapping a number of DPs together in one frame, each of the Type 2 DPs are grouped in frequency together, similar to FDM multiplexing of DPs.

Type 1 DPs and Type 2 DPs can coexist in a frame if needed with one restriction; Type 1 DPs always precede Type 2 DPs. The total number of OFDM cells carrying Type 1 and Type 2 DPs cannot exceed the total number of OFDM cells available for transmission of DPs:
D_DP1+D_DP2≤D_DP   [Math figure 2]

where DDP1 is the number of OFDM cells occupied by Type 1 DPs, DDP2 is the number of cells occupied by Type 2 DPs. Since PLS, EAC, FIC are all mapped in the same way as Type 1 DP, they all follow “Type 1 mapping rule”. Hence, overall, Type 1 mapping always precedes Type 2 mapping.

FIG. 21 illustrates DP mapping according to an embodiment of the present invention.

shows an addressing of OFDM cells for mapping type 1 DPs and (b) shows an addressing of OFDM cells for mapping for type 2 DPs.

Addressing of OFDM cells for mapping Type 1 DPs (0, . . . , DDP1-1) is defined for the active data cells of Type 1 DPs. The addressing scheme defines the order in which the cells from the TIs for each of the Type 1 DPs are allocated to the active data cells. It is also used to signal the locations of the DPs in the dynamic part of the PLS2.

Without EAC and FIC, address 0 refers to the cell immediately following the last cell carrying PLS in the last FSS. If EAC is transmitted and FIC is not in the corresponding frame, address 0 refers to the cell immediately following the last cell carrying EAC. If FIC is transmitted in the corresponding frame, address 0 refers to the cell immediately following the last cell carrying FIC. Address 0 for Type 1 DPs can be calculated considering two different cases as shown in (a). In the example in (a), PLS, EAC and FIC are assumed to be all transmitted. Extension to the cases where either or both of EAC and FIC are omitted is straightforward. If there are remaining cells in the FSS after mapping all the cells up to FIC as shown on the left side of (a).

Addressing of OFDM cells for mapping Type 2 DPs (0, . . . , DDP2-1) is defined for the active data cells of Type 2 DPs. The addressing scheme defines the order in which the cells from the TIs for each of the Type 2 DPs are allocated to the active data cells. It is also used to signal the locations of the DPs in the dynamic part of the PLS2.

Three slightly different cases are possible as shown in (b). For the first case shown on the left side of (b), cells in the last FSS are available for Type 2 DP mapping. For the second case shown in the middle, FIC occupies cells of a normal symbol, but the number of FIC cells on that symbol is not larger than CFSS. The third case, shown on the right side in (b), is the same as the second case except that the number of FIC cells mapped on that symbol exceeds CFSS.

The extension to the case where Type 1 DP(s) precede Type 2 DP(s) is straightforward since PLS, EAC and FIC follow the same “Type 1 mapping rule” as the Type 1 DP(s).

A data pipe unit (DPU) is a basic unit for allocating data cells to a DP in a frame.

A DPU is defined as a signaling unit for locating DPs in a frame. A Cell Mapper 7010 may map the cells produced by the TIs for each of the DPs. A Time interleaver 5050 outputs a series of TI-blocks and each TI-block comprises a variable number of XFECBLOCKs which is in turn composed of a set of cells. The number of cells in an XFECBLOCK, Ncells, is dependent on the FECBLOCK size, Nldpc, and the number of transmitted bits per constellation symbol. A DPU is defined as the greatest common divisor of all possible values of the number of cells in a XFECBLOCK, Ncells, supported in a given PHY profile. The length of a DPU in cells is defined as LDPU. Since each PHY profile supports different combinations of FECBLOCK size and a different number of bits per constellation symbol, LDPU is defined on a PHY profile basis.

FIG. 22 illustrates an FEC structure according to an embodiment of the present invention.

FIG. 22 illustrates an FEC structure according to an embodiment of the present invention before bit interleaving. As above mentioned, Data FEC encoder may perform the FEC encoding on the input BBF to generate FECBLOCK procedure using outer coding (BCH), and inner coding (LDPC). The illustrated FEC structure corresponds to the FECBLOCK. Also, the FECBLOCK and the FEC structure have same value corresponding to a length of LDPC codeword.

The BCH encoding is applied to each BBF (Kbch bits), and then LDPC encoding is applied to BCH-encoded BBF (Kldpc bits=Nbch bits) as illustrated in FIG. 22.

The value of Nldpc is either 64800 bits (long FECBLOCK) or 16200 bits (short FECBLOCK).

The below table 28 and table 29 show FEC encoding parameters for a long FECBLOCK and a short FECBLOCK, respectively.

TABLE 28
				BCH error
LDPC				correction
Rate	Nldpc	Kldpc	Kbch	capability	Nbch − Kbch
5/15	64800	21600	21408	12	192
6/15		25920	25728
7/15		30240	30048
8/15		34560	34368
9/15		38880	38688
10/15		43200	43008
11/15		47520	47328
12/15		51840	51648
13/15		56160	55968

TABLE 29
				BCH error
LDPC				correction
Rate	Nldpc	Kldpc	Kbch	capability	Nbch − Kbch
5/15	16200	5400	5232	12	168
6/15		6480	6312
7/15		7560	7392
8/15		8640	8472
9/15		9720	9552
10/15		10800	10632
11/15		11880	11712
12/15		12960	12792
13/15		14040	13872

The details of operations of the BCH encoding and LDPC encoding are as follows:

A 12-error correcting BCH code is used for outer encoding of the BBF. The BCH generator polynomial for short FECBLOCK and long FECBLOCK are obtained by multiplying together all polynomials.

LDPC code is used to encode the output of the outer BCH encoding. To generate a completed Bldpc (FECBLOCK), Pldpc (parity bits) is encoded systematically from each Ildpc (BCH-encoded BBF), and appended to Ildpc. The completed Bldpc (FECBLOCK) are expressed as follow Math figure.
B_ldpc=[I_ldpcP_ldpc]=[i₀,i₁, . . . ,i_Kldpc−1,p₀,p₁, . . . ,p_{Nldpc−Kldpc−1}]  [Math figure 3]

The parameters for long FECBLOCK and short FECBLOCK are given in the above table 28 and 29, respectively.

The detailed procedure to calculate Nldpc

Kldpc parity bits for long FECBLOCK, is as follows:

1) Initialize the parity bits,
p₀=p₁=p₂= . . . =p_{Nldpc−Kldpc−1}=0   [Math figure 4]

2) Accumulate the first information bit—i0, at parity bit addresses specified in the first row of an addresses of parity check matrix. The details of addresses of parity check matrix will be described later. For example, for rate 13/15:
p₉₈₃=p₉₈₃⊕i₀p₂₈₁₅=p₂₈₁₅⊕i₀
p₄₈₃₇=p₄₈₃₇⊕i₀p₄₉₈₉=p₄₉₈₉⊕i₀
p₆₁₃₈=p₆₁₃₈⊕i₀p₆₄₅₈=p₆₄₅₈⊕i₀
p₆₉₂₁=p₆₉₂₁⊕i₀p₆₉₇₄=p₆₉₇₄⊕i₀
p₇₅₇₂=p₇₅₇₂⊕i₀p₈₂₆₀=p₈₂₆₀⊕i₀
p₈₄₉₆=p₈₄₉₆⊕i₀   [Math figure 5]

3) For the next 359 information bits, is, s=1, 2, . . . , 359 accumulate is at parity bit addresses using following Math figure.
{x+(s mod 360)×Q_ldpc} mod(N_ldpc−K_ldpc)   [Math figure 6]

where x denotes the address of the parity bit accumulator corresponding to the first bit i0, and Qldpc is a code rate dependent constant specified in the addresses of parity check matrix. Continuing with the example, Qldpc=24 for rate 13/15, so for information bit i1, the following operations are performed:
p₈₄₉₆=p₁₀₀₇⊕i₁p₂₈₃₉=p₂₈₃₉⊕i₁
p₄₈₆₁=p₄₈₆₁⊕i₁p₅₀₁₃=p₅₀₁₃⊕i₁
p₆₁₆₂=p₆₁₆₂⊕i₁p₆₄₈₂=p₆₄₈₂⊕i₁
p₆₉₄₅=p₆₉₄₅⊕i₁p₆₉₉₈=p₆₉₉₈⊕i₁
p₇₅₉₆=p₇₅₉₆⊕i₁p₈₂₈₄=p₈₂₈₄⊕i₁
p₈₅₂₀=p₈₅₂₀⊕i₁   [Math figure 7]

4) For the 361st information bit i360, the addresses of the parity bit accumulators are given in the second row of the addresses of parity check matrix. In a similar manner the addresses of the parity bit accumulators for the following 359 information bits is, s=361, 362, . . . , 719 are obtained using the Math FIG. 6, where x denotes the address of the parity bit accumulator corresponding to the information bit i360, i.e., the entries in the second row of the addresses of parity check matrix.

5) In a similar manner, for every group of 360 new information bits, a new row from addresses of parity check matrixes used to find the addresses of the parity bit accumulators.

After all of the information bits are exhausted, the final parity bits are obtained as follows:

6) Sequentially perform the following operations starting with i=1
p_ip_i⊕p_i−1,i=1,2, . . . ,N_ldpc−K_ldpc−1   [Math figure 8]

where final content of pi, i=0, 1, . . . Nldpc−Kldpc−1 is equal to the parity bit pi.

TABLE 30

Code Rate Qldpc


5/15      120
6/15      108
7/15      96
8/15      84
9/15      72
10/15     60
11/15     48
12/15     36
13/15     24

This LDPC encoding procedure for a short FECBLOCK is in accordance with t LDPC encoding procedure for the long FECBLOCK, except replacing the table 30 with table 31, and replacing the addresses of parity check matrix for the long FECBLOCK with the addresses of parity check matrix for the short FECBLOCK.

TABLE 31

Code Rate Qldpc


5/15      30
6/15      27
7/15      24
8/15      21
9/15      18
10/15     15
11/15     12
12/15     9
13/15     6

FIG. 23 illustrates a bit interleaving according to an embodiment of the present invention.

The outputs of the LDPC encoder are bit-interleaved, which consists of parity interleaving followed by Quasi-Cyclic Block (QCB) interleaving and inner-group interleaving.

shows Quasi-Cyclic Block (QCB) interleaving and (b) shows inner-group interleaving.

The FECBLOCK may be parity interleaved. At the output of the parity interleaving, the LDPC codeword consists of 180 adjacent QC blocks in a long FECBLOCK and 45 adjacent QC blocks in a short FECBLOCK. Each QC block in either a long or short FECBLOCK consists of 360 bits. The parity interleaved LDPC codeword is interleaved by QCB interleaving. The unit of QCB interleaving is a QC block. The QC blocks at the output of parity interleaving are permutated by QCB interleaving as illustrated in FIG. 23, where Ncells=64800/η mod or 16200/η mod according to the FECBLOCK length. The QCB interleaving pattern is unique to each combination of modulation type and LDPC code rate.

After QCB interleaving, inner-group interleaving is performed according to modulation type and order (η mod) which is defined in the below table 32. The number of QC blocks for one inner-group, NQCB_IG, is also defined.

TABLE 32
	Modulation type	ηmod	NQCB_IG
	QAM-16	4	2
	NUC-16	4	4
	NUQ-64	6	3
	NUC-64	6	6
	NUQ-256	8	4
	NUC-256	8	8
	NUQ-1024	10	5
	NUC-1024	10	10

The inner-group interleaving process is performed with NQCB_IG QC blocks of the QCB interleaving output. Inner-group interleaving has a process of writing and reading the bits of the inner-group using 360 columns and NQCB_IG rows. In the write operation, the bits from the QCB interleaving output are written row-wise. The read operation is performed column-wise to read out m bits from each row, where m is equal to 1 for NUC and 2 for NUQ.

FIG. 24 illustrates a cell-word demultiplexing according to an embodiment of the present invention.

shows a cell-word demultiplexing for 8 and 12 bpcu MIMO and (b) shows a cell-word demultiplexing for 10 bpcu MIMO.

Each cell word (c0,1, c1,1, . . . , cη mod−1,1) of the bit interleaving output is demultiplexed into (d1,0,m, d1,1,m . . . , d1,η mod−1,m) and (d2,0,m, d2,1,m . . . , d2,η mod−1,m) as shown in (a), which describes the cell-word demultiplexing process for one XFECBLOCK.

For the 10 bpcu MIMO case using different types of NUQ for MIMO encoding, the Bit Interleaver for NUQ-1024 is re-used. Each cell word (c0,1, c1,1, . . . , c9,1) of the Bit Interleaver output is demultiplexed into (d1,0,m, d1,1,m . . . , d1,3,m) and (d2,0,m, d2,1,m . . . , d2,5 m), as shown in (b).

FIG. 25 illustrates a time interleaving according to an embodiment of the present invention.

to (c) show examples of TI mode.

The time interleaver operates at the DP level. The parameters of time interleaving (TI) may be set differently for each DP.

The following parameters, which appear in part of the PLS2-STAT data, configure the TI:

DP_TI_TYPE (allowed values: 0 or 1): Represents the TI mode; ‘0’ indicates the mode with multiple TI blocks (more than one TI block) per TI group. In this case, one TI group is directly mapped to one frame (no inter-frame interleaving). ‘1’ indicates the mode with only one TI block per TI group. In this case, the TI block may be spread over more than one frame (inter-frame interleaving).

DP_TI_LENGTH: If DP_TI_TYPE=‘0’, this parameter is the number of TI blocks NTI per TI group. For DP_TI_TYPE=‘1’, this parameter is the number of frames PI spread from one TI group.

DP_NUM_BLOCK_MAX (allowed values: 0 to 1023): Represents the maximum number of XFECBLOCKs per TI group.

DP_FRAME_INTERVAL (allowed values: 1, 2, 4, 8): Represents the number of the frames IJUMP between two successive frames carrying the same DP of a given PHY profile.

DP_TI_BYPASS (allowed values: 0 or 1): If time interleaving is not used for a DP, this parameter is set to ‘1’. It is set to ‘0’ if time interleaving is used.

Additionally, the parameter DP_NUM_BLOCK from the PLS2-DYN data is used to represent the number of XFECBLOCKs carried by one TI group of the DP.

When time interleaving is not used for a DP, the following TI group, time interleaving operation, and TI mode are not considered. However, the Delay Compensation block for the dynamic configuration information from the scheduler will still be required. In each DP, the XFECBLOCKs received from the SSD/MIMO encoding are grouped into TI groups. That is, each TI group is a set of an integer number of XFECBLOCKs and will contain a dynamically variable number of XFECBLOCKs. The number of XFECBLOCKs in the TI group of index n is denoted by NxBLOCK_Group (n) and is signaled as DP_NUM_BLOCK in the PLS2-DYN data. Note that NxBLOCK_Group(n) may vary from the minimum value of 0 to the maximum value NxBLOCK_Group MAX (corresponding to DP_NUM_BLOCK_MAX) of which the largest value is 1023.

Each TI group is either mapped directly onto one frame or spread over PI frames. Each TI group is also divided into more than one TI blocks (NTI), where each TI block corresponds to one usage of time interleaver memory. The TI blocks within the TI group may contain slightly different numbers of XFECBLOCKs. If the TI group is divided into multiple TI blocks, it is directly mapped to only one frame. There are three options for time interleaving (except the extra option of skipping the time interleaving) as shown in the below table 33.

TABLE 33

Mode     Description

Option-1 Each TI group contains one TI block and is mapped directly
         to one frame as shown in (a). This option is signaled in the
         PLS2-STAT by DP_TI_TYPE = ‘0’ and
         DP_TI_LENGTH = ‘1’(NTI = 1).
Option-2 Each TI group contains one TI block and is mapped to more
         than one frame. (b) shows an example, where one TI group is
         mapped to two frames, i.e., DP_TI_LENGTH = ‘2’
         (PI = 2) and DP_FRAME_INTERVAL (IJUMP = 2). This
         provides greater time diversity for low data-rate services.
         This option is signaled in the PLS2-STAT by
         DP_TI_TYPE = ‘1’.
Option-3 Each TI group is divided into multiple TI blocks and is
         mapped directly to one frame as shown in (c). Each TI block
         may use full TI memory, so as to provide the maximum
         bit-rate for a DP. This option is signaled in the
         PLS2-STAT signaling by DP_TI_TYPE = ‘0’ and
         DP_TI_LENGTH = NTI, while PI = 1.

In each DP, the TI memory stores the input XFECBLOCKs (output XFECBLOCKs from the SSD/MIMO encoding block). Assume that input XFECBLOCKs are defined as
(d_n,s,0,0, d_n,s,0,1, . . . , d_{n,s,0,Ncells−1}, d_n,s,1,0, . . . , d_{n,s,1,Ncells−1}, . . . , d_{n,s,NxBLOCK_TI(n,s)−1,0}, . . . , d_{n,s,NxBLOCK_TI(n,s)−1,Ncells−1}),
where d_n,s,r,q is the qth cell of the rth XFECBLOCK in the sth TI block of the nth TI group and represents the outputs of SSD and MIMO encodings as follows

$d_{n,s,r,q}=\{\begin{array}{cc}{f}_{n,s,r,q},& \mathrm{the}\mathrm{output}\mathrm{of}\mathrm{SSD}\dots \mathrm{encoding}\\ g_{n,s,r,q},& \mathrm{the}\mathrm{output}\mathrm{of}\mathrm{MIMO}\mathrm{encoding}\end{array}.$

In addition, assume that output XFECBLOCKs from the time interleaver 5050 are defined as
(h_n,s,0, h_n,s,1, . . . , h_n,s,i, . . . , h_{n,s,NxBLOCK_TI(n,s)×Ncells−1}),

where h_n,s,i is the ith output cell (for i=0, . . . , N_{xBLOCK_TI} (n,s)×N_cells−1) in the sth TI block of the nth TI group.

Typically, the time interleaver will also act as a buffer for DP data prior to the process of frame building. This is achieved by means of two memory banks for each DP. The first TI-block is written to the first bank. The second TI-block is written to the second bank while the first bank is being read from and so on.

The TI is a twisted row-column block interleaver. For the sth TI block of the nth TI group, the number of rows N_r of a TI memory is equal to the number of cells N_cells, i.e., N_r=N_cells while the number of columns N_c is equal to the number N_{xBLOCK_TI}(n,s).

FIG. 26 illustrates a basic operation of a twisted row-column block interleaver according to an exemplary embodiment of the present invention.

FIG. 26A illustrates a writing operation in a time interleaver and FIG. 26B illustrates a reading operation in the time interleaver. As illustrated in FIG. 26A, a first XFECBLOCK is written in a first column of a time interleaving memory in a column direction and a second XFECBLOCK is written in a next column, and such an operation is continued. In addition, in an interleaving array, a cell is read in a diagonal direction. As illustrated in FIG. 26B, while the diagonal reading is in progress from a first row (to a right side along the row starting from a leftmost column) to a last row, N_r cells are read. In detail, when it is assumed that z_n,s,i (i=, . . . , N_rN_c) is a time interleaving memory cell position to be sequentially read, the reading operation in the interleaving array is executed by calculating a row index R_n,s,i, a column index C_n,s,i, and associated twist parameter T_n,s,i as shown in an equation given below.

$\begin{array}{cc}\begin{array}{c}\mathrm{GENERATE}\left(R_{n,s,i},C_{n,s,i}\right)=\\ \{\\ R_{n,s,i}=\mathrm{mod}\left(i,N_r\right),\\ T_{n,s,i}=\mathrm{mod}\left(S_{\mathrm{shift}}\times R_{n,s,i},N_c\right),\\ C_{n,s,i}=\mathrm{mod}\left(T_{n,s,i}+\lfloor \frac{i}{N_r}\rfloor ,N_c\right)\\ \}\end{array}& \left[\mathrm{Equation}9\right]\end{array}$

Where, S_shift is a common shift value for a diagonal reading process regardless of N_{xBLOCK IT}(n,s) and the shift value is decided by N_{xBLOCK TI MAX} given in PLS2-STAT as shown in an equation given below.

$\begin{array}{cc}\mathrm{for}\{\begin{array}{cc}\begin{array}{c}{N}_{\mathrm{xBLOCK\_TI}\mathrm{\_MAX}}^{\prime }=\\ N_{\mathrm{xBLOCK\_TI}\mathrm{\_MAX}}+1,\end{array}& \mathrm{if}{N}_{\mathrm{xBLOCK\_TI}\mathrm{\_MAX}}\mathrm{mod}2=0\\ \begin{array}{c}{N}_{\mathrm{xBLOCK}\mathrm{TI}\mathrm{MAX}}^{\prime }=\\ N_{\mathrm{xBLOCK}\mathrm{TI}\mathrm{MAX}},\end{array}& \mathrm{if}{N}_{\mathrm{xBLOCK}\mathrm{TI}\mathrm{MAX}}\mathrm{mod}2=1^{\prime }\end{array}{S}_{\mathrm{shift}}=\frac{N_{\mathrm{xBLOCK\_TI}\mathrm{\_MAX}}^{\prime }-1}{2}& \left[\mathrm{Equation}10\right]\end{array}$

Consequently, the cell position to be read is calculated by a coordinate z_n,s,i=N_rC_n,s,i+R_n,s,i.

FIG. 27 illustrates an operation of a twisted row-column block interleaver according to another exemplary embodiment of the present invention.

In more detail, FIG. 27 illustrates an interleaving array in the time interleaving memory for respective time interleaving groups including a virtual XFECBLOCK when N_{xBLOCK_TI}(0,0)=3, N_{xBLOCK TI}(1,0)=6, and N_{xBLOCK TI}(2,0)=5.

A variable N_{xBLOCK TI}(n,s)=N_r will be equal to or smaller than N′_{xBLOCK_TI_MAX}. Accordingly, in order for a receiver to achieve single memory interleaving regardless of N_{xBLOCK_TI}(n,s), the size of the interleaving array for the twisted row-column block interleaver is set to a size of N_i×N_c=N_cells×N′_{xBLOCK_TI_MAX} by inserting the virtual XFECBLOCK into the time interleaving memory and a reading process is achieved as shown in an equation given below.
p=0;
for i=0;i<N_cellsN_{xBLOCK_TI_MAX}′;i=i+1
{GENERATE(R_n,s,i,C_n,s,i);
V_i=N_rC_n,s,j+R_n,s,j
if V_i<N_cellsN_{xBLOCK TI}(n,s)
{
Z_n,s,p=V_i; p=p+1;
}
}  [Equation 11]

The number of the time interleaving groups is set to 3. An option of the time interleaver is signaled in the PLS2-STAT by DP_TI_TYPE=‘0’, DP_FRAME_INTERVAL=‘1’, and DP_TI_LENGTH=‘1’, that is, NTI=1, IJUMP=1, and PI=1. The number of respective XFECBLOCKs per time interleaving group, of which Ncells=30 is signaled in PLS2-DYN data by NxBLOCK_TI(0,0)=3, NxBLOCK_TI(1,0)=6, and NxBLOCK_TI(2,0)=5 of the respective XFECBLOCKs. The maximum number of XFECBLOCKs is signaled in the PLS2-STAT data by NxBLOCK_Group_MAX and this is continued to └N_{xBLOCK_Group_Max}/N_TI┘=N_{xBLOCK_TI_MAX}=6.

FIG. 28 illustrates a diagonal reading pattern of the twisted row-column block interleaver according to the exemplary embodiment of the present invention.

In more detail, FIG. 28 illustrates a diagonal reading pattern from respective interleaving arrays having parameters N′_{xBLOCK TI MAX}=7 and Sshift=(7−1)/2=3. In this case, during a reading process expressed by a pseudo code given above, when V_i≥N_cellsN_{xBLOCK_TI}(n,s), a value of Vi is omitted and a next calculation value of Vi is used.

FIG. 29 illustrates XFECBLOCK interleaved from each interleaving array according to an exemplary embodiment of the present invention.

FIG. 29 illustrates XFECBLOCK interleaved from each interleaving array having parameters N′_{xBLOCK_TI_MAX}=7 and Sshift=3 according to an exemplary embodiment of the present invention.

FIG. 30 illustrates a synchronization and demodulation module according to an embodiment of the present invention.

The synchronization and demodulation module illustrated in FIG. 30 corresponds to the embodiment of the synchronization and demodulation module described in FIG. 9. Further, the synchronization and demodulation module illustrated in FIG. 30 may perform an inverse operation of the waveform generation module described in FIG. 9.

As illustrated in FIG. 30, the synchronization and demodulation module according to the embodiment of the present invention as an embodiment of a synchronization and demodulation module of a receiving apparatus using m Rx antennas may include m processing blocks for demodulating and outputting a signal input as long as m paths. All m processing blocks may perform the same processing procedure. Hereinafter, an operation of a first processing block 30000 among m processing blocks will be primarily described.

The first processing block 30000 may include a tuner 30100, an ADC block 30200, a preamble detector 30300, a guard sequence detector 30400, a waveform transform block 30500, a time/frequency synchronization block 30600, a reference signal detector 30700, a channel equalizer 30800, and an inverse waveform transform block 30900.

The tuner 30100 selects a desired frequency band and compensates a magnitude of a received signal to output the signal to the ADC block 30200.

The ADC block 30200 may transform the signal output from the tuner 30100 to a digital signal.

The preamble detector 30300 may detect a preamble (alternatively, a preamble signal or a preamble symbol) in order to verify whether the digital signal is a signal of a system corresponding to the receiving apparatus. In this case, the preamble detector 30300 may decode basic transmission parameters received through the preamble.

The guard sequence detector 30400 may detect a guard sequence in the digital signal. The time frequency synchronization block 30600 may perform time/frequency synchronization by using the detected guard sequence and the channel equalizer 30800 may estimate a channel through a sequence received/restored by using the detected guard sequence.

When inverse waveform transform is performed at a transmitting side, the waveform transform block 30500 may perform an inverse transform procedure to the inverse waveform transform. When a broadcast transmitting/receiving system according to the embodiment of the present invention a multi-carrier system, the waveform transform block 30500 may perform an FFT transform procedure. Further, in the case where the broadcast transmitting/receiving system according to the embodiment of the present invention is a single carrier system, when received signals in a time domain are used to be processed in a frequency domain or all of the received signals are processed in the time domain, the waveform transform block 30500 may not be used.

The time/frequency synchronization block 30600 may receive output data of the preamble detector 30300, the guard sequence detector 30400, and the reference signal detector 30700 and perform time synchronization and carrier frequency synchronization including guard sequence detection and block window positioning for a detected signal. In this case, the time/frequency synchronization block 30600 may feed back and use an output signal of the waveform transform block 30500 for frequency synchronization.

The reference signal detector 30700 may detect a received reference signal. Therefore, the receiving apparatus according to the embodiment of the present invention may perform synchronization or channel estimation.

The channel equalizer 30800 may estimate a transmission channel up to each receiving apparatus from each transmitting antenna from the guard sequence or the reference signal and perform channel equalization for each received data by using the estimated channel.

When the waveform transform block 30500 performs waveform transform in order to efficiently perform the synchronization and channel estimation/equalization, the inverse waveform transform block 30900 may serve to restore each received data to an original received data domain again. In the case where the broadcast transmitting/receiving system according to the embodiment of the present invention is the single carrier system, the waveform transform block 30500 may perform FFT in order to perform the synchronization/channel estimation/equalization in the frequency domain and the inverse waveform transform block 30900 performs IFFT for a signal of which channel equalization is completed to restore a transmitted data symbol. When the broadcast transmitting/receiving system according to the embodiment of the present invention is a multi-carrier system, the inverse waveform transform block 30900 may not be used.

Further, the aforementioned blocks may be omitted according to an intention of a designer or substituted by other blocks having a similar or the same function.

FIG. 31 illustrates a frame parsing module according to an embodiment of the present invention.

The frame parsing module illustrated in FIG. 31 correspond to the embodiment of the frame parsing module described in FIG. 9.

As illustrated in FIG. 31, the frame parsing module according to the embodiment of the present invention may include at least one or more block deinterleavers 31000 and at least one or more cell demapper 31100.

The block deinterleaver 31000 may perform deinterleaving for data per each signal block with respect to data input into respective data paths of m receiving antennas and processed in the synchronization and demodulation module. In this case, as described in FIG. 8, when pair-wise interleaving is performed at the transmitting side, the block deinterleaver 31000 may process two consecutive data for each input path as one pair. Therefore, the block deinterleaver 31000 may output two consecutive output data even when deinterleaving the data. Further, the block deinterleaver 31000 performs an inverse procedure of the interleaving procedure performed at the transmitting side to output the data according to an original data sequence.

The cell demapper 31100 may extract cells corresponding to common data from a received signal frame, cells corresponding to a data pipe, and cells corresponding to PLS data. In case of need, the cell demapper 31100 merges data distributed and transmitted to a plurality of parts to output the merged data as one stream. Further, as described in FIG. 7, when two consecutive cell input data are processed as one pair to be mapped, the cell demapper 31100 may perform the pair-wise cell demapping of processing two consecutive input cells as one unit as an inverse procedure corresponding thereto.

Further, the cell demapper 31100 may extract and output all PLS signaling data received through a current frame as PLS-pre and PLS-post data, respectively.

The aforementioned blocks may be omitted according to an intention of a designer or substituted by other blocks having a similar or the same function.

FIG. 32 illustrates a demapping and decoding module according to an embodiment of the present invention.

The demapping and decoding module illustrated in FIG. 32 corresponds to the embodiment of the demapping and decoding module described in FIG. 9.

As described above, the coding and modulation module of the transmitting apparatus according to the embodiment of the present invention may independently apply and process SISO, MISO, and MIMO schemes to input data pipes for respective paths. Therefore, the demapping and decoding module illustrated in FIG. 32 may also include blocks for SISO, MISO, and MIMO-processing data output from a frame parser to correspond to the transmitting apparatus, respectively.

As illustrated in FIG. 32, the demapping and decoding module according to the embodiment of the present invention may include a first block 32000 for the SISO scheme, a second block 32100 for the MISO scheme, and a third block 32200 for the MIMO scheme, and a fourth block 32300 processing PLS pre/post information. The demapping and decoding module illustrated in FIG. 32 is just an embodiment and the demapping and decoding module may include only the first block 32000 and the fourth block 32300, only the second block 32100 and the fourth block 32300, and only the third block 32200 and the fourth block 32300 according to the intension of the designer. That is, the demapping and decoding module may include blocks for processing the respective data pipes similarly or differently according to the intention of the designer.

Hereinafter, each block will be described.

The first block 32000 as a block for SISO-processing the input data pipe may include a time de-interleaver block 32010, a cell de-interleaver block 32020, a constellation demapper block 32030, a cell to bit mux block 32040, a bit de-interleaver block 32050, and an FEC decoder block 32060.

The time de-interleaver block 32010 may perform an inverse procedure of a time interleaver block. That is, the time de-interleaver block 32010 may deinterleave an input symbol interleaved in the time domain to an original position.

The cell de-interleaver block 32020 may perform an inverse procedure of a cell interleaver block. That is, the cell de-interleaver block 32020 may deinterleave positions of cells spread in one FEC block to original positions.

The constellation demapper block 32030 may perform an inverse procedure of a constellation mapper block. That is, the constellation demapper block 32030 may demap an input signal of a symbol domain to data of a bit domain. Further, the constellation demapper block 32030 may output bit data decided by performing a hard decision and output a log-likelihood ratio (LLR) of each bit corresponding to a soft decision value or a probabilistic value. When the transmitting side applies a rotated constellation in order to acquire an additional diversity gain, the constellation demapper block 32030 may perform 2-dimensional LLR demapping corresponding to the rotated constellation. In this case, the constellation demapper 32030 may perform a calculation so that the transmitting apparatus compensates a delay value performed with respect to an I or Q component at the time of calculating the LLR.

The cell to bit mux block 32040 may perform an inverse procedure of a bit to cell demux block. That is, the cell to bit mux block 32040 may restore bit data mapped in a bit to cell demux block to an original bit stream form.

The bit de-interleaver block 32050 may perform an inverse procedure of a bit interleaver block. That is, the bit de-interleaver block 32050 may deinterleave the bit stream output in the cell to bit mux block 32040 according to an original sequence.

The FEC decoder block 32060 may perform an inverse procedure of an FEC encoder block. That is, the FEC decoder block 32060 may correct an error which occurs on a transmission channel by performing LDPC decoding and BCH decoding.

The second block 32100 as a block for MISO-processing the input data pipe may include the time de-interleaver block, the cell de-interleaver block, the constellation demapper block, the cell to bit mux block, the bit de-interleaver block, and the FEC decoder block similarly to the first block 32000 as illustrated in FIG. 32, but the second block 32100 is different from the first block 32000 in that the second block 32100 further includes an MISO decoding block 32110. Since the second block 32100 performs a procedure of the same role from the time deinterleaver up to the output similarly to the first block 32000, a description of the same blocks will be omitted.

The MISO decoding block 32110 may perform an inverse procedure of the MISO processing block. When the broadcast transmitting/receiving system according to the embodiment of the present invention is a system using STBC, the MISO decoding block 32110 may perform Alamouti decoding.

The third block 32200 as a block for MIMO-processing the input data pipe may include the time de-interleaver block, the cell de-interleaver block, the constellation demapper block, the cell to bit mux block, the bit de-interleaver block, and the FEC decoder block similarly to the second block 32100 as illustrated in FIG. 32, but the third block 32200 is different from the second block 32100 in that the third block 32200 further includes an MIMO decoding block 32210. Operations of the time de-interleaver, cell de-interleaver, constellation demapper, cell to bit mux, and bit de-interleaver blocks included in the third block 32200 may be different from operations and detailed functions of the corresponding blocks included in the first and second blocks 32000 and 32100, but the blocks included in the third block 32200 are the same as the blocks included in the first and second blocks in terms of basic roles.

The MIMO decoding block 32210 may receive output data of the cell deinterleaver as an input with respect to m receiving antenna input signal and perform MIMO decoding as an inverse procedure of the MIMO processing block. The MIMO decoding block 32210 may perform maximum likelihood decoding in order to perform maximum decoding performance or sphere decoding for reducing complexity. Alternatively, the MIMO decoding block 32210 performs MMSE detection or perform iterative decoding combinationally with the MMSE detection to secure improved decoding performance.

The fourth block 32300 as a block for processing PLS pre/post information may perform SISO or MISO decoding. The fourth block 32300 may perform an inverse procedure of the fourth block.

The operations of the time de-interleaver, cell de-interleaver, constellation demapper, cell to bit mux, and bit de-interleaver blocks included in the fourth block 32300 may be different from operations and detailed functions of the corresponding blocks included in the first to third blocks 32000 to 32200, but the blocks included in the fourth block 32300 are the same as the blocks included in the first to third blocks in terms of basic roles.

A shortened/punctured FEC decoder 32310 may perform an inverse procedure of the shortened/punctured FEC encoder block. That is, the shortened/punctured FEC decoder 32310 may perform de-shortening and de-puncturing, and thereafter, FEC decoding data received while being shortened/punctured according to the length of the PLS data. In this case, since the FEC decoder used in the data pipe may be similarly used even in the PLS, separate FEC decoder hardware for only the PLS is not required, and as a result, system design is easy and efficient coding is available.

The aforementioned blocks may be omitted according to an intention of a designer or substituted by other blocks having a similar or the same function.

Consequently, as illustrated in FIG. 32, the demapping and decoding module according to the embodiment of the present invention may output to the output processor the data pipe and the PLS information processed for each path.

FIGS. 33 and 34 illustrate an output processor according to an embodiment of the present invention.

FIG. 33 illustrates an output processor according to an embodiment of the present invention.

The output processor illustrated in FIG. 33 corresponds to the embodiment of the output processor described in FIG. 9. Further, the output processor illustrated in FIG. 33 which is used to receive a single data pipe output from the demapping and decoding module and output a single output stream may perform an inverse operation of the input formatting module.

The output processor of FIG. 33 implements functions, processes, and/or methods proposed in FIGS. 50, 51, and 53 to be described below.

The output processor illustrated in FIG. 33 may include a BB Descrambler 33000, a padding removable block 33100, a CRC-8 decoder block 33200, and a BB frame processor block 33300.

The BB Descrambler block 33000 generates the same PRBS as used at the transmitting side with respect to an input bit stream and XOR-operates the PRBS and the bit stream to perform descrambling.

The padding removable block 33100 may remove a padding bit inserted by the transmitting side as necessary.

The CRC-8 decoder block 33200 perform CRC decoding of the bit stream received from the padding removable block 33100 to check a block error.

The BB frame processor block 33300 may decode information transmitted to the BB frame header and restore an MP3G-TS, an IP stream (v4 or v6), or a generic stream.

The aforementioned blocks may be omitted according to the intention of the designer or substituted by other blocks having a similar or the same function.

FIG. 34 illustrates an output processor according to another embodiment of the present invention.

The output processor illustrated in FIG. 34 corresponds to the embodiment of the output processor described in FIG. 9. Further, the output processor illustrated in FIG. 34 corresponds to the case of receiving multiple data pipes output from the demapping and decoding module. Decoding the multiple data pipes may include the case of merging common data which may be commonly applied to a plurality of data pipes and a data pipe associated with the common data and decoding the merged common data and data pipe or the case in which the receiving apparatus simultaneously decodes several services or service components (including a scalable video service).

The output processor illustrated in FIG. 34 may include the BB descrambler block, the padding removable block, the CRC-8 decoder block, and the BB frame processor block 33300 similarly to the output processor.

The output processor of FIG. 34 implements functions, processes, and/or methods proposed in FIGS. 50, 51, and 53 to be described below.

The respective blocks may be different from the blocks described in FIG. 33 in terms of the operations and the detailed operations, but the respective blocks are the same as the blocks of FIG. 33 in terms of the basic role.

A de-jitter buffer block 34000 included in the output processor illustrated in FIG. 34 may compensate a delay arbitrarily inserted at the transmitting side according to a restored time to output (TTO) parameter for synchronizing the multiple data pipes.

Further, a null packet insertion block 34100 may restore a null packet removed in the stream by referring to restored deleted null packet (DNP) information and output the common data.

A TS clock regeneration block 34200 may restore detailed time synchronization of an output packet based on ISCR-input stream time reference information.

A TS recombining block 34300 recombines the common data output from the null packet insertion block 34100 and the data pipes associated with the common data to restore the recombined common data and data pipes to the original MPEG-TS, IP stream (v4 or v6), or generic stream and output the restored MPEG-TS, IP stream (v4 or v6), or generic stream. The TTO, DNP, and ISCR information may be all acquired through the BB frame header.

An in-band signaling decoder block 34400 may restore and output in-band physical layer signaling information transmitted through a padding bit field in each FEC frame of the data pipe.

The output processor illustrated in FIG. 34 performs BB descrambling PLS-pre information and PLS-post information input according to the PLS-pre path and the PLS-post path, respectively and decodes the descrambled data to restore the original PLS data. The restored PLS data may transferred to the system controller in the receiving apparatus and the system controller may provide a required parameter to the synchronization and demodulation module, the frame parsing module, the demapping and decoding module, and the output processor module in the receiving apparatus.

The aforementioned blocks may be omitted according to the intention of the designer or substituted by other blocks having a similar or the same function.

FIG. 35 illustrates a coding and modulation module according to another embodiment of the present invention.

The coding and modulation module illustrated in FIG. 35 may include a first block 35000 for the SISO scheme, a second block 35100 for the MISO scheme, and a third block 35200 for the MIMO scheme, and a fourth block 35300 for processing PLS pre/post information in order to control QoS for each service or service component transmitted through each data pipe. Further, the coding and modulation module according to the embodiment of the present invention may include blocks for similarly or differently processing the respective data pipes according to the intention of the designer as described above. The first to fourth blocks 35000 to 35300 illustrated in FIG. 35 may include substantially the same blocks as the first to fourth blocks.

However, the first to fourth blocks 35000 to 35300 are different from the aforementioned first to fourth blocks in that a function of a constellation mapper block 35010 included in the first to third blocks 35000 to 35200 is different from that of the constellation mapper block included in the first to third blocks, and a rotation and I/O interleaver block 35020 is included between the cell interleaver and the time interleaver of the first to fourth blocks 35000 to 35300, and a configuration of the third block 35200 for the MIMO scheme is different from that of the third block for the MIMO scheme.

The constellation demapper block 35010 illustrated in FIG. 35 may map an input bit word to a complex symbol.

The constellation mapper block 35010 illustrated in FIG. 35 may be commonly applied to the first to third blocks 35000 to 35200 as described above.

The rotation and I/O interleaver block 35020 independently interleaves in-phase and quadrature-phase components of respective complex symbols of cell-interleaved data output from the cell interleaver to output the interleaved components by the unit of the symbol. The number of input data and output symbols of the rotation and I/O interleaver block 35020 is two or more and may be changed according to the intention of the designer. Further, the rotation and I/O interleaver block 35020 may not interleave the in-phase components.

The rotation and I/O interleaver block 35020 may be commonly applied to the first to fourth blocks 35000 to 35300 as described above. In this case, whether the rotation and I/O interleaver block 35020 is applied to the fourth block 35300 for processing the PLS pre/post information may be signaled through the aforementioned preamble.

The third block 35200 for the MIMO scheme may include a Q-block interleaver block 35210 and a complex symbol generator block 35220 as illustrated in FIG. 35.

The Q-block interleaver block 35210 may perform permutation of a parity part of the FEC-encoded FEC block received from the FEC encoder. Therefore, a parity part of an LDPC H matrix may be made in a cyclic structure similarly to an information part. The Q-block interleaver block 35210 permutates sequences of bit blocks having a Q size in the LDPC H matrix and thereafter, performs row-column block interleaving of the bit blocks to generate and output a final bit stream.

The complex symbol generator block 35220 may receive the bit streams output from the Q-block interleaver block 35210 and map the received bit streams to the complex symbol and output the mapped bit streams and complex symbol. In this case, the complex symbol generator block 35220 may output the symbols through at least two paths. This may be changed according to the intension of the designer.

The aforementioned blocks may be omitted according to the intention of the designer or substituted by other blocks having a similar or the same function.

Consequently, as illustrated in FIG. 35, the coding and modulation according to another embodiment of the present invention may output the data pipe, the PLS-pre information, and the PLS-post information processed for each path to a frame structure module.

FIG. 36 illustrates a demapping and decoding module according to another embodiment of the present invention.

The demapping and decoding module illustrated in FIG. 36 corresponds to another embodiment of the demapping and decoding module described in FIGS. 9 and 32. Further, the demapping and decoding module illustrated in FIG. 36 may perform an inverse operation of the coding and modulation module described in FIG. 35.

As illustrated in FIG. 36, the demapping and decoding module according to another embodiment of the present invention may include a first block 36000 for the SISO scheme, a second block 36100 for the MISO scheme, a third block 36200 for the MIMO scheme, and a fourth block 36300 for processing the PLS pre/post information. Further, the demapping and decoding module according to the embodiment of the present invention may include blocks for similarly or differently processing the respective data pipes according to the intention of the designer as described above. The first to fourth blocks 36000 to 36300 illustrated in FIG. 36 may include substantially the same blocks as the first to fourth blocks 32000 to 32300 described in FIG. 32.

However, the first to fourth blocks 36000 to 36300 are different from the aforementioned first to fourth blocks in that an I/Q deinterleaver and derotation block 36010 is included between the time deinterleaver and the cell deinterleaver, a function a constellation demapper block 36020 included in the first to third blocks 36000 to 36200 is different from the function of the constellation mapper 42030 included in the first to third blocks 32000 to 32200 of FIG. 32, and a configuration of the third block 36200 for the MIMO scheme is different from that of the third block 36200 for the MIMO scheme illustrated in FIG. 36. Hereinafter, the same blocks as FIG. 36 will not described and the aforementioned differences will be primarily described.

The I/Q deinterleaver and derotation block 36010 may perform an inverse procedure of the rotation and I/Q interleaver block 35020 described in FIG. 35. That is, the I/Q deinterleaver and derotation block 36010 may deinterleave I and Q components I/Q interleaved and transmitted at the transmitting side and derotate and output the complex symbol having the restored I/Q component again.

The I/Q deinterleaver and derotation block 36010 may be commonly applied to the first to fourth blocks 36000 to 36300 as described above. In this case, whether the I/Q deinterleaver and derotation block 36010 is applied to the fourth block 36300 for processing the PLS pre/post information is may be signaled through the aforementioned preamble.

The constellation demapper block 36020 may perform an inverse procedure of the constellation mapper block 35010 described in FIG. 35. That is, the constellation demapper block 36020 may not perform derotation, but demap the cell-deinterleaved data.

The third block 36200 for the MIMO scheme may include a complex symbol generator block 36210 and a Q-block deinterleaver block 36220 as illustrated in FIG. 36.

The complex symbol parsing block 36210 may perform an inverse procedure of the complex symbol generator block 35220 described in FIG. 35. That is, the complex symbol parsing block 36210 may parse the complex data symbol, and demap the parsed complex data symbol to the bit data and output the data. In this case, the complex symbol parsing block 36210 may receive the complex data symbols through at least two paths.

The Q-block deinterleaver block 36220 may perform an inverse procedure of the Q-block interleaver block 35210 described in FIG. 35. That is, the Q-block deinterleaver block 36220 may restore the Q-size blocks by the row-column deinterleaving, restore the permutated sequences of the respective blocks to the original sequences, and thereafter, restore the positions of the parity bits to the original positions through the parity deinterleaving and output the parity bits.

The aforementioned blocks may be omitted according to the intention of the designer or substituted by other blocks having a similar or the same function.

Consequently, as illustrated in FIG. 36, the demapping and decoding module according to another embodiment of the present invention may output the data pipe and the PLS information processed for each path to the output processor.

Hereinafter, a new BBF header structure for reducing the overhead of the BBF transmission and adding various functions using the padding field proposed in the specification will be described in detail.

FIG. 37 illustrates one example of a mode adaptation module proposed in the specification.

As described above, the input formatting module includes the mode adaptation module.

A configuration of the mode adaptation module of FIG. 37 may be partially different from that of the mode adaptation module described above.

As illustrated in FIG. 37, the mode adaptation module may be configured to include at least one of a pre processing or splitting block 3710, an input interface block 3720, an input stream synchronizer block 3730, a delay compensating block 3740, a header compression block 3750, a null data reuse block 3760, a null packet detection block 3770, and a BB frame header insertion block 3780.

The pre processing block may split or demultiplex a plurality of input streams to a plurality of data pipes. Herein, the data pipe may be referred to as a physical layer pipe (PLP). Herein, the input stream may be a MPEG2-TS, an Internet protocol (IP), and/or the generic stream (GS).

In some embodiments, an input stream having a different form may also be available.

The header compression block may compress a packet header. This may used to increase transmission efficiency of the TS or IP input stream. Since the receiver has had a priory information of the header, known data may be removed at the transmitting side. For example, information such as the PID, or the like may be compressed and information having different forms may be removed or substituted. In some embodiments, the header compression block may be positioned subsequent to the null packet deletion block.

The null data reuse block may perform an operation of inserting null data into the packet after the header compression. This block may be omitted in some embodiments.

The BB frame header insertion block may operate in a different mode than the aforementioned BB frame header insertion block.

The specification provides a method for reducing signaling of a data field length of the frame (Data field length signaling reduction method).

Further, the specification provides a method for reducing the overhead for the transmission of the BB frame to the FEC block.

That is, a new BB frame configuration method proposed in the specification may be performed in the BB frame header insertion block.

By the method proposed in the specification, the BB frame and the BB frame header may be configured. The specification may relate to a procedure in which the BB frame is generated in order to transfer the input stream to the FEC block through the input processing.

Further, the specification may relate to a method for increasing the transmission efficiency by decreasing the size of the BB frame header. Detailed contents associated with the BB frame header insertion block will be described below.

In the related art, in the BB frame, a data field length (DFL) was allocated to each BB frame header in order to notify the length of the data field to the receiving apparatus. The DFL may be 16 bits or 11 bits. As a result, the related art is large in overhead for the BBF transmission.

When the data field length is changed in the BB frame having the continuously same size, the BB frame may not fully be filled with the data or the BB frame may include in-band signaling information.

In another related art, the BB frame transmitted only an indicator instead of directly notifying the length of the data field. In addition, the BB frame signaled the length of a padding of the BB frame in the padding. However, in this case, since the in-band signaling is not considered, when the in-band signaling is operated, there may be a restriction.

A method proposed in the specification may be a method for configuring the BB frame header that can reduce the DFL and insert an additional field. Herein, the additional field may indicate a type of the in-band signaling, or the like or may be used for another purpose.

Through the method proposed in the specification, the overhead for the BBF transmission may be minimized and various functions may be added to the padding (alternatively, stuffing) field.

FIG. 38 illustrates one example of an output processor proposed in the specification.

As described above, the output processor may include the BB frame header parser block. Components the output processor of FIG. 38 may be partially different from those of the output processor described above.

The output processor of FIG. 38 implements functions, processes, and/or methods proposed in FIGS. 50, 51, and 53 to be described below.

The output processor may be configured to include at least one of a BB frame header parser block 3810, a null packet insertion block 3820, a null data regenerator block 3830, a header decompression block 3840, a TS clock regeneration block 3850, a de-jitter buffer block 3860, and a TS recombining block 3870.

Herein, the null packet insertion block, the TS clock regeneration block, the de-jitter buffer bloc, and the TS recombining block may perform the same operations as the blocks of the output processor.

The BB frame header configuring method proposed in the specification may correspond to the BB frame header parser block at the receiving side (alternatively, the receiving apparatus or the receiver).

The BB frame header parser block 3810 may operate differently from the BB frame header parser block. The BB frame header parser block 3810 may perform an operation of parsing the BB frame header according to the method proposed in the specification.

The BB frame and the BB frame header configuring method proposed in the specification will be described below.

The null data regeneration block may correspond to the null data reuse block at the receiving side. The null data regeneration block may output an output to the heard decompression block. This block may be omitted in some embodiments.

The header decompression block may correspond to the header compression block at the receiving side. The header decompression block may restore the compression of the compressed packet header. As described above, the packet header may be compressed to increase the transmission efficiency of the TS or IP input stream. In some embodiments, the header decompression block may be positioned ahead of the null packet insertion block.

FIG. 39 illustrates one example of a BB frame structure in the related art.

Data streams input into the input formatting module, in particular, the mode adaptation module may be sliced with an appropriate length so that the BICM module may perform FEC. Therefore, the BB frame may be generated.

The length of the data field of the BB frame corresponds to a value acquired by subtracting the length of the BB frame header from the total length of the BB frame.

An actual user packet (UP) may be inserted into a data field part of the BBF.

The length of the data field may be notified in the data field length (DFL) field of the BB frame header. The DFL field may be expressed as DFL.

The BB frame generated through input formatting may be encoded in a predetermined FEC block.

Herein, the total length of the BB frame may be fixed.

Further, when the length of the data field of the BBF is changed, the BB frame may be not fully filled with the UP because the UP is not sufficient or the in-band signaling information may be intentionally included.

When the BB frame may be not fully filled, the corresponding space may be filled with stuffing. The stuffing may be expressed as the padding.

FIG. 40 illustrates yet another example of the BB frame structure in the related art.

As illustrated in FIG. 40b, when the data field (alternatively, payload) of the BB frame is not fully filled with data to be transmitted, stuffing bytes may be inserted.

A STUFFI field may be inserted into the BBF header in order to signal the stuffing bytes. The BBF header is a TS header.

The STUFFI field represents an indicator of 1 bit indicating whether the stuffing bytes are present in the BB frame.

When the payload of the BB frame is fully filled with the UP, the stuffing bytes are not present. In this case, the STUFFI may be set to ‘0’.

When the payload of the BB frame is not fully filled with the UP, the stuffing bytes may be present. In this case, the STUFFI may be set to ‘1’.

When the stuffing bytes are included in the BB frame, the length of the stuffing byte may be verified through a first byte of the BB frame payload.

As one example, when the first byte value of the BB frame payload is 0xFF, one stuffing byte (stuffing byte of 1 byte) may be included in the BB frame payload.

When values of the first byte and a second byte of the BB frame payload are 0xFE and 0xFF, respectively, two stuffing bytes may be included in the BB frame payload.

Herein, when the stuffing bytes are two or more (the size of the stuffing byte is 2 bytes or more), the first and second byte values are set to MSB and LSB, respectively to signal the length of the stuffing byte.

In a table of FIG. 36a, ‘N’ represents the total length of the stuffing byte.

When a value of ‘N’ is 1 byte, the length of a field indicating the total length of the stuffing byte may be 1 byte. In this case, the field value may be set to 0xFF.

Herein, the field indicating the total length of the stuffing byte may be expressed as a stuffing byte length field.

When the value of ‘N’ is 2 bytes, the length of the length field of the stuffing byte may be 2 bytes.

In this case, the stuffing byte length field value may be set to 0xFE and 0xFF.

When the value of ‘N’ is ‘3 or more’, as one example, even when N has a value between 3 and 65278, the length oft eh stuffing byte length field may be 2 bytes.

In this case, the stuffing byte length field may be constituted by the MSB and the LSB.

That is, the 2-byte stuffing byte length field may signal the total length of the stuffing byte.

As illustrated in FIG. 40, additional stuffing bytes may be present subsequent to the MSB and the LSB. That is, since the total stuff byte length is N and the lengths of the MSB and the LSB are 2 bytes, the length of the subsequent stuffing byte is N−2 bytes.

FIG. 41 illustrates yet another example of the BB frame structure in the related art.

As illustrated in FIG. 41, a 2-bit indicator may be used in order to indicate a state of the stuffing byte. The indicator may be expressed as a padding indicator (PADI).

When the stuffing byte, that is, the padding is not included in the BBF payload (alternatively, the data field or the FEC frame), the PADI may be set to ‘00’.

In a first BB frame illustrated in FIG. 41b, the PADI may be set to ‘00’ and it may be verified that no padding in the BBF payload.

When the PADI is ‘01’, it may be represented that the length of the padding included in the BBF payload is 1 byte.

In a second BB frame illustrated in FIG. 41b, the PADI may be set to ‘01’ and it may be verified that the length of the padding is 1 byte. ‘P’ which is shown represents the padding byte.

When the PADI is ‘10’, it may be represented that the padding bytes are two or more.

In this case, the padding field may signal the length of the padding by using the MSB and the LSB.

In a third BB frame illustrated in FIG. 41b, it can be seen that the PADI value is set to ‘10’ and the first and second bytes of the padding field are allocated to the MSB and the LSB, respectively.

An additional padding marked with ‘P’ may be present subsequent to the MSB and the LSB.

FIG. 42 illustrates one example of a BB frame structure proposed in the specification.

The specification provides the following scheme for the BB frame and the configuration of the BB frame header.

The BB frame may be configured to include at least one of the BB frame header, the stuffing field, and the payload.

FIG. 42 illustrates one example of a BB frame structure in which the stuffing field is positioned ahead of the payload.

The stuffing field may be positioned subsequent to the payload in some embodiments and this will be described in detail in FIGS. 44 and 45.

The stuffing field and the payload are combined to be referred to as the BB frame payload (alternatively, the BB frame data field or FEC frame).

The BB frame header may describe a format of the payload, that is, the data filed.

Further, information associated with a deleted null packet (DNP) or an input stream synchronizer (ISSY) may be additionally inserted ahead of the stuffing field.

As described above, the payload may mean the data field.

The BB frame header may include the STUFFI field.

The STUFFI field may serve as the indicator indicating whether the stuffing bytes are present in the BB frame.

The STUFFI field may be 1 bit. In some embodiments, the position of the STUFF1 may be changed.

As one example, when the STUFFI value is ‘0’, the BB frame does not include the stuffing field and may not include event he signaling field.

When the STUFFI field value is ‘1’, the BB frame may include stuffing field or the in-band signaling field. That is, information other than the UP, that is, the padding or in-band field may be additionally present in the payload.

In some embodiments of the present invention, meanings represented by ‘0’ and ‘1’ of the STUFFI value may be switched to each other.

The stuffing field may include at least one of a stuffing field header and a stuffing data area.

The stuffing data area may include at least one of stuffing data and in-band signaling information.

The stuffing field header may be 2 bytes in some embodiments.

Further, the stuffing field header may include at least one of STUFF_ONE (alternatively, PAD_ONE), STUFF_TYPE (PAD_TYPE), and STUFF_LEN (alternatively, PAD_LEN).

A 1st byte illustrated in FIG. 42 represents a first byte of the stuffing field.

A 2nd byte may also be included in the stuffing field. In some embodiments, first two bytes (1st byte and 2nd byte) may correspond to the stuffing field header.

In some embodiments, a third byte (3rd byte) or later may be included in the stuffing data area or the payload.

The PAD_ONE field may be expressed as a STUFF_ONE field in some embodiments.

When the STUFFI is ‘1’, STUFF_ONE may be verified. The STUFF_ONE may represent whether the length of the stuffing byte is 1 byte. The STUFF_ONE may be a 1-bit MSB. When the STUFF_ONE is 1, the length of the stuffing byte may be 1 byte. In this case, STUFF_LEN_LSB representing the length of the stuffing byte may not be used.

Further, all values of STUFF_LEN_MSB may be set to 0. In this case, all values of STUFF_LEN_MSB may be set to 1. That is, in some embodiments, the 1-byte stuffing byte may have a value of 00000000, 11111111, 10000000, or 01111111.

When the STUFF_ONE is 0, the length of the stuffing byte may be larger than 1 byte.

In this case, the 2-byte stuffing field header may be used to represent the length and the type of the stuffing data area.

The values of the STUFF_ONE may be switched meanings to each other depending on the designer. That is, the meanings represented by 1 and 0 may be switched to each other.

The illustrated STUFF_ONE (PAD_ONE) may be positioned at the first bit of the first byte. The position may be changed in some embodiments. The STUFF_ONE may be positioned at the BB frame header in some embodiments.

In some embodiments, one field of 2 bits, which serves as the STUFFI and the STUFF_ONE may be configured in some embodiments. Since each of the STUFFI and the STUFF_ONE is 1 bit, one field of 2 bits is configured and the roles of the STUFFI and the STUFF_ONE may be substituted. The field may be positioned at the BB frame header or in the stuffing field.

PAD_LEN may be referred to as STUFF_LEN in some embodiments. The STUFF_LEN may include at least one of STUFF_LEN_MSB and STUFF_LEN_LSB.

The STUFF_LEN_MSB and the STUFF_LEN_LSB may be 5 and 8-bit fields, respectively.

The STUFF_LEN_MSB and STUFF_LEN_LSB fields may be used to represent the total length of the stuffing field. In some embodiments, the lengths of the STUFF_LEN_MSB and the STUFF_LEN_LSB are switched to each other to be 8 bits and 5 bits, respectively. Further, in some embodiments, the positions of both sides may also be switched to each other. In some embodiments, the field indicating the length of the padding may be positioned in the stuffing data area.

In the related art, the length of the padding was expressed by using first 2 bytes. However, when 64K LDPC is used, the length of the padding has a value of maximum 6370 bytes (64 k, 5/6 code rate, BCH code). Therefore, the length of the padding may be sufficiently expressed by 13 bits (2{circumflex over ( )}13=8192 bytes).

Accordingly, the PAD_LEN proposed in the specification may have 13 (5+8) bits.

When the length of the padding is expressed by 13 bits, spare 2 bits in first 2 bytes may remain.

In the specification, a method is provided, which allocates spare 2 bits to PAD_TYPE to signal the type when the padding area is used for another purpose (for example, the in-band signaling).

STUFF_TYPE may be referred to as PAD_TYPE in some embodiments.

The STUFF_TYPE as the 2-bit field may represent the type of the stuffing data (alternatively, the stuffing data area) as described above.

As illustrated in FIG. 38, when the STUFF_TYPE value is ‘00’, the stuffing data area may include only the stuffing data.

When the STUFF_TYPE value is ‘01’, specific-type in-band signaling information may be included in the stuffing data area together with the stuffing data.

When the STUFF_TYPE value is ‘10’, another-type in-band signaling information may be included in the stuffing data area together with the stuffing data.

When the STUFF_TYPE value is ‘11’, both the specific-type and another-type in-band signaling information may be included in the stuffing data area together with the stuffing data.

Herein, the specific-type in-band signaling information may mean ‘in-band A’ and the another-type in-band signaling information may mean ‘in-band B’.

This is just one embodiment and the type indicated by the STUFF_TYPE value may be changed by various schemes.

Further, the STUFF_TYPE may indicate the BB frame payload and the configuration of the payload. For example, the STUFF_TYPE may indicate the position of a normal first packet which is not cut in the payload.

As proposed in the specification, when the signaling is performed in the stuffing field, the in-band signaling may be inserted into a plurality of other frames. Further, this case may be distinguished from the case in which only the padding is included without the in-band signaling.

The STUFF_TYPE may be positioned at the BB frame header in some embodiments.

Alternatively, as described in the embodiment, the STUFF_TYPE may be positioned in the stuffing field. In some embodiments, the length of the STUFF_TYPE may be changed.

The values of the STUFF_TYPE may be switched meanings to each other depending on the designer.

For example, a meaning represented by 00 and a meaning represented by 11 may be switched to each other. Further, a meaning represented by 10 and a meaning represented by 01 may be switched to each other.

All of the stuffing data may have the value of 0 or 1 in some embodiments.

Hereinafter, case #1 to case #6 illustrated in FIG. 42 will be described in detail.

(1) Case #1 illustrates a case where stuffing data and in-band signaling are not included in the BB frame.

In this case, the STUFFI field may be set to ‘0’. Accordingly, in the structure of the BB frame, the data area, that is, the payload may be positioned next to the BB frame header.

(2) Case #2 illustrates a case where a stuffing field of 1 byte exists in the BB frame and the in-band signaling does not exist.

In this case, the STUFFI field may be set to ‘1’. That is, the BB frame includes a stuffing field and the stuffing field may have a size of 1 byte.

Here, the first bit of the stuffing field represents a STUFF_ONE field, and has a value of ‘1’ because the size of the stuffing field is 1 byte.

The remaining 7 bits of the stuffing field may have a value of 1111111.

Accordingly, the stuffing field of 1 byte may be expressed by 11111111.

(3) Case #3 illustrates a case where a stuffing field of more than 1 byte exists in the BB frame and the in-band signaling does not exist.

That is, the stuffing field may be 2 byte or larger than 2 bytes.

Since the stuffing field exists, the STUFFI field may be set to ‘1’.

The stuffing field may have the stuffing field header of 2 bytes. The first bit of the first byte of the stuffing field header corresponds to a STUFF_ONE field.

The STUFF_ONE field may be set to a value of ‘0’ because the size of the stuffing field is larger than 1 byte.

The first bit of the first byte of the stuffing field header corresponds to a STUFF_TYPE field.

Since only the stuffing data exists in the stuffing data area of the BB frame, as described above, the STUFF_TYPE may have a value of 00.

In the drawing, as another exemplary embodiment, a case where the STUFF_TYPE has a value of 11 is illustrated.

That is, this case is the case where only the stuffing data exists in the stuffing data area of the BB frame, and the STUFF_TYPE field may be indicated as the value of 11.

Thereafter, STUFF_LEN_MSB and STUFF_LEN_LSB of the stuffing field header may have length information of the stuffing field. As described above, the length of the stuffing field may be expressed by using a total of 13 bits. After the STUFF_LEN_MSB and the STUFF_LEN_LSB, the stuffing data area may be positioned. In this case, only the stuffing data may be positioned in the stuffing data area.

(4) Case #4 illustrates a case where a stuffing field of more than 1 byte exists in the BB frame and the in-band signaling exists.

In this case, the stuffing data and in-band A signaling may exist in the stuffing data area of the BB frame.

The in-band A signaling may mean a specific type of in-band signaling described above. In this case, because the stuffing field exists, STUFFI may have a value of 1.

The first bit of the first byte of the stuffing field header is the STUFF_ONE field and may have a value of ‘0’ because the size of the stuffing field is larger than 1 byte.

Second and third bits of the first byte of the stuffing field header may be the aforementioned STUFF_TYPE field.

Since only the in-band A signaling exists in the stuffing data area of the BB frame, as described above, the STUFF_TYPE may have a value of 10. According to an exemplary embodiment, the value may also be 01.

Next, STUFF_LEN_MSB and STUFF_LEN_LSB of the stuffing field header may have length information of the stuffing field. As described above, the length of the stuffing field may be expressed by using a total of 13 bits. After the STUFF_LEN_MSB and the STUFF_LEN_LSB, the stuffing data area may be positioned. In this case, the in-band A signaling in addition to the stuffing data may exist in the stuffing data area of the BB frame.

(5) Case #5 illustrates a case where a stuffing field of more than 1 byte exists in the BB frame and in-band B signaling exists.

In this case, the stuffing data and the in-band B signaling may exist in the stuffing data area of the BB frame.

The in-band B signaling may mean a different type of in-band signaling described above. In this case, because the stuffing field exists, STUFFI may have a value of 1.

The first bit of the first byte of the stuffing field header is the STUFF_ONE field and may have a value of ‘0’ because the size of the stuffing field is larger than 1 byte.

Second and third bits of the first byte of the stuffing field header may be the aforementioned STUFF_TYPE field. Since only the in-band B signaling exists in the stuffing data area of the BB frame, as described above, the STUFF_TYPE may have a value of 01. According to an exemplary embodiment, the value may also be 10.

Next, STUFF_LEN_MSB and STUFF_LEN_LSB of the stuffing field header may have length information of the stuffing field. As described above, the length of the stuffing field may be expressed by using a total of 13 bits. After the STUFF_LEN_MSB and the STUFF_LEN_LSB, the stuffing data area may be positioned. In this case, the in-band B signaling in addition to the stuffing data may exist in the stuffing data area of the BB frame.

(6) Case #6 illustrates a case where a stuffing field of more than 1 byte exists in the BB frame and in-band A and B signaling exist.

In this case, all of the stuffing data and the in-band A and B signaling may exist in the stuffing data area of the BB frame.

In this case, STUFFI may have a value of ‘1’. The first bit of the first byte of the stuffing field header is the STUFF_ONE field and may have a value of ‘0’ because the size of the stuffing field is larger than 1 byte. Second and third bits of the first byte of the stuffing field header may be the aforementioned STUFF_TYPE field. Since the in-band A and B signaling exist in the stuffing data area of the BB frame, as described above, the STUFF_TYPE may have a value of 11.

In the drawing, as another exemplary embodiment, a case where the STUFF_TYPE has a value of 11 is illustrated. That is, this case is the case where all the in-band A and B signaling exist in the stuffing data area of the BB frame, and the STUFF_TYPE field may be indicated as a value of 00.

Next, STUFF_LEN_MSB and STUFF_LEN_LSB of the stuffing field header may have length information of the stuffing field. As described above, the length of the stuffing field may be expressed by using a total of 13 bits.

After the STUFF_LEN_MSB and the STUFF_LEN_LSB, the stuffing data area may be positioned. In this case, the in-band A and B signaling in addition to the stuffing data may exist in the stuffing data area.

FIG. 43 is a diagram illustrating another example of the BB frame structure proposed in the specification.

FIG. 43A may illustrate a BB frame in the case where only the data exists without padding, that is, the stuffing data.

STUFFI of the BB frame header may have a value of 0. A payload may be positioned immediately after the BB frame header without the stuffing field. The case may correspond to Case #1 of FIG. 42.

FIG. 43B may be a case of having padding of 1 byte.

In this case, STUFFI of the BB frame header may have a value of 1. The first bit of the first byte may have a value of 1 as STUFF_ONE. This may mean that the padding is 1 byte. In FIG. 43, each bit of the padding may have a value of 11111111 (0xFF). Alternatively, according to an exemplary embodiment, each bit may have a value of 10000000. The case may correspond to Case #2 of FIG. 42.

FIG. 43C may be a case of having padding of n byte.

In this case, STUFFI of the BB frame header may have a value of 1. Further, STUFF_ONE may have a value of 0. STUFF_TYPE may indicate that only the stuffing data is used without in-band signaling.

That is, according to an exemplary embodiment, STUFF_TYPE may have a value of 00.

Next, the remaining 13 bits may indicate that the length of the stuffing field is n bytes. The 13 bits may be STUFF_LEN_MSB and STUFF_LEN_LSB. Stuffing data may be positioned after the STUFF_LEN_MSB and the STUFF_LEN_LSB. The case may correspond to a case where the stuffing field is 3 bytes or more in Case #3 of FIG. 42.

FIG. 42D may be a case of having padding of n bytes in addition to the in-band A signaling.

In this case, STUFFI of the BB frame header may have a value of 1. Further, STUFF_ONE may have a value of 0. STUFF_TYPE may indicate that the in-band A signaling is used.

That is, according to an exemplary embodiment, STUFF_TYPE may have a value of 01. The value itself of STUFF_TYPE may be changed as described above. Next, the remaining 13 bits may indicate that the length of the stuffing field is n bytes. The 13 bits may be STUFF_LEN_MSB and STUFF_LEN_LSB. The in-band A signaling may be positioned after the STUFF_LEN_MSB and the STUFF_LEN_LSB. The case may correspond to Case #4 of FIG. 42.

FIG. 42E may be a case of having padding of n bytes in addition to the in-band B signaling.

In this case, STUFFI of the BB frame header may have a value of 1. Further, STUFF_ONE may have a value of 0. STUFF_TYPE may indicate that the in-band B signaling is used.

That is, according to an exemplary embodiment, STUFF_TYPE may have a value of 10. The value itself of STUFF_TYPE may be changed as described above.

Next, the remaining 13 bits may indicate that the length of the stuffing field is n bytes.

The 13 bits may be STUFF_LEN_MSB and STUFF_LEN_LSB. The in-band B signaling may be positioned after the STUFF_LEN_MSB and the STUFF_LEN_LSB. The case may correspond to Case #5 of FIG. 42.

FIG. 42F may be a case of having padding of n bytes in addition to the in-band A and B signaling.

In this case, STUFFI of the BB frame header may have a value of 1. Further, STUFF_ONE may have a value of 0. STUFF_TYPE may indicate that the in-band A and B signalings are used.

That is, according to an exemplary embodiment, STUFF_TYPE may have a value of 11. The value itself of STUFF_TYPE may be changed as described above. Next, the remaining 13 bits may indicate that the length of the stuffing field is n bytes. The 13 bits may be STUFF_LEN_MSB and STUFF_LEN_LSB. The in-band A and B signalings may be positioned after the STUFF_LEN_MSB and the STUFF_LEN_LSB. The case may correspond to Case #6 of FIG. 42.

FIG. 44 is a diagram illustrating another example of the BB frame structure proposed in the specification.

FIG. 44 illustrates an example of a BB frame structure in the case where a stuffing field is positioned at an end of the BB frame (next to the payload).

The BB frame includes a BBF header and a BB frame payload.

The BBF header is inserted before the BB frame payload in order to represent a format of a BBF data field.

The BBF header may have a fixed length of 2 bytes.

The BBF header includes a STUFFI field corresponding to an indicator representing whether stuffing and padding exists in the BB frame. The STUFFI field may be expressed by 1 bit.

The BB frame payload may include a stuffing field and a payload.

The stuffing field is included in a case where all user packets (Ups) are not filled in the BB frame payload.

As an example, when the STUFFI field is set to ‘1’, the BB frame payload may include the stuffing field.

The payload means an area where the UP is included.

The stuffing field may be configured by a stuffing header field (alternatively, stuffing field header) and stuffing data (area).

The stuffing data area may be expressed by the stuffing data field or the stuffing data.

The stuffing data, in-band signaling information, and the like may be included in the stuffing data area.

The stuffing header field may include a STUFF_ONE field, a STUFF_TYPE field, and a STUFF_LEN field.

The STUFF_LEN field represents a length of the entire stuffing field including the stuffing header field and may include a STUFF_LEN_MSB field and a STUFF_LEN_LSB field. The STUFF_LEN field is expressed by 13 bits.

The STUFF_ONE field means a field of 1 bit representing whether the length of the stuffing field is 1 byte or not.

As an example, when the STUFF_ONE field is set to ‘1’, the length of the stuffing field is 1 byte. In this case, the STUFF_LEN_LSB field is not included in the stuffing field, that is, the STUFF_LEN field.

When the STUFF_ONE field is set to ‘0’, the length of the stuffing field is larger than 1 byte. In this case, 2 bytes of the stuffing header is used for representing the type and the length of the stuffing data.

That is, the STUFF_TYPE field represents the type of the stuffing data and may be expressed by 2 bits.

The following Table 34 illustrates an example of the STUFF_TYPE field of FIG. 44.

TABLE 34

STUFF_TYPE Stuffing Data type

00         Stuffing data only
01         IN-BAND A is used with Stuffing data
10         IN-BAND B is used with Stuffing data
11         Both IN-BAND A and IN-BAND B are used with
           stuffing data

Referring to Table 34 and FIG. 44, when the STUFF_TYPE field is set to (1) ‘00’, the stuffing data area may be used as only the stuffing data, when the STUFF_TYPE field is set to (2) ‘01’, the stuffing data area may be used as the In-Band A Signaling information and the stuffing data, when the STUFF_TYPE field is set to (3) ‘10’, the stuffing data area may be used as the In-Band B Signaling information and the stuffing data, and when the STUFF_TYPE field is set to (4) ‘11’, the stuffing data area may be used as the In-Band B Signaling information and the stuffing data.

In Table 34, In-Band A may be In-Band-ISSY, and In-Band B may be In-Band-PLS.

The STUFF_LEN_MSB field represents a most significant bit (MSB) value of the entire stuffing field length including the stuffing header field and is expressed by 5 bits.

As an example, when the STUFF_ONE field is set to ‘1’, the STUFF_LEN_MSB field may be expressed by ‘11111’. Alternatively, the STUFF_LEN_MSB field may be expressed by ‘00000’.

The STUFF_LEN_LSB field represents a least significant bit (LSB) value of the entire stuffing field length and is expressed by 8 bits.

The stuffing data field may include stuffing and/or in-band signaling field(s).

Here, the ‘stuffing and/or in-band signaling’ means stuffing, in-band signaling or stuffing, and in-band signaling.

That is, the expression of ‘A and/or B’ may be the same as the meaning of at least one of A or B.

Referring to FIG. 44, the eighth bit of the Nth byte of the stuffing field represents the STUFF_ONE field, sixth and seventh bits of the Nth byte represent the STUFF_TYPE field, first to fifth bits of the Nth byte of the stuffing field represent the STUFF_LEN_LSB field, and the N−1-th byte of the stuffing field represents the STUFF_LEN_MSB field.

Further, the data UP, the stuffing data, the in-band A data, the in-band B data, or the in-band A data and B data from the (N−2)th byte of the stuffing field may be represented.

A more detailed description for Case #1 to Case #6 of FIG. 44 will refer to the description of Case #1 to Case #6 of FIG. 42 which corresponds to each case of FIG. 44.

The frame structure of FIG. 44 may perform the same function as the frame structure of FIG. 42.

Like the BB frame structure illustrated in FIG. 44, when the stuffing field is positioned at the end of the BB frame, the receiving apparatus may directly receive the user packet (UP) without checking the stuffing, and as a result, the access time to the UP is shorter than that in the BB frame structure illustrated in FIG. 42.

FIG. 45 is a diagram illustrating still another example of the BB frame structure proposed in the specification.

FIG. 45 illustrates various BB frame structures in the case where the stuffing field is positioned at the last of the BB frame (alternatively, positioned next to the payload and the FEC frame).

Since the frame structure of FIG. 45 is different from the frame structure of FIG. 43 in only the position of the stuffing field but the same as the frame structure of FIG. 43 in all other parts, the detailed description of FIG. 41 refers to FIG. 43.

FIG. 46 is a diagram illustrating comparison of a result of calculating overhead for transmission of a BB frame in various BB frame structures.

A graph represented by DVB-T2 may be an overhead graph in the related art described above. The DVB-T2 may mean a terrestrial television broadcasting system-related standard of digital video broadcasting (DVB). The DVB-T2 may mean a next-generation terrestrial broadcasting-related standard in Europe. The graph represented by the DVB-T2 may be a graph obtained by calculating the overhead in the BB frame according to this standard technique.

A graph represented by MH may be another overhead graph in the related art described above. The MH may mean a mobile/handheld DTV system-related standard of consumer electronics association (CEA). The MH may mean a mobile handheld-related standard in North America. The graph represented by the MH may be a graph obtained by calculating the overhead in the BB frame according to this standard technique.

A graph represented by SS&SN may be yet another overhead graph in the related art described above. The SS&SN may mean one of the related art. The graph obtained by calculating the overhead when the BB frame and the BB frame header are configured by the method proposed in the related art is illustrated as the graph represented by the SS&SN.

The following Table 35 is a table illustrating a result of calculating the overhead upon the transmission of each BB frame.

TABLE 35
	FEC
	64k	16k
	CR
	5/6	4/5	3/4	2/3	3/5	1/2	5/6	4/5	3/4	2/3	3/5	1/2
	Kbch
	53840	51648	48408	43040	38688	32208	13152	12600	11880	10800	9720	7200
VB-T2	0.0297	0.0310	0.0331	0.0372	0.0414	0.0497	0.1217	0.1270	0.1347	0.1481	0.1646	0.2222
H	0.0019	0.0019	0.0021	0.0023	0.0026	0.0031	0.0076	0.0079	0.0084	0.0093	0.0103	0.0139
S&SN	0.0037	0.0039	0.0041	0.0046	0.0052	0.0062	0.0152	0.0159	0.0168	0.0185	0.0206	0.0278
G	0.0019	0.0019	0.0021	0.0023	0.0026	0.0031	0.0076	0.0079	0.0084	0.0093	0.0103	0.0139

The overhead may mean an overhead of a field representing a length of the data field.

In the related art, since a field of 2 bytes is used for each BB frame, the overhead may be a maximum of 0.22%.

In another related art, since only the field of bit is used, the overhead may be just a maximum of 0.0139%. The overhead may be the lowest.

In yet another related art, a field of 2 bits may be used. In this case, the overhead may be two times larger than that of another related art.

A graph represented by LG may be an overhead graph according to the present invention. In the present invention, only the field of 1 bit may be used for signaling of the stuffing field. Accordingly, the overhead may be a minimum. Further, there is an advantage in that a residual field of 2 bits is additionally prepared to be used to indicate a type of the in-band signaling and the like. The present invention may support a structure which is usable as other uses, such as representing a configuration of the BB frame, by using the residual field.

FIG. 47 illustrates one example of a BB frame structure in the related art.

As illustrated in FIG. 47, the BB frame includes a header, an optional header, and payload data.

The header includes a packet start pointer mode indicator (PSPMI) field, a padding indicator (PADI) field, and a packet start pointer low significant bits (PKTSPTR_LSB) field.

The PSPMI field means a flag field having a size of 1 bit representing whether a packet start pointer (PKTSPTR) field is a short mode or a long mode.

The PKTSPTR field may be the same concept as a SYNCD field.

That is, the PSPMI field means a flag representing whether the length of the PKTSPTR field is small or large.

The PKTSPTR_LSB field represents 5 LSB bits of the PKTSPTR field of 13 bits.

The Optional Header may include a packet start pointer most significant bits (PKTSPTR_MSB) field and a padding field.

The PKTSPTR_MSB field represents 8 MSB bits of the PKTSPTR field of 13 bits.

Further, the padding field may include a padding data length (PADL) field and a PADDING_DATA field.

The PADL field represents a length of the padding data field and has a size of 15 bits.

The PADDING_DATA field has a variable length and represents padding information.

As illustrated in FIG. 47, the BB frame structure calculates the length of the data field in the receiving device by transmitting the length of the PADDING_DATA field without using information (for example, DFL) representing the length the data field, in order to express the length of the (payload) data field of a maximum of 13 bytes.

Here, the length of the padding field corresponds to the payload data size of the BB frame—the length of the data field.

When the padding field does not exist in the BB frame, the data field length (DFL) is calculated by using the BB frame size.

When the padding field exists in the BB frame, the PADI of 2 bits is included in the BB frame header to indicate the padding length.

More efficiently, in order to transmit the baseband frame (BBF) to the FEC block, that is, in order to reduce the overhead for the transmission of the BB frame header, the PKTSPRT field is divided into PKTSPTR_LSB and PKTSPTR_MSB to operate.

That is, the PKTSPTR field can support up to the size of 2 bytes, but when the length of the PKTSPTR field is small (≤31 byte), only the PKTSPTR_LSB may be used, and as a result, the transmission size of the PKTSPTR field may be shortened to 1 byte.

However, since the length of the PKTSPTR_LSB is small as 5 bits, only when the size of the PKTSPTR field is 31 byte or less, there is a disadvantage in that the BBF header of 1 byte can be configured.

As described in FIG. 39, the existing BB frame is used by allocating the DFL to each BB frame header in order to indicate the length of the data field of the BB frame to the receiving device (alternatively, receiving terminal, and as a result, the overhead when transmitting the BB frame to the FEC block largely occurs.

Accordingly, a new BB frame structure for enhancing transmission efficiency of the BB frame header and adding a new function of an error check will be described in detail.

That is, this specification provides a method of entirely reducing a size of the BB frame header by controlling the size of the SYNCD field included in the BB frame header, a method of performing an error check by using a residual 1 bit in the BB frame header, and the like.

Hereinafter, the methods and the BB frame structure proposed in this specification operate in a BB frame header insertion block of the transmitting device and a BB frame deader parser block in the receiving device.

FIG. 48 is a diagram illustrating an example of the BB frame structure proposed in the specification.

An input stream of FIG. 48A forms a BB frame structure of FIG. 48B through a mode adaptation module of an input formatting module.

As illustrated in FIG. 48, the input stream including a plurality of packets is sliced or mapped to the payload through the mode adaptation module, and a header including information on the payload is added before the payload.

The payload may be expressed by a BB frame data field.

The header may include at least one of an OPTIONI field, a STUFFI field, a SYNCD_LSB field, a SYNCD_MSB field, a Checksum field, and a Stuffing field.

As described above, the Stuffing field may include a Stuffing Header field and a Stuffing Byte field.

The Stuffing Byte field may be expressed by the stuffing data field or the stuffing data area.

The BB frame header including the OPTIONI field, the STUFFI field, and the SYNCD_LSB field may be defined, and the Option Header including the SYNCD_MSB field and the Checksum field may be defined.

FIG. 48 illustrates that the BB frame header and the Option header are defined.

Further, the stuffing field may be included in the header or may not be included in the header.

When the stuffing field is not included in the header, a BB frame payload may be configured together with the payload.

The stuffing field may be positioned before the payload (FIG. 48) or after the payload.

The SYNCD field may represent a distance from a start of the data field to a start of the first transmitted UP starting in the data field.

Here, the SYNCD field may be divided into a SYNCD_LSB field and a SYNCD_MSB field and has a size of 13 bits.

The SYNCD_LSB field has a size of 6 bits as a value representing the LSB of the SYNCD and may express the SYNCD of a maximum of 63 bytes.

As illustrated in FIG. 48, when the header is divided in to the BB frame header and the Option Header, the SYNCD_LSB field may be included in the BB frame header.

Further, the SYNCD_MSB field has a size of 7 bits as a value representing the MSB of the SYNCD.

As illustrated in FIG. 48, when the header is divided in to the BB frame header and the Option Header, the SYNCD_MSB field may be included in the Option header.

The usage of the SYNCD_MSB field is determined by the OPTIONI field.

The OPTIONI field represents whether a position of a packet which newly starts among the packets transmitted through the payload is expressed by SYNCD_LSB of 6 bits.

As an example, when the OPTIONI field is set to ‘0’, the OPTIONI field represents that a position of a packet which newly starts among the packets transmitted through the payload may be expressed by SYNCD_LSB of 6 bits.

When the OPTIONI field is set to ‘1’, the OPTIONI field represents that a position of a packet which newly starts among the packets transmitted through the payload may not be expressed by SYNCD_LSB of 6 bits.

Accordingly, when the OPTIONI field is set to ‘1’, the OPTIONI field needs to represent a position of a packet which newly starts in the payload by using the SYNCD_LSB field of 6 bits of the SYNCD_MSB field of 7 bits.

Here, when the SYNCD_MSB field is included in the Option header, the Option Header is include din the BB frame.

The STUFFI field has a size of 1 bit and means an indicator representing whether the stuffing field (alternatively, stuffing byte) or the in-band signaling field exists in the BB frame.

The Check-sum field may be used for an error check of the BB frame header or the OPTIONI field, with the size of 1 bit.

The Check-sum field may be included in the Option Header when the header is divided into the BB frame header and the Option Header.

As described above, the Stuffing field includes a STUFFING Header and a STUFFING Byte.

The SYNCD_LSB field of FIG. 48 and the PKTSPTR_LSB field of FIG. 47 may be used as the same meaning.

Here, the size of the SYNCD_LSB field of FIG. 48 proposed in this specification is increased to 6 bits by 1 bit, while the size of the PKTSPTR_LSB field is 5 bits.

That is, the length of the SYNCD which may be expressed by the SYNCD_LSB field of 6 bits becomes about two times to 63 (26-1) bytes, while the length of the PKTSPTR which may be expressed by the PKTSPTR_LSB field of 5 bits is a maximum of 31 (25-1) bytes.

That is, the case where the SYNCD_MSB field is added to the header or the BB frame header or the Option header by controlling the size of the SYNCD_LSB field proposed in this specification is reduced, and as a result, the overhead for the transmission of the BB frame may be reduced.

For example, it is assumed that a MPEG2-TS stream of 188 bytes is transmitted.

(1) In the case of the BB frame structure of FIG. 43, a case where only the PKTSPTR_LSB field is included in the BB frame header in order to transmit a TS packet of 188 bytes is included (that is, a case where the PKTSPTR length has a value of 31 bytes or less) corresponds to about 16.49% (31 bytes/188 bytes).

That is, the BB frame corresponding to 16.49% includes a header having a size of 1 byte, and the BB frame corresponding to remaining 83.51% includes a header having a size of 2 bytes.

Here, the header represents a format related with the payload, and may mean the BB frame header or mean including the BB frame header and the Option header.

Accordingly, the BB frame averagely includes a header having a size of 1.83 bytes.

(2) On the other hand, in the case of the BB frame structure of FIG. 48, a case where only the SYNCD_LSB field is included in the BB frame header in order to transmit a TS packet of 188 bytes is included (that is, a case where the SYNCD length has a value of 63 bytes or less) corresponds to about 33.51% (63 bytes/188 bytes).

That is, the BB frame corresponding to 33.51% includes a header having a size of 1 byte, and the BB frame corresponding to remaining 66.49% includes a header having a size of 2 bytes.

Accordingly, the BB frame averagely includes the BB frame header having a size of 1.66 bytes, and as a result, it can be seen that the overhead for the transmission of the BB frame may be largely reduced as compared with the case of having the BB frame structure of FIG. 47.

Further, the BB frame structure of FIG. 48 may perform an additional function which may detect an error for the header, by using 1 bit included in the Optional Header as the checksum 1 bit of the header or the check-sum 1 bit of the OPTIONI field included in the header.

FIG. 49 is a diagram illustrating another example of the BB frame structure proposed in the specification.

The output processor of FIG. 49 implements functions, processes, and/or methods proposed in FIGS. 50, 51, and 53 to be described below.

The BB frame structure of FIG. 49 is different from the BB frame structure of FIG. 48 in the sizes of the SYNCD_LSB field/SYNCD_MSB field and the position of the STUFFI field, but other parts thereof are the same.

Hereinafter, the description for the same parts as the BB frame structure of FIG. 48 is omitted, and the different parts will be mainly described.

The OPTIONI field and the SYNCD_LSB field are combined to be defined as the BB frame header, and the SYNCD_MSB field, the STUFFI field, and the Checksum field are combined to be defined as the Option Header.

Further, the OPTIONI field, the SYNCD_LSB field, the SYNCD_MSB field, the STUFFI field, and the Checksum field are combined to be defined as one header.

In this case, the header may also be expressed by the BB frame header.

As yet another example, the STUFFI field and the checksum field may be combined into one specific field. This will be described in detail in FIGS. 50 and 51 to be described below. As illustrated in FIG. 49, the size of the SYNCD_LSB field is 7 bits, and the size of the SYNCD_MSB field is 6 bits.

Like FIG. 49, when the size of the SYNCD_LSB field is 7 bits, a length of the larger number of SYNCDs may be expressed.

That is, when the size of the SYNCD_LSB field is 7 bits, an expressible length of the SYCND is 127 (27-1) bytes and becomes about four times larger than the case (31 bytes) of FIG. 48.

Similarly, it is assumed that a MPEG2-TS stream of 188 bytes is transmitted. As illustrated in FIG. 50, the size of the SYNCD_LSB field is 7 bits, and the size of the SYNCD_MSB field is 6 bits.

In the case of the BB frame structure of FIG. 49, a case where only the SYNCD_LSB field is included in the BB frame header in order to transmit a TS packet of 188 bytes is included (that is, a case where the SYNCD length has a value of 127 bytes or less) corresponds to about 67.55% (127 bytes/188 bytes).

That is, the BB frame corresponding to 67.55% includes a header having a size of 1 byte, and the BB frame corresponding to remaining 32.45% includes a header having a size of 2 bytes.

Accordingly, the BB frame averagely includes a header having a size of 1.32 bytes, and as a result, the overhead for the transmission of the BB frame may be largely reduced as compared with the case of having the BB frame structures of FIGS. 47 and 48.

Similarly, even in the BB frame structure of FIG. 49, the error check for the header may be additionally performed by using residual 1 bit existing in the header as the Checksum (as the check-sum 1 bit of the header or as the check-sum of the OPTIONI field.

FIG. 50 is a diagram illustrating still another example of the BB frame structure proposed in the specification.

As illustrated in FIG. 50, the aforementioned STUFFI field and checksum field may be combined into one specific field 5010.

The specific field 5010 may be used as a value indicating whether the stuffing field is present in the BB frame.

The specific field 5010 may be expressed as an extension indicator (EXT_I) field and may have a size of 2 bits.

Further, the specific field 5010 may be expressed as an optional header indicator (OPTI) field.

The OPTI field may mean a field indicating whether a header including the Stuffing is present.

The BB fame may be constituted by a header and a payload and the heard may be constituted by one or more sub-headers.

That is, one or more sub-headers may be expressed as a first header, a second header, a third header, and the like.

As one example, the first header may be expressed as a BBF header, a base header, or the like and the second header may be expressed as an option header, an optional header, or the like.

The specific field 5010 may be included in the option(al) header of the BB frame.

Table 36 given below illustrates one example of a specific field (EXT_I field) format.

TABLE 36

EXT_I Note

00    No stuffing
01    1 byte stuffing
10    2 byte stuffing
11    3~byte stuffing

In Table 36, the specific field value of (1) ‘00’ indicates the case where no stuffing is present in the BB frame, (2) ‘01’ indicates the case where the stuffing of 1 byte is present in the BB frame, (3) ‘10’ indicates the case where the stuffing of 1 bytes is present in the BB frame, and (4) ‘11’ indicates the case where the stuffing of 3 bytes or more is present in the BB frame.

As described above, the Stuffing field may include a Stuffing Header field and a Stuffing Byte field.

Further, the stuffing header field may include a STUFF_TYPE field, a STUFF_LEN_LSB field, and a STUFF_LEN_MSB field.

The STUFF_TYPE field may be expressed an extension type (EXT_TYPE) field. In this case, the EXT_TYPE field may indicate a type of the stuffing field.

Further, the stuffing field may be expressed an extension field.

The STUFF_TYPE field may be included in the BB frame or the BB frame header when the EXT_I field has ‘01’, ‘10’, or ‘11’. Detailed contents thereof will be described with reference to Table 37 given below.

The STUFF_TYPE field may be 3 bits, the STUFF_LEN_LSB field may be 5 bits, and the STUFF_LEN_MSB field may be 8 bits.

The STUFF_LEN_LSB field may be expressed as an EXT_LEN LSB field and the STUFF_LEN_MSB field may be expressed as an EXT_LEN_MSB field.

Hereinafter, the STUFF_TYPE field and the STUFF_LEN field which may be defined according to the specific field value, and meanings thereof will be described with Table 37 as one example.

TABLE 37
EXT_I	STUFF_TYPE	STUFF_LEN	description
00	Not exist	Not exist	No stuffing
01	000	00000	1 byte stuffing
10	000	00000	2 byte stuffing
11	000	stuff_len	3~byte stuffing
11	001	stuff_len	Stuffing + mode1(ISSY)
11	010	stuff_len	Stuffing + mode2
			(INBAND_SIG)
. . .	. . .	. . .	. . .
11	111	stuff_len	Stuffing + mode7(reserved)

In Table 37, when the specific field (e.g., EXT_I field) value is ‘00’, since no stuffing is present, the STUFF_TYPE field and the STUFF_LEN field are not present in the stuffing field.

When the specific field value ‘01’, the STUFF_TYPE field value is ‘000’, and the STUFF_LEN field value is ‘00000’, the stuffing of 1 byte is included in the BB frame (alternatively, the stuffing field).

When the specific field value ‘10’, the STUFF_TYPE field value is ‘000’, and the STUFF_LEN field value is ‘00000’, the stuffing of 2 bytes is included in the BB frame (alternatively, the stuffing field). When the specific field value ‘110’, the STUFF_TYPE field value is ‘000’, and the STUFF_LEN field value is ‘stuff_len’, the stuffing of 3 bytes or more is included in the BB frame (alternatively, the stuffing field).

When the specific field value ‘11’, the STUFF_TYPE field value is ‘001’, and the STUFF_LEN field value is ‘stuff_len’, the stuffing and in-band A signaling are included in the BB frame (alternatively, the stuffing field).

The in-band A may be the INBAND_ISSY.

When the specific field value ‘11’, the STUFF_TYPE field value is ‘010’, and the STUFF_LEN field value is ‘stuff_len’, the stuffing and in-band B signaling are included in the BB frame (alternatively, the stuffing field).

The in-band B may be INBAND_SIG.

When the specific field value ‘11’, the STUFF_TYPE field value is ‘111’, and the STUFF_LEN field value is ‘stuff_len’, the stuffing and other information are included in the BB frame (alternatively, the stuffing field).

Further, the STUFF_LEN field value may be divided into a STUFF_LEN_LSB field (5 bits) value and a STUFF_LEN_MSB field (8 bits) value.

This will be described with reference to Table 38.

TABLE 38
EXT_I	STUFF_TYPE	STUFF_LEN_LSB	STUFF_LEN_MSB	description
00	Not exist	Not exist	Not exist	No stuffing
01	000	00000	Not exist	1 byte stuffing
10	000	00000	00000000	2 byte stuffing
11	000	stuff_len_lsb	stuff_len_msb	3~byte stuffing
11	001	stuff_len_lsb	Not exist	mode1(ISSY) only
11	010	stuff_len_lsb	stuff_len_msb	Stuffing + mode1(ISSY)
. . .	. . .	. . .	. . .	. . .
11	111	stuff_len_lsb	stuff_len_msb	Stuffing + mode8(reserved)

In Table 38, when the specific field value ‘01’, the STUFF_TYPE field value is ‘000’, the STUFF_LEN_LSB field value is ‘00000’, and the STUFF_LEN_MSB field value is ‘Not exist’, the stuffing of 1 byte is included in the BB frame (alternatively, the stuffing field).

When the specific field value ‘10’, the STUFF_TYPE field value is ‘000’, the STUFF_LEN_LSB field value is ‘00000’, and the STUFF_LEN_MSB field value is ‘00000000’, the stuffing of 2 bytes is included in the BB frame (alternatively, the stuffing field).

When the specific field value ‘11’, the STUFF_TYPE field value is ‘000’, the STUFF_LEN_LSB field value is ‘stuff_len_lsb’, and the STUFF_LEN_MSB field value is ‘stuff_len_msb’, the stuffing of 3 bytes or more is included in the BB frame (alternatively, the stuffing field).

When the specific field value ‘11’, the STUFF_TYPE field value is ‘001’, the STUFF_LEN_LSB field value is ‘stuff_len_lsb’, and the STUFF_LEN_MSB field value is ‘Not exist’, only the in-band A signaling is included in the BB frame (alternatively, the stuffing field). Preferably, only the in-band A signaling is included in the stuffing field only when the in-band A signaling may be expressed by 32 bytes. The in-band A may be the INBAND_ISSY.

When the specific field value ‘11’, the STUFF_TYPE field value is ‘010’, the STUFF_LEN_LSB field value is ‘stuff_len_lsb’, and the STUFF_LEN_MSB field value is ‘stuff_len_msb’, the stuffing and the in-band A signaling are included in the BB frame (alternatively, the stuffing field).

When the specific field value ‘11’, the STUFF_TYPE field value is ‘111’, the STUFF_LEN_LSB field value is ‘stuff_len_lsb’, and the STUFF_LEN_MSB field value is ‘stuff_len_msb’, the stuffing and other information are included in the BB frame (alternatively, the stuffing field).

FIG. 51 is a diagram illustrating still another example of the BB frame structure proposed in the specification.

In FIG. 51, as a method associated with a use method of the STUFF_TYPE field, a method is provided, which divides and uses the 3-bit STUFF_TYPE field into a 1-bit MSB indicator (MSB_I) field 5111 and a 2-bit STUFF_TYPE field 5112 for efficient use.

The MSB_I field 5111 represents an indicator that indicates whether STUFF_LEN_MSB field is present.

As one example, when the MSB_I field value is ‘0’, this value may indicate that only SUTFF_LEN_LSB (5 bits) is used in the stuffing header and when the MSB_I field value is ‘1’, the value may indicate that the STUFF_LEN_LSB (5 bits) field and the STUFF_LEN_MSB (8 bits) are used in the stuffing header 5110.

As one example, when the MSB_I field value is ‘0’, only the STUFF_LEN_LSB (5 bits) field is used (alternatively, included) in the STUFFING header and the size of the stuffing field which may be expressed is 32 bytes.

When the MSB_I field value is ‘1’, the STUFF_LEN_LSB (5 bits) field and the STUFF_LEN_MSB (8 bits) field are used (alternatively, included) in the STUFFING header and the size of STUFF_LEN which may be expressed is 13 bits.

Next, the STUFF_TYPE field (2 bits, 4712) indicates a use type of the stuffing field.

On example of the STUFF_TYPE field may include ISSY, in-band signaling, and the like.

The STUFF_TYPE field indicates a stuff type designated so that the stuffing field interval is used for other purposes (e.g., in-band signaling and in-band ISSY).

Meanings of the MSB_I field and the STUFF_TYPE field newly defined with a size of 2 bits will be described in more detail with reference to Table 39 given below.

TABLE 39
EXT_I	MSB_I	STUFF_TYPE	STUFF_LEN_LSB	STUFF_LEN_MSB	description
11	0	00	stuff_len_lsb	Not exist	reserved
11	1	00	stuff_len_lsb	stuff_len_msb	3~byte
					stuffing(stuff_len)
11	0	01	stuff_len_lsb	Not exist	In-band ISSY table +
					stuffing(size ≤32 Bytes)
11	1	01	stuff_len_lsb	stuff_len_msb	In-band ISSY table +
					stuffing(size >32 Bytes)
11	0	10	stuff_len_lsb	Not exist	In-band PLS table +
					stuffing(size ≤32 Bytes)
11	1	10	stuff_len_lsb	stuff_len_msb	In-band PLS table +
					stuffing(size >32 Bytes)
11	0	11	stuff_len_lsb	Not exist	Reserved mode +
					stuffing(size ≤32 Bytes)
11	1	11	stuff_len_lsb	stuff_len_msb	Reserved mode +
					stuffing(size >32 Bytes)

In Table 39, when the STUFF_TYPE field value is ‘00’, the value indicates a case in which the stuffing field is constituted by only stuffing bytes and when the STUFF_TYPE field value is 01, 10, and 11, the values express respective modes used for different purposes in the stuffing field.

As illustrated in FIG. 51 and Table 39, in the case where both the MSB_I field and the STUFF_TYPE field are used in the stuffing header, when the size of the sum of ISSY and stuffing in the stuffing field is 32 bytes or less, since the stuffing header does not include the STUFF_LEN_MSB field, 1-byte overhead may be reduced.

When the size of the sum of ISSY and stuffing in the stuffing field is larger than 32 bytes, the MSI_I field may be set to (alternatively, marked with) ‘1’ and the STUFF_LEN_MSB field may be used in the stuffing header.

FIG. 52 is a flowchart illustrating one example of a method for transmitting a broadcast signal proposed in the specification.

Referring to FIG. 52, the broadcast signal transmitting apparatus proposed in the specification processes input streams through an input formatting module (S5210). That is, the broadcast signal transmitting apparatus formats the input streams with multiple data pipes (DPs) in the in put formatting module.

In detail, the broadcast signal transmitting apparatus allocates data packets to a payload of the baseband frame (BBF) and adds a header indicating a format for the payload of the baseband frame, for the input formatting in S5210.

The data pipes (DPs) can be represented to data transmission channels.

The header may include the EXT_I field and the stuffing field as illustrated in FIGS. 50 and 51.

The EXT_I field means a field indicating whether the stuffing field is present in the BB frame and may have a size of 2 bits.

The stuffing field includes the stuffing header and the stuffing header includes the MSB_I field and the STUFF_TYPE field.

The MSB_I field represents an indicator that indicates whether the STUFF_LEN_MSB field is present and may have a size of 1 bit.

Further, the STUFF_TYPE field means a field that indicates the use type of the stuffing field and may have the size of 2 bits.

The EXT_I field, the MSB_I field, and the STUFF_TYPE field may be used as an expression of control information so as to be applied to other exemplary embodiments.

Thereafter, the broadcast signal transmitting apparatus encodes data of multiple (formatted) DPs for each DP through a bit interleaved coding and modulation (BICM) module (S5220).

The bit interleaved coding and modulation (BICM) module can be represented to a encoder.

Thereafter, the broadcast signal transmitting apparatus maps the encoded DP data through a frame building module to generate at least one signal frame (S5230).

The frame building module can be represented to a frame builder.

Thereafter, the broadcast signal transmitting apparatus modulates data of the generated signal frame an orthogonal frequency division multiplexing (OFDM) generation module by an orthogonal frequency division multiplexing (OFDM) scheme and transmits a broadcast signal including the modulated data of the signal frame (S5240).

FIG. 53 is a flowchart illustrating one example of a broadcast signal receiving method proposed in the specification.

Referring to FIG. 53, a broadcast signal receiving apparatus receives a broadcast signal from the outside through a synchronization and demodulation module and demodulates data by an OFDM scheme with respect to the received broadcast signal (S5310).

The synchronization and demodulation module can be represented to a receiver and a demodulator.

Thereafter, the broadcast signal receiving apparatus parses the demodulated data to at least one signal frame through a parsing module (S5320).

The parsing module can be represented to a frame parser.

Then, the broadcast signal receiving apparatus decodes at least one parsed signal frame into multiple DPs through a demapping a decoding module (S5330).

The demapping and decoding module can be represented to a converter and decoder.

Thereafter, the broadcast signal receiving apparatus restores the multiple data pipes output from the demapping and decoding module to input streams through an output processor module.

The broadcast signal receiving apparatus decodes information transmitted to a header of the baseband frame through a baseband frame processor block and restores the input streams by using the decoded information, for the output processing in S5340.

The header may include the EXT_I field and the stuffing field as illustrated in FIGS. 50 to 52.

The EXT_I field means a field indicating whether a stuffing field is present in a BB frame and may have a size of 2 bits.

The stuffing field includes a stuffing header and the stuffing header includes an MSB_I field and a STUFF_TYPE field.

The MSB_I field represents an indicator that indicates whether a STUFF_LEN_MSB field is present and may have a size of 1 bit.

Further, the STUFF_TYPE field means a field that indicates a use type of the stuffing field and may have a size of 2 bits.

The EXT_I field, the MSB_I field, and the STUFF_TYPE field may be used as an expression of control information so as to be applied to other exemplary embodiments.

It will be appreciated by those skilled in the art that various changes and modifications of the present invention can be made without departing from the spirit or scope of the present invention. Accordingly, it is intended that the present invention includes the change and modification of the present invention provided in the appended claims and a range equivalent thereto.

In the specification, both the inventions of the apparatus and the method are mentioned and descriptions of the apparatus and method inventions may be applied to be complementary with each other.

In the specification, methods and apparatuses for receiving and transmitting a broadcast signal are used.

Claims

1. A method for transmitting a broadcast signal, the method comprising:

formatting input stream into at least one physical layer pipe (PLP);

encoding data of the at least one PLP;

generating at least one signal frame by mapping the encoded data;

modulating the at least one signal frame using an orthogonal frequency division multiplexing (OFDM) scheme; and

transmitting the broadcast signal comprising the at least one modulated signal frame,

wherein the formatting comprises

mapping data packets to a payload of a baseband frame (BBF), and

adding a header ahead of the payload,

wherein the header comprises first control indication information for indicating whether a specific first part is present in the header,

wherein the specific part comprises at least one of a second part or a third part, and

wherein the second part consists of a type field indicating a type of the third part and a length field indicating a length of the third part, wherein when the specific part is present in the header, the first control information is used to further indicate length of the second part comprised in the specific part, the length of the second part being either 1 byte or 2 bytes,

the first part includes a type field indicating a type of a second part and a length field indicating a length of the second part in response to the indication information indicating that the first part is present in the header,

a length of the first part being either 1 byte or 2 bytes,

wherein when the second part has length of 2 bytes, the a first byte of the second first part consists of the type field and a LSB (least significant bit) part of the length field and the a second byte of the second first part consists of a msb (most significant bit) part of the length field in response to the first part having the length of 2 bytes, and

wherein a length of the type field is 3 bits, a length of the LSB part of the length field is 5 bits, and a length of the msb part of the length field is 8 bits.

2. The method of claim 1, wherein if a value of the first control indication information is ‘01’, the first control indication information indicates that the a specific part is present in the header and comprises the second first part having a length of 1 byte.

3. The method of claim 1, wherein if a value of the first control indication information is ‘10’, the first control indication information indicates that the a specific part is present in the header and comprises the second first part having a length of 2 bytes.

4. The method of claim 1, wherein if a value of the first control indication information is ‘00’, the first control indication information indicates that the a specific part is not present in the header.

5. The method of claim 1, wherein the header comprises at least one of second control information or third control information,

wherein the third control information comprises at least one of a third control information LSB (least significant bit) field or a third control information msb(most significant bit) field,

wherein the second control information indicates whether the third control information msb (most significant bit) field is included or not, and

wherein the third control information is information related to the start position of a first data packet in the BBF.

6. The method of claim 5, wherein the value of the third control information is offset from the start of the payload to the start of the first data packet in the BBF.

7. The method of claim 1, wherein the first control indication information is an Extension Indicator (EXT_I) field, and the a specific part is a stuffing field.

8. The method of claim 1, wherein the second first part is a stuffing header, and the third second part is a stuffing byte.

9. The method of claim 1, wherein the third second part includes at least one of padding data or data indicating additional signaling information.

10. A transmission apparatus for transmitting a broadcast signal, the transmission apparatus comprising:

an input formatter for formatting input stream into at least one physical layer pipe (PLP);

an encoder for encoding data of the at least one PLP;

a frame builder for generating at least one signal frame by mapping the encoded data;

a modulator for modulating the at least one signal frame by an orthogonal frequency division multiplexing (OFDM) scheme; and

transmitter for transmitting the broadcast signal comprising the at least one modulated signal frame,

wherein the input formatter comprises

a baseband frame slicer for mapping data packets to a payload of a baseband frame (BBF), and

a baseband frame header inserter for adding a header ahead of the payload,

wherein the header comprises first control indication information for indicating whether a specific part is present in the header,

wherein the specific part comprises at least one of a second part or a third part, and

wherein the second part consists of a type field indicating a type of the third part and a length field indicating a length of the third part, wherein when the specific part is present in the header, the first control information is used to further indicate length of the second part comprised in the specific part, the length of the second part being either 1 byte or 2 bytes,

when the specific part is present in the header, the specific part comprises a first part having a length,

the length of the first part being either 1 byte or 2 bytes,

the first part includes a type field indicating a type of a second part and a length field indicating a length of the second part,

wherein when the second first part has a length of 2 bytes, the first byte of the second first part consists of the type field and a LSB (least significant bit) part of the length field and the second byte of the second first part consists of a msb (most significant bit) part of the length field, and

wherein a length of the type field is 3 bits, a length of the LSB part of the length field is 5 bits, and a length of the msb part of the length field is 8 bits.

11. The method of claim 9, wherein:

when the type field has a first value, the first value of the type field indicates that the third second part includes the padding data, or

when the type field has a second value, the second value of the type field indicates that the third second part includes the data indicating the additional signaling information.

12. A method for receiving a broadcast signal, the method comprising:

receiving the broadcast signal;

performing orthogonal frequency division multiplexing (OFDM) demodulation on the broadcast signal;

output-processing one or more baseband frame of the demodulated broadcast signal to output a data stream,

the baseband frame including a header and a payload,

wherein the header comprises indication information for indicating whether a first part is present in the header,

the first part includes a type field indicating a type of a second part and a length field indicating a length of the second part in response to the indication information indicating that the first part is present in the header,

a length of the first part being either 1 byte or 2 bytes,

a first byte of the first part consists of the type field and a LSB (least significant bit) part of the length field and a second byte of the first part consists of a msb (most significant bit) part of the length field in response to the first part having the length of 2 bytes, and

a length of the type field is 3 bits, a length of the LSB part of the length field is 5 bits, and a length of the msb part of the length field is 8 bits.

13. A device, comprising:

a tuner configured to receive a broadcast signal;

a demodulator configured to demodulate the broadcast signal by an orthogonal frequency division multiplexing (OFDM) scheme; and

an output processor configured to output process one or more baseband frame of the demodulated broadcast signal to output data stream,

the baseband frame including a header and a payload,

wherein the header comprises indication information for indicating whether a first part is present in the header,

the first part includes a type field indicating a type of a second part and a length field indicating a length of the second part in response to the indication information indicating that the first part is present in the header,

a length of the first part being either 1 byte or 2 bytes,

a first byte of the first part consists of the type field and a LSB (least significant bit) part of the length field and a second byte of the first part consists of a msb (most significant bit) part of the length field in response to the first part having the length of 2 bytes, and

a length of the type field is 3 bits, a length of the LSB part of the length field is 5 bits, and a length of the msb part of the length field is 8 bits.

14. A device, comprising:

a tuner configured to receive a broadcast signal;

a demodulator configured to demodulate the broadcast signal by an orthogonal frequency division multiplexing (OFDM) scheme;

one or more processor; and

one or more memories configured to store one or more programs, wherein the one or more programs are configured to be executed by the one or more processors, the one or more programs including instructions for:

processing one or more baseband frame of the demodulated broadcast signal to output data stream,

the baseband frame including a header and a payload,

wherein the header comprises indication information for indicating whether a first part is present in the header,

the first part includes a type field indicating a type of a second part and a length field indicating a length of the second part in response to the indication information indicating that the first part is present in the header,

a length of the first part being either 1 byte or 2 bytes,

a first byte of the first part consists of the type field and a LSB (least significant bit) part of the length field and a second byte of the first part consists of a msb (most significant bit) part of the length field in response to the first part having the length of 2 bytes, and

a length of the type field is 3 bits, a length of the LSB part of the length field is 5 bits, and a length of the msb part of the length field is 8 bits.

15. The method of claim 1, wherein

the length field of the first part is 5 bits and the length of the second part is less than or equal to 31 bytes, the second part is preceded by the first part in response to the first part having a length of 1 byte,

the length field of the first part represents end of the baseband frame in response to the first part having a length of 2 bytes.

16. The device of claim 10, wherein

the length field of the first part is 5 bits and the length of the second part is less than or equal to 31 bytes, the second part is preceded by the first part in response to the first part having a length of 1 byte,

the length field of the first part represents end of the baseband frame in response to the first part having a length of 2 bytes.

17. The method of claim 12, wherein

the length field of the first part is 5 bits and the length of the second part is less than or equal to 31 bytes, the second part is preceded by the first part in response to the first part having a length of 1 byte,

the length field of the first part represents end of the baseband frame in response to the first part having a length of 2 bytes.

18. The device of claim 13, wherein

the length field of the first part is 5 bits and the length of the second part is less than or equal to 31 bytes, the second part is preceded by the first part in response to the first part having a length of 1 byte,

the length field of the first part represents end of the baseband frame in response to the first part having a length of 2 bytes.

19. The device of claim 14, wherein

the length field of the first part is 5 bits and the length of the second part is less than or equal to 31 bytes, the second part is preceded by the first part in response to the first part having a length of 1 byte,

the length field of the first part represents end of the baseband frame in response to the first part having a length of 2 bytes.