The present invention provides a switched-mode power converter with regulation demand pulses sent across a galvanic isolation barrier.
|
0. 36. In an isolated switched-mode power converter having an input port and an output port, a method of regulation comprising:
(a) comparing a voltage or current at the output port with a reference that is galvanically associated therewith;
(b) generating or gating demand pulses responsive to that comparison;
(c) applying the demand pulses to an output-port side of galvanic isolation circuitry;
(d) receiving replicas of the demand pulses from an input-port side of the galvanic isolation circuitry; and
(e) adjusting commutation frequency of the converter responsive to the demand pulses to cause the voltage or current at the output port to attain a desired value, wherein step (b) comprises:
(b1) using a diode to charge a capacitor during forward pulses of the power converter, wherein the diode and the capacitor are galvanically connected within the output-port side of the galvanic isolation circuitry; and
(b2) generating or gating the demand pulses using energy stored in the capacitor.
0. 27. Apparatus configured to provide galvanically isolated switched-mode power conversion, the apparatus comprising:
an input port configured to receive input power;
a switch configured to commutate the input power;
a transformer comprising (i) a primary winding arranged in circuit with the input port and the switch and (ii) a single secondary winding arranged in circuit with a rectifier and an output port, wherein the transformer is configured to supply power from the input port to a load connected to the output port; and
a first pulse source circuitry located on an input side of the apparatus and configured to generate pulses to control the switch to start the power conversion;
a second pulse source circuitry located on an output side of the apparatus and configured to generate pulses to control the switch to continue the power conversion after being started by the first pulse source circuitry; and
a capacitor and a diode both galvanically connected to the secondary winding, wherein:
the diode is different from the rectifier and is poled to charge the capacitor during forward pulses of the apparatus; and
the second pulse source circuitry is powered by energy stored in the capacitor to generate the pulses.
0. 18. Apparatus configured to provide switched-mode power conversion, the apparatus comprising:
an input port configured to receive input power;
a switch configured to commutate the input power;
galvanic isolation circuitry configured to provide galvanic isolation between the input port and an output port, wherein the galvanic isolation circuitry comprises a transformer comprising (i) a primary winding arranged in circuit with the input port and the switch and (ii) a secondary winding arranged in circuit with a rectifier and the output port, wherein the transformer is configured to transfer power from the input port to supply voltage or current to a load connected to the output port;
a demand pulse generator galvanically connected to the secondary winding and configured to generate demand pulses applied via the galvanic isolation circuitry to the switch to adjust a frequency of the commutation of the input power to supply a desired amount of voltage or current to the load; and
a capacitor and a diode both galvanically connected to the secondary winding, wherein:
the diode is different from the rectifier and is poled to charge the capacitor during forward pulses of the apparatus; and
the demand pulse generator is powered by energy stored in the capacitor to generate the demand pulses.
0. 1. Apparatus configured to provide switched-mode power conversion, the apparatus comprising:
an input port configured to receive input power;
a switch configured to commutate the input power;
galvanic isolation circuitry configured to provide galvanic isolation between the input port and an output port, wherein the galvanic isolation circuitry comprises a transformer comprising (i) a primary winding arranged in circuit with the input port and the switch and (ii) a secondary winding arranged in circuit with a rectifier and the output port, wherein the transformer is configured to transfer power from the input port to supply voltage or current to a load connected to the output port; and
a demand pulse generator galvanically connected to the secondary winding and configured to generate demand pulses applied via the galvanic isolation circuitry to the switch to adjust a frequency of the commutation of the input power to supply a desired amount of voltage or current to the load.
0. 2. The apparatus of
a source configured to provide a reference signal; and
comparison circuitry configured to compare the output port voltage or current to the reference signal wherein frequency of the demand pulses is responsive to the comparison between the output port voltage or current and the reference signal.
0. 3. The apparatus of
0. 4. The apparatus of
0. 5. The apparatus of
a fast oscillator configured to initiate the generation of the demand pulses; and
logic circuitry configured to provide gating of the demand pulses applied to the galvanic isolation circuitry.
0. 6. The apparatus of
0. 7. The apparatus of
0. 8. The apparatus of
the galvanic isolation circuitry divides the apparatus into (i) an input side corresponding to the primary winding of the transformer and (ii) an output side corresponding to the secondary winding of the transformer; and
the demand pulse generator is located on the output side of the apparatus.
0. 9. The apparatus of
the diode is different from the rectifier and is poled to charge the capacitor during forward pulses of the apparatus; and
the demand pulse generator is powered by energy stored in the capacitor to generate the demand pulses.
0. 10. Apparatus configured to provide galvanically isolated switched-mode power conversion, the apparatus comprising:
an input port configured to receive input power;
a switch configured to commutate the input power;
a transformer comprising (i) a primary winding arranged in circuit with the input port and the switch and (ii) a secondary winding arranged in circuit with a rectifier and an output port, wherein the transformer is configured to supply power from the input port to a load connected to the output port; and
a first pulse source circuitry located on an input side of the apparatus and configured to generate pulses to control the switch to start the power conversion; and
a second pulse source circuitry located on an output side of the apparatus and configured to generate pulses to control the switch to continue the power conversion after being started by the first pulse source circuitry.
0. 11. The apparatus of
0. 12. The apparatus of
0. 13. The apparatus of
0. 14. The apparatus of
0. 15. The apparatus of
the diode is different from the rectifier and is poled to charge the capacitor during forward pulses of the apparatus; and
the second pulse source circuitry is powered by energy stored in the capacitor to generate the pulses.
0. 16. In an isolated switched-mode power converter having an input port and an output port, a method of regulation comprising:
(a) comparing a voltage or current at the output port with a reference that is galvanically associated therewith;
(b) generating or gating demand pulses responsive to that comparison;
(c) applying the demand pulses to an output-port side of galvanic isolation circuitry;
(d) receiving replicas of the demand pulses from an input-port side of the galvanic isolation circuitry; and
(e) adjusting commutation frequency of the converter responsive to the demand pulses to cause the voltage or current at the output port to attain a desired value.
0. 17. The method of
(b1) using a diode to charge a capacitor during forward pulses of the power converter, wherein the diode and the capacitor are galvanically connected within the output-port side of the galvanic isolation circuitry; and
(b2) generating or gating the demand pulses using energy stored in the capacitor.
0. 19. The apparatus of claim 18, wherein:
the demand pulses instruct input-side circuitry of the apparatus to turn on the switch;
the input-side circuitry is configured to determine when to turn off the switch independent of the demand pulses;
the demand pulse generator is configured to generate the demand pulses when a feedback signal based on the output port voltage or current is lower in magnitude than a reference signal;
the apparatus is configured to regulate the output port by driving the feedback signal to match the reference signal;
feedback from an output side of the apparatus to an input side of the apparatus for regulating the output port voltage or current is provided solely by the demand pulses generated by the demand pulse generator;
each demand pulse conveyed from the output side of the apparatus to the input side of the apparatus has a leading edge;
when a particular demand pulse results in a particular occurrence of the switch turning on, the particular occurrence of the switch turning on is in response to detecting the leading edge of the particular demand pulse independent of any other demand pulses conveyed from the output side to the input side and independent of any other pulse edges appearing on the input side; and
the demand pulse generator is configured to generate a demand pulse whenever a magnitude of the output port voltage or current is below a magnitude of the output port's regulation voltage or current.
0. 20. The apparatus of claim 18, wherein the demand pulse generator comprises:
an oscillator configured to generate oscillator pulses; and
logic circuitry configured to selectively block certain oscillator pulses in generating the demand pulses.
0. 21. The apparatus of claim 20, wherein the logic circuitry is configured to selectively block the certain oscillator pulses from becoming demand pulses that would otherwise result in the switch being turned on, while selectively allowing other oscillator pulses to become the demand pulses that do result in the switch being turned on.
0. 22. The apparatus of claim 18, wherein the demand pulse generator is configured to process, based on a comparator output, an output-side stream of oscillator pulses to generate the demand pulses.
0. 23. The apparatus of claim 18, wherein the demand pulse generator comprises:
a comparator configured to generate a comparator output based on a comparison between (i) a feedback signal based on the output port voltage or current and (ii) a reference signal;
an oscillator configured to generate a stream of oscillator pulses independent of the comparator output; and
logic circuitry configured to (i) receive the comparator output and the stream of oscillator pulses and (ii) process, based on the comparator output, the stream of oscillator pulses to generate the demand pulses.
0. 24. The apparatus of claim 18, wherein, when the output port is in regulation, the determination of when to turn off the switch is always originated on an input side of the apparatus and never on an output side of the apparatus.
0. 25. The apparatus of claim 18, wherein the galvanic isolation circuitry further comprises a pulse transformer, separate from the transformer, configured to transmit the demand pulses from an output side of the apparatus to an input side of the apparatus.
0. 26. The apparatus of claim 18, wherein the apparatus comprises the load.
0. 28. The apparatus of claim 27, wherein:
the pulses generated by the second pulse source circuitry are demand pulses;
the demand pulses instruct input-side circuitry of the apparatus to turn on the switch;
the input-side circuitry is configured to determine when to turn off the switch independent of the demand pulses;
the second pulse source circuitry is configured to generate the demand pulses when a feedback signal based on the output port voltage or current is lower in magnitude than a reference signal;
the apparatus is configured to regulate the output port by driving the feedback signal to match the reference signal;
feedback from the output side of the apparatus to the input side of the apparatus for regulating the output port voltage or current is provided solely by the demand pulses generated by the second pulse source circuitry;
each demand pulse conveyed from the output side of the apparatus to the input side of the apparatus has a leading edge;
when a particular demand pulse results in a particular occurrence of the switch turning on, the particular occurrence of the switch turning on is in response to detecting the leading edge of the particular demand pulse independent of any other demand pulses conveyed from the output side to the input side and independent of any other pulse edges appearing on the input side; and
the second pulse source circuitry is configured to generate a demand pulse whenever a magnitude of the output port voltage or current is below a magnitude of the output port's regulation voltage or current.
0. 29. The apparatus of claim 27, wherein the second pulse source circuitry comprises:
an oscillator that generates oscillator pulses; and
logic circuitry that selectively blocks certain oscillator pulses in generating the pulses conveyed from the output side of the apparatus to the input side of the apparatus.
0. 30. The apparatus of claim 29, wherein the logic circuitry is configured to selectively block the certain oscillator pulses from becoming pulses that would otherwise result in the switch being turned on, while selectively allowing other oscillator pulses to become the pulses that do result in the switch being turned on.
0. 31. The apparatus of claim 27, wherein the second pulse source circuitry is configured to process, based on a comparator output, an output-side stream of oscillator pulses to generate the pulses conveyed from the output side of the apparatus to the input side of the apparatus.
0. 32. The apparatus of claim 27, wherein the second pulse source circuitry comprises:
a comparator configured to generate a comparator output based on a comparison between (i) a feedback signal based on the output port voltage or current and (ii) a reference signal;
an oscillator configured to generate a stream of oscillator pulses independent of the comparator output; and
logic circuitry configured to (i) receive the comparator output and the stream of oscillator pulses and (ii) process, based on the comparator output, the stream of oscillator pulses to generate the pulses conveyed from the output side of the apparatus to the input side of the apparatus.
0. 33. The apparatus of claim 27, wherein, when the output port is in regulation, the determination of when to turn off the switch is always originated on the input side of the apparatus and never on the output side of the apparatus.
0. 34. The apparatus of claim 27, wherein the apparatus further comprises a pulse transformer, separate from the transformer, configured to transmit the pulses generated by the second pulse source circuitry from the output side of the apparatus to the input side of the apparatus.
0. 35. The apparatus of claim 27, wherein the apparatus comprises the load.
0. 37. The method of claim 36, wherein:
the demand pulses instruct input-side circuitry of the power converter to turn on a switch on the input-port side;
the input-side circuitry determines when to turn off the switch independent of the demand pulses;
the demand pulses are generated when a feedback signal based on the output port voltage or current is lower in magnitude than a reference signal;
the output port is regulated by driving the feedback to match the reference signal;
feedback from the output-port side to the input-port side for regulating the output port voltage or current is provided solely by the demand pulses;
each demand pulse conveyed from the output-port side to the input-port side has a leading edge;
when a particular demand pulse results in a particular occurrence of the switch turning on, the particular occurrence of the switch turning on is in response to detecting the leading edge of the particular demand pulse independent of any other demand pulses conveyed from the output-port side to the input-port side and independent of any other pulse edges appearing on the input-port side; and
step (b) comprises generating a demand pulse whenever a magnitude of the output port voltage or current is below a magnitude of the output port's regulation voltage or current.
0. 38. The method of claim 36, wherein step (b) comprises:
(b1) generating oscillator pulses; and
(b2) selectively blocking certain oscillator pulses in generating the demand pulses.
0. 39. The method of claim 38, wherein step (b2) comprises selectively blocking the certain oscillator pulses from becoming demand pulses that would otherwise result in the switch being turned on, while selectively allowing other oscillator pulses to become the demand pulses that do result in the switch being turned on.
0. 40. The method of claim 36, wherein step (b) comprises processing, based on the comparison of step (a), an output-side stream of oscillator pulses to generate the demand pulses.
0. 41. The method of claim 36, wherein step (b) comprises:
(b1) generating a stream of oscillator pulses independent of the comparison of step (a); and
(b2) processing, based on the comparison of step (a), the stream of oscillator pulses to generate the demand pulses.
0. 42. The method of claim 36, wherein, when the output port is in regulation, the determination of when to turn off the switch is always originated on the input-port side and never on the output-port side.
0. 43. The method of claim 36, wherein the galvanic isolation circuitry comprises:
a power transformer that transmits power from the input port to the output port; and
a pulse transformer, separate from the power transformer, that transmits the demand pulses from the output-port side to the input-port side.
|
This application Notice: The following multiple reissue applications have been filed for the reissue of U.S. Pat. No. 9,071,152: (1) reissue application Ser. No. 15/090,929, filed on Apr. 5, 2016 and reissued as U.S. Reissue Pat. No. RE47,031; (2) reissue application Ser. No. 15/168,998, filed on May 31, 2016 and reissued as U.S. Reissue Pat. No. RE47,713, which is a reissue continuation of Ser. No. 15/090,929; (3) reissue application Ser. No. 15/202,746, filed on Jul. 6, 2016 and reissued as U.S. Reissue Pat. No. RE47,714, which is a reissue continuation of Ser. No. 15/090,929; (4) the present reissue application Ser. No. 16/547,850, filed on Aug. 22, 2019, which is a reissue continuation of Ser. No. 15/202,746; (5) reissue application Ser. No. 16/548,897, filed on Aug. 23, 2019, which is a reissue continuation of Ser. No. 15/202,746; and (6) reissue application Ser. No. 16/987,654, filed on Aug. 7, 2020, which is a reissue continuation of Ser. No. 16/547,850. U.S. Pat. No. 9,071,152 claims the benefit of the filing dates of U.S. provisional application Nos. 61/667,473, filed on Jul. 03, 2012, and 61/727,795, filed on Nov. 19, 2012, the teachings of both of which are incorporated herein by reference in their entirety.
1. Field of the Invention
The present invention relates to electronics and, more specifically but not exclusively, to switched-mode power converters.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Switched-mode DC-DC power converters, often powered by rectified DC from AC mains, are ubiquitous as plug-in adapters used to power a plethora of electronic devices.
A typical such converter is copiously documented in the Power Integrations Design example report DER-227. Such converters are also taught in U.S. Pat. No. 4,459,651 and U.S. Patent Application Publication Nos. 2011/0026277 A1 and 2011/0018590 A1. Such converters typically generate commutation pulses on the mains side of galvanic isolation circuitry.
Some known converters use forms of absorption modulation to convey feedback information through the power transformer. In U.S. Pat. No. 8,000,115, a temporary decrease in the loading of a transformer secondary winding during a flyback pulse generates a corresponding voltage disruption of the same pulse, which disruption is detected on another transformer winding to effect primary-winding-side converter control. In U.S. Pat. No. 5,973,945, a similar method is taught, but instead of unloading a flyback pulse, temporary loading of a forward power pulse is taught. The circuitry for extracting the resulting information-bearing current disruption in the transformer primary circuit is quite involved. A similar absorption modulator is taught in U.S. Pat. No. 4,996,638.
Converters are also known wherein an analog voltage reflection of the converter output voltage seen on a primary-side winding is processed to generate a primary-side analog feedback signal which is used to control the commutating signals applied to the commutating switch to regulate converter output on its secondary side. Such feedback methods are taught in U.S. Pat. Nos. 4,597,036 and 3,889,173. Such methods are becoming less common due to the difficulty of reliably processing the analog information reflected into a primary-side winding to obtain an accurate feedback signal.
U.S. Pat. No. 4,937,727 teaches a mains-side pulse generator that is pulse-width controlled by a voltage-responsive clamp on the output side of a galvanic isolation barrier.
Other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.
Transformer 100a also comprises a secondary winding 104a which may be connected to a floating common terminal 14a. A diode 300a and a capacitor 301a form a rectifier circuit to rectify and filter voltage pulses from winding 104a to supply power through a power output port comprising terminals 13a and 14a to an external load represented by resistor 7a connected in circuit therewith, one end of which may be referred to a floating common 8a. The power input port 11a/12a and the power output port 13a/14a may be galvanically isolated from each other.
Flyback pulses of transformer 100a occur when MOSFET 200a ceases conduction, i.e., turns OFF. Winding 104a is poled to cause diode 300a to rectify only these flyback pulses.
Forward pulses, of opposite polarity to the flyback pulses, occur while MOSFET 200a is ON. Another diode 500a, poled to rectify forward pulses, and another capacitor 501a form an auxiliary rectifier circuit to rectify and filter forward pulses from winding 104a, and to store energy for triggering the input-side blocking oscillator formed by MOSFET 200a, transformer 100a, capacitor 202a, and resistor 201a. Resistor 201a is made sufficiently large to set a low free-running frequency of the blocking oscillator, perhaps 1 KHz or less, to minimize power consumption. Nevertheless, the miniscule power thus provided suffices to charge capacitor 501a to a voltage related, through the turns ratio of transformer 100a, to the voltage at the power input port, even with the power output port short-circuited.
This magnetically-coupled blocking oscillator may be triggered through any transformer winding magnetically coupled thereto. Therefore, just as MOSFET 200a may be turned ON through winding 102a, it may as easily be triggered through winding 104a. To trigger thusly, diode 500a is briefly short-circuited by a switch 502a which is driven by a demand pulse generator 503a to source a pulse of energy from capacitor 501a into transformer 100a. When this is done, the voltage at the cathode of diode 500a falls rapidly to the voltage on its anode, also being the voltage across capacitor 501a. Since winding 104a is coupled to winding 101a, the voltage on drain D of MOSFET 200a also rapidly falls from near the voltage on terminal 11a to near the voltage on terminal 12a. Since winding 102a is also magnetically coupled, the voltage at its node shared with capacitor 202a abruptly rises, turning ON MOSFET 200a. This triggering action occurs in a few tens of nanoseconds. Until regeneration is established in MOSFET 200a through winding 102a, triggering energy is supplied by capacitor 501a of the auxiliary rectifier circuit. However, once regeneration is established in MOSFET 200a, capacitor 501a is charged for the duration of the ON time of MOSFET 200a, fully replacing any energy lost during triggering. The demand pulse generator 503a may be used to adjust the commutation frequency of the converter 10a to cause its output to attain a desired value, as will be described below.
It is important to understand certain important advantages of this embodiment. Firstly, this embodiment allows minimal, simple, and robust circuitry to be galvanically associated with the power input port where high voltages and mains transients may be expected. According to this embodiment, more complex and vulnerable regulation circuitry may be galvanically associated with the power output port where voltages are often lower and protection is more easily implemented. Secondly, the control of a flyback converter that may cross from the discontinuous conduction mode (DCM), through the critical conduction mode, to the continuous conduction mode (CCM), is well known to be problematic. This embodiment simply avoids that problem. In the embodiment shown in
This converter may be fitted with a reference voltage 400a and a comparison circuit 401a. When the voltage at terminal 13a falls below the comparison voltage, comparison circuit 401a causes pulse generator circuit 503a to pulse, turning ON switch 502a, triggering an energy-bearing ON cycle of the blocking oscillator, and charging capacitor 301a. As load 7a drains capacitor 301a, terminal 13a voltage repeatedly falls to the voltage of reference 400a, causing comparison circuit 401a to initiate energy-bearing ON cycles. An interesting property of this embodiment is that the bottom of its output ripple corresponds to the voltage of reference 400a, and the amplitude of its ripple decreases with increased current in load 7a.
As in
Please note that, in this embodiment, the poling of winding 104b, diode 300b, and diode 500b are reversed, and the output polarity is reversed, with respect to
We now depart from the
The pulses of energy from capacitor 501c sourced to transformer 100c, though a switch 502c, during the pulse of generator 503c, under the command of gate 506c, appear as voltage pulses across the primary winding of transformer 100c. These pulses are detected and processed to logic levels by a demand pulse detector 215c and passed through an OR gate 214c to a pulse generator that turns ON switch 200c to energize transformer 100c to begin an energy-bearing cycle. When switch 200c turns OFF, the subsequent flyback pulse charges capacitor 301c through diode 300c, as previously described. Since capacitor 501c is charged from the converter forward pulse, its voltage persists even in the presence of a short-circuit load, allowing the converter to recover once the short-circuit is removed.
Had no energy-bearing cycle ever occurred, there might be insufficient, or no, charge in capacitor 501c to be used to initiate energy-bearing cycles as described above. Therefore, a slow pulse oscillator 213c, preferably about 1 KHz, is also connected to gate 214c, through which it initiates energy-bearing cycles by triggering a pulse generator 216c, thus turning on switch 200c. These infrequent pulses cause energy-bearing cycles that are sufficient to charge capacitor 501c, which also may supply power to generator 503c, gate 506c, oscillator 505c, reference 400c, and comparison circuit 401c. Of course, slow oscillator 213c must somehow be powered along with gate 214c and pulse generator 216c. A bias supply (not shown but well known in the art) powered from terminals 11c and 12c, may be used to power these components of the circuit.
Input voltage from terminals 11d and 12d powers a slow oscillator 213d, preferably of less than 1 KHz frequency, and a start-up regulator 232d which, through a supply node +5d, initially powers, with a voltage preferably about 4V, logic and drive circuitry described below. Each label “+5d” in
Responsive to its clock pulse, flip-flop 220d turns ON a switch 200d, preferably a MOSFET, ON Semiconductor type NDD02N60, which is in circuit with a primary winding 101d of a transformer 100d, with a sense resistor 209d, and with terminals 11d and 12d. Current then flows in this circuit, and the voltage of source 5d is impressed upon primary winding 101d. According to the turns-ratio between primary winding 101d and a secondary winding 104d of transformer 100d, a voltage appears across winding 104d. This latter voltage charges a capacitor 416d through a diode 417d.
As current in resistor 209d rises, a voltage is applied to an input of a comparator 217d, which voltage is compared with a reference 216d, also connected to an input of comparator 217d. When current in resistor 209d exceeds a value set by reference 216d, comparator 217d issues a reset signal which propagates through NAND gates 218d and 219d to a node /Ra where the reset signal resets flip-flop 220d, turning OFF switch 200d.
When switch 200d is turned ON, unavoidable gate-to-source capacitance of MOSFET switch 200d causes a current spike in resistor 209d. To prevent comparator 217d from prematurely resetting flip-flop 220d responsive to this spike, the rise of node Qa charges a capacitor 231d through a resistor 230d to reach the threshold of a gate 219d in about 75 nS, prior to which the low voltage of capacitor 231d inhibits gate 219d from resetting flip-flop 220d.
Prior to its rise, node Qa has been low, and a complementary node/Qa has been high. When node Qa rises, node/Qa falls, discharging a capacitor 229d through a resistor 228d to the threshold of NAND gate 218d in about 2 uS, and though NAND gate 219d resetting flip-flop 220d, thus limiting the maximum ON time of switch 200d, should comparator 217d fail to reset flip-flop 220d.
In addition to limiting ON times of switch 200d, it is desirable to limit maximum frequency of these ON times. To this end, the voltage across a capacitor 226d is charged to a logic high through a resistor 225d and applied to a node Da, the D-input of flip-flop 220d. When node/Qa falls, capacitor 226d is discharged through a diode 227d, slowly to be recharged through resistor 225d. Until the capacitor 226d voltage is recharged to the D-input threshold voltage, flip-flop 220d is inhibited from turning ON switch 200d.
When switch 200d is turned OFF, the energy in the magnetic field of transformer 100d generates flyback voltage across its windings. Flyback voltage of winding 104d is rectified by a diode 300d and begins to charge a filter capacitor 301d to begin to supply output voltage to terminals 13d and 14d. This flyback voltage also raises the voltage on capacitor 416d, causing diode 417d to turn OFF and a diode 418d to turn ON, charging a capacitor 419d. Voltage across capacitor 419d supplies an auxiliary regulator 420d, which in turn powers a fast oscillator 505d, preferably of about 60 KHz frequency. Regulator 420d also powers logic and drive circuitry on the winding 104d side of the power converter.
The ON pulses of switch 200d responsive to oscillator 213d are sufficiently frequent to start the converter of this embodiment, but insufficiently frequent to drive it to full output. To initiate more frequent pulses, an oscillator 505d drives a capacitor 507d and a resistor 508d to supply differentiated pulses of about 100 nS width to a NAND gate 509d, which in turn drives a primary winding 111d of demand pulse transformer 110d, thus producing demand pulses across a secondary winding 112d thereof. These winding 112d pulses are conveyed through a NAND gate 223d to clock flip-flop 220d at up to the frequency of oscillator 505d.
If all of the pulses of oscillator 505d were allowed to clock flip-flop 220d, under some conditions, the converter of this embodiment would produce excess output. To regulate this output, a flip-flop 412d is used to gate the pulses passed by NAND gate 509d. At a node CKc, oscillator 505d clocks a flip-flop 412d, which generates a logic high at a node Qc only when a logic high is present at a node Dc at the rising edge of its clock. Thus, pulses driving transformer 110d are permitted responsive to a logic high only at node Dc.
It would be wasteful of power to drive winding 111d for the full duration of the differentiated pulse at resistor 508d. Therefore, when switch 200d turns ON causing a negative transition at the dotted end of winding 101d, a corresponding negative transition appears at the dotted end of winding 104d. This transition is coupled through a small capacitor 414d, preferably about 10 pF, through a current-limiting resistor 415d to a node/Rc, the reset input of flip-flop 412d, which is normally held high by a resistor 413d. Thus, once the turning ON of switch 200d has propagated through transformer 100d, flip-flop 412d is reset, usually in less than 20 nS.
Node Dc is usually held at a logic high by a resistor 411d, thus enabling pulses gated by flip-flop 412d. However, between terminals 13d and 14d is disposed a voltage divider comprising resistors 408d and 409d, the voltage at the junction of which is applied to an input of a comparator 401d. Should the voltage at that junction exceed the voltage of a reference 400d, also applied to a comparator 401d input, an output of comparator 401d will drop to a logic low, drawing current through a diode 410d, thus presenting a logic low at node Dc and, after clocking, responsively at node Qc, inhibiting pulses through gate 509d that would otherwise turn ON switch 200d. Thus, the voltage between terminals 13d and 14d is regulated responsive to the voltage of reference 400d.
Since the voltage between terminals 11d and 12d may be high, perhaps 375V, and the desired regulated voltage at node +5d is typically 5V, it might be inefficient to obtain the power to supply the logic and drive circuitry associated with winding 101d from regulator 232d. Therefore, transformer 100d is fitted with an auxiliary winding 102d, which is connected in circuit with an inductor 235d, a diode 241d, and a switch 233d, preferably a MOSFET. While switch 200d is ON, current flows in this circuit. When switch 200d turns OFF, diode 241d also turns OFF and energy in inductor 235d generates a positive flyback voltage, causing current through a diode 236d to charge a filter capacitor 237d, raising the voltage of node +5d. As node +5d approaches 5V, regulator 232d ceases to supply energy to node +5d, but continues to power a voltage reference 242d, which drives an input of a comparator 240d. Should the voltage of node +5d exceed 5V, the voltage at the junction of resistors 238d and 239d, connected to another input of comparator 240d, will exceed that of reference 242d, causing the output of comparator 240d at node Db to drop to a logic low.
A flip-flop 234d drives node Qb to turn ON switch 233d responsive to clock pulses on node Qa, and to a logic high being present at node Db. When node Db drops to a logic low, node Qb follows it upon the next clock, and switch 233d turns OFF. In this state, inductor 235d no longer receives energy and no longer charges capacitor 237d through diode 236d. Thus, node +5d is regulated to approximately 5V, and the energy supplying node +5d is provided efficiently through transformer 100d.
In one embodiment, the invention is a switched-mode power-converter comprising a power input port, a transformer comprising windings, a commutating switch connected in circuit with the input port and a winding of the transformer, a driver circuit for toggling the commutating switch, a power output port, a rectifier circuit for supplying power to the power output port, a reference voltage or current source, a comparison circuit for comparing the voltage or current at the power output port with the reference voltage or current, and a demand pulse source circuit coupled to the transformer for transmitting galvanically isolated trigger information through the transformer to the driver circuit responsive to the comparison circuit.
The converter may comprise as its driver circuit a blocking oscillator comprising the converter transformer. The converter may further comprise an input-side, master blocking oscillator for power conversion and an output-side, slave blocking oscillator for generating demand pulses. Both blocking oscillators may be mutually coupled through the converter power transformer or may drive separate transformers.
The converter may comprise inductive, capacitive, opto-coupled, or piezoelectric galvanic isolation circuitry to transmit demand pulses across the galvanic isolation barrier.
The converter may have one or more output rectifier circuits poled to rectify flyback pulses of its transformer.
The converter may comprise one or more auxiliary rectifier circuits which may be poled as forward converters.
The converter may be powered by a rectifier circuit to provide an AC/DC converter.
It should be understood that replicas of pulses generated and applied to one winding of the power transformer appear, suitably modified by turns-ratio, across all other windings of the power transformer.
Though blocking oscillators usually require tickler windings, single output embodiments of this invention may comprise a power transformer with as few as two, and in excess of five windings, with multiple output embodiments possibly comprising yet more windings.
Startup pulse generation circuitry resides on the powered side of the isolation barrier, though its pulses appear on both sides of the isolation barrier. This circuitry may comprise a blocking oscillator, another form of oscillator with drive circuitry to turn ON the commutating switch, or this circuitry may comprise an external source of pulses.
Demand pulse generator circuitry resides with the output port to be regulated, though its pulses appear on both sides of the isolation barrier. This circuitry may comprise a slave blocking oscillator, another form of oscillator with drive circuitry to turn ON the demand pulse generator switch, or may be externally applied.
Demand pulses may be generated to regulate the power converter to provide either a desired output voltage or a desired output current responsive to the voltage across or a current through an output port.
Between the commencement of start-up and the attainment of regulation, a pulse generator sources pulses to turn ON the commutating switch. This pulse generator may be the same generator that sources regulation pulses, or may be a separate pulse generator.
Each internal pulse generator is powered. The startup pulse generator is powered from the input port. The demand pulse generator is only indirectly powered from the input port by DC-DC power conversion through the power transformer and one or more rectifiers and filters powering the power output port with which the generator is associated.
Power for pulse generation circuitry may be rectified from either forward pulses, from flyback pulses, or both, appearing across one or more power transformer windings. Rectification of forward pulses helps to assure startup.
Windings, switches, and diodes may be poled to provide either polarity of input, and either polarity of output.
In each of the embodiments of
In each of the embodiments of
In each of the embodiments of
Embodiments of the invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes, including possible implementation as one or more integrated circuits (such as an ASIC or an FPGA), a multichip module, a single card, or a multicard circuit pack.
Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy or signals are allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements.
Also, for purposes of this disclosure, it is understood that all gates are powered from a fixed voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources.
Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here.
Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors.
The terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bipolar device when an embodiment of the invention is implemented using bi-polar transistor technology. p Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range.
It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims.
The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.
It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the invention.
Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”
The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to nonstatutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.
Lawson, Thomas E., Morong, William H.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
10008942, | Apr 12 2017 | Power Integrations, Inc | High side signal interface in a power converter |
3321685, | |||
3742336, | |||
3889173, | |||
4119103, | Oct 27 1976 | Medtronic, Inc. | Detachable power source with low current leakage |
4209847, | Dec 22 1977 | Toyoda Koki Kabushiki Kaisha | Computerized numerical controller for a machine apparatus |
4413224, | Apr 30 1979 | OMICRON SCIENTIFIC LTD KIRYAT WEIZMAN | Micropower system |
4438486, | Feb 22 1982 | General Electric Company | Low loss snubber for power converters |
4459651, | Jul 01 1982 | Honeywell Information Systems Inc. | Regulated flyback power supply using a combination of frequency and pulse width modulation |
4597036, | Oct 06 1983 | Siemens Aktiengesellschaft | Blocking oscillator power pack |
4694384, | Dec 04 1986 | General Electric Company | HVIC power supply controller with primary-side edge detector |
4758937, | Jan 16 1986 | Sanken Electric Company, Ltd. | DC-DC converter |
4887199, | Feb 07 1986 | Astec International Limited | Start circuit for generation of pulse width modulated switching pulses for switch mode power supplies |
4937727, | Mar 07 1989 | RCA Licensing Corporation | Switch-mode power supply with transformer-coupled feedback |
4958268, | Apr 05 1988 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD , 1006, OAZA KADOMA, KADOMA-SHI, OSAKA, JAPAN A CORP OF JAPAN; MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | Switching power supply |
4996638, | Feb 15 1990 | Astec International Limited | Method of feedback regulating a flyback power converter |
5161022, | May 15 1990 | Victor Company of Japan, Ltd. | dc-dc Converter for video apparatus |
5418410, | May 25 1993 | Semiconductor Components Industries, L L C | Leading edge blanking circuit |
5498995, | Mar 17 1993 | National Semiconductor Corporation | Short circuit frequency shift circuit for switching regulators |
5546040, | Jan 22 1993 | Apple Inc | Power efficient transistor and method therefor |
5642267, | Jan 16 1996 | California Institute of Technology | Single-stage, unity power factor switching converter with voltage bidirectional switch and fast output regulation |
5687068, | Dec 22 1995 | WEISS CONTROLS, INC | Power supply for in-line power controllers and two-terminal electronic thermostat employing same |
5719755, | Dec 11 1995 | Sanken Electric Co., Ltd. | Dc to dc converter |
5751171, | Mar 22 1995 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Predriver for fast current switching through a two-terminal inductive load |
5825640, | Jun 30 1997 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Charge pump circuit and method |
5841641, | Dec 31 1996 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Protected zero-crossing detection using switching transistor's on-resistance |
5973945, | Jul 01 1998 | Power Integrations, Inc | Coupled inductor power supply with reflected feedback regulation circuitry |
5986484, | Jul 05 1996 | SOURCE RECOVERY COMPANY, INC , THE | Semiconductor device drive circuit with voltage surge suppression |
6072702, | Nov 13 1998 | FDK Corporation | Ringing choke converter |
6297623, | Feb 27 1998 | Power Integrations, Inc. | Off-line converter with digital control |
6301135, | Mar 01 1999 | Texas Instruments Incorporated | Isolated switching-mode power supply control circuit having secondary-side controller and supervisory primary-side controller |
6304462, | Sep 24 1999 | Power Integrations, Inc. | Method and apparatus providing a multi-function terminal for a power supply controller |
6456511, | Feb 17 2000 | LAPIS SEMICONDUCTOR CO , LTD | Start-up circuit for flyback converter having secondary pulse width modulation |
6466461, | Feb 09 2001 | Netpower Technologies, Inc. | Method and circuit for reducing voltage level variation in a bias voltage in a power converter |
6504267, | Dec 14 2001 | Koninklijke Philips Electronics N.V. | Flyback power converter with secondary-side control and primary-side soft switching |
6563718, | Dec 06 2001 | Koninklijke Philips Electronics N.V. | Capacitively coupled power converter |
6711034, | Sep 04 2001 | KONINKLIJIKE PHILIPS ELECTRONICS N V | DC-DC converter and a regulation method for this DC-DC converter |
6738267, | Oct 19 1999 | Alcatel | Switched power supply converter with a piezoelectric transformer |
7368880, | Jul 19 2004 | INTERSIL AMERICAS LLC | Phase shift modulation-based control of amplitude of AC voltage output produced by double-ended DC-AC converter circuitry for powering high voltage load such as cold cathode fluorescent lamp |
7450402, | Apr 12 2002 | DET International Holding Limited | Soft switching high efficiency flyback converter |
7773392, | Aug 11 2005 | Murata Manufacturing Co., Ltd. | Isolated switching power supply apparatus |
7835163, | Jun 11 2007 | LEADTREND TECHNOLOGY CORP | Switching power converter with a secondary-side control |
7876583, | Dec 22 2008 | Power Integrations, Inc.; Power Integrations, Inc | Flyback power supply with forced primary regulation |
8000115, | Dec 22 2008 | Power Integrations, Inc. | Flyback power supply with forced primary regulation |
8125799, | Oct 23 2009 | BCD SHANGHAI MICRO-ELECTRONICS COMPANY LIMITED | Control circuits and methods for switching mode power supplies |
8243477, | Dec 22 2008 | Power Integrations, Inc. | Flyback power supply with forced primary regulation |
8587968, | Oct 23 2009 | BCD SHANGHAI MICRO-ELECTRONICS COMPANY LIMITED | Control circuits and methods for switching mode power supplies |
8767418, | Mar 17 2010 | Power Systems Technologies, Ltd | Control system for a power converter and method of operating the same |
8792258, | May 06 2008 | BCD SHANGHAI MICRO-ELECTRONICS COMPANY LIMITED | Method and apparatus for reducing standby power of switching mode power supplies |
8823353, | Oct 20 2011 | Power Integrations, Inc | Power controller with smooth transition to pulse skipping |
8913407, | Jan 30 2009 | Power Integrations, Inc. | Method and apparatus to regulate an output voltage of a power converter at light/no load conditions |
8933649, | Dec 28 2009 | Power Integrations, Inc | Power converter having a switch coupled between windings |
8976561, | Nov 14 2012 | Power Integrations, Inc.; Power Integrations, Inc | Switch mode power converters using magnetically coupled galvanically isolated lead frame communication |
9019728, | Mar 08 2013 | Power Integrations, Inc.; Power Integrations, Inc | Power converter output voltage clamp and supply terminal |
9035435, | Nov 14 2012 | Power Integrations, Inc.; Power Integrations, Inc | Magnetically coupled galvanically isolated communication using lead frame |
9071153, | Apr 06 2007 | Power Integrations, Inc. | Method and apparatus for power converter fault condition detection |
9083251, | Oct 20 2011 | Power Integrations, Inc. | Power controller with pulse skipping |
9112425, | Jun 14 2013 | Power Integrations, Inc. | Switch mode power converter having burst mode with current offset |
9178411, | Jan 22 2013 | Power Integrations, Inc. | Charging circuit for a power converter controller |
9246392, | Mar 13 2013 | Power Integrations, Inc | Switched mode power converter controller with ramp time modulation |
9275946, | Nov 14 2012 | Power Integrations, Inc. | Switch mode power converters using magnetically coupled galvanically isolated lead frame communication |
9374019, | Feb 16 2011 | ON-BRIGHT ELECTRONICS SHANGHAI CO , LTD | Systems and methods for discharging an AC input capacitor with automatic detection |
20050254266, | |||
20060267514, | |||
20070024254, | |||
20080181316, | |||
20080267212, | |||
20080278975, | |||
20080303560, | |||
20080310191, | |||
20090097291, | |||
20100026268, | |||
20100157630, | |||
20100231279, | |||
20110018590, | |||
20110022867, | |||
20110026277, | |||
20110096573, | |||
20110096578, | |||
20110305043, | |||
20120153921, | |||
20120281439, | |||
20130100710, | |||
20130299841, | |||
20160079877, | |||
EP585789, | |||
EP2717449, | |||
JP2005503099, | |||
RE46369, | Oct 23 2009 | BCD SHANGHAI MICRO-ELECTRONICS COMPANY LIMITED | Control circuits and methods for switching mode power supplies |
WO2009154523, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 22 2019 | CogniPower, LLC | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Aug 22 2019 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Sep 03 2019 | SMAL: Entity status set to Small. |
Date | Maintenance Schedule |
Feb 21 2026 | 4 years fee payment window open |
Aug 21 2026 | 6 months grace period start (w surcharge) |
Feb 21 2027 | patent expiry (for year 4) |
Feb 21 2029 | 2 years to revive unintentionally abandoned end. (for year 4) |
Feb 21 2030 | 8 years fee payment window open |
Aug 21 2030 | 6 months grace period start (w surcharge) |
Feb 21 2031 | patent expiry (for year 8) |
Feb 21 2033 | 2 years to revive unintentionally abandoned end. (for year 8) |
Feb 21 2034 | 12 years fee payment window open |
Aug 21 2034 | 6 months grace period start (w surcharge) |
Feb 21 2035 | patent expiry (for year 12) |
Feb 21 2037 | 2 years to revive unintentionally abandoned end. (for year 12) |