High/low speed mode selection for output driver circuits of a memory interface

Abstract

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

100′the100a 100 and an electric-photo conversion circuit 1010. The electric-photo conversion circuit 1010 may convert an electrical signal output from the first memory device 100a 100 into a photo signal, and output the converted photo signal to the second system 1100 through optical connection means 901.

The second system 1100 includes a photoelectric conversion circuit 1120 and a second memory device 100b 100-2. The photoelectric conversion circuit 1120 may convert a photo signal input through the optical connection means 901 into an electric signal, and transmit the converted electrical signal to the second memory device 100b 100-2.

The first system 1000 may further include the photo-electric conversion circuit 1020, and the second system 1100 may further include the electric-photo conversion circuit 1110.

When the second system 1100 transmits data to the first system 1000, the electric-photo conversion circuit 1110 may convert an electrical signal output from the second memory device 100b 100-2 into a photo signal, and output the converted photo signal to the first system through the optical connection means 901. The photoelectric conversion circuit 1020 may convert a photo signal input through the optical connection means 901 into an electric signal, and transmit the converted electrical signal to the first memory device 100a 100. A structure and an operation of each memory device 100a 100 and 100b 100-2 are substantially the same as a structure and an operation of the memory device 100 of FIG. 1.

A method according to an example embodiment of the inventive concepts, by selecting and using an output driver circuit or an input receiver circuit according to an operation mode, may embody an appropriate input/output interface in the operation mode.

The method according to an example embodiment of the inventive concepts, by selecting and using the appropriate output driver circuit or an input receiver circuit in an operation mode, may improve efficiency in electricity and maintain good property of a transmission signal.

Although a some example embodiments of the inventive concepts have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the inventive concepts, the scope of which is defined in the appended claims and their equivalents.

Claims

1. An input/output interface for a memory device comprising:

a mode selection circuit configured to generate a mode selection signal; and

an output driver block configured to be connected to an input/output pad and to transmit an output data signal, the input/output pad being terminated at the pad with one of a vssq termination, a vddq termination and a termination off mode based on the mode selection signal, and the output driver block comprising a plurality of output driver circuits, and one of the plurality of output driver circuits being configured to selectively operate or not operate during transmitting the output data signal based on the mode selection signal, wherein

each of the plurality of output driver circuits has different topology suitable for different operation speed, the operation speed selected from a group including a low speed operation, and a high speed operation faster than the low speed operation.

2. The input/output interface of claim 1, wherein the vssq termination has a termination voltage level of a ground voltage level and the vddq termination has a termination voltage level of a supply voltage level respectively.

3. The input/output interface of claim 1, wherein the mode selection signal is configured to receive include operating frequency information for selecting one among a plurality of on-die termination (ODT) circuits.

4. The input/output interface of claim 3, wherein the mode selection signal is configured to select the termination off mode if the operating frequency information indicates the low speed operation.

5. The input/output interface of claim 3, wherein the mode selection signal is configured includes information indicating to select the vddq termination if the operating frequency information indicates an intermediate speed operation which is faster than the low speed operation but slower than the high speed operation.

6. The input/output interface of claim 3, wherein the mode selection signal is configured includes information indicating to select the vssq termination if the operating frequency information indicates the high speed operation.

7. The input/output interface of claim 3, wherein the mode selection signal is configured includes information indicating to select a first output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates the high speed operation, wherein a pull-up driver of the first output driver circuit comprises a nmos transistor.

8. The input/output interface of claim 3, wherein the mode selection signal is configured includes information indicating to select a second output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates one of an intermediate speed operation and the low speed operation, the intermediate speed operation being faster than the low speed operation and slower than the high speed operation, wherein a pull-up driver of the second output driver circuit comprises a pmos transistor.

9. An input/output interface for a memory device comprising:

a mode selection circuit configured to generate a mode selection signal;

a termination circuit configured to provide the input/output interface with one of a vssq termination, a vddq termination and a termination off mode in response to the mode selection signal; and

an output driver block configured to transmit a data output signal, the output driver block being connected to an input/output pad and comprising a plurality of output driver circuits, wherein one of the plurality of output driver circuits is configured to selectively operate or not operate according to the mode selection signal, the mode selection signal indicating a termination type of the termination circuit,

wherein each of the plurality of output driver circuits has different topology suitable for different operation speed, the operation speed selected from a group including a low speed operation, and a high speed operation faster than the low speed operation.

10. The input/output interface of claim 9, wherein the vssq termination has a termination voltage level of a ground voltage level and the vddq termination has a termination voltage level of a supply voltage level respectively.

11. The input/output interface of claim 9, wherein the mode selection signal is configured includes information indicating to receive operating frequency information for selecting one among a plurality of on-die termination (ODT) circuits.

12. The input/output interface of claim 11, wherein the mode selection signal is configured includes information indicating to select the termination off mode if the operating frequency information indicates the low speed operation.

13. The input/output interface of claim 11, wherein the mode selection signal is configured includes information indicating to select the vddq termination if the operating frequency information indicates an intermediate speed operation, the intermediate speed operation faster than the low speed operation and slower than the high speed operation.

14. The input/output interface of claim 11, wherein the mode selection signal is configured includes information indicating to select the vssq termination if the operating frequency information indicates the high speed operation.

15. The input/output interface of claim 11, wherein the mode selection signal is configured includes information indicating to select a first output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates the high speed operation, wherein a pull-up driver of the first output driver circuit comprises a nmos transistor.

16. The input/output interface of claim 11, wherein the mode selection signal is configured includes information indicating to select a second output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates one of an intermediate speed operation faster than the low speed operation and slower than the high speed operation, and the low speed operation, wherein a pull-up driver of the second output driver circuit comprises a pmos transistor.

17. An input/output interface circuit for a memory device comprising:

a mode selection circuit configured to generate a mode selection signal;

a termination circuit configured to provide the input/output interface with one of a vssq termination, a vddq termination and a termination off mode in response to the mode selection signal; and

an output driver block connected to an input/output pad including,

a first output driver circuit configured to transmit a output data signal, the first output driver circuit including a nmos pull-up driver;, and

a second output driver circuit configured to transmit the output data signal, the second output driver circuit including a pmos pull-up driver,

wherein one of the first output driver circuit and the second output driver circuit is selected to transmit the output data signal in response to the mode selection signal.

18. The input/output interface of claim 17, wherein the vssq termination has a termination voltage level of a ground voltage level and the vddq termination has a termination voltage level of a supply voltage level respectively.

19. The input/output interface of claim 17, wherein the mode selection circuit is configured to receive operating frequency information for selecting one among a plurality of on-die termination (ODT) circuits.

20. The input/output interface of claim 19, wherein the mode selection signal is configured includes information indicating to select the first output driver circuit if the operating frequency information indicates a high speed operation.

21. The input/output interface of claim 19, wherein the mode selection signal is configured includes information indicating to select the second output driver circuit if the operating frequency information indicates one of a medium speed operation and a low speed operation.