Systems and methods for adaptive modulation of MOSFET driver key parameters for improved voltage regulator efficiency and reliability in a voltage regulator may include a power stage. The power stage may include a high side switch including a high side gate, a peak voltage detection circuit, and a high side driver strength modulator circuit. The high side driver strength modulator circuit may determine a high side driver strength level. The high side driver strength modulator circuit may also connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level. The high side driver strength modulator circuit may also disconnect a remaining subset of the set of high side gate drivers from the high side gate.
|
0. 15. A voltage regulator, comprising:
a power stage including:
a first power switch having a high side switch including a high side gate;
a current sense circuit coupled to the high side switch to monitor and report a load current level of the power stage;
a high side driver strength modulator circuit that is coupled to the current sense circuit and that is configured to:
determine a high side driver strength level for a set of high side gate drivers based on the load current level of the power stage;
connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level; and
disconnect a remaining subset of the set of high side gate drivers from the high side gate; and
a dead-time management circuit that is configured to:
adjust a dead-time duration of the set of high side gate drivers to a first dead-time duration based on a first power stage temperature; and
adjust the dead-time duration of the set of high side gate drivers to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature,
wherein the adjusting of the dead-time duration of the set of high side gate drivers prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on.
0. 16. A voltage regulator, comprising:
a power stage including:
a first power switch having a high side switch including a high side gate;
a peak voltage detection circuit coupled to the high side switch to provide a voltage stress level of a high side output voltage of the high side switch;
a high side driver strength modulator circuit that is coupled to the peak voltage detection circuit and that is configured to:
determine a high side driver strength level for a set of high side gate drivers based on the voltage stress level of the high side output voltage of the high side switch;
connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level; and
disconnect a remaining subset of the set of high side gate drivers from the high side gate; and
a dead-time management circuit that is configured to:
adjust a dead-time duration of the set of high side gate drivers to a first dead-time duration based on a first power stage temperature; and
adjust the dead-time duration of the set of high side gate drivers to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature,
wherein the adjusting of the dead-time duration of the set of high side gate drivers prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on.
0. 22. A voltage regulator, comprising:
a first power switch;
a turn-on gate driver that is configured to turn on the first power switch;
a plurality of pmos devices coupling the turn-on gate driver to the first power switch;
a turn-off gate driver that is configured to turn off the first power switch;
a plurality of nmos devices coupling the turn-off gate driver to the first power switch;
a voltage detection device that is configured to monitor and report voltage stress information associated with a peak voltage produced by the first power switch during switching operations;
at least one driver strength modulator that is coupled to the voltage detection device, the plurality of pmos devices, and the plurality of nmos devices, wherein the at least one driver strength modulator is configured to turn on the first power switch by:
determining, based on the voltage stress information reported by the voltage detection device, a turn-on driver strength level for the turn-on gate driver; and
connecting the turn-on gate driver to the first power switch via at least a first subset of the plurality of pmos devices that is based on the turn-on driver strength level, and
wherein the at least one driver strength modulator is configured to turn off the first power switch by:
determining, based on the voltage stress information reported by the voltage detection device, a turn-off driver strength level for the turn-off gate driver; and
connecting the turn-off gate driver to the first power switch via at least a first subset of the plurality of nmos devices that is based on the turn-off driver strength level; and
a dead-time management device that is configured to:
adjust a dead-time duration of the turn-on gate driver and the turn-off gate driver to a first dead-time duration based on a first power stage temperature; and
adjust the dead-time duration of the turn-on gate driver and the turn-off gate driver to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature,
wherein the adjusting of the dead-time duration of the turn-on gate driver and the turn-off gate driver prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on.
0. 17. A voltage regulator, comprising:
a first power switch;
a turn-on gate driver that is configured to turn on the first power switch;
a plurality of p-channel Metal Oxide Semiconductor (pmos) devices coupling the turn-on gate driver to the first power switch;
a turn-off gate driver that is configured to turn off the first power switch;
a plurality of n-channel Metal Oxide Semiconductor (nmos) devices coupling the turn-off gate driver to the first power switch;
a current sense device that is configured to monitor and report load current information associated with a power stage load current;
at least one driver strength modulator that is coupled to the current sense device, the plurality of pmos devices, and the plurality of nmos devices, wherein the at least one driver strength modulator is configured to turn on the first power switch by:
determining, based on the load current information reported by the current sense device, a turn-on driver strength level for the turn-on gate driver; and
connecting the turn-on gate driver to the first power switch via at least a first subset of the plurality of pmos devices that is based on the turn-on driver strength level, and
wherein the at least one driver strength modulator is configured to turn off the first power switch by:
determining, based on the load current information reported by the current sense device, a turn-off driver strength level for the turn-off gate driver; and
connecting the turn-off gate driver to the first power switch via at least a first subset of the plurality of nmos devices that is based on the turn-off driver strength level; and
a dead-time management device that is configured to:
adjust a dead-time duration of the turn-on gate driver and the turn-off gate driver to a first dead-time duration based on a first power stage temperature; and
adjust the dead-time duration of the turn-on gate driver and the turn-off gate driver to a second dead-time duration that is different than the first dead-time duration based on a second power stage temperature that is greater than the first power stage temperature,
wherein the adjusting of the dead-time duration of the turn-on gate driver and the turn-off gate driver prevents the first power switch from turning on when a second power switch that is complementary to the first power switch is turned on.
0. 1. A voltage regulator, comprising:
a power stage including:
a high side switch including a high side gate;
a peak voltage detection circuit coupled to the high side switch to provide a voltage stress level based on a high side output voltage of the high side switch;
a high side driver strength modulator circuit coupled to the peak voltage detection circuit configured to:
determine a high side driver strength level for a set of high side gate drivers based on a load current level of the power stage and the voltage stress level;
connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level; and
disconnect a remaining subset of the set of high side gate drivers from the high side gate; and
a dead-time management circuit configured to:
adjust a programmable portion of a dead-time duration for the set of high side gate drivers and a set of low side gate drivers, the dead-time duration including the programmable portion of the dead-time duration and a dynamic portion of the dead-time duration proportional to a change in temperature of the power stage when the power stage is in an operating temperature region, wherein the programmable portion of the dead-time duration is adjusted to a low temperature duration value when the dead-time management circuit determines that a current temperature of the power stage is less than or equal to a low temperature region threshold, and wherein the programmable portion of the dead-time duration is adjusted to a high temperature duration value when the dead-time management circuit determines that the current temperature of the power stage is greater than or equal to a high temperature region threshold.
0. 2. The voltage regulator of
higher positive load current levels correlate to higher driver voltage levels and lower positive load current levels correlate to lower driver voltage levels, and wherein
higher magnitude negative load current levels correlate to higher driver voltage levels and lower magnitude negative load current levels correlate to lower driver voltage values.
0. 3. The voltage regulator of
a low side switch including a low side gate; and
a low side driver strength modulator circuit coupled to the peak voltage detection circuit configured to:
determine a low side driver strength level for the set of low side gate drivers based on the load current level of the power stage and the voltage stress level;
connect a subset of the set of low side gate drivers to the low side gate based on the low side driver strength level; and
disconnect a remaining subset of the set of low side gate drivers from the low side gate.
0. 4. The voltage regulator of
0. 5. The voltage regulator of
a driver strength modulator circuit including:
a source impedance modulator circuit;
a set of high side driver switches, each coupled between a corresponding high side gate driver of the set of high side gate drivers and the high side gate, wherein the connection of the subset of the set of high side gate drivers to the high side gate further comprises:
the source impedance modulator circuit configured to close a subset of the set of high side driver switches to connect the subset of the set of high side gate drivers to the high side gate;
a sink impedance modulator circuit; and
a set of low side driver switches, each coupled between a corresponding low side gate driver of the set of low side gate drivers and the low side gate, wherein the connection of the subset of the set of low side gate drivers to the low side gate further comprises:
the sink impedance modulator circuit configured to close a subset of the set of low side driver switches to connect the subset of the set of low side gate drivers to the low side gate.
0. 6. The voltage regulator of
a driver voltage optimizer circuit configured to adjust a driver voltage level for the set of high side gate drivers and the set of low side gate drivers.
0. 7. The voltage regulator of
reduce the driver voltage level when the driver voltage optimizer circuit determines that the load current level is less than or equal to a light load current threshold level; and
increase the driver voltage level when the driver voltage optimizer circuit determines that the load current level is greater than a heavy load condition threshold level.
0. 8. A method comprising:
providing, by a peak voltage detection circuit of a power stage of a voltage regulator, a voltage stress level based on a high side output voltage of a high side switch of the power stage;
determining, by a high side driver strength modulator circuit of the power stage, a high side driver strength level for a set of high side gate drivers of the power stage based on a load current level of the power stage and the voltage stress level;
connecting a subset of the set of high side gate drivers to a high side gate of the high side switch based on the high side driver strength level;
disconnecting a remaining subset of the set of high side gate drivers from the high side gate; and
adjusting, by a dead-time management circuit, a programmable portion of a dead-time duration for the set of high side gate drivers and a set of low side gate drivers, wherein the dead-time duration includes the programmable portion of the dead-time duration and a dynamic portion of the dead-time duration proportional to a change in temperature of the power stage when the power stage is in an operating temperature region, and wherein adjusting the programmable portion of the dead-time duration for the set of high side gate drivers and the set of low side gate drivers comprises:
determining when a current temperature of the power stage is less than or equal to a low temperature region threshold;
in response to determining that the current temperature is less than or equal to the low temperature region threshold, adjusting the programmable portion of the dead-time duration for the set of high side gate drivers and the set of low side gate drivers to a low temperature duration value;
determining when the current temperature of the power stage is greater than or equal to a high temperature region threshold; and
in response to determining that the current temperature is greater than or equal to the high temperature region threshold, adjusting the programmable portion of the dead-time duration for the set of high side gate drivers and the set of low side gate drivers to a high temperature duration value.
0. 9. The method of
higher positive load current levels correlate to higher driver voltage levels and lower positive load current levels correlate to lower driver voltage levels, and wherein
higher magnitude negative load current levels correlate to higher driver voltage levels and lower magnitude negative load current levels correlate to lower driver voltage values.
0. 10. The method of
determining, by a low side driver strength modulator circuit of the power stage, a low side driver strength level for the set of low side gate drivers of the power stage based on the load current level of the power stage and the voltage stress level;
connecting a subset of the set of low side gate drivers to a low side gate of a low side switch based on the low side driver strength level; and
disconnecting a remaining subset of the set of low side gate drivers from the low side gate.
0. 11. The method of
0. 12. The method of
closing, by a source impedance modulator circuit, a subset of a set of high side driver switches of the power stage to connect the subset of the set of high side gate drivers to the high side gate; and wherein connecting the subset of the set of low side gate drivers to the low side gate further comprises:
closing, by a sink impedance modulator circuit, a subset of a set of low side driver switches to connect the subset of the set of low side gate drivers to the low side gate.
0. 13. The method of
adjusting, by a driver voltage optimizer circuit, a driver voltage level for the set of high side gate drivers and the set of low side gate drivers.
0. 14. The method of
reducing the driver voltage level when the driver voltage optimizer circuit determines that the load current level is less than or equal to a light load current threshold level; and
increasing the driver voltage level when the driver voltage optimizer circuit determines that the load current level is greater than a heavy load condition threshold level.
0. 18. The voltage regulator of claim 17, wherein the at least one driver strength modulator is configured to determine the turn-on driver strength level for the turn-on gate driver based on the load current information reported by the current sense device by accessing a load current information/turn-on driver strength level table that associates respective turn-on driver strength levels with respective load current information, and wherein the at least one driver strength modulator is configured to determine the turn-off driver strength level for the turn-off gate driver based on the load current information reported by the current sense device by accessing a load current information/turn-off driver strength level table that associates respective turn-off driver strength levels with respective load current information.
0. 19. The voltage regulator of claim 17, wherein the plurality of pmos devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn on the first power switch by:
connecting the turn-on gate driver to the first power switch via the first subset of the plurality of pmos devices that is based on the turn-on driver strength level; and
disconnecting the turn-on gate driver from the first power switch via the second subset of the plurality of pmos devices that is based on the turn-on driver strength level.
0. 20. The voltage regulator of claim 17, wherein the plurality of nmos devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn off the first power switch by:
connecting the turn-off gate driver to the first power switch via the first subset of the plurality of nmos devices that is based on the turn-on driver strength level; and
disconnecting the turn-off gate driver from the first power switch via the second subset of the plurality of nmos devices that is based on the turn-on driver strength level.
0. 21. The voltage regulator of claim 17, wherein the plurality of pmos device and the plurality of nmos devices are provided by a plurality of respective pmos device/nmos device pairs.
0. 23. The voltage regulator of claim 22, wherein the at least one driver strength modulator is coupled to each of the plurality of pmos devices by respective pmos switch devices and is configured to close each respective pmos switch device connected to that pmos device to connect the turn-on gate driver to the first power switch via that pmos device.
0. 24. The voltage regulator of claim 22, wherein the plurality of pmos devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn on the first power switch by:
connecting the turn-on gate driver to the first power switch via the first subset of the plurality of pmos devices that is based on the turn-on driver strength level; and
disconnecting the turn-on gate driver from the first power switch via the second subset of the plurality of pmos devices that is based on the turn-on driver strength level.
0. 25. The voltage regulator of claim 22, wherein the plurality of nmos devices include the first subset and a second subset, and wherein the at least one driver strength modulator is configured to turn off the first power switch by:
connecting the turn-off gate driver to the first power switch via the first subset of the plurality of nmos devices that is based on the turn-on driver strength level; and
disconnecting the turn-off gate driver from the first power switch via the second subset of the plurality of nmos devices that is based on the turn-on driver strength level.
0. 26. The voltage regulator of claim 22, wherein the plurality of pmos device and the plurality of nmos devices are provided by a plurality of respective pmos device/nmos device pairs.
|
|||||||||||||||||
328
where Pgate is the power consumption of the gate drivers 320 of power switch 186, Pgate_LS is the portion of power consumption of the high side gate drivers 320-1, Pgate_HS is the portion of power consumption of the high side gate drivers 320-1, Qg(HS) is the gate charge at the high side gate drivers 320-1, Qg(LS) is the gate charge at the low side gate drivers 320-2, VDriver is the gate driver voltage at the gate drivers 320, and is the switching loss at the switching node output of power switch 186.
Pcond=Rds(ON)LS*I2RMS(LS)+Rds(ON)HS*I2RMS(HS) (2)
where Pcond is the conduction loss at the power switch 186, Rds(ON)LS is the on resistance of the low side switch 189, Rds(ON)HS is the on resistance of the high side switch 188, I2RMS(LS) is the root-mean-square (RMS) value of the current flowing through the low side switch 189, and I2RMS(HS) is the RMS value of the current flowing through the high side switch 188. In a light load operating condition, the switching loss in a power switch is a more dominant factor than the conduction loss in the overall multi-phase voltage regulator power loss. Gate driver loss belongs to the switching loss and can be further reduced by reducing the driver voltage in the light load condition. At the same time, the charge level of the power switch 186 will decrease as well with the decrease of the gate driver voltage. In the heavy load operation, the conduction loss is a more dominant factor than the switching loss in the overall multi-phase voltage regulator power loss. The higher gate drive voltage creates smaller on resistance of the power switch 186 and results an overall efficiency increase.
During operation, driver voltage optimizer circuit 316 may receive load current information 332 including a load current IMON and a load current reference IREF of power stage 182 from current sense circuit 310. Driver voltage optimizer circuit 316 may determine the load current level by a comparison of the load current to the load current reference. Then, driver voltage optimizer circuit 316 may adjust a driver voltage level for the set of high side gate drivers 320-1 and the set of low side gate drivers 320-2 based on the received load current level of power stage 182. When driver voltage optimizer circuit 316 determines that the load current level is less than or equal to a light load current threshold level, driver voltage optimizer circuit 316 may reduce the driver voltage level to adjust the driver voltage level for the set of high side gate drivers 320-1 and the set of low side gate drivers 320-2. When driver voltage optimizer circuit 316 determines that the load current level is greater than a heavy load condition threshold level, driver voltage optimizer circuit 316 may increase the driver voltage level to adjust the driver voltage level.
In one or more embodiments, driver voltage optimizer circuit 316 may use a threshold based logic table to determine the driver voltage level. The dynamic range of gate driver voltage levels may be controlled in a window of operation so that no other parameters, e.g. driver strength level or dead-times, are impacted. An example of a predefined threshold based logic table for determining the driver voltage level based on load current information is given in table II below. In exemplary table II, low voltage is 4.5V, nominal voltage is 5V and high voltage is 5.5V.
TABLE II
Driver Voltage versus IMON
IMON
Driver Voltage
Below the Defined Positive
Low Voltage
Load Level I
Below the defined positive
Nominal Voltage
load level II
Below the Defined Positive
High Voltage
Load Level III
Below the Defined Negative
Low Voltage
Load Level III
Below the Defined Negative
Nominal Voltage
Load Level II
Below the Defined Negative
High Voltage
Load Level I
As shown in table II, higher positive load current levels may correlate to higher driver voltage levels and lower positive load current levels may correlate to lower driver voltage levels. Similarly, higher magnitude negative load current levels may correlate to higher driver voltage levels and lower magnitude negative load current levels may correlate to lower driver voltage values. For example, a high gate driver voltage (5.5V) should be used when the load current is within the range of greater than or equal to the defined positive load level II and less than the defined positive load level III. In another example, a low gate driver voltage (4.5V) should be used when the load current is less than the defined negative load level III.
Driver voltage optimizer circuit 316 of power stage 182 allows individual control of the gate driver voltage of the set of gate drivers 320 of each power switch 186 of multi-phase voltage regulator 180 and only adjusts the gate driver voltage based on meeting predefined load current criteria as described above. As such, optimization for either reducing the gate driver loss or resistance on loss dynamically and autonomously occurs in each individual phase when meeting the predefined load current criteria and exits and does not occur when failing the predefined load current criteria.
In
During operation, dead-time management circuit 306 may receive temperature information including a current temperature of power stage 182 from thermal sense circuit 304. Dead-time management circuit 306 may determine whether the current temperature of power stage 182 is less than or equal to a low temperature region threshold. In response to determining that the current temperature of power stage 182 is less than or equal to the low temperature region threshold, dead-time management circuit 306 may adjust a programmable portion of a dead-time duration for the set of high side gate drivers 320-1 and the set of low side gate drivers 320-2 to a low temperature duration value. Dead-time management circuit 306 may determine whether the current temperature of power stage 182 is greater than or equal to a high temperature region threshold. In response to determining that the current temperature of power stage 182 is greater than or equal to a high temperature region threshold, dead-time management circuit 306 may adjust the programmable portion of the dead-time duration for the set of high side gate drivers 320-1 and the set of low side gate drivers 320-2 to a high temperature duration value. The dead-time duration of power switch 182 may include the programmable portion of the dead-time duration and a dynamic portion of the dead-time duration, where the dynamic portion of the dead-time duration may be proportional to a change in temperature of the power stage when the power stage may be in an operating temperature region. Power stage 182 operates across a wide range of temperatures due to the dynamic load conditions of power stage 182 and its ambient thermal environment, which may result in significant changes in the dynamic portion of the dead-time duration of power switch 186. For example, when power stage 182 is operating in a high temperature region, the dynamic dead-time duration may increase by a few extra nano-seconds. By dead-time management circuit 306 adjusting the programmable portion of the duration of dead-time based on the temperature of the power stage 182, the changes in the dynamic portion of the dead-time duration may be compensated for and may result in increased system efficiency.
The multi-phase voltage regulator may include a voltage regulator controller and a plurality of power stages coupled to the voltage regulator controller. Each power stage of the plurality of the power stages may include a high side switch including a high side gate, a peak voltage detection circuit coupled to the high side switch, and a HS driver strength modulator circuit coupled to the peak voltage detection circuit.
Method 500 may begin at step 502, providing, by the peak voltage detection circuit of a power stage of a multi-phase voltage regulator, a voltage stress level based on a high side output voltage of the high side switch of the power stage. At step 504, determining, by the HS driver strength modulator circuit of the power stage, a HS driver strength level for a set of high side gate drivers of the power stage based on one or more of a load current level of the power stage and the voltage stress level. At step 506, connecting a subset of the set of high side gate drivers to a high side gate of the high side switch based on the HS driver strength level. At step 508, disconnecting a remaining subset of the set of high side gate drivers from the high side gate.
As disclosed herein, systems and methods for adaptive modulation of MOSFET driver key parameters for improved voltage regulator efficiency and reliability in a multi-phase voltage regulator may include a power stage. The power stage may include a high side switch including a high side gate, a peak voltage detection circuit, and a high side driver strength modulator circuit. The high side driver strength modulator circuit may determine a high side driver strength level. The high side driver strength modulator circuit may also connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level. The high side driver strength modulator circuit may also disconnect a remaining subset of the set of high side gate drivers from the high side gate.
The above disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments which fall within the true spirit and scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present disclosure is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Johnson, Ralph H., Luo, Shiguo, Zhang, Kejiu
| Patent | Priority | Assignee | Title |
| Patent | Priority | Assignee | Title |
| 10135430, | Jan 19 2016 | Texas Instruments Incorporated | Adjusting drive strength for driving transistor device |
| 9143079, | Jun 27 2012 | Denso Corporation | Power converter |
| 9240722, | Jun 19 2014 | Dell Products LP | Methods and systems for improving light load efficiency for power stages of multi-phase voltage regulator circuits |
| 9343949, | Sep 22 2014 | Texas Instruments Incorporated | Control circuit to detect a noise signal during a state change of a switch |
| 9443431, | May 08 2012 | Western Digital Technologies, Inc.; Western Digital Technologies, INC | System and method for preventing undesirable substantially concurrent switching in multiple power circuits |
| 9678555, | Jun 19 2014 | Dell Products L.P. | Methods and systems for calibration of voltage regulator systems with multiple types of power stages |
| 20060250183, | |||
| 20080278123, | |||
| 20120206121, | |||
| 20150091539, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Aug 06 2021 | Dell Products L.P. | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| Aug 06 2021 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
| Nov 06 2023 | REM: Maintenance Fee Reminder Mailed. |
| Nov 21 2023 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Nov 21 2023 | M1554: Surcharge for Late Payment, Large Entity. |
| Date | Maintenance Schedule |
| Aug 29 2026 | 4 years fee payment window open |
| Mar 01 2027 | 6 months grace period start (w surcharge) |
| Aug 29 2027 | patent expiry (for year 4) |
| Aug 29 2029 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Aug 29 2030 | 8 years fee payment window open |
| Mar 01 2031 | 6 months grace period start (w surcharge) |
| Aug 29 2031 | patent expiry (for year 8) |
| Aug 29 2033 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Aug 29 2034 | 12 years fee payment window open |
| Mar 01 2035 | 6 months grace period start (w surcharge) |
| Aug 29 2035 | patent expiry (for year 12) |
| Aug 29 2037 | 2 years to revive unintentionally abandoned end. (for year 12) |