A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (jfet) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.
|
0. 26. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is in a range from 1.0 to 2.5 microns and is provided at a fourth depth that is greater than the first depth, and
wherein a thickness of the jfet region is in a range from 0.75 to 1.5 microns.
0. 37. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and
wherein the doping concentration of the spreading layer at the third depth is greater than or equal to a doping concentration of the jfet region.
0. 38. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and
wherein the base region of each of the junction implants in the pair of junction implants is positioned between the respective well region of the respective junction implants in the pair of junction implants and the jfet region.
0. 36. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer comprising a first doping type;
a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:
a well region with a second doping type that is opposite the first doping type; and
a base region with the second doping type;
wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and
a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;
wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and
wherein a width of the spreading layer at the second depth and between the base region of each of the junction implants in the pair of junction implants is less than a width of the spreading layer at the first depth and between the well region of each of the junction implants in the pair of junction implants.
0. 1. A transistor device comprising a gate, a source, and a drain, wherein the gate and the source are separated from the drain by at least a jfet region, a spreading layer including a graded doping profile, and a drift layer, wherein a doping concentration of the spreading layer varies more than a factor of about 102 cm−3 between the jfet region and the drift layer.
0. 2. The transistor device of
0. 3. The transistor device of
0. 4. The transistor device of
0. 5. The transistor device of
0. 6. The transistor device of
0. 7. The transistor device of
0. 8. The transistor device of
0. 9. The transistor device of
0. 10. The transistor device of
0. 11. The transistor device of
0. 12. The transistor device of
0. 13. A transistor device comprising:
a substrate;
a drift layer on the substrate;
a spreading layer on the drift layer, the spreading layer having a graded doping profile such that a doping concentration of the spreading layer varies more than a factor of about 102 cm−3 between a jfet region and the drift layer;
a pair of junction implants in the spreading layer and separated by the jfet region, each one of the pair of junction implants comprising a deep well region, a base region, and a source region;
a gate contact and a source contact on the spreading layer, such that the gate contact partially overlaps and runs between each source region in the pair of junction implants; and
a drain contact on the substrate opposite the drift layer.
0. 14. The transistor device of
0. 15. The transistor device of
0. 16. The transistor device of
0. 17. The transistor device of
0. 18. The transistor device of
0. 19. The transistor device of
0. 20. The transistor device of
0. 21. The transistor device of
0. 22. The transistor device of
0. 23. The transistor device of
0. 24. The transistor device of
0. 25. The transistor device of
0. 27. The transistor device of claim 26, wherein the transistor device comprises silicon carbide.
0. 28. The transistor device of claim 26, further comprising a gate contact, a drain contact, and a source contact.
0. 29. The transistor device of claim 28, wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).
0. 30. The transistor device of claim 28, further comprising a channel regrowth layer between the gate contact and the jfet region, the channel regrowth layer comprising the first doping type with a doping concentration that is less than a doping concentration of the jfet region.
0. 31. The transistor device of claim 30, wherein the doping concentration of the channel regrowth layer is less than a doping concentration of the spreading layer at an interface between the spreading layer and the drift layer.
0. 32. The transistor device of claim 31, wherein the spreading layer has a doping concentration in a range from 2×1017 cm−3 to 5×1016 cm−3 and the channel regrowth layer has the doping concentration in a range from 1×1015 cm−3 to 1×1017 cm−3.
0. 33. The transistor device of claim 26, wherein a channel width of the transistor device is less than 3 microns.
0. 34. The transistor device of claim 33, wherein an on-state resistance of the transistor device is between 1.8 mΩ/cm2 and 2.2 mΩ/cm2, and a blocking voltage of the transistor device is rated to handle between 600 volts and 1200 volts.
0. 35. The transistor device of claim 26, wherein a thickness of each of the junction implants in the pair of junction implants is in a range from 1.0 to 2.0 microns.
|
decrease increase in proportion to the distance of the layer from the JFET region 54. The layer of the spreading layer 50 closest to the drift layer 48 JFET region 54 may have a doping concentration about 2×1017 cm−3.
The JFET region 54 may be an N-doped layer with a doping concentration from about 1×1016 cm−3 to 2×1017 cm−3. The drift layer 48 may be an N-doped layer with a doping concentration from about 6×1015 cm−3 to 1.5×1016 cm−3. The deep well region 56 may be a heavily P-doped region with a doping concentration from about 5×1017 cm−3 to 1×1020 cm−3. The base region 58 may be a P-doped region with a doping concentration from about 5×1016 cm−3 to 1×1019 cm−3. The source region 60 may be an N-doped region with a doping concentration from about 1×1019 cm−3 to 1×1021 cm−3. The N doping agent may be nitrogen, phosphorous, or any other suitable element, as will be appreciated by those of ordinary skill in the art. The P doping agent may be aluminum, boron, or any other suitable element, as will be appreciated by those of ordinary skill in the art.
The gate contact 66, the source contacts 68, and the drain contact 70 may be comprised of multiple layers. For example, each one of the contacts may include a first layer of nickel or nickel-aluminum, a second layer of titanium over the first layer, a third layer of titanium-nickel over the second layer, and a fourth layer of aluminum over the third layer. Those of ordinary skill in the art will appreciate that the gate contact 66, the source contacts 68, and the drain contact 70 may be formed of any suitable material.
Next, as illustrated by
Next, as illustrated by
Next, as illustrated by
Next, as illustrated by
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
Cheng, Lin, Pala, Vipindas, Palmour, John Williams, Lichtenwalner, Daniel Jenner, Agarwal, Anant Kumar
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
10192960, | Jul 26 2013 | SUMITOMO ELECTRIC INDUSTRIES, LTD | Silicon carbide semiconductor device and method for manufacturing same |
4126900, | Jan 28 1977 | U.S. Philips Corporation | Random access junction field-effect floating gate transistor memory |
4803533, | Sep 30 1986 | Fairchild Semiconductor Corporation | IGT and MOSFET devices having reduced channel width |
4967243, | Jul 19 1988 | Fairchild Semiconductor Corporation | Power transistor structure with high speed integral antiparallel Schottky diode |
5111253, | May 09 1989 | Lockheed Martin Corporation | Multicellular FET having a Schottky diode merged therewith |
5241195, | Aug 13 1992 | North Carolina State University at Raleigh | Merged P-I-N/Schottky power rectifier having extended P-I-N junction |
5365102, | Jul 06 1993 | North Carolina State University | Schottky barrier rectifier with MOS trench |
5378911, | Feb 23 1993 | Nissan Motor Co., Ltd. | Structure of semiconductor device |
5536977, | Nov 30 1993 | Siliconix Incorporated | Bidirectional current blocking MOSFET for battery disconnect switching |
5661314, | May 09 1990 | International Rectifier Corporation | Power transistor device having ultra deep increased concentration |
5674766, | Dec 30 1994 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
5689144, | May 15 1996 | Siliconix Incorporated | Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance |
5886383, | Jan 10 1997 | International Rectifier Corporation | Integrated schottky diode and mosgated device |
5973367, | Oct 13 1995 | Siliconix Incorporated | Multiple gated MOSFET for use in DC-DC converter |
6057558, | Mar 05 1997 | Denso Corporation | Silicon carbide semiconductor device and manufacturing method thereof |
6239463, | Aug 28 1997 | Siliconix Incorporated | Low resistance power MOSFET or other device containing silicon-germanium layer |
6700175, | Jul 02 1999 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Vertical semiconductor device having alternating conductivity semiconductor regions |
6979863, | Apr 24 2003 | Cree, Inc. | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same |
7221010, | Dec 20 2002 | Cree, Inc. | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors |
7498633, | Jan 21 2005 | THE TRUSTEES OF PURDUE UNIVERSITY | High-voltage power semiconductor device |
7592647, | Mar 31 2005 | Eudyna Devices Inc. | Semiconductor device and manufacturing method thereof |
7923320, | Dec 20 2002 | Cree, Inc. | Methods of fabricating vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors |
8178920, | Jan 17 2006 | FUJI ELECTRIC CO , LTD | Semiconductor device and method of forming the same |
8283973, | Aug 19 2009 | PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO , LTD | Semiconductor element, semiconductor device, and electric power converter |
8415671, | Apr 16 2010 | Cree, Inc | Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices |
8492827, | Dec 20 2002 | Cree, Inc. | Vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors |
8575692, | Feb 11 2011 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Near zero channel length field drift LDMOS |
8686439, | Jun 27 2011 | Panasonic Corporation | Silicon carbide semiconductor element |
9318597, | Sep 20 2013 | WOLFSPEED, INC | Layout configurations for integrating schottky contacts into a power transistor device |
9331197, | Aug 08 2013 | WOLFSPEED, INC | Vertical power transistor device |
9741842, | Aug 08 2013 | WOLFSPEED, INC | Vertical power transistor device |
20020038891, | |||
20020047124, | |||
20020125541, | |||
20030006452, | |||
20030040144, | |||
20030080355, | |||
20030178672, | |||
20030214011, | |||
20040099905, | |||
20040195618, | |||
20040212011, | |||
20040251503, | |||
20050035398, | |||
20050045960, | |||
20050082611, | |||
20050253190, | |||
20060192256, | |||
20060202264, | |||
20060214221, | |||
20070012983, | |||
20070034901, | |||
20070045655, | |||
20070096237, | |||
20070120201, | |||
20070145414, | |||
20070235745, | |||
20080012026, | |||
20080029812, | |||
20080050876, | |||
20080105949, | |||
20080128850, | |||
20080142811, | |||
20080149963, | |||
20080197439, | |||
20080206941, | |||
20080230787, | |||
20080308838, | |||
20090057757, | |||
20090065814, | |||
20090072242, | |||
20090078971, | |||
20090079001, | |||
20090090920, | |||
20090146154, | |||
20090173949, | |||
20090179297, | |||
20090189228, | |||
20090218621, | |||
20090236612, | |||
20090272983, | |||
20090278197, | |||
20090283776, | |||
20090283798, | |||
20100013007, | |||
20100025693, | |||
20100073039, | |||
20100078710, | |||
20100093116, | |||
20100176443, | |||
20100219417, | |||
20100270586, | |||
20110049564, | |||
20110156810, | |||
20110193057, | |||
20110241068, | |||
20110254088, | |||
20120025874, | |||
20120037955, | |||
20120088339, | |||
20120187419, | |||
20120236615, | |||
20120256195, | |||
20120280258, | |||
20120292742, | |||
20120306009, | |||
20120313212, | |||
20130026493, | |||
20130026568, | |||
20130105889, | |||
20130153995, | |||
20130306983, | |||
20130313635, | |||
20130341674, | |||
20140021484, | |||
20140027781, | |||
20140048847, | |||
20140070268, | |||
20140077311, | |||
20140117376, | |||
20140203299, | |||
20140252554, | |||
20150041886, | |||
20150053920, | |||
20150084062, | |||
20150084063, | |||
20150084118, | |||
20150084119, | |||
20150084125, | |||
20160211360, | |||
CN1729577, | |||
EP748520, | |||
EP867943, | |||
EP1576672, | |||
FR2814855, | |||
JP2007184434, | |||
JP2012114104, | |||
JP2013149837, | |||
JP5742164, | |||
JP6149474, | |||
JP65867, | |||
KR101020344, | |||
TW330894, | |||
WO2012137914, | |||
WO2013014943, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Oct 26 2020 | WOLFSPEED, INC. | (assignment on the face of the patent) | / | |||
Oct 01 2021 | Cree, Inc | WOLFSPEED, INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 057891 | /0880 | |
Jun 23 2023 | WOLFSPEED, INC | U S BANK TRUST COMPANY, NATIONAL ASSOCIATION | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 064185 | /0755 |
Date | Maintenance Fee Events |
Oct 26 2020 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Date | Maintenance Schedule |
Apr 09 2027 | 4 years fee payment window open |
Oct 09 2027 | 6 months grace period start (w surcharge) |
Apr 09 2028 | patent expiry (for year 4) |
Apr 09 2030 | 2 years to revive unintentionally abandoned end. (for year 4) |
Apr 09 2031 | 8 years fee payment window open |
Oct 09 2031 | 6 months grace period start (w surcharge) |
Apr 09 2032 | patent expiry (for year 8) |
Apr 09 2034 | 2 years to revive unintentionally abandoned end. (for year 8) |
Apr 09 2035 | 12 years fee payment window open |
Oct 09 2035 | 6 months grace period start (w surcharge) |
Apr 09 2036 | patent expiry (for year 12) |
Apr 09 2038 | 2 years to revive unintentionally abandoned end. (for year 12) |