Vertical power transistor device

Abstract

A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (jfet) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Description

decrease increase in proportion to the distance of the layer from the JFET region 54. The layer of the spreading layer 50 closest to the drift layer 48 JFET region 54 may have a doping concentration about 2×10¹⁷ cm⁻³.

The JFET region 54 may be an N-doped layer with a doping concentration from about 1×10¹⁶ cm⁻³ to 2×10¹⁷ cm⁻³. The drift layer 48 may be an N-doped layer with a doping concentration from about 6×10¹⁵ cm⁻³ to 1.5×10¹⁶ cm⁻³. The deep well region 56 may be a heavily P-doped region with a doping concentration from about 5×10¹⁷ cm⁻³ to 1×10²⁰ cm⁻³. The base region 58 may be a P-doped region with a doping concentration from about 5×10¹⁶ cm⁻³ to 1×10¹⁹ cm⁻³. The source region 60 may be an N-doped region with a doping concentration from about 1×10¹⁹ cm⁻³ to 1×10²¹ cm⁻³. The N doping agent may be nitrogen, phosphorous, or any other suitable element, as will be appreciated by those of ordinary skill in the art. The P doping agent may be aluminum, boron, or any other suitable element, as will be appreciated by those of ordinary skill in the art.

The gate contact 66, the source contacts 68, and the drain contact 70 may be comprised of multiple layers. For example, each one of the contacts may include a first layer of nickel or nickel-aluminum, a second layer of titanium over the first layer, a third layer of titanium-nickel over the second layer, and a fourth layer of aluminum over the third layer. Those of ordinary skill in the art will appreciate that the gate contact 66, the source contacts 68, and the drain contact 70 may be formed of any suitable material.

FIG. 5 shows the power MOSFET 44 according to an additional embodiment of the present disclosure. The power MOSFET 44 shown in FIG. 5 is substantially similar to that of FIG. 3, but further includes a channel Re-growth layer 80 between the gate oxide layer 64 and the spreading layer 50. The channel re-growth layer 80 is provided to lower the threshold voltage of the power MOSFET 44. Specifically, the deep well region 56, due to a heavy level of doping, may raise the threshold voltage of the power MOSFET 44 to a level that inhibits optimum performance. Accordingly, the channel re-growth layer 80 may offset the effects of the deep well region 56 in order to lower the threshold voltage of the power MOSFET 44. The channel re-growth layer 80 may be an N-doped region with a doping concentration from about 1×10¹⁵ cm⁻³ to 1×10¹⁷ cm⁻³

FIGS. 6-15 illustrate a process for manufacturing the power MOSFET 44 shown in FIG. 3. First, as illustrated by FIG. 6, the drift layer 48 is grown on top of the substrate 46. Those of ordinary skill in the art will recognize that any suitable growth process may be used to produce the drift layer 48 without departing from the principles of the present disclosure. For example, a chemical vapor deposition process may be used to form the drift layer 48.

Next, as illustrated by FIG. 7, the spreading layer 50 is grown on top of the drift layer 48. As discussed above, any suitable growth process may be used to create the spreading layer 50 without departing from the principles of the present disclosure. According to one embodiment, the spreading layer 50 is grown such that it includes a graded doping profile.

Next, as illustrated by FIG. 8, the deep well region 56 of each one of the junction implants 52 is implanted in the spreading layer 50. As will be appreciated by those of ordinary skill in the art, the deep well regions 56 may be implanted by any suitable implantation process. For example, an ion implantation process may be used to form the deep well regions 56. The base regions 58 are then implanted, as illustrated by FIG. 9, followed by the source regions 60, as illustrated by FIG. 10.

Next, as illustrated by FIG. 11, the JFET region 54 is implanted. As discussed above, any suitable implantation process may be used to create the JFET region 54 without departing from the principles of the present disclosure. Additionally, although not illustrated, the JFET region 54 may alternatively be created by a growth process.

Next, as illustrated by FIG. 12, the gate oxide layer 64 is formed on top of the spreading layer 50, such that the gate oxide layer 64 partially overlaps and runs between the surface of each source region 60 in the junction implants 52. In FIG. 13, the gate contact 66 is formed on top of the gate oxide layer 64. The source contacts 68 are then formed on the surface of the spreading layer 50 such that each one of the source contacts 68 partially overlaps both the source region 60 and the deep well region 56 of the junction implants 52, respectively, and does not contact the gate oxide layer 64 or the gate contact 66, as illustrated by FIG. 14. Finally, in FIG. 15, the drain contact 70 is provided on the surface of the substrate 46 opposite the drift layer 48.

FIG. 16 is a chart depicting the effect of the spreading layer 50 on the ON resistance of the power MOSFET 44. As shown, the spreading layer provides about a 20% decrease in the ON resistance of the device.

FIG. 17 is a chart depicting the effect of the spreading layer 50 on the electric field seen by the gate oxide layer 64. Because the spreading layer 50 allows a reduction in channel width 62 without impeding the performance of the power MOSFET 44, up to 26% of the electric field seen by the gate oxide layer 64 may be terminated by the opposing junction implants 52, thereby significantly increasing the longevity of the device.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A transistor device comprising a gate, a source, and a drain, wherein the gate and the source are separated from the drain by at least a jfet region, a spreading layer including a graded doping profile, and a drift layer, wherein a doping concentration of the spreading layer varies more than a factor of about 10² cm⁻³ between the jfet region and the drift layer.

2. The transistor device of claim 1 wherein the jfet region, the spreading layer, and the drift layer comprise silicon carbide.

3. The transistor device of claim 1 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).

4. The transistor device of claim 1 wherein the jfet region has a first doping concentration, the spreading layer has a second doping concentration that is different from the first doping concentration, and the drift layer has a third doping concentration that is different from the first doping concentration and the second doping concentration.

5. The transistor device of claim 4 wherein the spreading layer has a doping concentration in the range of approximately 2×10¹⁷ cm⁻³ to approximately 5×10¹⁶ cm⁻³.

6. The transistor device of claim 4 wherein the jfet region has a doping concentration in the range of approximately 1×10¹⁶ cm⁻³ to approximately 2×10¹⁷ cm⁻³.

7. The transistor device of claim 1 wherein a thickness of the jfet region is in the range of approximately 0.75 microns to approximately 1 micron.

8. The transistor device of claim 1 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.

9. The transistor device of claim 1 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.

10. The transistor device of claim 1 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm².

11. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm².

12. The transistor device of claim 1 wherein the transistor device is adapted to support a voltage between the source and the drain of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm².

13. A transistor device comprising:

a substrate;

a drift layer on the substrate;

a spreading layer on the drift layer, the spreading layer having a graded doping profile such that a doping concentration of the spreading layer varies more than a factor of about 10² cm⁻³ between a jfet region and the drift layer;

a pair of junction implants in the spreading layer and separated by the jfet region, each one of the pair of junction implants comprising a deep well region, a base region, and a source region;

a gate contact and a source contact on the spreading layer, such that the gate contact partially overlaps and runs between each source region in the pair of junction implants; and

a drain contact on the substrate opposite the drift layer.

14. The transistor device of claim 13 further comprising a gate oxide layer between the gate contact and the spreading layer.

15. The transistor device of claim 13 wherein the source contact is divided into two sections, and each section of the source contact is on a portion of the spreading layer such that each section of the source contact partially overlaps both the source region and the deep well region of each one of the pair of junction implants, respectively.

16. The transistor device of claim 13 wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).

17. The transistor device of claim 13 wherein the drift layer and the spreading layer comprise silicon carbide.

18. The transistor device of claim 13 wherein a width of the jfet region is approximately 3 microns or less.

19. The transistor device of claim 18 wherein an internal resistance of the transistor device is less than approximately 2.2 mΩ/cm².

20. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 600V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 1.8 mΩ/cm².

21. The transistor device of claim 13 wherein the transistor device is adapted to support a voltage between the source contact and the drain contact of at least 1200V while in an OFF state, and further wherein the transistor device has an internal resistance of less than approximately 2.2 mΩ/cm².

22. The transistor device of claim 13 wherein a thickness of the drift layer is in the range of approximately 3.5 microns to approximately 12 microns.

23. The transistor device of claim 13 wherein a thickness of the spreading layer is in the range of approximately 1.0 microns to approximately 2.5 microns.

24. The transistor device of claim 13 wherein a thickness of the jfet region is in the range of approximately 0.75 microns to approximately 1.0 microns.

25. The transistor device of claim 13 wherein a thickness of each one of the pair of junction implants is in the range of approximately 1.0 microns to approximately 2.0 microns.

26. A transistor device comprising:

a substrate;

a drift layer on the substrate;

a spreading layer on the drift layer, the spreading layer comprising a first doping type;

a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:

a well region with a second doping type that is opposite the first doping type; and

a base region with the second doping type;

wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and

a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;

wherein a thickness of the spreading layer is in a range from 1.0 to 2.5 microns and is provided at a fourth depth that is greater than the first depth, and

wherein a thickness of the jfet region is in a range from 0.75 to 1.5 microns.

27. The transistor device of claim 26, wherein the transistor device comprises silicon carbide.

28. The transistor device of claim 26, further comprising a gate contact, a drain contact, and a source contact.

29. The transistor device of claim 28, wherein the transistor device is a vertically disposed metal-oxide-semiconductor field-effect transistor (MOSFET).

30. The transistor device of claim 28, further comprising a channel regrowth layer between the gate contact and the jfet region, the channel regrowth layer comprising the first doping type with a doping concentration that is less than a doping concentration of the jfet region.

31. The transistor device of claim 30, wherein the doping concentration of the channel regrowth layer is less than a doping concentration of the spreading layer at an interface between the spreading layer and the drift layer.

32. The transistor device of claim 31, wherein the spreading layer has a doping concentration in a range from 2×10¹⁷ cm⁻³ to 5×10¹⁶ cm⁻³ and the channel regrowth layer has the doping concentration in a range from 1×10¹⁵ cm⁻³ to 1×10¹⁷ cm⁻³.

33. The transistor device of claim 26, wherein a channel width of the transistor device is less than 3 microns.

34. The transistor device of claim 33, wherein an on-state resistance of the transistor device is between 1.8 mΩ/cm² and 2.2 mΩ/cm², and a blocking voltage of the transistor device is rated to handle between 600 volts and 1200 volts.

35. The transistor device of claim 26, wherein a thickness of each of the junction implants in the pair of junction implants is in a range from 1.0 to 2.0 microns.

36. A transistor device comprising:

a substrate;

a drift layer on the substrate;

a spreading layer on the drift layer, the spreading layer comprising a first doping type;

a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:

a well region with a second doping type that is opposite the first doping type; and

a base region with the second doping type;

wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and

a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;

wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and

wherein a width of the spreading layer at the second depth and between the base region of each of the junction implants in the pair of junction implants is less than a width of the spreading layer at the first depth and between the well region of each of the junction implants in the pair of junction implants.

37. A transistor device comprising:

a substrate;

a drift layer on the substrate;

a spreading layer on the drift layer, the spreading layer comprising a first doping type;

a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:

a well region with a second doping type that is opposite the first doping type; and

a base region with the second doping type;

wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and

a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;

wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and

wherein the doping concentration of the spreading layer at the third depth is greater than or equal to a doping concentration of the jfet region.

38. A transistor device comprising:

a substrate;

a drift layer on the substrate;

a spreading layer on the drift layer, the spreading layer comprising a first doping type;

a pair of junction implants that are provided to a first depth in the spreading layer, wherein each of the junction implants in the pair of junction implants comprises:

a well region with a second doping type that is opposite the first doping type; and

a base region with the second doping type;

wherein the well region is provided to the first depth in the spreading layer, and the base region is provided to a second depth in the spreading layer that is less than the first depth; and

a jfet region that is provided to a third depth in the spreading layer that is less than the first depth and less than the second depth;

wherein a thickness of the spreading layer is provided at a fourth depth that is greater than the first depth, and a doping concentration of the spreading layer increases as a distance from the drift layer increases such that a ratio of the doping concentration at an interface between the spreading layer and the drift layer to the doping concentration at the third depth is 1:x where x is greater than or equal to 2 and less than or equal to 4, and

wherein the base region of each of the junction implants in the pair of junction implants is positioned between the respective well region of the respective junction implants in the pair of junction implants and the jfet region.