Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code

Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code
RE49989

Certain aspects of the present disclosure provide low-density parity-check (LDPC) codes having pairwise orthogonality of adjacent rows, and a new decoder that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion of the rows.

PTO Wrapper PDF
Dossier Espace Google

Patent RE49989
Priority Jun 10 2017
Filed May 28 2021
Issued May 28 2024
Expiry Jun 07 2038
Inventors Soriaga, J…
Assg.orig Qualcomm I…
Assg.curr Qualcomm I…
Entity Large
Referenced by 0
References 348
Maint.: currently ok

CROSS-REFERENCE TO R…

27. A method for wireless communication, comprising:

encoding a set of information bits with encoder circuitry based on a low density parity check (LDPC) code to produce a codeword wherein:

the LDPC code is stored in a memory and defined by a base matrix having a first number plurality of columns corresponding to variable nodes of a base graph and a second number plurality of rows corresponding to check nodes of the base graph, and;

elements in all adjacent rows of a column are orthogonal, for each of the first number plurality of columns, all adjacent rows are orthogonal in a last portion of the second number of at least twenty-one rows starting from a last row of the base matrix; and

each row of the twenty-one rows contains a non-zero element in a first column, of the plurality of columns, with a column index 0, or a non-zero element in a second column, of the plurality of columns, with a column index 1; and

transmitting the codeword in accordance with a radio technology across a wireless channel via one or more antenna elements.

22. A method for wireless communication, comprising:

receiving a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal a receiver; and

decoding the codeword via decoder circuitry based on a low density parity check (LDPC) code to produce a set of information bits, wherein:

15. An apparatus for wireless communication, comprising:

at least one processor coupled with a memory and comprising an encoder circuit configured to encode a set of information bits based on a low density parity check (LDPC) code to produce a codeword, wherein:

the LDPC code is stored in the memory and defined by a base matrix having a first number plurality of columns corresponding to variable nodes of a base graph and a second number plurality of rows corresponding to check nodes of the base graph, and;

elements in all adjacent rows of a column are orthogonal, for each of the first number plurality of columns, all adjacent rows are orthogonal in a last portion of the second number of at least rows starting from a last row of the base matrix; and

a transmitter configured to transmit the codeword in accordance with a radio technology across a wireless channel via one or more antenna elements arranged proximal the transmitter.

1. An apparatus for wireless communication, comprising:

a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver; and

at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a low density parity check (LDPC) code to produce a set of information bits, wherein:

2. The apparatus of claim 1, wherein entries each element in the base matrix correspond corresponds to an edge between the a variable node and the a check node, of the a base graph, associated with the entry in base matrix.

3. The apparatus of claim 2, wherein entries each non-zero element in the base matrix include corresponds to a cyclic integer lifting values value.

4. The apparatus of claim 2, wherein in each column of the first number plurality of columns, at most one row of each pair of the adjacent orthogonal rows in the last portion of the twenty-one rows has an entry contains a non-zero element.

0. 5. The apparatus of claim 1, wherein the last portion of the rows comprises at least the bottom twenty-one rows of the base matrix.

0. 6. The apparatus of claim 1, wherein the memory is configured to store at least a portion of the LDPC code.

7. The apparatus of claim 1, wherein the at least one processor includes a layered decoder configured to decode the codeword.

8. The apparatus of claim 1, wherein the at least one processor is configured to decode the codeword based on a decoding schedule.

9. The apparatus of claim 8, wherein the decoding schedule includes decoding at least one processor is configured to decode the codeword based on the LDPC code by decoding sequentially row by row in the base matrix or by to simultaneously decoding decode pairs of rows in the base matrix based on the decoding schedule.

10. The apparatus of claim 9, wherein the at least one processor is configured to select from two combinations a combination of two rows from any three sequential rows in the last portion for the simultaneous decoding pairs of the decoding schedule twenty-one rows to simultaneously decode.

11. The apparatus of claim 9, wherein the row by row or pairs of rows is performed at least one processor is further configured to decode sequentially column by column in the base matrix.

12. The apparatus of claim 8, wherein the decoding schedule includes skipping at least one processor is further configured to skip decoding portions elements of the base matrix that do not contain an associated entry a zero.

13. The apparatus of claim 1, wherein the LDPC code comprises a lifted LDPC code.

14. The apparatus of claim 1, wherein:

the codeword comprises a punctured codeword,; and

the at least one processor further comprises a depuncturer configured to depuncture the codeword, and

the decoding comprises decoding the depunctured codeword.

16. The apparatus of claim 15, wherein entries each element in the base matrix correspond corresponds to an edge between the a variable node and the a check node, of the a base graph, associated with the entry in base matrix.

17. The apparatus of claim 16, wherein entries each non-zero element in the base matrix are replaced corresponds to a cyclic integer lifting values value.

18. The apparatus of claim 16, wherein in each column of the first number plurality of columns, at most one row of each pair of the adjacent orthogonal rows in the last portion of the twenty-one rows has an entry contains a non-zero element.

0. 19. The apparatus of claim 15, wherein the last portion of the rows comprises at least the bottom twenty-one rows of the base matrix.

20. The apparatus of claim 15, wherein:

the at least one processor is further configured to lifted the LDPC code by generating generate an integer number of copies of the base matrix; and

the LDPC code comprises a lifted LDPC code to lift the LDPC code.

21. The apparatus of claim 15, wherein:

the at least one processor further comprises a puncturer configured to puncture the codeword, and

the transmitting the codeword comprises transmitting transmitter is configured to transmit the punctured codeword.

23. The method of claim 22, wherein in each column of the first number plurality of columns, at most one row of each pair of the adjacent orthogonal rows in the last portion of the twenty-one rows has an entry a non-zero element.

0. 24. The method of claim 22, wherein the last portion of the rows comprises at least the bottom twenty-one rows of the base matrix.

25. The method of claim 22, wherein: the decoding is based on a decoding schedule; and the decoding schedule the codeword includes decoding the codeword based on the LDPC code by decoding sequentially row by row in the base matrix or by simultaneously decoding pairs of rows in the base matrix based on a decoding schedule.

26. The method of claim 25, further comprising selecting from two combinations of two each pair of the pairs of rows from any three sequential rows in of the last portion for the simultaneous decoding pairs of the decoding schedule twenty-one rows to decode.

28. The method of claim 27, wherein in each column of the first number plurality of columns, at most one row of each pair of the adjacent orthogonal rows in the last portion of the twenty-one rows has an entry contains a non-zero element.

0. 29. The method of claim 27, wherein the last portion of the rows comprises at least the bottom twenty-one rows of the base matrix.

30. The method of claim 27, further comprising puncturing the codeword, wherein transmitting the codeword comprises transmitting the punctured codeword.

0. 31. The apparatus of claim 1, wherein each row of the plurality of rows, except the twenty-one rows, contains a non-zero element in the first column, a non-zero element in the second column, or a non-zero element in both the first column and the second column.

0. 32. The apparatus of claim 1, wherein:

the set of information bits is K information bits, where K is a positive integer;

the base matrix is a base matrix H lifted by a lifting factor Z;

the plurality of columns consists of V columns corresponding to i variable nodes, where V is 68;

the plurality of rows consists of C rows corresponding to j check nodes, where C is 46; and

the elements in the base matrix are represented by a row index i and a column index j.

0. 33. The apparatus of claim 32, wherein an element V_i,jof the base matrix is a non-zero element at least when i=[25], j=[1]; i=[26], j=[0]; i=[27], j=[1]; i=[28], j=[0]; i=[29], j=[1]; i=[30], j=[0]; i=[31], j=[1]; i=[32], j=[0]; i=[33], j=[1]; i=[34], j=[0]; i=[35], j=[1]; i=[36], j=[0]; i=[37], j=[1]; i=[38], j=[0]; i=[39], j=[1]; i=[40], j=[0]; i=[41], j=[1]; i=[42], j=[0]; i=[43], j=[1]; i=[44], j=[0]; i=[45], j=[1].

0. 34. The apparatus of claim 33, wherein an element V_i,jof the base matrix is further a non-zero element at least when j=[0] and i=[24], i=[22], i=[20], i=[19], i=[17], i=[15], i=[14], i=[13], i=[12], i=[11], i=[9], i=[8], i=[7], i=[6], i=[5], i=[4], i=[3], i=[2], i=[1], i=[0]; and when j=[1] and i=[23], i=[21], i=[20], i=[19], i=[18], i=[16], i=[15], i=[12], i=[11], i=[10], i=[9], i=[8], i=[7], i=[5], i=[4], i=[3], i=[2], i=[0].

0. 35. The apparatus of claim 1, wherein:

the receiver is configured to receive the codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver;

the at least one processor is configured to select a combination pairs of rows from any three sequential rows in the twenty-one rows; and

the at least one processor comprises decoder circuitry configured to simultaneously decode each pair of rows.

0. 36. The apparatus of claim 1, wherein the first column having the column index 0 and the second column having the column index 1 have a highest degree among the plurality of columns, where the first column and the second column have a highest number of non-zero entries among the plurality of columns.

0. 37. The apparatus of claim 36, wherein:

the codeword comprises a punctured codeword, where systematic bits corresponding to the first column and the second column are punctured; and

the at least one processor comprises a depuncturer configured to depuncture the systematic bits corresponding to the first column and the second column.

0. 38. The apparatus of claim 15, wherein each row of the plurality of rows, except the twenty-one rows, contains a non-zero element in the first column, a non-zero element in the second column, or a non-zero element in both the first column and the second column.

0. 39. The apparatus of claim 15, wherein:

the set of information bits is K information bits, where K is a positive integer;

the base matrix is a base matrix H lifted by a lifting factor Z;

the plurality of columns consists of V columns corresponding to i variable nodes, where V is 68;

the plurality of rows consists of C rows corresponding to j check nodes, where C is 46; and

the elements in the base matrix are represented by a row index i and a column index j.

0. 40. The apparatus of claim 39, wherein an element V_i,jof the base matrix is a non-zero element at least when i=[25], j=[1]; i=[26], j=[0]; i=[27], j=[1]; i=[28], j=[0]; i=[29], j=[1]; i=[30], j=[0]; i=[31], j=[1]; i=[32], j=[0]; i=[33], j=[1]; i=[34], j=[0]; i=[35], j=[1]; i=[36], j=[0]; i=[37], j=[1]; i=[38], j=[0]; i=[39], j=[1]; i=[40], j=[0]; i=[41], j=[1]; i=[42], j=[0]; i=[43], j=[1]; i=[44], j=[0]; i=[45], j=[1].

0. 41. The apparatus of claim 40, wherein an element V_i,jof the base matrix is further a non-zero element at least when j=[0] and i=[24], i=[22], i=[20], i=[19], i=[17], i=[15], i=[14], i=[13], i=[12], i=[11], i=[9], i=[8], i=[7], i=[6], i=[5], i=[4], i=[3], i=[2], i=[1], i=[0]; and when j=[1] and i=[23], i=[21], i=[20], i=[19], i=[18], i=[16], i=[15], i=[12], i=[11], i=[10], i=[9], i=[8], i=[7], i=[5], i=[4], i=[3], i=[2], i=[0].

0. 42. The apparatus of claim 15, wherein:

the transmitter is configured to transmit the codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the transmitter;

the at least one processor is configured to select a combination pairs of rows from any three sequential rows in the twenty-one rows; and

the at least one processor comprises encoder circuitry configured to simultaneously encode each pair of rows.

0. 43. The apparatus of claim 15, wherein the first column having the column index 0 and the second column having the column index 1 have a highest degree among the plurality of columns, where the first column and the second column have a highest number of non-zero entries among the plurality of columns.

0. 44. The apparatus of claim 43, wherein the at least one processor comprises a puncturer configured to puncture systematic bits in the codeword corresponding to the first column and the second column.

0. 45. The apparatus of claim 1, wherein the receiver is configured to receive the codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver.

0. 46. The apparatus of claim 15, wherein the transmitter is configured to transmit the codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the transmitter.

CROSS-REFERENCE TO RELATED APPLICATION & PRIORITY CLAIM

Shortening can be applied before the LDPC encoding. Systematic bits may be punctured.

Aspects of the present disclosure provide LDPC encoders using LDPC codes having pairwise orthogonality of adjacent rows in the PCM describing the code and LDPC decoders that can exploit the LDPC coding with the pairwise row orthogonality to perform flexible decoder scheduling without performance loss.

In NR, the PCM for some basegraphs used for LDPC coding have the PCM structure 1100 shown in FIG. 11. The PCM structure 1100 includes an upper portion with the region 1102 corresponding to systems bits; the region 1104 corresponding to parity bits; and the region 1106 corresponding to hybrid automatic repeat request (HARQ) extension bits (e.g., all zeros). The regions 1102 and 1106 may have a horizontally rectangular shape. In some examples, the first two, highest degree, systematic bits in the region 1102 may be punctured (e.g., the first two columns in the PCM). The region 1104 has a square shape. The region 1104 may include a special parity bit. The first or last column in the region 1104 may have a weight of 1, while the remaining columns may have a weight of 3 and dual diagonal.

The PCM structure 1100 also includes a lower portion with the region 1108 and the region 1110. In some examples, the lower portion of the PCM structure 1100 may be used for puncturing and/or incremental redundancy (IR) HARQ. The region 1110 may be a diagonal matrix (i.e., a diagonal of entries with the rest not having entries, i.e., zero). The lower diagonal structure may ensure that puncturing of the mother code does not require decoding of the mother code, thereby reducing complexity. The diagonal structure may render the code amenable to node-parallel decoding architectures. The columns of region 1110 may correspond to HARQ bits and the region 1108. According to certain aspects, the region 1108 (and also maybe a portion of the region 1110) in the lower power portion of the PCM structure 1100 may have pairwise row orthogonality in each adjacent row.

FIG. 12 an example PCM 1200 for an LDPC code, illustrating the PCM structure 1100 of FIG. 11, in accordance with certain aspects of the present disclosure. In the PCM 1200 shown in FIG. 12, a “1” represents an entry in the PCM (which may be replaced with a cyclic lifting value V_i,j) and a “0” represents absence of an entry. As shown in FIG. 12, the PCM 1200 includes a bottom portion with pairwise row orthogonality in adjacent rows. As shown, in the rows 26-46, in the columns (e.g., columns 1-22) before the bottom diagonal structure (e.g., corresponding to the region 1108 before the region 1110) and, in some cases, a first portion of the region 1110 (e.g., columns 23-27), in any given column there are not entries in adjacent (i.e., consecutive) rows. In other words, adjacent rows in the lower portion of the columns can both have no entries (i.e., shown as 0's) or only one has an entry (i.e., a 1,0 or 0,1), such that there entries are not in any pair of adjacent rows (i.e., 1,1 does not occur).

Although FIG. 12 illustrates an example PCM with the pairwise row orthogonality in the rows 26-46, the different numbers of rows could be non-orthogonal. In some examples, in the first portion of the rows of the lower structure (i.e., region 1108), the first two columns include some non-orthogonality of the rows, while in the remaining columns in the first portion are non-orthogonal. However, in the second portion of the rows in the lower structure, adjacent rows in all of the columns are orthogonal. For example, as shown in FIG. 12, in the rows 6-25 in a PCM (e.g., a first portion of the lower structure), adjacent rows in the first two columns (i.e., columns 102) are not always orthogonal, however, the adjacent rows in the remaining columns (i.e., columns 3-27) are pairwise orthogonal. As shown in FIG. 12, in the bottom portion of the lower structure, rows 26-46, all of the columns in the region (e.g., columns 1-27) have pairwise row orthogonality.

According to certain aspects, at least a portion of the description of the basegraph may be stored on chip, for example, at the BS and/or the UE. The description may be basegraph, the PCM, or some other representation of the sparse matrix.

To recover the information bits, the receiving decodes the codeword received from the transmitting device. The receiving device may decode according to decoding schedule. The receiving device may decode the codeword using a layered decoder. The decoding schedule may be based, at least in part, on the stored description of the basegraph. The decoding schedule may decode the codeword row by row (e.g., using the basegraph). The decoding schedule may decode the codeword column by column. The decoding schedule may decode the two columns at a time (e.g., within a row or pair of rows). The decoding schedule may skip absent entries for decoding.

In some examples, the receiving device may use a new decoder with improved performance. The decoder may exploit the pairwise orthogonality of the LDPC described herein to increase decoding speed, for example, by decoding the codeword by pairs of rows at a time, without performance loss. In addition, the decoder may have increased decoding scheduling flexibility, due to the pairwise row orthogonality, because for any set of three consecutive rows in the lower portion of the code, the decoder can select between two different orthogonal combinations for simultaneous decoding.

FIG. 13 illustrates a communications device 1300 that may include various components (e.g., corresponding to means-plus-function components) configured to perform operations for the techniques disclosed herein, such as the operations illustrated in FIG. 14 and/or FIG. 15. The communications device 1300 includes a processing system 1302 coupled to a transceiver 1308. The transceiver 1308 is configured to transmit and receive signals for the communications device 1300 via an antenna 1310, such as the various signals as described herein. The processing system 1302 may be configured to perform processing functions for the communications device 1300, including processing signals received and/or to be transmitted by the communications device 1300.

The processing system 1302 includes a processor 1304 coupled to a computer-readable medium/memory 1312 via a bus 1306. In certain aspects. the computer-readable medium/memory 1312 is configured to store instructions (e.g., computer executable code) that when executed by the processor 1304, cause the processor 1304 to perform the operations illustrated in FIG. 14 and/or FIG. 15, or other operations for performing the various techniques discussed herein for LDPC coding with pairwise row orthogonality. In certain aspects, computer-readable medium/memory 1512 stores code 1314 for encoding information bits using LDPC code with pairwise row orthogonality; code 1316 for transmitting the codeword over a wireless channel; code 1318 for receiving a codeword; and code 1320 for decoding the codeword using LDPC code with pairwise row orthogonality to obtain information bits.

FIG. 14 is a flow diagram illustrating example operations 1400 for wireless communications by a receiving device using LDPC coding, in accordance with certain aspects of the present disclosure. The receiving device may be a BS (e.g., such as a BS 110 in the wireless communication network 100) on the uplink or a UE (e.g., such as a UE 120 in the wireless communication network 100) on the downlink.

The operations 1400 begin, at 1402. by receiving a codeword (e.g., or punctured codeword) in accordance with a radio technology (e.g., NR or 5G radio technology) across a wireless channel via one or more antenna elements situated proximal a receiver. At 1404, the receiving device decodes (e.g., with a layered decoder) the codeword (e.g., and depunctures if the codeword is punctured) via decoder circuitry based on a LDPC code to produce a set of information bits. The LDPC code (e.g., or a lifted LDPC code) is stored and defined by a base matrix having a first number of columns corresponding to variable nodes of a base graph and a second number of rows corresponding to check nodes of the base graph. For each of the first number of columns, all adjacent rows are orthogonal in a last portion (e.g., the bottom 21 rows) of the second number of rows. For example, in each of the first number of columns, at most one row of each pair of the adjacent orthogonal rows in the last portion of the rows has an entry. The decoding may be based on a decoding schedule. The decoding schedule may include decoding sequentially row by row in the base matrix or by simultaneously decoding pairs of rows (e.g., an column by column) in the base matrix. The receiving device may select from two combinations of two rows from any three sequential rows in the last portion for the simultaneous decoding pairs of the decoding schedule. The decoding schedule skips for decoding portions of the base matrix that do not contain an associated entry.

FIG. 15 is a flow diagram illustrating example operations 1500 for wireless communications by a transmitting device using LDPC coding, in accordance with certain aspects of the present disclosure. The transmitting device may be a UE (e.g., such as a UE 120 in the wireless communication network 100) on the uplink or a BS (e.g., such as a BS 121 in the wireless communication network 100) on the downlink. The operations 1500 may be complementary to the operations 1400 by the receiving device.

The operations 1500 begin, at 1502. by encoding a set of information bits with encoder circuitry based on a LDPC code to produce a codeword. The LDPC code is defined by a base matrix having a first number of columns corresponding to variable nodes of a base graph and a second number of rows corresponding to check nodes of the base graph. For each of the first number of columns, all adjacent rows are orthogonal in a last portion of the second number of rows. At 1504, the transmitting device transmits the codeword in accordance with a radio technology across a wireless channel via one or more antenna elements.

The methods disclosed herein comprise one or more steps or actions for achieving the methods. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”

The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

If implemented in hardware, an example hardware configuration may comprise a processing system in a wireless node. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the PHY layer. In the case of a user terminal 120 (see FIG. 1), a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer readable medium. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The processor may be responsible for managing the bus and general processing, including the execution of software modules stored on the machine-readable storage media. A computer-readable storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer readable storage medium with instructions stored thereon separate from the wireless node, all of which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Examples of machine-readable storage media may include, by way of example, RAM (Random Access Memory), flash memory, ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product.

A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. The computer-readable media may comprise a number of software modules. The software modules include instructions that, when executed by an apparatus such as a processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.

Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For example, instructions for performing the operations described herein and illustrated in FIG. 14 and FIG. 15.

Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

INVENTORS:

Soriaga, Joseph Binamira, Sarkis, Gabi, Kudekar, Shrinivas, Richardson, Thomas Joseph

THIS PATENT IS REFERENCED BY THESE PATENTS:

Patent

Priority

Assignee

Title

THIS PATENT REFERENCES THESE PATENTS:

Patent	Priority	Assignee	Title
10051333,	Aug 01 2013	LG Electronics Inc	Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
10075266,	Oct 09 2013	Qualcomm Incorporated	Data transmission scheme with unequal code block sizes
10177787,	Sep 17 2015	Seagate Technology LLC	Mitigation of error correction failure due to trapping sets
10291354,	Jun 14 2016	Qualcomm Incorporated	High performance, flexible, and compact low-density parity-check (LDPC) code
10291359,	Jul 27 2016	Qualcomm Incorporated	Of hybrid automatic repeat request (HARQ) feedback bits for polar codes
10312939,	Jun 10 2017	Qualcomm Incorporated	Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code
10313057,	Jun 01 2016	Qualcomm Incorporated	Error detection in wireless communications using sectional redundancy check information
10340949,	Feb 06 2017	Qualcomm Incorporated	Multiple low density parity check (LDPC) base graph design
10348451,	Jun 01 2016	Qualcomm Incorporated	Enhanced polar code constructions by strategic placement of CRC bits
10355822,	Jul 07 2017	Qualcomm Incorporated	Communication techniques applying low-density parity-check code base graph selection
10454499,	May 12 2016	Qualcomm Incorporated	Enhanced puncturing and low-density parity-check (LDPC) code structure
10469104,	Jun 14 2016	Qualcomm Incorporated	Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
10560118,	Feb 06 2017	Qualcomm Incorporated	Multiple low density parity check (LDPC) base graph design
10644836,	Jun 01 2016	Qualcomm Incorporated	Enhanced polar code constructions by strategic placement of CRC bits
10659079,	May 05 2017	MEDIATEK INC.	QC-LDPC codes
10735138,	May 02 2017	FUTUREWEI TECHNOLOGIES, INC	Multi-label offset lifting method
10784901,	Nov 12 2015	Qualcomm Incorporated	Puncturing for structured low density parity check (LDPC) codes
11025276,	May 12 2016	Qualcomm Incorporated	Enhanced puncturing and low-density parity-check (LDPC) code structure
11031953,	Jun 14 2016	Qualcomm Incorporated	High performance, flexible, and compact low-density parity-check (LDPC) code
11032026,	Jun 14 2016	Qualcomm Incorporated	High performance, flexible, and compact low-density parity-check (LDPC) code
11277151,	Feb 06 2017	Qualcomm Incorporated	Multiple low density parity check (LDPC) base graph design
5583500,	Feb 10 1993	RICOH COMPANY, LTD A CORP OF JAPAN; RICOH CORPORATION A CORP OF DELAWARE	Method and apparatus for parallel encoding and decoding of data
5844918,	Nov 28 1995	SANYO ELECTRIC CO , LTD	Digital transmission/receiving method, digital communications method, and data receiving apparatus
6438724,	Mar 16 1999	GLOBALFOUNDRIES Inc	Method and apparatus for deterministically altering cyclic redundancy check information for data storage
6633865,	Dec 23 1999	PMC-Sierra Limited	Multithreaded address resolution system
6674768,	Oct 09 1998	NEC Corporation	Data transmission device and data transmission method capable of minimizing delay of fast data
6854082,	Nov 27 2001	AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED	Unequal error protection Reed-Muller code generator and decoder
6931581,	Oct 25 2000	Oracle America, Inc	Method for superimposing a sequence number in an error detection code in a data network
6961388,	Feb 01 2001	Qualcomm Incorporated	Coding scheme for a wireless communication system
6961888,	Aug 20 2002	Qualcomm Incorporated	Methods and apparatus for encoding LDPC codes
7133853,	Jun 15 2001	Qualcomm Incorporated	Methods and apparatus for decoding LDPC codes
7222284,	Jun 26 2003	Nokia Corporation	Low-density parity-check codes for multiple code rates
7231557,	Apr 02 2003	Qualcomm Incorporated	Methods and apparatus for interleaving in a block-coherent communication system
7237171,	Feb 26 2003	Qualcomm Incorporated	Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
7237181,	Dec 22 2003	Qualcomm Incorporated	Methods and apparatus for reducing error floors in message passing decoders
7493551,	Sep 22 2004	STMICROELECTRONICS INTERNATIONAL N V	Method and device for delivering punctured code words encoded with a LDPC code
7526717,	Jun 16 2004	Postech Academy Industry Foundation	Apparatus and method for coding and decoding semi-systematic block low density parity check codes
7552097,	Jun 15 2001	Qualcomm Incorporated	Methods and apparatus for decoding LDPC codes
7571372,	Jun 23 2005	CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD	Methods and algorithms for joint channel-code decoding of linear block codes
7581159,	Nov 23 2004	Texas Instruments Incorporated	Simplified decoding using structured and punctured LDPC codes
7627801,	Aug 20 2002	Qualcomm Incorporated	Methods and apparatus for encoding LDPC codes
7685495,	May 12 2005	Qualcomm Incorporated	Apparatus and method for channel interleaving in communications system
7747934,	Oct 12 2004	Malikie Innovations Limited	Method for selecting low density parity check (LDPC) code used for encoding of variable length data
7793194,	Sep 08 2007	LG Electronics Inc	Signal segmentation method and CRC attachment method for reducing undetected error
7840880,	Sep 25 2006	Altera Corporation	Methods and apparatus for error checking code computation
7979784,	Mar 29 2006	Samsung Electronics Co., Ltd.	Method and system for enhancing transmission reliability of video information over wireless channels
7986622,	Oct 24 2006	AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED	Method and system for physical layer aggregation
8006162,	May 16 2005	SAMSUNG ELECTRONICS CO , LTD	Method for padding and puncturing low density parity check code
8117516,	Nov 06 2006	Samsung Electronics Co., Ltd; Industry-Academic Cooperation Foundation, Yonsei University; SAMSUNG ELECTRONICS CO , LTD	Apparatus and method for signal transmission/reception in a communication system
8132072,	Jan 06 2006	Qualcomm Incorporated	System and method for providing H-ARQ rate compatible codes for high throughput applications
8151157,	Jun 07 2006	LG Electronics Inc	Method of encoding/decoding using low density check code matrix
8261155,	Mar 09 2007	Qualcomm Incorporated	Methods and apparatus for encoding and decoding low density parity check (LDPC) codes
8271846,	Feb 26 2008	Samsung Electronics Co., Ltd; Postech Academy Industry Foundation; SAMSUNG ELECTRONICS CO , LTD	Method and apparatus for channel encoding and decoding in a communication system using low-density parity-check codes
8356227,	Jun 16 2006	LG Electronics Inc	Method of encoding/decoding using low density check code matrix
8392789,	Jul 28 2009	Texas Instruments Incorporated	Method and system for decoding low density parity check codes
8418015,	Jun 08 2007	DATANG MOBILE COMMUNICATIONS EQUIPMENT CO , LTD	Method, apparatus and system for coding and decoding of LDPC codes
8453030,	Oct 26 2006	Qualcomm Incorporated	Coding schemes for wireless communication transmissions
8473821,	Nov 09 2010	Qualcomm, Incorporated	Packet-level erasure protection coding in aggregated packet transmissions
8484545,	Apr 23 2009	Electronic and Telecommunications Research Institute; Georgia Tech Research Corporation	Secure communication using error correction codes
8495450,	Aug 24 2009	Samsung Electronics Co., Ltd.; SAMSUNG ELECTRONICS CO , LTD	System and method for structured LDPC code family with fixed code length and no puncturing
8495459,	Nov 24 2008	Samsung Electronics Co., Ltd	Channel-encoding/decoding apparatus and method using low-density parity-check codes
8516334,	Jun 12 2007	ZTE Corporation	Channel coding, modulating and mapping method for hybrid automatic repeat request of low density parity check code
8578249,	Jan 24 2007	Qualcomm Incorporated	LDPC encoding and decoding of packets of variable sizes
8601345,	May 12 2010	Tellabs Operations, Inc.	Method and apparatus for searching frame alignment with false alignment protection
8601352,	Jul 30 2009	Apple Inc	Efficient LDPC codes
8650457,	Sep 03 2010	Marvell International Ltd.	Methods and systems for reconfigurable LDPC decoders
8687751,	Apr 02 2010	CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD	Multiple-input multiple-output receivers using successive interference cancellation based on cyclic redundancy check
8751902,	Aug 20 2002	Qualcomm Incorporated	Methods and apparatus for encoding LDPC codes
8892979,	Oct 26 2006	Qualcomm Incorporated	Coding schemes for wireless communication transmissions
9214960,	Jan 18 2011	Samsung Electronics Co., Ltd	Apparatus and method for transmitting and receiving data in communication/broadcasting system
9325347,	Feb 21 2014	IP GEM GROUP, LLC	Forward error correction decoder and method therefor
9362956,	Jan 23 2013	SAMSUNG ELECTRONICS CO , LTD	Method and system for encoding and decoding data using concatenated polar codes
9479375,	Apr 02 2015	University of South Florida	Joint physical layer security and PAPR mitigation in OFDM systems
9602133,	Jan 27 2015	IP GEM GROUP, LLC	System and method for boost floor mitigation
9667381,	Dec 14 2012	Samsung Electronics Co., Ltd.; Sungkyunkwan University Research & Business Foundation	Packet decoding method and apparatus
9692451,	Sep 30 2014	AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED	Non-binary low density parity check (NB-LDPC) codes for communication systems
9742439,	Jun 08 2015	MICROSEMI SOLUTIONS U S , INC	Method and device for forward error correction decoder system utilizing orthogonality of an H matrix
9774893,	Aug 01 2013	LG Electronics Inc	Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
9917675,	Jun 01 2016	Qualcomm Incorporated	Enhanced polar code constructions by strategic placement of CRC bits
20020147954,
20030033575,
20030053435,
20030123409,
20030172342,
20040098659,
20040187129,
20040262376,
20050050435,
20050078765,
20050149842,
20050246617,
20050283707,
20050283708,
20060020868,
20060020872,
20060026486,
20060036925,
20060156199,
20060184855,
20060274687,
20060294445,
20070011567,
20070011568,
20070022362,
20070089025,
20070101243,
20070113147,
20070113148,
20070136636,
20070162815,
20080059862,
20080062975,
20080109708,
20080126916,
20080178065,
20080204286,
20080207120,
20080298334,
20080317152,
20080320353,
20090077456,
20090113256,
20090113276,
20090125735,
20090158129,
20090204868,
20090217129,
20090259915,
20090300461,
20100023834,
20100077275,
20100107033,
20100153812,
20100153819,
20100185926,
20100199153,
20100211844,
20100257425,
20100275089,
20100287438,
20100325511,
20110047433,
20110066916,
20110096862,
20110126072,
20110161772,
20110202820,
20110239075,
20120084625,
20120166917,
20120240001,
20120317461,
20130031438,
20130051556,
20130086445,
20130117344,
20130272378,
20140003533,
20140019820,
20140040214,
20140068375,
20140101116,
20140169388,
20140173376,
20140201592,
20140223254,
20140229788,
20140229789,
20140304574,
20140365842,
20140365844,
20140365845,
20150120798,
20150178149,
20150188666,
20150229337,
20150249473,
20150293716,
20150334700,
20150381208,
20160012465,
20160013810,
20160013931,
20160020783,
20160043745,
20160087648,
20160164537,
20160164629,
20160173132,
20160183187,
20160197701,
20160218750,
20160309482,
20160337083,
20160380763,
20170031599,
20170047947,
20170063493,
20170075754,
20170141798,
20170187489,
20170222663,
20170230149,
20170331494,
20170331497,
20170353267,
20170353269,
20170353271,
20170359086,
20170359148,
20180007712,
20180034593,
20180152205,
20180205498,
20180226992,
20180358984,
20180367245,
20180367253,
20190013900,
20190052400,
20190068318,
20190199475,
20190245654,
20190260507,
20190280817,
20190356337,
20190394000,
20200028523,
20200044665,
20200052817,
20200059317,
20200067641,
20200162109,
20200235759,
20200235854,
20200322085,
20200404069,
20200412387,
20210058192,
20210281359,
20220224356,
20230275599,
20230327683,
CN101005301,
CN101019328,
CN101047387,
CN101076946,
CN101141133,
CN101188428,
CN101217337,
CN101601187,
CN101645763,
CN101682381,
CN101826878,
CN102017426,
CN102340378,
CN102437858,
CN102474386,
CN102571105,
CN102651652,
CN102783206,
CN103152056,
CN103188044,
CN103281166,
CN103441816,
CN103636130,
CN103716130,
CN103746708,
CN103780329,
CN103905152,
CN104202126,
CN105227189,
CN105284053,
CN105306165,
CN105337696,
CN106341138,
CN107733442,
CN109150191,
CN1399829,
CN1780199,
CN1868145,
CN1953335,
CN1960188,
EP1601109,
EP1724932,
EP2091171,
EP2096760,
EP2518923,
EP2899912,
EP3046259,
EP3264611,
EP3622627,
IN104981978,
JP2007507156,
JP2009081577,
JP2010508728,
JP2010517444,
JP2010537460,
JP2011512106,
JP2011514049,
JP2012142968,
JP2016507200,
JP2016518035,
JP2016539534,
JP7288479,
KR100833515,
KR101157246,
KR101524869,
KR101598754,
KR20090092197,
KR20090130176,
KR20110106438,
KR20150034561,
KR20150118992,
KR20170053589,
NO2015054268,
RU2426241,
RU2520405,
RU2520406,
RU2718171,
SG11201905916,
TW200711359,
TW201334425,
TW272777,
TW427076,
WO2002062002,
WO2006124428,
WO2008052202,
WO2008092040,
WO2008112625,
WO2009005264,
WO2009011134,
WO2009107990,
WO2012064869,
WO2014117836,
WO2014127129,
WO2014127140,
WO2015139297,
WO2017091244,
WO2017092693,
WO2017197267,
WO2017209837,
WO2018029633,
WO2018030927,
WO2018050062,
WO2018128560,
WO2018144251,
WO2018144560,

ASSIGNMENT RECORDS Assignment records on the USPTO

/////

Executed on	Assignor	Assignee	Conveyance	Frame	Reel	Doc
Feb 12 2019	SARKIS, GABI	Qualcomm Incorporated	ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS	057012	0470	pdf
Feb 13 2019	SORIAGA, JOSEPH BINAMIRA	Qualcomm Incorporated	ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS	057012	0470	pdf
Mar 06 2019	KUDEKAR, SHRINIVAS	Qualcomm Incorporated	ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS	057012	0470	pdf
Mar 19 2019	RICHARDSON, THOMAS	Qualcomm Incorporated	ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS	057012	0470	pdf
May 28 2021		Qualcomm Incorporated	(assignment on the face of the patent)

MAINTENANCE FEES AND DATES: Maintenance records on the USPTO

Date	Maintenance Fee Events
May 28 2021	BIG: Entity status set to Undiscounted (note the period is included in the code).

Date	Maintenance Schedule
May 28 2027	4 years fee payment window open
Nov 28 2027	6 months grace period start (w surcharge)
May 28 2028	patent expiry (for year 4)
May 28 2030	2 years to revive unintentionally abandoned end. (for year 4)
May 28 2031	8 years fee payment window open
Nov 28 2031	6 months grace period start (w surcharge)
May 28 2032	patent expiry (for year 8)
May 28 2034	2 years to revive unintentionally abandoned end. (for year 8)
May 28 2035	12 years fee payment window open
Nov 28 2035	6 months grace period start (w surcharge)
May 28 2036	patent expiry (for year 12)
May 28 2038	2 years to revive unintentionally abandoned end. (for year 12)