Pixel and display device including the same

Abstract

A pixel, wherein: gates of second and fifth transistors receive a first gate signal; gates of third and fourth transistors respectively receive second and third gate signals; first terminals (FTs) of the second to fifth transistors respectively receive a data voltage, reference voltage, initialization voltage, and first power supply voltage (PSV); a second electrode of a second capacitor receives the first PSV; a second terminal (ST) of a light emitting element (LEE) receives a second PSV; a gate of a first transistor, STs of the second and third transistors, and a first electrode of a first capacitor are connected to a first node; STs of the first and fourth transistors, a FT of the LEE, and second and first electrodes respectively of the first and second capacitors are connected to a second node; and a ST of the fifth transistor is connected to a FT of the first transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application The first transistor may be a double gate transistor.

Here, VN2 represents the voltage of the second node N2, VR represents the reference voltage, and Vth represents the threshold voltage of the first transistor T1.

As illustrated in FIGS. 3 and 4C, in the third period P3, the data voltage DATA may be applied to a gate of the driving transistor (i.e., the first transistor T1) (or a data writing operation may be performed). For example, during the third period P3, the first gate signal G1 may have the first logic level, and the second gate signal G2 and the third gate signal G3 may have the second logic level. The second transistor T2 may be turned on, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 may be turned off. Thus, during the third period P3, the voltage of the first node N1 may be set as the data voltage DATA via the turned-on second transistor T2, and the voltage of the second node N2 may be changed according to a change of the voltage of the first node N1 based on a capacitance of first and second capacitors C1 and C2 connected in series. For example, the voltage of the second node N2 may be changed to a voltage according to Equation 2.

$\begin{array}{cc}\mathrm{VN2}=\mathrm{VR}-\mathrm{Vth}+\frac{C1}{C1+C2}\left(\mathrm{Vdata}-\mathrm{VR}\right)& \mathrm{Equation}2\end{array}$

Here, VN2 represents the voltage of the second node N2, VR represents the reference voltage, Vth represents the threshold voltage of the first transistor T1, C1 represent a capacitance of the first capacitor, C2 represents a capacitance of the second capacitor, and Vdata represents the data voltage.

As illustrated in FIGS. 3 and 4D, in the fourth period P4, a light emitting diode OLED may emit light based on a driving current corresponding to the data voltage DATA. For example, during the fourth period P4, the first gate signal G1, the second gate signal G2 and the third gate signal G3 may have the second logic level. The fifth transistor T5 may be turned on, and the second transistor T2, the third transistor T3 and the fourth transistor T4 may be turned off. Thus, in the fourth period T4, the driving current may be generated based on a voltage difference between a gate and a source of the first transistor T1, and the light emitting diode OLED may emit light based on the driving current. For example, the driving current provided to the light emitting diode OLED may be calculated according to Equation 3

$\begin{array}{cc}\mathrm{ld}={\left(\frac{k}{2}\right)\left[\frac{C2}{C1+C2}\left(\mathrm{Vdata}-\mathrm{VR}\right)\right]}^2& \mathrm{Equation}3\end{array}$

Here, k represents a constant according to a characteristic of the first transistor T1, C1 represents the capacitance of the first capacitor, C2 represents the capacitance of the second capacitor, Vdata represents the data voltage, and VR represents the reference voltage.

FIGS. 5A and 5B are timing diagrams for describing exemplary operation of the display device of FIG. 1 according to some exemplary embodiments.

Referring to FIGS. 5A and 5B, a pixel may receive a data voltage DATA through a data line, and may receive a reference voltage VR through a reference voltage line, and thus, a display device may set a length of a threshold voltage sensing period for each pixel row to be longer than 1H.

In some exemplary embodiments, as illustrated in FIG. 5A, the display device may adjust a length of an on-period of a second gate signal G2(i) and G2(i+1) applied to the pixel and timings of gate signals G1(i), G2(i), G3(i), G1(i+1), G2(i+1) and G3(i+1) such that a length of a second period P2 in which a threshold voltage of a driving transistor is sensed may be set to 3H.

A third gate signal G3(i) applied to an i-th pixel row may have a first logic level for 1H from a first time point T1. A second gate signal G2(i) applied to the i-th pixel row may have the first logic level for 4H from the first time point T1. A first gate signal G1(i) applied to the i-th pixel row may have the first logic level for 1H from a fifth time point T5.

Gate signals G1(i+1), G2(i+1) and G3(i+1) applied to an (i+1)-th pixel row may be delayed by 1H from the gate signals G1(i), G2(i) and G3(i) applied to the i-th pixel row. For example, the third gate signal G3(i+1) applied to the (i+1)-th pixel row may have the first logic level for 1H from a second time point T2. The second gate signal G2(i+1) applied to the (i+1)-th pixel row may have the first logic level for 4H from the second time point T2. The first gate signal G1(i+1) applied to the (i+1)-th pixel row may have the first logic level for 1H from a sixth time point T6. As such, respective pixels may sequentially perform an initialization operation for 1H, a threshold voltage compensation operation for 3H, and a data writing operation for 1H.

In some exemplary embodiments, the first logic level of the gate signals G1(i), G2(i), G3(i), G1(i+1), G2(i+1), and G3(i+1) may be about 10V, and a second logic level of the gate signals G1(i), G2(i), G3(i), G1(i+1), G2(i+1), and G3(i+1) may be about 0V. A transistor to which a relatively low voltage is applied may be implemented with an n-channel MOS transistor, and a transistor to which a relatively high voltage is applied may be implemented with a p-channel MOS transistor. Thus, the first and second logic levels of the gate signals G1(i), G2(i), G3(i), G1(i+1), G2(i+1), and G3(i+1) may be relatively low voltage levels compared with gate signal of a conventional display device. For example, second through fourth transistors to which relatively low reference voltage (e.g., about 1.5V), initialization voltage (e.g., about 0V), and data voltage (e.g., from about 0V to about 5V) are applied may be implemented with n-channel MOS transistors, and a fifth transistor to which a relatively high first power supply voltage (e.g., about 10V) is applied may be implemented with a p-channel MOS transistor. Accordingly, a gate driver may generate the gate signals G1(i), G2(i), G3(i), G1(i+1), G2(i+1), and G3(i+1) without an additional voltage boosting circuit, and deterioration of the transistors in the pixel PXA may be reduced.

In other exemplary embodiments, as illustrated in FIG. 5B, the display device may adjust the length of the on-period of the second gate signal G2(i) and G2(i+1) applied to the pixel and timings of the gate signals G1(i), G2(i), G3(i), G1(i+1), G2(i+1), and G3(i+1) such that the length of the second period P2 in which the threshold voltage of the driving transistor is sensed may be set to 5H. The third gate signal G3(i) applied to the i-th pixel row may have the first logic level for 1H from the first time point T1. The second gate signal G2(i) applied to the i-th pixel row may have the first logic level for 6H from the first time point T1. The first gate signal G1(i) applied to the i-th pixel row may have the first logic level for 1H from a seventh time point T7. The gate signals G1(i+1), G2(i+1) and G3(i+1) applied to the (i+1)-th pixel row may be delayed by 1H from the gate signals G1(i), G2(i) and G3(i) applied to the i-th pixel row. Accordingly, respective pixels may sequentially perform the initialization operation for 1H, the threshold voltage compensation operation for 5H and the data writing operation for 1H.

Lengths of the first period P1 and the second period P2 may not be limited to examples illustrated in FIGS. 5A and 5B. The lengths of the first period P1 and the second period P2 may be set in various ranges where the initialization operation and the threshold voltage compensation operation are normally performed. Further, although FIGS. 5A and 5B illustrate examples where the first logic level is about 10V and the second logic level is about 0V, the first and second logic levels may not be limited thereto. For example, the first logic levels and/or the second logic levels of the first through third gate signals may be different from each other.

FIG. 6 is a circuit diagram illustrating a pixel included in a display device according to some exemplary embodiments. FIG. 7 is a cross-sectional diagram illustrating a driving transistor included in the pixel of FIG. 6 according to some exemplary embodiments. FIG. 8 is a graph for describing a characteristic of the driving transistor of FIG. 7 according to some exemplary embodiments. It is noted that the pixel PXB of FIG. 6 may be included in the display device 1000A of FIG. 1.

Referring to FIGS. 6 through 8, the pixel PXB may include a first transistor T1′, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, a second capacitor C2, and a light emitting element OLED. The pixel PXB may be substantially the same as the pixel PXA of FIG. 2, except that the first transistor T1′ may be a double gate transistor. The same or similar reference numerals may be used to indicate the same or similar elements, and duplicated descriptions are primarily omitted.

The first transistor T1′ may be a driving transistor. The first transistor T1′ may be connected between a first power supply voltage ELVDD and a second node N2, and may provide a driving current corresponding to a data voltage DATA to the light emitting element OLED. For example, the first transistor T1′ may include a first gate connected to a first node N1, a second gate connected to the second node N2, a first terminal connected to a second terminal of the fifth transistor T5, and a second terminal connected to the second node N2.

In some exemplary embodiments, as illustrated in FIG. 7, the first transistor T1′ may be a double gate transistor including a lower gate layer under an active layer. For example, the first transistor T1′ may include a substrate 110, a lower gate layer 112 on the substrate 110, a first gate insulation layer 115 on the lower gate layer 112, an active layer 120 on the first gate insulation layer 115, a second gate insulation layer 125 on the active layer 120, an upper gate pattern 130 on the second gate insulation layer 125, and an interlayer insulation layer 135 on the upper gate pattern 130.

The substrate 110 may include an insulation material. For example, the substrate 110 may include, but is not limited to, a glass substrate, a transparent plastic substrate, a transparent metal oxide substrate, etc. In some exemplary embodiments, at least one buffer layer may be provided on the substrate 110. For example the buffer layer may include, but not limited to, a silicon oxide, a silicon nitride, a silicon oxy-nitride, etc.

The lower gate layer 112 may be disposed on the substrate 110. The lower gate layer 112 may include, but not limited to, a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. In some exemplary embodiments, the lower gate layer 112 may be the second gate of the first transistor T1′, and may be electrically connected to the second node N2.

The first gate insulation layer 115 may cover the lower gate layer 112, and may be disposed on the substrate 110. In some exemplary embodiments, the first gate insulation layer 115 may have a substantially flat upper surface while covering cover the lower gate layer 112. The first gate insulation layer 115 may include, but not limited to, a silicon compound, a metal oxide, etc.

The active layer 120 may be disposed on the first gate insulation layer 115. The active layer 120 may include silicon. The active layer 120 may include impurity-doped regions 121 and 123. The impurity-doped regions 121 and 123 may correspond to the first terminal (e.g., a drain) and the second terminal (e.g., a source) of the first transistor T1′, and may have an electrical conductivity higher than that of the remaining region 122.

The second gate insulation layer 125 may cover the active layer 120, and may be disposed on the first gate insulation layer 115. In some exemplary embodiments, the second gate insulation layer 125 may be disposed with a substantially uniform thickness according to a profile of the active layer 120 while covering cover the active layer 120. In other exemplary embodiments, the second gate insulation layer 125 may have a substantially flat upper surface while covering cover the active layer 120.

The upper gate pattern 130 may be disposed on the second gate insulation layer 125. The upper gate pattern 130 may include, but not limited to, a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. In some exemplary embodiments, the upper gate pattern 130 may be the first gate of the first transistor T1′, and may be electrically connected to the first node N1.

The interlayer insulation layer 135 may cover the upper gate pattern 130, and may be disposed on the second gate insulation layer 125. In some exemplary embodiments, the interlayer insulation layer 135 may have a substantially flat upper surface while covering cover the upper gate pattern 130. The interlayer insulation layer 135 may be formed of an organic material, such as a silicon compound, or an inorganic material, such as a transparent insulation resin. For example, the interlayer insulation layer 135 may include, but not limited to, a silicon oxide, a silicon nitride, a silicon oxy-nitride, etc.

As illustrated in FIG. 8, in a case where a first transistor has one gate (e.g., in case of a pixel PXA of FIG. 2), as indicated by A in FIG. 8, the first transistor may have a relatively low sub-threshold slope (or swing). However, in a case where the first transistor T1′ has double gates (e.g., in case of the pixel PXB of FIG. 6), as indicated by B in FIG. 8, the first transistor T1′ may have a relatively high sub-threshold slope. Accordingly, since the second gate of the first transistor T1′ of the pixel PXB of FIG. 6 is connected to the second node N2, the first transistor T1′ may have the relatively high sub-threshold slope, a relatively large voltage margin may be obtained, and a display device may readily represent a grayscale.

The second transistor T2 may transfer a data voltage DATA received through a data line corresponding to a j-th pixel column to the first node N1 in response to a first gate signal G1 received through a first gate line GLAi corresponding to an i-th pixel row. The third transistor T3 may transfer a reference voltage VR to the first node N1 in response to a second gate signal G2 received through a second gate line GLBi corresponding to the i-th pixel row. The fourth transistor T4 may transfer an initialization voltage VI to the second node N2 in response to a third gate signal G3 received through a third gate line GLCi corresponding to the i-th pixel row. The fifth transistor T5 may transfer the first power supply voltage ELVDD to the first transistor T1 in response to the first gate signal G1. The first capacitor C1 may be connected between the first node N1 and the second node N2. The second capacitor C2 may be connected between the second node N2 and the first power supply voltage ELVDD. The light emitting element OLED may include a first terminal (e.g., an anode) connected to the second node N2 and a second terminal (e.g., a cathode) receiving a second power supply voltage ELVSS. Configurations of the second through fifth transistors T2 through T5 and the first and second capacitors C1 and C2 are described above, and duplicated descriptions are omitted. Also, an operation of the pixel PXB of FIG. 6 may be substantially the same as an operation of the pixel PXA of FIG. 2, and duplicated descriptions are omitted.

FIG. 9 is a block diagram illustrating a display device according to some exemplary embodiments.

Referring to FIG. 9, a display device 1000B may include a display panel 100 including a plurality of pixels PX, and a panel driver for driving the display panel 100. In some exemplary embodiments, the panel driver may include a gate driver 200B, a source driver 300, a power supply 400, and a timing controller 500. The display device 1000B may be substantially the same as the display device 1000A of FIG. 1, except that the display device 1000B may further provide a fourth gate signal to the pixels PX through fourth gate lines GLD1 through GLDn. The same or similar reference numerals may be used to indicate the same or similar elements, and duplicated descriptions are primarily omitted.

The display panel 100 may include the plurality of pixel PX to display an image. Each pixel PX may compensate a threshold voltage of a driving transistor in a source follower manner. To compensate the threshold voltage, the pixel PX may receive a reference voltage VR, which is applied to a gate of the driving transistor through a reference voltage line, and may receive a data voltage through a data line among data lines DL1 through DLm. The display device 1000B may adjust a gate signal such that a threshold voltage sensing period (or a threshold voltage compensation period) has a sufficient length.

Based on a first control signal CTL1, the gate driver 200B may provide a first gate signal to the pixels PX through first gate lines GLA1 through GLAn, may provide a second gate signal to the pixels PX through second gate lines GLB1 through GLBn, may provide a third gate signal to the pixels PX through third gate lines GLC1 through GLCn, and may provide a fourth gate signal to the pixels PX through fourth gate lines GLD1 through GLDn. Here, the first gate signal may be a control signal for applying the data voltage. The second gate signal may be a control signal for applying the reference voltage VR to the pixels PX. The third gate signal may be a control signal for applying an initialization voltage VI to the pixels PX. The fourth gate signal may be a control signal for controlling emission of the pixels PX.

The source driver 300 may convert digital image data into an analog-type data voltage and may provide the data voltage to the pixels PX via the data lines DL1 through DLm based on a second control signal CTL2.

The power supply 400 may provide a first power supply voltage ELVDD, a second power supply voltage ELVSS, the initialization voltage VI, and the reference voltage VR to the pixels PX based on a third control signal CNT3.

The timing controller 500 may control the gate driver 200B, the source driver 300, and the power supply 400.

FIG. 10 is a circuit diagram illustrating a pixel included in the display device of FIG. 9 according to some exemplary embodiments. FIG. 11 is a timing diagram for describing exemplary operation of the pixel of FIG. 10 according to some exemplary embodiments.

Referring to FIGS. 10 and 11, a pixel PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5′, a first capacitor C1, a second capacitor C2, and a light emitting element OLED. The pixel PXC may be substantially the same as the pixel PXA of FIG. 2, except that the fifth transistor T5′ is an n-channel MOS transistor, and a fourth gate signal G4 is received. The same or similar reference numerals may be used to indicate the same or similar elements, and duplicated descriptions are primarily omitted.

As illustrated in FIG. 10, the first transistor T1 may be a driving transistor. The first transistor T1 may be connected between a first power supply voltage ELVDD and a second node N2, and may provide a driving current corresponding to a data voltage DATA to the light emitting element OLED. The second transistor T2 may transfer the data voltage DATA received through a data line corresponding to a j-th pixel column to a first node N1 in response to a first gate signal G1 received through a first gate line corresponding to an i-th pixel row. The third transistor T3 may transfer a reference voltage VR to the first node N1 in response to a second gate signal G2 received through a second gate line corresponding to the i-th pixel row. The fourth transistor T4 may transfer an initialization voltage VI to the second node N2 in response to a third gate signal G3 received through a third gate line corresponding to the i-th pixel row.

The fifth transistor T5′ may transfer the first power supply voltage ELVDD to the first transistor T1 in response to the fourth gate signal G4. For example, the fifth transistor T5′ may include a gate receiving the fourth gate signal G4, a first terminal receiving the first power supply voltage ELVDD, and a second terminal connected to the first terminal of the first transistor T1.

The first capacitor C1 may be connected between the first node N1 and the second node N2. The second capacitor C2 may be connected between the second node N2 and the first power supply voltage ELVDD. The light emitting element OLED may include a first terminal (e.g., an anode) connected to the second node N2 and a second terminal (e.g., a cathode) receiving a second power supply voltage ELVSS.

As illustrated in FIG. 11, one frame period for a pixel PXC may include a first period P1 in which the first node N1 and the second node N2 are initialized, a second period P2 in which a threshold voltage of the first transistor T1 is sensed, a third period P3 in which the data voltage DATA is applied to the first transistor T1, and a fourth period P4 in which the light emitting element OLED emits light based on the data voltage DATA. An operation of the pixel PXC may be substantially the same as an operation of a pixel PXA, except that the fifth transistor T5′ is controlled in response to the fourth gate signal G4 that is inverted from the first gate signal G1, and duplicated descriptions are omitted.

FIG. 12 is a circuit diagram illustrating a pixel included in a display device according to some exemplary embodiments. FIG. 13 is a timing diagram for describing exemplary operation of the pixel of FIG. 12 according to some exemplary embodiments.

Referring to FIGS. 12 and 13, a pixel PXD may include a first transistor T1″, a second transistor T2′, a third transistor T3′, a fourth transistor T4′, a fifth transistor T5″, a first capacitor C1′, a second capacitor C2′, and a light emitting element OLED′. The pixel PXD may be substantially the same as the pixel PXC of FIG. 10, except that the pixel PXD is implemented with p-channel MOS transistors. The same or similar reference numerals may be used to indicate the same or similar elements, and duplicated descriptions are primarily omitted.

As illustrated in FIG. 12, the first transistor T1″ may be a driving transistor. The first transistor T1′ may be connected between a first power supply voltage ELVSS and a second node N2′, and may provide a driving current corresponding to a data voltage DATA to the light emitting element OLED′. The second transistor T2′ may transfer the data voltage DATA received through a data line corresponding to a j-th pixel column to a first node N1′ in response to a first gate signal G1 received through a first gate line corresponding to an i-th pixel row. The third transistor T3′ may transfer a reference voltage VR to the first node N1′ in response to a second gate signal G2 received through a second gate line corresponding to the i-th pixel row. The fourth transistor T4′ may transfer an initialization voltage VI to the second node N2′ in response to a third gate signal G3 received through a third gate line corresponding to the i-th pixel row. The fifth transistor T5″ may transfer the first power supply voltage ELVSS to the first transistor T1′ in response to a fourth gate signal G4. The first capacitor C1′ may be connected between the first node N1′ and the second node N2′. The second capacitor C2′ may be connected between the second node N2′ and the first power supply voltage ELVSS. The light emitting element OLED′ may include a first terminal (e.g., an anode) connected to the second node N2′ and a second terminal (e.g., a cathode) receiving a second power supply voltage ELVDD.

As illustrated in FIG. 13, one frame period for a pixel PXD may include a first period P1 in which the first node N1′ and the second node N2′ are initialized, a second period P2 in which a threshold voltage of the first transistor T1″ is sensed, a third period P3 in which the data voltage DATA is applied to the first transistor T1″, and a fourth period P4 in which the light emitting element OLED′ emits light based on the data voltage DATA. An operation of the pixel PXD may be substantially the same as an operation of the pixel PXC of FIG. 10, except that the first through fourth gate signals G1, G2, G3 and G4 are inverted, and duplicated descriptions are omitted.

Unlike the pixel PXC of FIG. 10 and the pixel PXD of FIG. 12, the pixel PXA of FIG. 2 may not receive the fourth gate signal G4. Thus, the number of lines (or gate lines) may be reduced, and a complexity of a gate driver may be reduced. Further, with respect to the pixel PXA of FIG. 2, a fifth transistor receiving a relatively high voltage (or a first power supply voltage ELVDD) may be implemented with a p-channel MOS transistor, second through fourth transistors receiving relatively low voltages may be implemented with n-channel MOS transistors, thereby reducing a voltage range (e.g., from about 0V to about 10V) of gate signals. However, the pixel PXC of FIG. 10 may be implemented with only n-channel MOS transistors, the pixel PXD of FIG. 12 may be implemented with only p-channel MOS transistors, and thus, a process complexity and a manufacturing cost may be reduced compared with the pixel PXA of FIG. 2.

Although some exemplary embodiments of pixel structures have been described, types of transistors of pixels according to exemplary embodiments may not be limited thereto. For example, a second transistor and/or a third transistor of each pixel may be implemented as a dual gate transistor to retain a charge amount of a storage capacitor (or a first capacitor).

The inventive concepts may be applied to any electronic device including a display device. For example, the inventive concepts may be applied to a television (TV), a digital TV, a 3D TV, a smart phone, a mobile phone, a tablet computer, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concepts. For example, although exemplary embodiments where the display device is an organic light emitting display device are described above, the type of the display device may not be limited thereto.

Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the accompanying claims and various obvious modifications and equivalent arrangements as would be apparent to one of ordinary skill in the art.

Claims

1. A pixel comprising:

a first transistor comprising a gate connected to a first node, a first terminal, and a second terminal connected to a second node;

a second transistor comprising a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node;

a third transistor comprising a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node;

a fourth transistor comprising a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node;

a fifth transistor comprising a gate configured to receive the first gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor;

a first capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node;

a second capacitor comprising a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage; and

a light emitting element comprising a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.

2. The pixel of claim 1, wherein:

the second transistor is configured to turn on in response to a first logic level of the first gate signal; and

the fifth transistor is configured to turn on in response to a second logic level of the first gate signal, the second logic level being different from the first logic level.

3. The pixel of claim 2, wherein:

the second transistor is an n-channel metal oxide semiconductor (MOS) transistor; and

the fifth transistor is a p-channel MOS transistor.

4. The pixel of claim 3, wherein the third transistor and the fourth transistor are n-channel MOS transistors.

5. The pixel of claim 4, wherein the first power supply voltage is greater than the reference voltage, the initialization voltage, and the data voltage.

6. The pixel of claim 1, wherein:

the second transistor is configured to receive the data voltage through a data line; and

the third transistor is configured to receive the reference voltage through a reference voltage line different from the data line.

7. The pixel of claim 1, wherein the reference voltage is greater than the initialization voltage.

8. The pixel of claim 1, wherein the first transistor further comprises a second gate connected to the second node.

9. The pixel of claim 1, wherein the first transistor is an n-channel MOS transistor.

10. A display device comprising:

a display panel comprising a plurality of pixels; and

a panel driver configured to drive the display panel,

wherein at least one pixel among the pixels comprises:

a first transistor comprising a gate connected to a first node, a first terminal, and a second terminal connected to a second node;

a second transistor comprising a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node;

a third transistor comprising a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node;

a fourth transistor comprising a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node;

a fifth transistor comprising a gate configured to receive the first gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor;

a first capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node;

a second capacitor comprising a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage; and

a light emitting element comprising a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.

11. The display device of claim 10, wherein a frame period of the display device comprises:

a first period in which the first node and the second node are initialized;

a second period in which a threshold voltage of the first transistor is sensed;

a third period in which the data voltage is applied to the first transistor; and

a fourth period in which the light emitting element emits light based on the data voltage.

12. The display device of claim 11, wherein a length of the second period is longer than one horizontal period.

13. The display device of claim 11, wherein a length of the third period is one horizontal period.

14. The display device of claim 11, wherein, in the first period:

the third transistor, the fourth transistor, and the fifth transistor are configured to be turned on; and

the second transistor is configured to be turned off.

15. The display device of claim 11, wherein, in the second period:

the third transistor and the fifth transistor are configured to be turned on; and

the second transistor and the fourth transistor are configured to be turned off.

16. The display device of claim 11, wherein, in the third period:

the second transistor is configured to be turned on; and

the third transistor, the fourth transistor and the fifth transistor are configured to be turned off.

17. The display device of claim 11, wherein, in the fourth period:

the fifth transistor is configured to be turned on; and

the second transistor, the third transistor, and the fourth transistor are configured to be turned off.

18. The display device of claim 11, wherein:

the second transistor is an n-channel metal oxide semiconductor (MOS) transistor; and

the fifth transistor is a p-channel MOS transistor.

19. The display device of claim 11, wherein:

the second transistor is configured to receive the data voltage through a data line; and

the third transistor is configured to receive the reference voltage through a reference voltage line different from the data line.

20. The display device of claim 11, wherein the first transistor further comprises a second gate connected to the second node.

21. A pixel comprising:

a first transistor comprising a gate connected to a first node, a first terminal, and a second terminal connected to a second node;

a second transistor comprising a gate configured to receive a first gate signal, a first terminal configured to receive a data voltage, and a second terminal connected to the first node;

a third transistor comprising a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage, and a second terminal connected to the first node;

a fourth transistor comprising a gate configured to receive a third gate signal, a first terminal configured to receive an initialization voltage, and a second terminal connected to the second node;

a fifth transistor comprising a gate configured to receive a fourth gate signal, a first terminal configured to receive a first power supply voltage, and a second terminal connected to the first terminal of the first transistor;

a first capacitor comprising a first electrode connected to the first node, and a second electrode connected to the second node;

a second capacitor comprising a first electrode connected to the second node, and a second electrode configured to receive the first power supply voltage; and

a light emitting element comprising a first terminal connected to the second node, and a second terminal configured to receive a second power supply voltage.

22. The pixel of claim 21, wherein the first transistor is a double gate transistor.

23. The pixel of claim 21, wherein the first transistor further comprises a second gate connected to the second node.

24. The pixel of claim 23, wherein the second gate of the first transistor is under an active layer of the first transistor.

25. The pixel of claim 21, wherein the first power supply voltage is higher than the reference voltage and the initialization voltage.

26. The pixel of claim 25, wherein the reference voltage is higher than the initialization voltage.

27. The pixel of claim 21, wherein the first, second, third, fourth and fifth transistors are n-channel MOS transistors.

28. The pixel of claim 21, wherein:

the second transistor is configured to receive the data voltage through a data line; and

the third transistor is configured to receive the reference voltage through a reference voltage line different from the data line.

29. The pixel of claim 21, wherein a frame period includes:

a first period in which the first node and the second node are initialized;

a second period in which a threshold voltage of the first transistor is sensed;

a third period in which the data voltage is applied to the first transistor; and

a fourth period in which the light emitting element emits light based on the data voltage.

30. The pixel of claim 29, wherein a length of the second period is longer than a length of the third period.

31. The pixel of claim 30, wherein the length of the second period is three to ten times as long as the length of the third period.

32. The pixel of claim 29, wherein a length of the second period is longer than one horizontal period.

33. The pixel of claim 29, wherein a length of the third period is one horizontal period.

34. The pixel of claim 29, wherein, in the first period:

the third transistor and the fourth transistor are configured to be turned on; and

the second transistor is configured to be turned off.

35. The pixel of claim 29, wherein, in the second period:

the third transistor and the fifth transistor are configured to be turned on; and

the second transistor and the fourth transistor are configured to be turned off.

36. The pixel of claim 29, wherein, in the third period:

the second transistor is configured to be turned on; and

the third transistor, the fourth transistor and the fifth transistor are configured to be turned off.

37. The pixel of claim 29, wherein, in the fourth period:

the fifth transistor is configured to be turned on; and

the second transistor, the third transistor, and the fourth transistor are configured to be turned off.

38. The pixel of claim 21, wherein:

the second transistor is an n-channel metal oxide semiconductor transistor; and

the fifth transistor is a p-channel MOS transistor.

39. The pixel of claim 21, wherein the first, second, third, fourth and fifth transistors are p-channel MOS transistors.

40. The pixel of claim 21, wherein the first power supply voltage is a low power supply voltage, and the second power supply voltage is a high power supply voltage.