The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers. The plurality of output buffers provides the vertical scalar with simultaneous parallel access to multiple lines of buffered digital image data. The frame memory preferably comprises DRAM that stores the image data such that row faults are minimized. The DRAM frame memory preferably includes at least two memory banks, each including a plurality of rows and a plurality of columns. The DRAM frame memory has multiple purposes including storing digital image data frames for sample rate conversion, as well as, storing bitmaps for access by an On Screen display controller and storing microprocessor data for access by a microprocessor.
|
1. A pixelated display controller integrated circuit, comprising:
an image scalar circuit for vertically scaling digital data of a pixelated image; a frame memory coupled to the image scaling circuit adapted to store digital image data frames; and a plurality of buffers positioned between the image scalar and the frame memory, each buffer storing a corresponding portion of the digital image data frame such that the image scalar circuit parallel accesses the portions of the digital image data frame stored in the plurality of buffers.
20. A method for vertically scaling digital data representative of a pixelated digital image, comprising:
embedding a frame memory and a vertical scalar in an integrated circuit; storing the digital data in the frame memory; transferring portions of selected digital data lines from the frame memory to a corresponding output buffer until a plurality of output buffers stores corresponding portions of sequential digital data lines; and scaling the pixelated digital image with the vertical scalar by parallel accessing the portions of selected data lines stored in the plurality of output buffers.
10. A vertical scaling circuit for vertically scaling digital data of a pixelated image, comprising:
a frame memory for storing the digital data, the digital data being divided into a plurality of frames, each frame including a plurality of lines; a plurality of output buffers, each output buffer adapted to store at least a portion of a selected line; and a vertical scalar coupled to the plurality of output buffers adapted to vertically scale the pixelated image by parallel accessing the portions of the selected lines stored in each of the output buffers; wherein the frame memory, the plurality of output buffers, and the vertical scalar are embedded in an integrated circuit.
2. The pixelated display controller of
4. The pixelated display controller of
5. The pixelated display controller of
6. The pixelated display controller of
7. The pixelated display controller of
8. The pixelated display controller of
12. The vertical scaling circuit of
13. The vertical scaling circuit of
14. The vertical scaling circuit of
15. The vertical scaling circuit of
17. The vertical scaling circuit of
18. The vertical scaling circuit of
21. The method of
22. The method of
23. The method of
24. The method of
25. The method of
26. The method of
28. The method of
29. The method of
|
This application claims priority from U.S. patent application Ser. No. 09/198,314, filed Nov. 23, 1998, that claims priority from U.S. Prov. Appln. No. 60/065,445, filed Nov. 24, 1997, and U.S. Prov. Appln. No. 60/086,121, filed May 20, 1998, all incorporated herein by reference.
1. Field of the Invention
This invention relates to a memory system for the visual display of digital image data and, more particularly, to an embedded ultra-high bandwidth multi-port memory system for ok digital image scaling applications.
2. Description of the Prior Art
Digital image data generally defines one or more frames. A frame is an image displayed for viewing on a display or panel at one time, i.e., one frame of data fits on the display screen or panel. Each frame includes a rectangular array of pixels. Each pixel has one or more values, for example, a gray scale value for a monochrome display or RGB values for a color display. The resolution of the array, i.e., the number of horizontal and vertical pixels, can also be referred to as the image sample rate or resolution. Common display resolutions include that shown in Table 1 indicating, in the second and third columns, the number of pixels in the vertical and horizontal dimensions, respectively:
TABLE 1 | |||
VGA | 640 | 480 | |
SVGA | 800 | 600 | |
XGA | 1024 | 768 | |
SXGA | 1280 | 1024 | |
UXGA | 1600 | 1200 | |
HDTV | 1280 | 720 | |
Where the resolution or sample rate of the display device matches the resolution of the image data, the data can be displayed directly; if not, it is desirable in many cases that the image be appropriately scaled. Scaling can be done in either vertical or horizontal or both dimensions, and the sample rates can be scaled up or down. Increasing the size a digital image (scaling up) is accomplished by introducing additional pixels in either or both the vertical and horizontal directions. The additional pixels can be introduced by linearly interpolating between two existing pixels or by using more sophisticated techniques such as multi-rate Finite Impulse Response (FIR) filters. The use of FIR filters to accomplish vertical and horizontal scaling is described in U.S. Pat. Nos. 4,020,332 to Crochiere, et al., 4,682,301 to Hiroba et al., and 5,355,328 to Arbeiter, et al., all incorporated herein by reference.
Generally, vertical scalars, like scalar 12, are embedded in Application Specific Integrated Circuits (ASICs) designed for the specific application envisioned, vertically scaling digital images in this case. In addition to line memories, conventional vertical scalar ASICs use external Dynamic Random Access Memory (DRAM) type memory for certain other applications, e.g., frame rate conversion. Thus, vertical scalar ASICs of the type shown in
Accordingly, a need remains for improvements in image scaling methods and apparatus. In particular, a need remains for a simplified image scaling memory system that improves reliability, lowers cost, and improves silicon area usage.
The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage.
The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The input buffer packs input data pixels to form data words. Once a predetermined number of data words are stored, the input buffer transfers the stored data words to the frame memory. The plurality of output buffers is coupled to the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers. The plurality of output buffers provides the vertical scalar with simultaneous parallel access to sequential lines of buffered digital image data. The input and output buffers are preferably implemented using First-In First-Out (FIFO) buffers.
The frame memory preferably comprises DRAM that stores the image data such that row faults are minimized. However, the frame memory may include other suitable memory types, e.g., SRAM. The DRAM frame memory preferably includes at least two memory banks, each including a plurality of rows and a plurality of columns. Each row of the DRAM frame memory contains digital data from multiple lines and stores portions of a plurality of digital data line such that corresponding portions of sequential digital data lines are stored in no more than one row in each bank thereby minimizing row faults. Only one row per bank is active at any given time. There are preferably at least N-1 partial image lines stored in each row of the DRAM frame memory to minimize the row fault rate, where N is the number of lines simultaneously required by the vertical scalar to vertically scale the digital image data. The DRAM frame memory includes an image portion for storing the digital image data frames, an On Screen Display (OSD) portion for storing OSD bitmaps for access by an OSD controller, a microprocessor portion for storing microprocessor data for access by a microprocessor, or a combination thereof.
Another embodiment of the present invention is a vertical scaling circuit embedded in an integrated circuit for vertically scaling digital data of a pixelated image. The vertical scaling circuit comprises a frame memory for storing the digital data, the digital data being divided into a plurality of frames, each frame including a plurality of lines. A plurality of output buffers is coupled to the frame memory. Each output buffer stores at least a portion of a selected line. A vertical scalar is coupled to the plurality of output buffers for vertically scaling the pixelated image by simultaneously parallel accessing the portions of the selected lines stored in each of the output buffers. The vertical scalar can be implemented using a variety of techniques including, but not limited to, the FIR filter techniques described herein.
As mentioned above, the frame memory is preferably DRAM memory but can comprise other similar memory types, e.g., SRAM. Where DRAM is used, the frame memory preferably comprises at least two memory banks, each including a plurality of rows and columns. Each row stores portions of sequential digital image data lines. Row faults are minimized by storing sequential digital data lines in no more than one row in each bank. The DRAM frame memory includes an image portion for storing the digital image frames, an OSD portion for storing OSD bitmaps for access by an OSD controller, a microprocessor portion for storing microprocessor data for access by a microprocessor, or a combination thereof.
The vertical scaling circuit further includes an input buffer coupled to an input side of the frame memory for buffering the digital image data. The input buffer is also embedded in the integrated circuit. The frame memory includes an output port. Each output buffer sequentially accesses the frame memory through the output port and buffers portions of image lines stored therein. The input and plurality of output buffers are preferably implemented using FIFO buffers.
A method for vertically scaling data representative of a pixelated digital image is provided. The method comprises embedding a frame memory and a vertical scalar in an integrated circuit, storing the data in the frame memory, transferring portions of selected data lines from the frame memory to a corresponding output buffer until a plurality of output buffers stores corresponding portions of sequential digital data lines, and simultaneous parallel accessing the portions of selected data lines stored in the plurality of output buffers.
Storing the data in the frame memory includes storing the data in a DRAM memory. Storing the data in the frame memory includes storing the data in at least two memory banks, each bank including a plurality of rows and columns. Each row stores corresponding portions of sequential digital data lines such that corresponding portions of sequential digital data lines are stored in no more than one row in each bank thereby minimizing row faults.
Storing the digital data in the frame memory includes storing a digital data frame in the frame memory for conversion from an input refresh rate to an output refresh rate, storing OSD bitmaps in the frame memory, or storing microprocessor data in the frame memory.
The frame memory includes an output port. Transferring portions of selected digital data lines includes having each output buffer sequentially access the output port. The method further includes buffering the data in an input buffer. The input buffer and the plurality of output buffers are preferably implemented using FIFO buffers.
The foregoing and other objects, features, and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment that proceeds with reference to the following drawings.
As explained in detail below, the input buffer 15 and the plurality of output buffers R1, R2, . . . Rn minimize the time penalty incurred when switching between data input and data output. The key impediment to the frame memory 16 is that it includes a single access port 14. The single access port 14 limits accesses to the frame memory 16 to one unit, e.g., one word, every clock cycle. However, the vertical scalar 17 needs simultaneous parallel access to multiple lines of image data to vertically scale the image. The plurality of output buffers R1, R2, . . . Rn provides the vertical scalar 17 with such simultaneous parallel access. The output buffers R1, R2, . . . Rn function as miniature line memories thereby transforming the frame memory 16 into a multi-port high bandwidth serial access memory.
The frame memory 16 is divided into different portions. The frame memory 16 includes an image portion for storing the digital image frames, an OSD portion for storing OSD bitmaps for access by an OSD controller, a microprocessor portion for storing microprocessor data for access by a microprocessor, or a combination thereof. A person skilled in the art should recognize that the above-described frame memory portions might be distinct, overlap, and/or combined.
As its name suggests, the multipurpose frame memory 16 is used to accomplish several different functions, e.g., frame rate conversion, frame dropping, image compression, and image scaling. Frame rate conversion involves converting the refresh rate of the digital image data 11 to accommodate the limited refresh rate range of many displays. Thus, the multipurpose frame memory 16 allows the refresh rate of the digital image data signal 11 to be different than the refresh rate of the digital output signal 13. For example, the digital image data 11 received from a typical personal computer graphics card varies from 60 Hz to 100 Hz while the display device may require an output signal 13 having a fixed 60 Hz refresh rate.
Input signals having high resolutions can be double buffered or frame dropped, i.e., inhibit the capture of frames for a limited time, to eliminate frame tear when the input and display refresh rates are different. The frame memory 16 includes an intelligent image compression feature and an interlaced RGB image capture feature. The intelligent image compression feature compresses image pixels from 24 bits per pixel down to 16 bits per pixel or from 24 bits per pixel down to either 19 or 12 bits per pixel with negligible loss of image quality. The frame memory 16 includes sufficient memory storage for on screen display (OSD) bitmaps. However, a primary purpose of the frame memory 16 remains buffering the data for scaling in both vertical and horizontal dimensions.
The frame memory 16 contains enough memory to store a frame of digital image data 11. For example, the frame memory 16 contains 16 Mbits of high-speed DRAM with a 256-bit internal data bus. The buffer can store up to SXGA (1280×1024) images at 24 bits per pixel or UXGA (1600×1200) or HDTV (1920×1080) images at 16 bits per pixel. The frame memory 16 is included in a monolithic integrated circuit that includes other blocks of the image scaling circuit 20 shown in
The image scaling circuit 20 operates in the following manner. The digital image data 11 is received as a serial stream of image pixel data at input buffer 15. The input buffer 15 writes or captures pixels one at a time from the digital image data 11. Once a sufficient number of pixels are packed, the input buffer 15 reads or bursts the captured pixels to the go frame memory 16. For example, assume a memory word comprises sixteen 16-bit pixels. The input buffer 15 captures (writes) sixteen pixels or more before bursting out (reading) a word or plurality of words to the frame memory 16.
The frame memory 16 stores the digital image data 11 and provides the buffered digital image data to the plurality of output buffers R1, R2, . . . Rn. The plurality of output buffers R1, R2, . . . Rn, in turn, provide parallel access to multiple lines of buffered digital image data to the vertical scalar 17.
Where the frame memory 16 comprises DRAM memory, each row of the frame memory 16 contains digital data from multiple lines. The frame memory 16 includes at least two memory banks to minimize row faults. Only one row per bank is active at any given time. When a row must be activated, there is a multiple clock cycle penalty, e.g., 8 clocks. The frame memory 16 includes a single output port 14. The output buffers R1, R2, . . . Rn sequentially access the frame memory 16 through the single port 14 in a round robin fashion. In the preferred embodiment, the frame memory 16 transfers one memory word representative of a portion of an image line to an output buffer per output register access.
The output buffers R1, R2, . . . Rn thus contain portions of image data from multiple lines thereby minimizing the overall register depth. This is because each output buffer, e.g., R1, receives new data more frequently than if a packet transfer methodology were used to supply data to the output buffers R1, R2, . . . Rn. The currently preferred output buffers are First-In, First-Out (FIFO) registers 6 words deep, i.e., about 96 pixels deep--assuming 16 pixels/word. A person skilled in the art should recognize that the size and type of the input and output buffers can vary depending on the specific scaling system being designed.
The output buffers R1, R2, . . . Rn sequentially access the frame memory 16 in the following exemplary manner. Assume five output buffers and a frame memory organization as shown in
The vertical scalar 17 requests words from memory by issuing a memory request to the memory controller 19. The memory controller 19 arbitrates access to the frame memory 16 from subsystems within the image scaling circuit 20 including the vertical image scalar 17, the plurality of output buffers R1, R2, . . . Rn, and the input buffer 15. The memory controller 19 also arbitrates access to the frame memory 16 from the circuit blocks shown in
Note that the vertical scalar 17 requests memory words because all of the pixels in these words will be required to produce an output line that is scaled in both the vertical and horizontal dimensions. Additionally, the vertical scalar requests words from memory ahead of when the data is actually used. The vertical scalar 17 scales the image only in the vertical dimension resulting in the horizontal output dimension of the vertically scaled image being equal to its horizontal input dimension. For example, assume the input image is 640×480 pixels and we desire a scaled output image having 1024×768 pixels. The vertical scalar 17 will produce output image data 13 having 640×768 pixels. Thus, each line of the output image contains 640 pixels same as the input image. These pixels are contiguous in the horizontal dimension such that each pixel in a word is used once for a given vertically-scaled output image followed by the next output until all the pixels in a word have been processed.
Once the vertical scalar 17 finishes processing a word, the vertical scalar 17 moves on to the next word by, for example, advancing a read pointer for a corresponding output buffer. Where a plurality of FIFOs is used to implement the plurality of output buffers, the vertical scalar 17 simply requests and packs memory words in order into the output buffers. The vertical scalar 17 then reads pixels out one at a time, i.e., one from each output buffer every clock cycle, until all the pixels in a word have been processed. If any one of the output buffers R1, R2, . . . Rn are empty, the vertical scalar 17 stalls until data is available. In other words, each output buffer, e.g., R1, receives one word per clock from frame memory 16 at an input terminal, each word including a predetermined number of pixels, and produces one pixel per clock at an output terminal. If five lines are required to scale the image in the vertical dimension, five output buffers each produce one pixel clock, i.e., the five registers operate in parallel. Thus, the plurality of output buffers have an input bandwidth that is greater than or equal to its output bandwidth ensuring that the output buffers receive new data before going empty.
The scalars 17 and 22 shown in
Calculate FIR Phase:
IntegerOutputPosition=int(OutputPosition+0.5)
InputPixelPosition=int((IntegerOutputPosition+L-1)/L)
FIRPhase=InputPixelPosition*L-IntegerOutputPosition
Using decimal values of M allows very fine control of the resizing scale factor even when L is a fixed value. In the preferred embodiment L=2K. Limiting the value L to a power of two reduces complexity of the phase calculation process shown in
The phase calculation circuit described in
Using the FIR phase and input pixel position defined in
Likewise, using the FIR phase and input pixel position defined in
As explained above, each of the output buffers R1, R2, . . . Rn contains the data from a line of data with the nth pixel of each line available at the same time to a multiplexer. The output pixel value is then calculated using multipliers 82 and adders 83. The length of the FIR filter can be increased using an optional recirculation adder 85 that is enabled by selecting the feedback path on multiplexer 84. Since the FIR filter length was restricted to N*L, each coefficient of RAM need only contain R*L coefficients of the filter where R is the number of recirculations required to compute the final result. In the preferred embodiment of the invention, vertical scaling is performed first, where the nth pixel of a series of lines or rows is factored to produce a single vertical value for these lines or rows. This value is then sent into the pipeline feeding the horizontal scalar 22.
After a vertical value is calculated, a new phase is calculated that defines the next set of coefficients to use for calculating the next vertical value. The data used for the next vertical value may advance to the next pixel in the rows. For the case of up sampling, since new lines are being created, the same pixels may be used to produce two vertical values for two separate output lines, though the weight each pixel is given will vary as the coefficients have been updated.
Referring to
The circuit shown in
A more general method of image warping involves calculating M as a function of the current output pixel position X,Y (i.e., M=f(X,Y)). For all cases of image warping to prevent aliasing and imaging artifacts, the FIR filter cutoff is the smaller of 1/M' or 1/L where M' is the largest down sample rate used in the image warp, i.e., M'=max(f(X,Y)). Any standard technique for FIR filter design may be used; window methods such a Kaiser, Harris, Hanning, and Hamming work well.
When image warping is used in the present invention, the delta position Δpos in register 43 is non-zero. For each line, the delta position register 43 (
For aspect ratio conversion, the outer regions are distorted, once again needing fewer pixels and a larger M value than in the center of the image. As the pixels are processed toward the center, the down sample value M will decrease until reaching a halfway point. At the halfway point, the value M will again increase.
Definitions:
α=Keystone correction amount (+ or -)
H=Input Image Height
W=Input Image Width
Nx=Number of horizontal multiplication's (FIR Length=Nx* Lx)
Lx0=Initial horizontal up sample value
Mx0=Initial horizontal down sample value
Lx=Horizontal up sample value
Mx=Horizontal down sample value
ΔMx=Horizontal down sample rate line increment
X0=Initial horizontal start position
ΔX=Horizontal start position line increment
Y0=Initial vertical start position
My0=Initial vertical down sample value
Ly=Vertical up sample value
My=Vertical down sample value ΔMy=Vertical down sample value line increment
Equations:
if α>=0 then
ΔMx=(Mx0*α)/((1-α)*(H-1))
ΔX=-(Lx0*W*ΔMx)/(2*Mx0)
X0=-(Nx*Lx0)/2
Mx=Mx0-ΔMx*(H-1)
ΔMy=(α*My02)/(H*Ly)
My=My0
Y0=-(Ny*Ly0)/2 else
ΔMx=-(Mx0*α)/((1-α)*(H-1))
ΔX=(Lx0*W*ΔMx)/(2*Mx0)
X0=-(Nx*Lx0)/2-(H-1)*ΔX
Mx=Mx0-ΔMx*(H-1)
ΔMy=-(α*My02)/(H*Ly)
My=My0-ΔMy*(H-1)
Y0=-(Ny*Ly0)/2 end if.
The RGB input port 105 receives digital data for a pixelated image previously converted from an analog image source (not shown). The preferred RGB port 105 receives data at up to 230 Mpixels/second thereby supporting a variety of display modes up to UXGA. The RGB port 105 receives RGB data having 1 or 2, 24-bit pixels per clock. The RGB port 105 includes a sync processing circuit that can operate from separate, composite, or sync-on-green sync signals. The RGB port 105 supports both interlaced and progressive scanned RGB inputs and half-frequency sampling for lower cost display system implementations. Half-frequency sampling reduces system cost by allowing the use of 100 MHz analog to digital converters--
The video port 115 receives YUV or RGB digital data for a pixelated image previously converted from an analog image source (not shown). The video port 115 includes a variety of image processing features including intra-field and inter-field video de-interlacing, double buffered and frame locked image capture modes, and simultaneous signal capture of up to 30 Mpixels/second with RGB input port 105. The video input port 115 includes a rotational feature that allows rotating a received image by 90 degrees. The 90-degree image rotation is made possible by the high internal memory bandwidth in the display system controller 100. The video port 115 supports all common video decoder integrated circuits.
The automatic image optimizer 110 monitors and characterizes the digital input signals received by the RGB port 105 and the video port 115. The automatic image optimizer 110 generates the necessary control signals to allow the RGB port 105 and the video port 115 to interface with the image sources. The control signals include a Phase Locked Loop (PLL) reference signal, a PLL feedback pulse, a PLL coast control signal that disables the PLL during a vertical sync interval, and a Direct Current (DC) restore clamp pulse. The automatic image optimizer 10 sets the clock frequency, the clock phase, and the image size, position, and gain without requiring user intervention. The preferred automatic image optimizer 110 works with a variety of external PLL devices (
The microprocessor 120 performs all of the control functions necessary for the display system controller 100. The microprocessor 120 is preferably an on-chip general-purpose 16-bit, ×86-compatible processor. The microprocessor 120 preferably runs at clock rates of up to 50 MHz and has a one-megabyte address space.
A fill complement of microprocessor peripherals 135 are included in the display system controller 100. In the preferred embodiment, the microprocessor peripherals 135 include three 8-bit I/O ports, two 16-bit timers, a watchdog timer, a programmable interrupt controller, an RS-232 serial port, an infrared remote control decoder, a glue-less ROM & RAM interface, and decode logic for external peripherals. The microprocessor peripherals 135 include in the system 100 are on-chip allowing a complete microprocessor system to be implemented by merely adding external read-only and random access memory.
The vertical and horizontal scalars 17 and 22, as mentioned above, scale the captured image up or down to any arbitrary resolution. Vertical and horizontal scale factors are completely independent. The scalars 17 and 22 allow a wide range of captured image resolutions to be displayed on a fixed pixel resolution display device. For example, in the case of an XGA LCD desktop monitor, the scalars 17 and 22 can be used to perform the following resizing factors:
NTSC up to XGA
VGA up to XGA
SVGAup to XGA
XGA to XGA (no scaling)
SXGA down to XGA
UXGA down to XGA
HDTV down to XGA
The display system controller 100 includes an OSD controller 145. The OSD controller 145 fills and draws OSD bitmaps into the frame memory 16. An overlay function included in the OSD controller 145 allows transparent and semi-transparent overlays to be displayed. The OSD controller 145 selects on a pixel-by-pixel basis whether to display the scaled, captured image or the OSD bitmap stored in the frame memory 16. The OSD controller 145 can be used to implement simple, opaque, character-based menu systems or complex, bitmap-based, menus with transparent backgrounds. Advanced functions such as a translucent highlighter pen and embossed transparent logos are also possible. The OSD controller 145 preferably supports up to 16 bits per pixel or 64K colors.
The display controller 150 generates timing signals to control the pixelated output display device. The display timing is fully programmable and is completely independent of the image being captured. The display controller 150 supports display refresh rates between about 50 Hz to over 100 Hz. The displayed image may be flipped horizontally or vertically. The display controller 150 includes a color space expander that allows full color display on displays with fewer than 8-bits per color channel. Programmable color lookup tables are provided to allow for gamma correction, i.e., matching the display's color space to the desired range. Gain and contrast controls are also included in the controller 150. Single and dual pixel outputs are supported at up to UXGA (1600×1200) resolution.
The display system controller 100 includes a variety of circuits that support unique features not shown in FIG. 14. For example, a picture-in-picture feature allows the input image received at the video port 115 to be simultaneously displayed in the same window as the input image received at the RGB port 105. The captured image can also be panned and zoomed by the user. Additionally, an average picture level (APL) monitoring circuit allows monitoring the overall brightness of the pixels sent to the display.
Having illustrated and described the principles of my invention in a preferred embodiment thereof, it should be readily apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. I claim all modifications coming within the spirit and scope of the accompanying claims.
West, Michael G., Greenberg, Robert Y.
Patent | Priority | Assignee | Title |
6850231, | Jan 02 2001 | SAMSUNG DISPLAY CO , LTD | Organic electroluminescent display control system |
6903733, | Nov 24 1997 | Pixelworks, Inc. | Ultra-high bandwidth multi-port memory system for image scaling applications |
6943783, | Dec 05 2001 | Etron Technology Inc. | LCD controller which supports a no-scaling image without a frame buffer |
6997563, | May 19 2004 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Keystone correction derived from the parameters of projectors |
7038729, | Dec 26 2000 | Sony Corporation | Device and method for producing coefficient seed data used for format conversion, and information-providing medium therefore |
7042464, | Aug 01 2003 | Apple Inc | Methods and apparatuses for the automated display of visual effects |
7065263, | Aug 21 2001 | Canon Kabushiki Kaisha | Image processing apparatus, image input/output apparatus, scaling method and memory control method |
7175286, | May 19 2004 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Keystone correction derived from the parameters of projectors |
7199837, | Nov 13 2001 | ATI Technologies, Inc. | System for improved ratiometric expansion and method thereof |
7209146, | Aug 01 2003 | Apple Inc | Methods and apparatuses for the automated display of visual effects |
7236648, | Dec 27 1999 | Intel Corporation | Scaling images for display |
7268755, | Mar 25 2003 | Intel Corporation | Architecture for smart LCD panel interface |
7283173, | Jan 30 2002 | Sony Corporation | Coefficient seed data or coefficient data production device used in image display apparatus, method for producing coefficient seed data or coefficient data used in image display apparatus, program therefor, and computer-readable medium for storing the same |
7286720, | Aug 21 2001 | Canon Kabushiki Kaisha | Image processing apparatus, image input/output apparatus, scaling method and memory control method |
7304763, | May 22 2002 | Canon Kabushiki Kaisha | Image processing apparatus and method |
7308159, | Jan 16 2004 | Nvidia Corporation | Image processing system and method with dynamically controlled pixel processing |
7324024, | Feb 28 2005 | Sanyo Electric Co., Ltd.; Yutaka, Yamamoto | High frequency compensator and reproducing device |
7355606, | Aug 01 2003 | Apple Inc. | Methods and apparatuses for the automated display of visual effects |
7359007, | Oct 12 2004 | MEDIATEK INC. | System for format conversion using clock adjuster and method of the same |
7380946, | Jan 28 2003 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Semiautomatic keystone correction system and method |
7441906, | Jul 05 2005 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Keystone correction system and method |
7461939, | Nov 19 2004 | Hewlett-Packard Development Company, L.P.; HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Automatic zoom for screen fitting |
7511713, | Mar 02 2004 | Ittiam Systems (P) Ltd. | Method and apparatus for high rate concurrent read-write applications |
7536062, | Dec 27 1999 | Intel Corporation | Scaling images for display |
7551230, | Dec 26 2000 | Sony Corporation | Device and method for producing coefficient seed data used for format conversion, and information-providing medium therefore |
7581839, | May 19 2004 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Keystone correction derived from the parameters of projectors |
7609228, | Jan 28 2003 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Automatic keystone correction system and method |
7640294, | Nov 21 2003 | Canon Kabushiki Kaisha | Image processor and image processing method |
7657711, | Sep 08 2003 | Sony Corporation | Dynamic memory bandwidth allocation |
7705862, | Nov 26 2003 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | System and method for improved keystone correction |
7720304, | May 31 2005 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | System and method for implementing graphics and video scaling algorithm using interpolation based on symmetrical polyphase filtering |
7738740, | Jan 13 2005 | Nvidia Corporation | Video processing system and method with dynamic tag architecture |
7774577, | Dec 22 2006 | SOCIONEXT INC | Memory device, memory controller and memory system |
7808513, | Jan 28 2003 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Automatic keystone correction system and method |
7814294, | Dec 22 2006 | SOCIONEXT INC | Memory device, memory controller and memory system |
7825989, | Jul 26 2005 | Pixelworks, Inc. | Television channel change picture-in-picture circuit and method |
7850312, | May 19 2004 | PIXELWORKS SEMICONDUCTOR TECHNOLOGY SHANGHAI CO , LTD | Keystone correction derived from the parameters of projectors |
7853044, | Jan 13 2005 | Nvidia Corporation | Video processing system and method with dynamic tag architecture |
7869666, | Jan 13 2005 | Nvidia Corporation | Video processing system and method with dynamic tag architecture |
7903104, | Mar 21 2007 | SPATIAL PHOTONICS, INC | Spatial modulator display system using two memories and display time slices having differing times |
8005312, | May 31 2005 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | System and method for implementing graphics and video scaling algorithm using interpolation based on symmetrical polyphase filtering |
8015389, | Dec 22 2006 | SOCIONEXT INC | Memory device, memory controller and memory system |
8144170, | Mar 28 2007 | Himax Technologies Limited | Apparatus for scaling image and line buffer thereof |
8350963, | Feb 03 2006 | DYNAMIC DATA TECHNOLOGIES LLC | Video processing device and method of processing video data |
8421916, | Jan 14 2005 | GRASS VALLEY LIMITED | Image processing |
8576251, | Aug 13 2010 | AU Optronics Corp. | Scaling-up control method and scaling-up control apparatus for use in display device |
8675994, | Jun 17 2010 | Ambarella International LP | High performance warp correction in two-dimensional images |
8872856, | Aug 14 2008 | NXP USA, INC | Macroblock based scaling of images using reduced memory bandwidth |
9292904, | Jan 16 2004 | Nvidia Corporation | Video image processing with parallel processing |
9330438, | Jun 17 2010 | Ambarella International LP | High performance warp correction in two-dimensional images |
9343124, | Jul 29 2011 | TAHOE RESEARCH, LTD | Method and system for operating a multi-port memory system |
9357162, | Jan 13 2005 | Nvidia Corporation | Video processing system and method with dynamic tag architecture |
Patent | Priority | Assignee | Title |
4020332, | Sep 24 1975 | Bell Telephone Laboratories, Incorporated | Interpolation-decimation circuit for increasing or decreasing digital sampling frequency |
4682301, | Sep 02 1982 | Hitachi Medical Corp. | Digital filter for processing two-dimensional digital image |
5239628, | Nov 13 1985 | Sony Corporation | System for asynchronously generating data block processing start signal upon the occurrence of processing end signal block start signal |
5285192, | Sep 16 1988 | Intel Corporation | Compensation method and circuitry for flat panel display |
5335296, | Apr 30 1991 | Optigraphics Corporation | Process for high speed rescaling of binary images |
5355328, | Sep 27 1991 | A2ZLOGIX, INC | Resampling apparatus suitable for resizing a video image |
5608425, | Aug 31 1993 | IXYS Intl Limited | Technique for generating on-screen display characters using software implementation |
5650955, | Jun 20 1994 | Intellectual Ventures I LLC | Graphics controller integrated circuit without memory interface |
5703806, | Jun 20 1994 | Intellectual Ventures I LLC | Graphics controller integrated circuit without memory interface |
5742261, | Jun 21 1991 | Canon Kabushiki Kaisha | Display control apparatus and display device with sampling frequency control for optimizing image size |
5767916, | Mar 13 1996 | Seiko Epson Corporation | Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion |
5790096, | Sep 03 1996 | LG Electronics Inc | Automated flat panel display control system for accomodating broad range of video types and formats |
5805233, | Mar 13 1996 | Seiko Epson Corporation | Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion |
5900917, | Sep 17 1991 | Hitachi, Ltd. | Image composing and displaying method and apparatus |
5920659, | Jun 24 1996 | Mineral Lassen LLC | Method and apparatus for scaling image data having associated transparency data |
5977933, | Jan 11 1996 | S3 GRAPHICS CO , LTD | Dual image computer display controller |
6008794, | Feb 10 1998 | S3 GRAPHICS CO , LTD | Flat-panel display controller with improved dithering and frame rate control |
6025853, | Mar 24 1995 | ZIILABS INC , LTD | Integrated graphics subsystem with message-passing architecture |
6064359, | Jul 09 1997 | Seiko Epson Corporation | Frame rate modulation for liquid crystal display (LCD) |
6064404, | Nov 05 1996 | Silicon Light Machines Corporation | Bandwidth and frame buffer size reduction in a digital pulse-width-modulated display system |
6088045, | Jul 22 1991 | MEDIATEK INC | High definition multimedia display |
6125199, | Nov 14 1995 | Mitsubishi Denki Kabushiki Kaisha | Color correcting method and apparatus and a system incorporating the same |
6175592, | Mar 12 1997 | MATSUSHITA ELECTRIC INDUSTRIAL CORP , LTD | Frequency domain filtering for down conversion of a DCT encoded picture |
6204887, | Dec 11 1998 | Hitachi America, Ltd. | Methods and apparatus for decoding and displaying multiple images using a common processor |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 17 1999 | Pixelworks, Inc | (assignment on the face of the patent) | / | |||
Aug 10 1999 | GREENBURG, ROBERT Y | Pixelworks, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010229 | /0975 | |
Aug 10 1999 | WEST, MICHAEL G | Pixelworks, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010229 | /0975 |
Date | Maintenance Fee Events |
Mar 26 2004 | ASPN: Payor Number Assigned. |
Feb 26 2007 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Mar 23 2007 | R2551: Refund - Payment of Maintenance Fee, 4th Yr, Small Entity. |
Mar 23 2007 | STOL: Pat Hldr no Longer Claims Small Ent Stat |
Feb 28 2011 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Nov 07 2014 | LTOS: Pat Holder Claims Small Entity Status. |
Feb 26 2015 | M2553: Payment of Maintenance Fee, 12th Yr, Small Entity. |
Date | Maintenance Schedule |
Aug 26 2006 | 4 years fee payment window open |
Feb 26 2007 | 6 months grace period start (w surcharge) |
Aug 26 2007 | patent expiry (for year 4) |
Aug 26 2009 | 2 years to revive unintentionally abandoned end. (for year 4) |
Aug 26 2010 | 8 years fee payment window open |
Feb 26 2011 | 6 months grace period start (w surcharge) |
Aug 26 2011 | patent expiry (for year 8) |
Aug 26 2013 | 2 years to revive unintentionally abandoned end. (for year 8) |
Aug 26 2014 | 12 years fee payment window open |
Feb 26 2015 | 6 months grace period start (w surcharge) |
Aug 26 2015 | patent expiry (for year 12) |
Aug 26 2017 | 2 years to revive unintentionally abandoned end. (for year 12) |