A method of forming self-aligned MRAM contacts is disclosed. MRAM stacks including an upper layer of a conductive material are formed over portions of integrated circuitry. An insulating material is formed over the substrate, including the MRAM stacks with the upper layer of conductive material. The insulating material is subsequently chemically mechanically polished or etched, stopping on the upper layer of conductive material, to expose portions of the conductive material which are used as self-aligned MRAM contacts.
|
1. A method of forming a magnetic random access memory, said method comprising:
forming a plurality of spaced apart first conductive layers over an insulating layer formed over a substrate; forming a plurality of spaced apart magnetic memory element stacks over said plurality of first conductive layers, wherein each of said magnetic memory element stacks is formed by the steps of forming a first magnetic layer over a corresponding first conductive layer and forming a second magnetic layer over said first magnetic layer, said second magnetic layer having an associated top conductive layer; forming an insulating material over and in between said spaced apart magnetic memory element stacks; and removing at least a portion of said insulating material over at least one of said memory element stacks to expose the top conductive layer of said at least one memory element stack.
21. A method of forming a magnetic random access memory, said method comprising:
forming a plurality of spaced apart first conductive layers over an insulating layer formed over a substrate; forming a plurality of spaced apart magnetic memory element stacks over said plurality of first conductive layers, wherein each of said magnetic memory element stacks is formed by the steps of forming a first magnetic layer over a corresponding first conductive layer and forming a second magnetic layer over said first magnetic layer, said second magnetic layer having an associated a top conductive layer; forming an insulating material over and in between said spaced apart magnetic memory element stacks; removing at least a portion of said insulating material to expose upper surfaces of a plurality of said memory element stacks; and forming a plurality of spaced apart second conductive layers over respective sets of said exposed upper surfaces, said second conductive layers running substantially orthogonal to said first conductive layers, one of said first and second conductive layers being bit lines and the other of said first and second conductive layers being word lines.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
9. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
17. The method of
22. The method of
23. The method of
24. The method of
25. The method of
26. The method of
27. The method of
28. The method of
29. The method of
31. The method of
33. The method of
34. The method of
35. The method of
36. The method of
37. The method of
38. The method of
39. The method of
|
The present invention relates MRAM semiconductor structures and, more particularly, to a method of forming self-aligned contacts in MRAM structures.
Magnetic random access memories (MRAMs) employ magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, which in turn depend on the alternative states of magnetization of thin magnetic multilayer films forming each memory cell. As such, the MRAM cell has two stable magnetic configurations, high resistance representing a logic state 0 and low resistance representing a logic state 1, or vice versa.
A typical multilayer-film MRAM includes a number of bit or digit lines intersected by a number of word lines. At each intersection, a film of a magnetically coercive material is interposed between the corresponding bit line and word line. Thus, this magnetic material and the multilayer films from the digit lines form a magnetic memory cell which stores a bit of information.
The basic memory element of an MRAM is a patterned structure of a multilayer material, which is typically composed of a stack of different materials, such as copper (Cu), tantalum (Ta), permalloy (NiFe) or aluminum oxide (Al2O3), among others. The stack may contain as many as ten different overlapping material layers and the layer sequence may repeat up to ten times. Fabrication of such stacks requires deposition of the thin magnetic materials layer by layer, according to a predefined order.
Many attempts are currently being made to integrate structures of magnetic random access memories, such as the MRAM stack 22 of
As known in the art, the photolithography techniques employ a mask that must be previously aligned to define small openings in such MRAM structures. With increased packing density of MRAM cells, however, there is a need for minimizing if not eliminating mask misalignment problems posed by the conventional photolithography techniques when forming small contact openings from MRAM stacks to adjacent circuitry. Accordingly, there is a need for an improved method for fabricating high quality MRAM structures, such as pinned layers and digit lines, which are highly integrated with a CMOS circuit, and which have self-aligned contacts that minimize the misalignment drawbacks of the prior art.
The present invention provides a method for forming self-aligned MRAM contacts for MRAM structures, such as magnetic layers of an MRAM stack, formed over various underlayers of an integrated circuit substrate. In an exemplary embodiment of the invention, MRAM stacks are formed to include a top layer of a conductive material, such as tungsten nitrogen. An insulating material is formed over the whole substrate including the MRAM stacks. The insulating material is subsequently chemically mechanically polished (CMP) to expose the upper surface of such conductive material and to form a self-aligned MRAM contact on a respective MRAM stack. Subsequent word lines and conductive plugs are formed over the self-aligned MRAM contacts.
These and other features and advantages of the invention will be more apparent from the following detailed description which is provided in connection with the accompanying drawings, which illustrate exemplary embodiments of the invention.
In the following detailed description, reference is made to various exemplary embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention.
The term "substrate" used in the following description may include any semiconductor-based structure that has an exposed semiconductor surface. Structure must be understood to include silicon, silicon-on insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could be silicon-germanium, germanium, or gallium arsenide. When reference is made to substrate in the following description, previous process steps may have been utilized to form regions or junctions in or on the base semiconductor or foundation.
The term "metal" is intended to include not only elemental metal, but metal with other trace metals or in various alloyed combinations with other metals as known in the semiconductor art. The term "metal" is also intended to include conductive oxides of such metals, as well as doped semiconductors and their respective conductive oxides.
Referring now to the drawings, where like elements are designated by like reference numerals,
Referring now to
Next, as illustrated in
Although
An etch step is next performed to obtain grooves 58 in the insulating layer 54, as illustrated in
Subsequent to the formation of the grooves 58 (FIGS. 7-8), a thin barrier layer 59 is formed in the grooves 58 and over the insulating layer 54, and then chemical mechanical polished to remove barrier layer material from the top portions of the insulating layer 54, as shown in FIG. 9. The barrier layer 59 may comprise bonding materials such as tantalum (Ta), titanium (Ti), titanium-tungsten (TiW), titanium nitride (TiN) or chromium (Cr), among others. The barrier layer 59 forms a strong mechanical and chemical bond between the conductive material which will be formed later and the insulating layer 54 to help prevent peeling of the formed conductive layer from the insulating layer. In a preferred embodiment of the invention, the barrier layer 59 is formed of sputtered tantalum. In this embodiment, tantalum is deposited to a thickness of about 5 nm to about 10 nm.
Next, as illustrated in
The conductive material layer 60 is formed over the barrier layer 59 by deposition, for example, and then excess material is removed to form metal lines 62 (FIG. 11). In an exemplary embodiment of the present invention, the excess conductive material layer 60 is removed by means of chemical mechanical polishing (CMP) or a well-known RIE dry etching process. Either way, the top surfaces of the barrier layer 59 and the metal lines 62 are substantially flat and uniform across the entire surface of the substrate, as shown in FIG. 11. Each metal line 62 will form the bit or digit line of a conventional MRAM structure.
After the CMP polishing process, the processing steps for the completion of the MRAM structures 100 having self-aligned MRAM contacts 99 (
In an exemplary embodiment of the present invention and as illustrated in
Following the deposition of the layers 71, 73, 75 and 77, a nonmagnetic, electrically nonconductive layer 80 formed of, for example, aluminum oxide (Al2O3) (of about 5-25 Angstroms thick, more preferably of about 15 Angstroms thick) is next formed overlying the first magnetic member 79, as shown in FIG. 13. Although aluminum oxide is the preferred material, it must be understood that the invention is not limited to its use, and other nonmagnetic materials, such as copper (Cu), titanium oxide (TiO2), magnesium oxide (MgO), silicon oxide (SiO2) or aluminum nitride (AlN), may be used also.
Referring now to
In an exemplary embodiment of the present invention, the conductive layer 85 may be formed of tungsten nitrogen (WN), which is deposited to a thickness of about 100-400 Angstroms, more preferably of about 200-300 Angstroms. However, the invention is not limited to this exemplary embodiment, and other conductive materials, for example metals such as tungsten (W), copper (Cu), gold (Au) or platinum (Pt), among others, may be used also, as desired.
Next, layers 71, 73, 75, 77, 80, 81, 83 and 85 (
Patterning of the plurality of layers forming the pinned and sense layers of the MRAM structures 100 (FIG. 16), that is patterning of layers 71, 73, 75, 77, 80, 81, 83 and 85 may be accomplished by ion milling which typically involves physical sputtering of each layer by an argon ion beam. Patterning may be also accomplished by using a reactive plasma etch, performed, for example, in electron cyclotron resonance (ECR) or other high density plasmas, such as an inductively coupled plasma system, or a helicon plasma system containing chlorine as the source gas. A mixture of chlorine with other gases, such as argon, neon or helium, among others, may be used also. In any event, the pinned and sense layers 91, 92 are patterned and etched so that the pinned layers 91 correspond to the metal lines 62 that form the bottom electrodes of the pinned layers 91.
Next, an insulating layer 95 (
Subsequent to the formation of the insulating layer 95 (FIG. 17), portions of the insulating layer 95 that are formed over the top surface of the MRAM structures 100 are removed by means of chemical mechanical polishing (CMP) or well-known RIE dry etching processes. In an exemplary embodiment of the invention, the insulating layer 95 is chemical mechanical polished so that an abravise polish removes the top surface of the insulating layer 95 above the MRAM structures 100, down to or near the planar surface of the top surface of the conductive layer 85, to form respective self-aligned MRAM contacts 99 in a polished insulating layer 96, as illustrated in FIG. 18. This way, the conductive layer 85, which was formed as part of the sense layer 92 of the MRAM structure 100, acts as a polishing stop layer in the formation of the self-aligned contacts 99.
Additional steps to create a functional MRAM cell having a self-aligned contact may be carried out. Thus, additional insulating layers and conductive plugs from the self-aligned MRAM contacts 99 to word line conductors, to enable bidirectional current flow in the presence of a read and write signal, may be formed to complete the fabrication process of such MRAM structures. For example,
Although
A typical processor based system 400 which includes a memory circuit 448, for example an MRAM with MRAM cell structures 100 having self-aligned MRAM contacts 99 (
In the case of a computer system, the processor system may include peripheral devices such as a floppy disk drive 454 and a compact disk (CD) ROM drive 456 which also communicate with CPU 444 over the bus 452. Memory 448 may be combined with the processor, i.e. CPU 444, in a single integrated circuit.
Although the exemplary embodiments described above illustrate the formation of three MRAM cell structures 100 having respective self-aligned MRAM contacts 99 (
The present invention is thus not limited to the details of the illustrated embodiment. Accordingly, the above description and drawings are only to be considered illustrative of exemplary embodiments which achieve the features and advantages of the present invention. Modifications and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.
Patent | Priority | Assignee | Title |
10003014, | Jun 20 2014 | International Business Machines Corporation; CROCUS TECHNOLOGY | Method of forming an on-pitch self-aligned hard mask for contact to a tunnel junction using ion beam etching |
10134980, | Apr 04 2014 | Samsung Electronics Co., Ltd. | Magnetoresistive random access memory device |
11195993, | Sep 16 2019 | International Business Machines Corporation | Encapsulation topography-assisted self-aligned MRAM top contact |
11374170, | Sep 25 2018 | Applied Materials, Inc | Methods to form top contact to a magnetic tunnel junction |
6984530, | Mar 29 2004 | SAMSUNG ELECTRONICS CO , LTD | Method of fabricating a MRAM device |
7015059, | Jan 30 2003 | Renesas Electronics Corporation | Thin film magnetic memory device and manufacturing method therefor |
7119388, | Apr 11 2002 | OVONYX MEMORY TECHNOLOGY, LLC | MRAM device fabricated using chemical mechanical polishing |
7122385, | Nov 05 2002 | Kabushiki Kaisha Toshiba | Magnetic memory device having magnetic circuit and method of manufacture thereof |
7285811, | Apr 11 2002 | OVONYX MEMORY TECHNOLOGY, LLC | MRAM device for preventing electrical shorts during fabrication |
8021897, | Feb 19 2009 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods of fabricating a cross point memory array |
8105867, | Nov 18 2008 | SanDisk Technologies LLC | Self-aligned three-dimensional non-volatile memory fabrication |
8207557, | Feb 19 2009 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Cross-point memory structures |
8530939, | Feb 19 2009 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Cross-point memory structures |
8802451, | Feb 29 2008 | AVALANCHE TECHNOLOGY INC | Method for manufacturing high density non-volatile magnetic memory |
9306156, | Feb 18 2014 | Samsung Electronics Co., Ltd. | Methods of manufacturing a magnetoresistive random access memory device |
9525125, | Aug 20 2015 | International Business Machines Corporation | Linear magnetoresistive random access memory device with a self-aligned contact above MRAM nanowire |
9735349, | Apr 04 2014 | Samsung Electronics Co., Ltd. | Magnetoresistive random access memory device and method of manufacturing the same |
Patent | Priority | Assignee | Title |
5659499, | Nov 24 1995 | Everspin Technologies, Inc | Magnetic memory and method therefor |
5841692, | Mar 18 1996 | GLOBALFOUNDRIES Inc | Magnetic tunnel junction device with antiferromagnetically coupled pinned layer |
5940319, | Aug 31 1998 | Everspin Technologies, Inc | Magnetic random access memory and fabricating method thereof |
6153443, | Dec 21 1998 | Everspin Technologies, Inc | Method of fabricating a magnetic random access memory |
6269018, | Apr 13 2000 | International Business Machines Corporation | Magnetic random access memory using current through MTJ write mechanism |
6358756, | Feb 07 2001 | OVONYX MEMORY TECHNOLOGY, LLC | Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme |
6368878, | Feb 10 1998 | GLOBALFOUNDRIES Inc | Intentional asymmetry imposed during fabrication and/or access of magnetic tunnel junction devices |
6413788, | Feb 28 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Keepers for MRAM electrodes |
6555858, | Nov 15 2000 | Everspin Technologies, Inc | Self-aligned magnetic clad write line and its method of formation |
20010040778, | |||
20020132473, | |||
EP1054449, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 08 2001 | LEE, ROGER | Micron Technologies, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 011611 | /0864 | |
Mar 15 2001 | Micron Technology, Inc. | (assignment on the face of the patent) | / | |||
Apr 26 2016 | Micron Technology, Inc | MORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENT | PATENT SECURITY AGREEMENT | 038954 | /0001 | |
Apr 26 2016 | Micron Technology, Inc | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE SECURITY INTEREST | 043079 | /0001 | |
Apr 26 2016 | Micron Technology, Inc | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 038669 | /0001 | |
Jun 29 2018 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Micron Technology, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 047243 | /0001 | |
Jul 03 2018 | MICRON SEMICONDUCTOR PRODUCTS, INC | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 047540 | /0001 | |
Jul 03 2018 | Micron Technology, Inc | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 047540 | /0001 | |
Jul 31 2019 | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | Micron Technology, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 051028 | /0001 | |
Jul 31 2019 | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | MICRON SEMICONDUCTOR PRODUCTS, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 051028 | /0001 | |
Jul 31 2019 | MORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENT | Micron Technology, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 050937 | /0001 |
Date | Maintenance Fee Events |
Feb 01 2008 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Feb 07 2008 | RMPN: Payer Number De-assigned. |
Sep 21 2011 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Feb 10 2016 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Aug 24 2007 | 4 years fee payment window open |
Feb 24 2008 | 6 months grace period start (w surcharge) |
Aug 24 2008 | patent expiry (for year 4) |
Aug 24 2010 | 2 years to revive unintentionally abandoned end. (for year 4) |
Aug 24 2011 | 8 years fee payment window open |
Feb 24 2012 | 6 months grace period start (w surcharge) |
Aug 24 2012 | patent expiry (for year 8) |
Aug 24 2014 | 2 years to revive unintentionally abandoned end. (for year 8) |
Aug 24 2015 | 12 years fee payment window open |
Feb 24 2016 | 6 months grace period start (w surcharge) |
Aug 24 2016 | patent expiry (for year 12) |
Aug 24 2018 | 2 years to revive unintentionally abandoned end. (for year 12) |