A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The lanthanide doped TiOx dielectric layer is arranged as a layered structure of one or more monolayers of the lanthanide doped TiOx. The dopant may be selected from a group consisting of Nd, Tb, and Dy.
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1. An electronic device comprising:
a substrate;
a dielectric layer having a lanthanide doped TiOx film, the lanthanide doped TiOx film structured as one or more monolayers, the dielectric layer disposed on the substrate.
7. A capacitor, comprising:
a first conductive layer on a substrate;
a dielectric layer containing a lanthanide doped TiOx film, the lanthanide doped TiOx film structured as one or more monolayers, the dielectric layer disposed on the first conductive layer; and
a second conductive layer disposed on the dielectric layer.
28. A memory comprising:
a memory array having a number of transistors, at least one transistor including a gate coupled to a dielectric film containing lanthanide doped TiOx, the lanthanide doped TiOx layer structured as one or more monolayers, the dielectric film disposed above a body region between a source region and a drain region.
13. A transistor comprising:
a body region between a source region and a drain region on a substrate;
a dielectric film containing having a lanthanide doped TiOx layer, the lanthanide doped TiOx layer structured as one or more monolayers, the dielectric disposed above the body region between a source region and a drain region; and
a gate coupled to the dielectric film.
22. A transistor comprising:
a body region between a source region and a drain region on a substrate; and
a stack disposed on the body region between a source region and a drain region, the stack including a first dielectric layer containing a first lanthanide doped TiOx layer, the first lanthanide doped TiOx layer structured as one or more monolayers, the first dielectric layer disposed between and contacting a floating gate and a control gate.
34. An electronic system comprising:
a processor;
a memory, the memory including a memory array having a number of transistors, at least one transistor having a gate coupled to a dielectric film containing lanthanide doped TiOx, the lanthanide doped TiOx layer structured as one or more monolayers, the dielectric film disposed above a body region between a source region and a drain region; and
a system bus that couples the processor to the memory.
2. The electronic device of
6. The electronic device of
9. The capacitor of
12. The capacitor of
15. The transistor of
16. The transistor of
17. The transistor of
19. The transistor of
23. The transistor of
24. The transistor of
25. The transistor of
26. The transistor of
29. The memory of
30. The memory of
31. The memory of
32. The memory of
35. The electronic system of
36. The electronic system of
38. The electronic system of
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This application is a divisional under 37 CFR 1.53(b) of U.S. application Ser. No. 10/233,309, filed Aug. 29, 2002, now U.S. Pat. No. 7,084,078, which application is incorporated herein by reference.
This application is related to the following, commonly assigned applications, incorporated herein by reference:
U.S. application Ser. No. 10/219,870, issued as U.S. Pat. No. 6,884,739, entitled: “Lanthanide doped TiOx Dielectric Films By Plasma Oxidation,”
U.S. application Ser. No. 10/219,878, issued as U.S. Pat. No. 6,790,791, entitled: “Lanthanide doped TiOx Dielectric Films,”
U.S. application Ser. No. 10/137,058, entitled: “Atomic Layer Deposition and Conversion,”
U.S. application Ser. No. 10/137,168, issued as U.S. Pat. No. 7,160,577, entitled: “Methods, Systems, and Apparatus for Atomic-Layer Deposition of Aluminum Oxides in Integrated Circuits,” and
U.S. application Ser. No. 09/797,324, issued as U.S. Pat. No. 6,852,167, entitled: “Methods, Systems, and Apparatus for Uniform Chemical-Vapor Depositions.”
The invention relates to semiconductor devices and device fabrication. Specifically, the invention relates to gate dielectric layers and their method of fabrication.
The semiconductor device industry has a market driven need to improve speed performance, improve its low static (off-state) power requirements, and adapt to a wide range of power supply and output voltage requirements for it silicon based microelectronic products. In particular, in the fabrication of transistors, there is continuous pressure to reduce the size of devices such as transistors. The ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs). The smaller devices are frequently powered by batteries, where there is also pressure to reduce the size of the batteries, and to extend the time between battery charges. This forces the industry to not only design smaller transistors, but to design them to operate reliably with lower power supplies.
Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of its basic devices, primarily, the silicon based metal-oxide-semiconductor field effect transistor (MOSFET). A common configuration of such a transistor is shown in
In fabricating transistors to be smaller in size and reliably operate on lower power supplies, one important design criteria is gate dielectric 140. The mainstay for forming the gate dielectric has been silicon dioxide, SiO2. A thermally grown amorphous SiO2 layer provides an electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying Si provides a high quality interface as well as superior electrical isolation properties. In typical processing, use of SiO2 on Si has provided defect charge densities on the order of 1010/cm2, midgap interface state densities of approximately 1010/cm2 eV, and breakdown voltages in the range of 15 MV/cm. With such qualities, there would be no apparent need to use a material other than SiO2, but increased scaling and other requirements for gate dielectrics create the need to find other dielectric materials to be used for a gate dielectric.
In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors.
The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
A gate dielectric 140 of
A SiO2 layer of thickness, t, deposited on a Si surface as a gate dielectric will have a teq larger than its thickness, t. This teq results from the capacitance in the surface channel on which the SiO2 is deposited due to the formation of a depletion/inversion region. This depletion/inversion region can result in teq being from 3 to 6 Angstroms (Å) larger than the SiO2 thickness, t. Thus, with the semiconductor industry driving to someday scale the gate dielectric equivalent oxide thickness to under 10 Å, the physical thickness requirement for a SiO2 layer used for a gate dielectric would be need to be approximately 4 to 7 Å.
Additional requirements on a SiO2 layer would depend on the gate electrode used in conjunction with the SiO2 gate dielectric. Using a conventional polysilicon gate would result in an additional increase in teq for the SiO2 layer. This additional thickness could be eliminated by using a metal gate electrode, though metal gates are not currently used in typical complementary metal-oxide-semiconductor field effect transistor (CMOS) technology. Thus, future devices would be designed towards a physical SiO2 gate dielectric layer of about 5 Å or less. Such a small thickness requirement for a SiO2 oxide layer creates additional problems.
Silicon dioxide is used as a gate dielectric, in part, due to its electrical isolation properties in a SiO2—Si based structure. This electrical isolation is due to the relatively large band gap of SiO2 (8.9 eV) making it a good insulator from electrical conduction. Signification reductions in its band gap would eliminate it as a material for a gate dielectric. As the thickness of a SiO2 layer decreases, the number of atomic layers, or monolayers of the material in the thickness decreases. At a certain thickness, the number of monolayers will be sufficiently small that the SiO2 layer will not have a complete arrangement of atoms as in a larger or bulk layer. As a result of incomplete formation relative to a bulk structure, a thin SiO2 layer of only one or two monolayers will not form a full band gap. The lack of a full band gap in a SiO2 gate dielectric would cause an effective short between an underlying Si channel and an overlying polysilicon gate. This undesirable property sets a limit on the physical thickness to which a SiO2 layer can be scaled. The minimum thickness due to this monolayer effect is thought to be about 7-8 Å. Therefore, for future devices to have a teq less than about 10 Å, other dielectrics than SiO2 need to be considered for use as a gate dielectric.
For a typical dielectric layer used as a gate dielectric, the capacitance is determined as one for a parallel plate capacitance: C=κ∈0A/t, where κ is the dielectric constant, ∈0 is the permittivity of free space, A is the area of the capacitor, and t is the thickness of the dielectric. The thickness, t, of a material is related to its teq for a given capacitance, with SiO2 having a dielectric constant κox=3.9, as
t=(κ/κox)teq=(κ/3.9)teq.
Thus, materials with a dielectric constant greater than that of SiO2, 3.9, will have a physical thickness that can be considerably larger than a desired teq, while providing the desired equivalent oxide thickness. For example, an alternate dielectric material with a dielectric constant of 10 could have a thickness of about 25.6 Å to provide a teq of 10 Å, not including any depletion/inversion layer effects. Thus, a reduced equivalent oxide thickness for transistors can be realized by using dielectric materials with higher dielectric constants than SiO2.
The thinner equivalent oxide thickness required for lower transistor operating voltages and smaller transistor dimensions may be realized by a significant number of materials, but additional fabricating requirements makes determining a suitable replacement for SiO2 difficult. The current view for the microelectronics industry is still for Si based devices. This requires that the gate dielectric employed be grown on a silicon substrate or silicon layer, which places significant restraints on the substitute dielectric material. During the formation of the dielectric on the silicon layer, there exists the possibility that a small layer of SiO2 could be formed in addition to the desired dielectric. The result would effectively be a dielectric layer consisting of two sublayers in parallel with each other and the silicon layer on which the dielectric is formed. In such a case, the resulting capacitance would be that of two dielectrics in series. As a result, the teq of the dielectric layer would be the sum of the SiO2 thickness and a multiplicative factor of the thickness of the dielectric being formed, written as
teq=tSiO2+(κox/κ)t.
Thus, if a SiO2 layer is formed in the process, the teq is again limited by a SiO2 layer. In the event that a barrier layer is formed between the silicon layer and the desired dielectric in which the barrier layer prevents the formation of a SiO2 layer, the teq would be limited by the layer with the lowest dielectric constant. However, whether a single dielectric layer with a high dielectric constant or a barrier layer with a higher dielectric constant than SiO2 is employed, the layer interfacing with the silicon layer must provide a high quality interface to maintain a high channel carrier mobility.
In a recent article by G. D. Wilk et al., Journal of Applied Physics, vol. 89: no. 10, pp. 5243-5275 (2001), material properties of high dielectric materials for gate dielectrics were discussed. Among the information disclosed was the viability of Al2O3 as a substitute for SiO2. Al2O3 was disclosed has having favourable properties for use as a gate dielectric such as high band gap, thermodynamic stability on Si up to high temperatures, and an amorphous structure. In addition, Wilk disclosed that forming a layer of Al2O3 on silicon does not result in a SiO2 interfacial layer. However, the dielectric constant of Al2O3 is only 9, where thin layers may have a dielectric constant of about 8 to about 10. Though the dielectric constant of Al2O3 is in an improvement over SiO2, a higher dielectric constant for a gate dielectric is desirable. Other dielectrics and their properties discussed by Wilk include
Band gap
Material
Dielectric Constant (κ)
Eg (eV)
Crystal Structure(s)
SiO2
3.9
8.9
Amorphous
Si3N4
7
5.1
Amorphous
Al2O3
9
8.7
Amorphous
Y2O3
15
5.6
Cubic
La2O3
30
4.3
Hexagonal, Cubic
Ta2O5
26
4.5
Orthorhombic
TiO2
80
3.5
Tetrag. (rutile, anatase)
HfO2
25
5.7
Mono., Tetrag., Cubic
ZrO2
25
7.8
Mono., Tetrag., Cubic
One of the advantages using SiO2 as a gate dielectric has been that the formation of the SiO2 layer results in an amorphous gate dielectric. Having an amorphous structure for a gate dielectric is advantageous because grain boundaries in polycrystalline gate dielectrics provide high leakage paths. Additionally, grain size and orientation changes throughout a polycrystalline gate dielectric can cause variations in the film's dielectric constant. The abovementioned material properties including crystal structure are for the materials in a bulk form. The materials having the advantage of a high dielectric constants relative to SiO2 also have the disadvantage of a crystalline form, at least in a bulk configuration. The best candidates for replacing SiO2 as a gate dielectric are those with high dielectric constant, which can be fabricated as a thin layer with an amorphous form.
In one embodiment, a method of forming a dielectric film includes the formation of lanthanide doped TiOx by atomic layer deposition (ALD). The ALD formation of the lanthanide doped TiOx layer includes depositing titanium and oxygen onto a substrate surface by atomic layer deposition, and depositing a lanthanide dopant by atomic layer deposition onto the substrate surface containing the deposited titanium and oxygen. In one embodiment, the dopant is selected from a group consisting of Nd, Tb, and Dy. The lanthanide doped TiOx layer thickness is controlled by processing a total number of ALD cycles to produce the desired thickness.
A dielectric film containing lanthanide doped TiOx has a larger dielectric constant than silicon dioxide, a relatively small leakage current, and good stability with respect to a silicon based substrate. Embodiments include forming capacitors, transistors, memory devices, and electronic systems having dielectric layers containing atomic layer deposited lanthanide doped TiOx.
Other embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric films containing atomic layer deposited lanthanide doped TiOx. Such dielectric films provide a significantly thinner equivalent oxide thickness compared with a silicon oxide layer having the same physical thickness. Alternatively, such dielectric films provide a significantly thicker physical thickness than a silicon oxide layer having the same equivalent oxide thickness.
Based solely on the size of the dielectric constant, titanium oxide, TiO2, appears to be an excellent candidate for replacing SiO2. However, TiO2 does not provide the electrical properties generally desired for integrated circuits, such as, high electric field breakdown and low leakage current. Dielectric films substituting various cations, including the lanthanides Nd, Tb, and Dy, into amorphous TiOx films by magnetron sputtering were found to provide improved electric field breakdown and leakage current with respect to undoped TiO2 films. See, R. B. Dover, Applied Physics Letters, vol. 74: no. 20, pp. 3041-3043 (2001).
However, another consideration for selecting the material and method for forming a dielectric film for use in electronic devices and systems concerns the roughness of a dielectric film on a substrate. Surface roughness of the dielectric film has a significant effect on the electrical properties of the gate oxide, and the resulting operating characteristics of the transistor. The leakage current through a physical 1.0 nm gate oxide increases by a factor of 10 for every 0.1 increase in the root-mean-square (RMS) roughness.
During a conventional sputtering deposition process stage, particles of the material to be deposited bombard the surface at a high energy. When a particle hits the surface, some particles adhere, and other particles cause damage. High energy impacts remove body region particles creating pits. The surface of such a deposited layer can have a rough contour due to the rough interface at the body region.
In an embodiment according to the teachings of the present invention, a lanthanide doped TiOx dielectric film having a substantially smooth surface relative to other processing techniques is formed using atomic layer deposition (ALD). Further, forming a dielectric film using atomic layer deposition can provide for controlling transitions between material layers. Thus, atomic layer deposited lanthanide doped TiOx dielectric films can have an engineered transition with a substrate surface that has a substantially reduced or no interfacial SiO2 layer.
ALD, also known as atomic layer epitaxy (ALE), was developed in the early 1970's as a modification of chemical vapor deposition (CVD) and is also called “alternatively pulsed-CVD.” In ALD, gaseous precursors are introduced one at a time to the substrate surface mounted within a reaction chamber (or reactor). This introduction of the gaseous precursors takes the form of pulses of each gaseous precursor. Between the pulses, the reaction chamber is purged with a gas, which in many cases is an inert gas, or evacuated.
In a chemisorption-saturated ALD (CS-ALD) process, during the first pulsing phase, reaction with the substrate occurs with the precursor saturatively chemisorbed at the substrate surface. Subsequent pulsing with a purging gas removes precursor excess from the reaction chamber.
The second pulsing phase introduces another precursor on the substrate where the growth reaction of the desired film takes place. Subsequent to the film growth reaction, reaction byproducts and precursor excess are purged from the reaction chamber. With favourable precursor chemistry where the precursors adsorb and react with each other on the substrate aggressively, one ALD cycle can be preformed in less than one second in properly designed flow type reaction chambers. Typically, precursor pulse times range from about 0.5 sec to about 2 to 3 seconds.
In ALD, the saturation of all the reaction and purging phases makes the growth self-limiting. This self-limiting growth results in large area uniformity and conformality, which has important applications for such cases as planar substrates, deep trenches, and in the processing of porous silicon and high surface area silica and alumina powders. Significantly, ALD provides for controlling film thickness in a straightforward manner by controlling the number of growth cycles.
ALD was originally developed to manufacture luminescent and dielectric films needed in electroluminescent displays. Significant efforts have been made to apply ALD to the growth of doped zinc sulfide and alkaline earth metal sulfide films. Additionally, ALD has been studied for the growth of different epitaxial II-V and II-VI films, nonepitaxial crystalline or amorphous oxide and nitride films and multilayer structures of these. There also has been considerable interest towards the ALD growth of silicon and germanium films, but due to the difficult precursor chemistry, this has not been very successful.
The precursors used in an ALD process may be gaseous, liquid or solid. However, liquid or solid precursors must be volatile. The vapor pressure must be high enough for effective mass transportation. Also, solid and some liquid precursors need to be heated inside the reaction chamber and introduced through heated tubes to the substrates. The necessary vapor pressure must be reached at a temperature below the substrate temperature to avoid the condensation of the precursors on the substrate. Due to the self-limiting growth mechanisms of ALD, relatively low vapor pressure solid precursors can be used though evaporation rates may somewhat vary during the process because of changes in their surface area.
There are several other requirements for precursors used in ALD. The precursors must be thermally stable at the substrate temperature because their decomposition would destroy the surface control and accordingly the advantages of the ALD method which relies on the reaction of the precursor at the substrate surface. A slight decomposition, if slow compared to the ALD growth, can be tolerated.
The precursors have to chemisorb on or react with the surface, though the interaction between the precursor and the surface as well as the mechanism for the adsorption is different for different precursors. The molecules at the substrate surface must react aggressively with the second precursor to form the desired solid film. Additionally, precursors should not react with the film to cause etching, and precursors should not dissolve in the film. Using highly reactive precursors in ALD contrasts with the selection of precursors for conventional CVD.
The by-products in the reaction must be gaseous in order to allow their easy removal from the reaction chamber. Further, the by-products should not react or adsorb on the surface.
In a reaction sequence ALD (RS-ALD) process, the self-limiting process sequence involves sequential surface chemical reactions. RS-ALD relies on chemistry between a reactive surface and a reactive molecular precursor. In an RS-ALD process, molecular precursors are pulsed into the ALD reaction chamber separately. The metal precursor reaction at the substrate is typically followed by an inert gas pulse to remove excess precursor and by-products from the reaction chamber prior to pulsing the next precursor of the fabrication sequence.
By RS-ALD, films can be layered in equal metered sequences that are all identical in chemical kinetics, deposition per cycle, composition, and thickness. RS-ALD sequences generally deposit less than a full layer per cycle. Typically, a deposition or growth rate of about 0.25 to about 2.00 Å per RS-ALD cycle can be realized.
The advantages of RS-ALD include continuity at an interface, conformality over a substrate, use of low temperature and mildly oxidizing processes, growth thickness dependent solely on the number of cycles performed, and ability to engineer multilayer laminate films with resolution of one to two monolayers. RS-ALD allows for deposition control on the order on monolayers and the ability to deposit monolayers of amorphous films.
Herein, a sequence refers to the ALD material formation based on an ALD reaction of one precursor with its reactant precursor. For example, forming titanium oxide from a TiI4 precursor and H2O2, as its reactant precursor, forms one embodiment of a titanium/oxygen sequence, which can also be referred to as titanium sequence. A cycle of a sequence includes pulsing a precursor, pulsing a purging gas for the precursor, pulsing a reactant precursor, and pulsing the reactant's purging gas.
In an embodiment, a layer of lanthanide doped TiOx is formed on a substrate mounted in a reaction chamber using ALD in a repetitive sequence using precursor gases individually pulsed into the reaction chamber. Alternately, solid or liquid precursors can be used in an appropriately designed reaction chamber. ALD formation of other materials is disclosed in co-pending, commonly assigned U.S. patent application: entitled “Atomic Layer Deposition and Conversion,” Ser. No. 10/137,058, and “Methods, Systems, and Apparatus for Atomic-Layer Deposition of Aluminum Oxides in Integrated Circuits,” Ser. No. 10/137,168, issued as U.S. Pat. No. 7,160,577.
In
Also included in the ALD system are purging gas sources 261, 262, each of which is coupled to mass-flow controllers 266, 267, respectively. Furthermore, additional purging gas sources can be constructed in ALD system 200, one purging gas source for each precursor gas. For a process that uses the same purging gas for multiple precursor gases less purging gas sources are required for ALD system 200. Gas sources 251-254 and purging gas sources 261-262 are coupled by their associated mass-flow controllers to a common gas line or conduit 270 which is coupled to the gas-distribution fixture 240 inside the reaction chamber 220. Gas conduit 270 is also coupled to vacuum pump, or exhaust pump, 281 by mass-flow controller 286 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from the gas conduit.
Vacuum pump, or exhaust pump, 282 is coupled by mass-flow controller 287 to remove excess precursor gases, purging gases, and by-product gases at the end of a purging sequence from reaction chamber 220. For convenience, control displays, mounting apparatus, temperature sensing devices, substrate maneuvering apparatus, and necessary electrical connections as are known to those skilled in the art are not shown in
The use, construction and fundamental operation of reaction chambers for deposition of films are understood by those of ordinary skill in the art of semiconductor fabrication. The present invention may be practiced on a variety of such reaction chambers without undue experimentation. Furthermore, one of ordinary skill in the art will comprehend the necessary detection, measurement, and control techniques in the art of semiconductor fabrication upon reading the disclosure.
The elements of ALD system 200 can be controlled by a computer. To focus on the use of ALD system 200 in the various embodiments of the present invention, the computer is not shown. Those skilled in the art can appreciate that the individual elements such as pressure control, temperature control, and gas flow within ALD system 200 can be under computer control. In one embodiment, instructions stored in a computer readable medium are executed by a computer to accurately control the integrated functioning of the elements of ALD system 200 to form a dielectric film containing lanthanide doped TiOx.
In one embodiment, a method of forming a dielectric film includes depositing titanium and oxygen onto a substrate surface by atomic layer deposition and depositing a lanthanide dopant by atomic layer deposition onto the substrate surface containing the deposited titanium and oxygen. In one embodiment, the titanium sequence and the lanthanide dopant sequence include using precursors that form oxides of the titanium and the lanthanide dopant. For example, precursor TiI4 with H2O2 as its reactant precursor in an ALD process can form TiOx, and precursor La(thd)3 (thd=2,2,6,6-tetramethyl-3,5-heptanedione) with ozone as its reactant precursor in an ALD process can form La2O3.
Depositing the lanthanide dopant includes regulating the deposition of the lanthanide dopant relative to the titanium and oxygen deposited on the substrate surface to form a dielectric layer containing TiOx doped with a predetermined percentage of the lanthanide. In a further embodiment, depositing a lanthanide dopant includes depositing a lanthanide selected from a group consisting of Nd, Tb, and Dy.
The lanthanide dopant can be included in the TiOx film using different embodiments for atomic layer deposition. In one embodiment, a lanthanide can be doped in the TiOx film by pulsing a lanthanide dopant sequence in place of a titanium sequence. The lanthanide dopant level is then controlled by regulating the number of cycles of the lanthanide dopant sequence with respect to the number of cycles of the titanium sequence. In another embodiment, a lanthanide can be doped in the TiOx film by pulsing a lanthanide dopant precursor substantially simultaneously with a titanium precursor. The titanium/lanthanide dopant sequence includes a precursor for oxidizing the titanium/lanthanide dopant at the substrate surface. The lanthanide dopant level is then controlled by regulating the mixture of the titanium containing precursor and the lanthanide containing precursor.
Atomic layer deposition of the individual components of the lanthanide doped TiOx layer allows for individual control of each precursor pulsed into the reaction chamber. Thus, each precursor is pulsed into the reaction chamber for a predetermined period, where the predetermined period can be set separately for each precursor. Repeating the cycle for pulsing a titanium containing precursor and oxygen containing precursor results in a TiOx film whose film thickness is determined by the total number of cycles of the titanium/oxygen sequence completed.
To provide the dopant into this TiOx film, a variation to the repeated cycles is made. In the embodiment discussed above, doping is included in the atomic layer deposition process by pulsing a dopant containing precursor and reactant precursor in place of one or more cycles of the titanium sequence. Associated with the dopant cycle there is also a growth rate substantially constant at a fixed number of angstroms per cycle, for constant environmental conditions in the reaction chamber and constant sequencing parameters in the dopant cycle. However, when a combined cycle consists of a large number of cycles of a titanium sequence for one cycle of a lanthanide dopant cycle, the growth rate for forming the lanthanide doped TiOx dielectric film can be substantially the same as for an undoped TiOx dielectric film.
Depending on the percentage of the lanthanide dopant, the growth rate for the lanthanide doped TiOx dielectric film may vary between that of an undoped TiOx dielectric film towards that of an oxide of the lanthanide dopant. As an example, for a combined cycle having 100 cycles of a titanium sequence and 1 cycle of a lanthanide dopant sequence with a growth rate for the titanium sequence of about 1.2 Å/cycle, a dielectric film grown by ALD processing for 10 combined cycles would have a thickness of about 1200 Å. With a dielectric constant for lanthanide doped TiOx dielectric films ranging from about 50 to about 100, the dielectric film grown with 10 combined cycles has a teq of about 93.6 Å to about 46.8 Å, respectively. As previously discussed, when the number of cycles for a dopant sequence is no longer small with respect to the number of cycles for a titanium sequence, growth rates can vary from that of an undoped TiOx dielectric film. As can be understood by those skilled in the art, particular growth rates can be determined during normal initial testing of the ALD system for processing a lanthanide doped TiOx dielectric film for a given application without undue experimentation.
Alternately, the lanthanide dopant containing precursor can be pulsed simultaneously with the titanium containing precursor. Then, following a gas purge, a reactant precursor that provides an ALD reaction for both the titanium containing precursor and the dopant precursor is pulsed into the reaction. The percentage of the lanthanide dopant can be controlled by regulating the percentage of the lanthanide dopant containing precursor in the precursor mixture that is injected into the reaction chamber to the substrate. The growth per cycle would then depend on the growth rate using the given mixture. As can be understood by those skilled in the art, determining the growth rate for a particular mixture can be determined during normal initial testing of the ALD system for processing a lanthanide doped TiOx dielectric film without undue experimentation.
Additionally, for an embodiment for ALD formation of a lanthanide doped TiOx layer, each precursor can be pulsed into the reaction under separate environmental conditions. The substrate can be maintained at a selected temperature and the reaction chamber maintained at a selected pressure independently for pulsing each precursor. Appropriate temperatures and pressures are maintained dependent on the nature of the precursor, whether the precursor is a single precursor or a mixture of precursors.
Using atomic layer deposition, the pulsing of the precursor gases is separated by purging the reaction chamber with a purging gas following each pulsing of a precursor. In one embodiment, nitrogen gas is used as the purging gas following the pulsing of each precursor used in a cycle to form a layer of lanthanide doped TiOx. Additionally, the reaction chamber can also be purged by evacuating the reaction chamber.
At block 405, a substrate 210 is prepared. The substrate used for forming a transistor is typically a silicon or silicon containing material. In other embodiments, germanium, gallium arsenide, silicon-on-sapphire substrates, or other suitable substrates may be used. This preparation process includes cleaning of substrate 210 and forming layers and regions of the substrate, such as drains and sources of a metal oxide semiconductor (MOS) transistor, prior to forming a gate dielectric. The sequencing of the formation of the regions of the transistor being processed follows typical sequencing that is generally performed in the fabrication of a MOS transistor as is well known to those skilled in the art. Included in the processing prior to forming a gate dielectric is the masking of substrate regions to be protected during the gate dielectric formation, as is typically performed in MOS fabrication. In this embodiment, the unmasked region includes a body region of a transistor, however one skilled in the art will recognize that other semiconductor device structures may utilize this process. Additionally, the substrate 210 in its ready for processing form is conveyed into a position in reaction chamber 220 for ALD processing.
At block 410, a titanium containing precursor is pulsed into reaction chamber 220. In an embodiment, TiI4 is used as a precursor. The TiI4 is pulsed into reaction chamber 220 through the gas-distribution fixture 240 onto substrate 210. The flow of the TiI4 is controlled by mass-flow controller 256 from gas source 251, where the TiI4 is maintained at about 105-110° C. The pressure in reaction chamber is at about 10 mbar. In one embodiment, the substrate temperature is maintained between about 250° C. and about 490° C. In another embodiment, the substrate temperature is maintained between about 250° C. and about 300° C. The TiI4 reacts with the surface of the substrate 210 in the desired region defined by the unmasked areas of the substrate 210. In other embodiments, a titanium containing precursor is selected from a group consisting of TiCl4, Ti(OC2H5)4, and Ti(OC3H7)4.
At block 415, a first purging gas is pulsed into the reaction chamber 220. In particular, nitrogen is used as a purging gas and a carrier gas. The nitrogen flow is controlled by mass-flow controller 266 from the purging gas source 261 into the gas conduit 270. Using the pure nitrogen purge avoids overlap of the precursor pulses and possible gas phase reactions. Following the purge, an oxygen containing precursor is pulsed into the reaction chamber 220, at block 420.
For the titanium sequence using a TiI4 or TiCl4 as the precursor, H2O2 vapor is selected as the precursor acting as a reactant to form a Ti and O on the substrate 210. Alternately, water vapor can be used as the oxygen containing precursor. The H2O2 vapor is pulsed into the reaction chamber 220 through gas conduit 270 from gas source 252 by mass-flow controller 257. The H2O2 vapor aggressively reacts at the surface of substrate 210.
Following the pulsing of an oxygen containing precursor, a second purging gas is injected into the reaction chamber 220, at block 425. Nitrogen gas is used to purge the reaction chamber after pulsing each precursor gas in the titanium/oxygen sequence. Excess precursor gas, and reaction by-products are removed from the system by the purge gas in conjunction with the exhausting of the reaction chamber 220 using vacuum pump 282 through mass-flow controller 287, and exhausting of the gas conduit 270 by the vacuum pump 281 through mass-flow controller 286.
During a TiI4/water vapor sequence, the substrate is held between about 250° C. and about 490° C. by the heating element 230. In other embodiments the substrate is held between about 250° C. and 300° C. The TiI4 pulse time ranges from about 0.2 sec to about 0.5 sec. After the TiI4 pulse, the titanium sequence continues with a purge pulse followed by a H2O2 vapor pulse followed by a purge pulse. In one embodiment, the H2O2 vapor pulse time ranges from about 0.5 sec to about 2.0 sec, and the first and second purging pulse times are each at about 0.5 sec.
At block 430, the pulsing of the titanium containing precursor, the pulsing of the oxygen containing precursor, and the pulsing of the first and second purging gas are repeated for a number of cycles. After repeating the titanium/oxygen sequence for a selected number of cycles, a lanthanide containing precursor is pulsed into the reaction chamber, at block 435. In one embodiment, the lanthanide is selected from a group consisting of Nd, Tb, and Dy.
At block 440, a third purging gas is introduced into the system. Nitrogen gas can also be used as a purging and carrier gas. The nitrogen flow is controlled by mass-flow controller 267 from the purging gas source 262 into the gas conduit 270 and subsequently into the reaction chamber 220. In another embodiment, argon gas is used as the purging gas. Following the pulsing of the third purging gas, a reactant precursor is pulsed into the reaction chamber 220, at block 445. The reactant precursor is selected to produce an atomic layer deposition reaction with the lanthanide containing precursor. The selection of the reactant precursor is based on the selected lanthanide dopant for a particular application.
Following the pulsing of the reactant precursor, a fourth purging gas is injected into the reaction chamber 220, at block 450. Nitrogen gas is used to purge the reaction chamber after pulsing each precursor gas. In another embodiment, argon gas is used as the purging gas. Excess precursor gas, and reaction by-products are removed from the system by the purge gas in conjunction with the exhausting of the reaction chamber 220 using vacuum pump 282 through mass-flow controller 287, and exhausting of the gas conduit 270 by the vacuum pump 281 through mass-flow controller 286.
At block 455, a determination is made as to whether the number of substituted dopant cycles has equaled a predetermined number. The predetermined number of substitution cycles is selected to set the percentage of lanthanide dopant in the TiOx film. In one embodiment, the percentage is set ranging from about 5% to about 40% lanthanide in the lanthanide doped TiOx film. If the number of completed substitution cycles is less than the predetermined number, the lanthanide containing precursor is pulsed into the reaction chamber, at block 435, and the process continues. If the number of completed substitution cycles equals the predetermined number, then a determination is made as to whether a total number of combined cycles has been completed to form a desired thickness, at block 460. If the total number of cycles to form the desired thickness has not been completed, a number of cycles for the titanium/oxygen sequence is repeated, at block 430, and the process continues. If the total number of cycles to form the desired thickness has been completed, the dielectric film containing lanthanide doped TiOx can be annealed. The lanthanide doped TiOx formed is amorphous and remains amorphous after annealing.
The thickness of a lanthanide doped TiOx film is determined by a fixed growth rate for the pulsing periods and precursors used, set at a value such as N nm/combined cycle, dependent upon the lanthanide dopant used and the number of cycles of the lanthanide dopant sequence relative to the titanium sequence that form a combined sequence. For a desired lanthanide doped TiOx film thickness, t, in an application such as forming a gate dielectric of a MOS transistor, the ALD process is repeated for t/N total combined cycles. Once the t/N cycles have completed, no further ALD processing for lanthanide doped TiOx is required.
At block 470, after forming the lanthanide doped TiOx, processing the device having the dielectric layer containing lanthanide doped TiOx is completed. In one embodiment, completing the device includes completing the formation of a transistor. In another embodiment, completing the device includes completing the formation of a capacitor. Alternately, completing the process includes completing the construction of a memory device having a array with access transistors formed with gate dielectrics containing atomic layer deposited lanthanide doped TiOx. Further, in another embodiment, completing the process includes the formation of an electronic system including an information handling device that uses electronic devices with transistors formed with dielectric films containing atomic layer deposited lanthanide doped TiOx. Typically, information handling devices such as computers include many memory devices, having many access transistors.
It can appreciated by those skilled in the art that the elements of a method for forming an atomic layer deposited lanthanide doped TiOx film in the embodiment of
At block 480, a substrate 210 is prepared in a similar manner has at block 405 in
A reactant containing precursor is pulsed into reaction chamber 220, at block 488. The reactant containing precursor provides an oxidizing reaction at substrate 210. A second purging gas is pulsed into reaction chamber 220, at block 490. Completing the pulsing of the second purging gas into reaction chamber 220 completes one cycle for a titanium-lanthanide dopant sequence. Then, it is determined whether the total number of cycles for the titanium-lanthanide dopant sequence has been reached to form the desired thickness for a dielectric film containing lanthanide doped TiOx, at block 492.
If the total number of cycles to form the desired thickness has not been completed, the titanium containing precursor is pulsed into reaction chamber, at block 482, and the process continues. If the total number of cycles to form the desired thickness has been completed, the dielectric film containing lanthanide doped TiOx can be annealed. The lanthanide doped TiOx formed is amorphous and remains amorphous after annealing.
The thickness of a lanthanide doped TiOx film is determined by a fixed growth rate for the pulsing periods and precursors used, set at a value such as N nm/cycle, dependent upon the titanium precursor/lanthanide dopant precursor mixture used. For a desired lanthanide doped TiOx film thickness, t, in an application such as forming a gate dielectric of a MOS transistor, the ALD process is repeated for t/N total cycles. Once the t/N cycles have completed, no further ALD processing for lanthanide doped TiOx is required. After forming the lanthanide doped TiOx, processing the device having the dielectric layer containing lanthanide doped TiOx is completed, at block 494, in a similar manner as for block 470 of
It can appreciated by those skilled in the art that the elements of a method for forming an atomic layer deposited lanthanide doped TiOx film in the embodiment of
Atomic layer deposition of a lanthanide doped TiOx dielectric layer can be processed in a atomic layer deposition system such as ALD system 200 under computer control to perform various embodiments, in accordance with the teachings of the current invention, and operated under computer-executable instructions to perform these embodiments. In an embodiment, a computerized method and the computer-executable instructions for a method for forming a dielectric film can include depositing titanium and oxygen onto a substrate surface by atomic layer deposition, and depositing a lanthanide dopant by atomic layer deposition onto the substrate surface containing the deposited titanium and oxygen. In another embodiment, a computerized method and the computer-executable instructions for a method for forming a dielectric film can include pulsing a titanium containing precursor into a reaction chamber containing a substrate, pulsing an oxygen containing precursor into the reaction chamber, repeating for a number of cycles the pulsing of the titanium containing precursor and the pulsing of the oxygen containing precursor, and substituting a dopant cycle for one or more cycles of the pulsing of the titanium containing precursor and the pulsing of the oxygen containing precursor. The dopant cycle can include pulsing a lanthanide containing precursor into the reaction chamber, and pulsing a reactant precursor into the reaction chamber, where the reactant precursor is selected to produce an oxidizing reaction for the lanthanide at the substrate.
In another embodiment, a computerized method and the computer-executable instructions for a method for forming a dielectric film can include pulsing a titanium containing precursor into a reaction chamber containing a substrate, pulsing a lanthanide containing precursor into the reaction chamber substantially simultaneously with the pulsing of the titanium containing precursor, and pulsing a reactant precursor into the reaction chamber. The reactant precursor provides an oxidizing reaction at the substrate.
In another embodiment, a computerized method and the computer-executable instructions for a method for forming a dielectric film can further include controlling an environment of a reaction chamber. Additionally, the computerized method controls the pulsing of purging gases, one for each precursor gas and pulsing each purging gas after pulsing the associated precursor gas. Using a computer to control parameters for growing the dielectric film provides for processing the dielectric film over a wide range of parameters allowing for the determination of an optimum parameter set for the ALD system used. The computer-executable instructions can be provided in any computer-readable medium. Such computer-readable medium includes, but is not limited to, floppy disks, diskettes, hard disks, CD-ROMS, flash ROMS, nonvolatile ROM, and RAM.
An embodiment of this method can be realized using ALD system 200 of
The computer can also regulate the environment of reactor chamber 220 in which a dielectric film is being formed on substrate 210. The computer regulates the pressure in reaction chamber 220 within a predetermined pressure range by controlling vacuum pumps 281, 282 through mass-flow controllers 286, 287, respectively. The computer also regulates the temperature range for substrate 210 within a predetermined range by controlling heater 230.
For convenience, the individual control lines to elements of ALD 200, as well as a computer, are not shown in
The embodiments described herein provide a process for growing a dielectric film having a wide range of useful equivalent oxide thickness, teq, associated with a dielectric constant in the range from about 47 to about 110. The teq range in accordance with embodiments of the present invention are shown in the following
Physical
Physical
Physical
Physical
Thickness
Thickness
Thickness
Thickness
t = 1.0 nm
t = 5.0 nm
t = 100.0 nm
t = 350 nm
(1.0 × 101 □)
(5.0 × 101 □)
(1 × 103 □)
(3.5 × 103 □)
κ
teq (□)
teq (□)
teq (□)
teq (□)
50
0.78
3.90
78.00
273.00
75
0.52
2.60
52.00
182.00
100
0.39
1.95
39.00
136.50
110
0.35
1.77
35.45
124.09
The relatively large dielectric constant for material layers of lanthanide doped TiOx allows for the engineering of dielectric films having a physical thickness in the 100 nm (1000 Å) range, while achieving a teq of less than 100 Å. Further, growing thin layers, or films, of lanthanide doped TiOx provides for teq in the monolayer range. From above, it is apparent that a film containing lanthanide doped TiOx can be attained with a teq ranging from 1.5 Å to 5 Å. Further, such a film can provide a teq significantly less than 2 or 3 Å, even less than 1.5 Å.
Further, dielectric films of lanthanide doped TiOx formed by atomic layer deposition can provide not only ultra thin teq films, but also films with relatively low leakage current. In addition to using ALD to provide precisely engineered film thicknesses, attainment of relatively low leakage current is engineered by doping with lanthanides selected from a group consisting of Nd, Tb, and Dy. Though a layer of undoped TiOx can be amorphous, which assists the reduction of leakage current, doping with these lanthanides yields a doped amorphous TiOx with enhanced leakage current characteristics. Leakage currents on the order of 10−7 A/cm2 or smaller in TiOx layers doped with Nd, Tb, or Dy can be attained, which are orders of magnitude smaller than for undoped TiOx. Further, the breakdown electric fields are several factors larger for layers of TiOx doped with Nd, Tb, or Dy than for layers of undoped TiOx.
The doping of the TiOx layer with a lanthanide occurs as a substitution of a lanthanide atom for a Ti atom. The resultant doped TiOx layer is a layer of amorphous Ti1-yLyOx, where L is a lanthanide. Controlling the ALD cycles of the titanium sequence and the lanthanide dopant sequence allows a Ti1-yLyOx, or lanthanide doped TiOx, dielectric layer to be formed where the lanthanide, L, can range from about 5% to about 40% of the dielectric layer formed. Such TiOx layers doped with Nd, Tb, or Dy formed by ALD can provide the reduced leakage current and increased breakdown electric fields mentioned above.
The novel processes described above for performing atomic layer deposition of lanthanide doped TiOx can precisely control the thickness of the dielectric layer formed. In addition to providing an ultra thin teq, atomic layer deposition provides for substantially smooth surfaces and limited interfacial layer formation. Additionally, the novel process can be implemented to form transistors, capacitors, memory devices, and other electronic systems including information handling devices. With careful preparation and engineering of the lanthanide doped TiOx layer, limiting the size of interfacial regions, a teq of about 3 Å or lower is anticipated.
A transistor 100 as depicted in
A gate 150 is formed over gate dielectric 140. Typically, forming gate 150 includes forming a polysilicon layer, though a metal gate can be formed in an alternative process. Forming the substrate, the source and drain regions, and the gate is performed using standard processes known to those skilled in the art. Additionally, the sequencing of the various elements of the process for forming a transistor is conducted with standard fabrication processes, also as known to those skilled in the art.
The method for forming an atomic layer deposited lanthanide doped TiOx in various embodiments can be applied to other transistor structures having dielectric layers.
The embodiments of methods for forming lanthanide doped TiOx dielectric films can also be applied to forming capacitors in various integrated circuits, memory devices, and electronic systems. In one embodiment for forming a capacitor, a method can include forming a first conductive layer, forming a dielectric film containing lanthanide doped TiOx on the first conductive layer by depositing titanium and oxygen onto the first conductive layer by atomic layer deposition and depositing a lanthanide dopant by atomic layer deposition onto the first conductive layer containing the deposited titanium and oxygen, and forming a second conductive layer on the dielectric film. ALD formation of the lanthanide doped TiOx film allows the lanthanide to be selectively doped into the TiOx film within a predetermined range for the percentage of the lanthanide in the film. Alternately, a capacitor can be constructed by forming a conductive layer on a substrate, forming a dielectric film containing lanthanide doped TiOx using any of the embodiments described herein, and forming another conductive layer on the dielectric film.
Transistors, capacitors, and other devices having dielectric films containing atomic layer deposited lanthanide doped TiOx formed by the methods described above may be implemented into memory devices and electronic systems including information handling devices. Such information devices can include wireless systems, telecommunication systems, and computers. An embodiment of a computer having a dielectric layer containing atomic layer deposited lanthanide doped TiOx is shown in
A personal computer, as shown in
Microprocessor 706 produces control and address signals to control the exchange of data between memory bus circuit 708 and microprocessor 706 and between memory bus circuit 708 and peripheral circuitry 710. This exchange of data is accomplished over high speed memory bus 720 and over high speed I/O bus 722.
Coupled to memory bus 720 are a plurality of memory slots 712(a-n) which receive memory devices well known to those skilled in the art. For example, single in-line memory modules (SIMMs) and dual in-line memory modules (DIMMs) may be used in the implementation of embodiment of the present invention.
These memory devices can be produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells of memory slots 712. One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell arrays and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode DRAMs require access steps which limit the communication speed of memory circuit 708.
An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on memory bus 720. Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM and Direct RDRAM as well as others such as SRAM or Flash memories.
Control, address and data information provided over memory bus 720 is further represented by individual inputs to DRAM 800, as shown in
As is well known in the art, DRAM 800 includes memory array 810 which in turn comprises rows and columns of addressable memory cells. Each memory cell in a row is coupled to a common word line. The word line is coupled to gates of individual transistors, where at least one transistor has a gate coupled to a gate dielectric containing atomic layer deposited lanthanide doped TiOx in accordance with the method and structure previously described above. Additionally, each memory cell in a column is coupled to a common bit line. Each cell in memory array 810 includes a storage capacitor and an access transistor as is conventional in the art.
DRAM 800 interfaces with, for example, microprocessor 706 through address lines 804 and data lines 802. Alternatively, DRAM 800 may interface with a DRAM controller, a micro-controller, a chip set or other electronic system. Microprocessor 706 also provides a number of control signals to DRAM 800, including but not limited to, row and column address strobe signals RAS and CAS, write enable signal WE, an output enable signal OE and other conventional control signals.
Row address buffer 812 and row decoder 814 receive and decode row addresses from row address signals provided on address lines 804 by microprocessor 706. Each unique row address corresponds to a row of cells in memory array 810. Row decoder 814 includes a word line driver, an address decoder tree, and circuitry which translates a given row address received from row address buffers 812 and selectively activates the appropriate word line of memory array 810 via the word line drivers.
Column address buffer 816 and column decoder 818 receive and decode column address signals provided on address lines 804. Column decoder 818 also determines when a column is defective and the address of a replacement column. Column decoder 818 is coupled to sense amplifiers 820. Sense amplifiers 820 are coupled to complementary pairs of bit lines of memory array 810.
Sense amplifiers 820 are coupled to data-in buffer 822 and data-out buffer 824. Data-in buffers 822 and data-out buffers 824 are coupled to data lines 802. During a write operation, data lines 802 provide data to data-in buffer 822. Sense amplifier 820 receives data from data-in buffer 822 and stores the data in memory array 810 as a charge on a capacitor of a cell at an address specified on address lines 804.
During a read operation, DRAM 800 transfers data to microprocessor 706 from memory array 810. Complementary bit lines for the accessed cell are equilibrated during a precharge operation to a reference voltage provided by an equilibration circuit and a reference voltage supply. The charge stored in the accessed cell is then shared with the associated bit lines. A sense amplifier of sense amplifiers 820 detects and amplifies a difference in voltage between the complementary bit lines. The sense amplifier passes the amplified voltage to data-out buffer 824.
Control logic 806 is used to control the many available functions of DRAM 800. In addition, various control circuits and signals not detailed herein initiate and synchronize DRAM 800 operation as known to those skilled in the art. As stated above, the description of DRAM 800 has been simplified for purposes of illustrating an embodiment of the present invention and is not intended to be a complete description of all the features of a DRAM. Those skilled in the art will recognize that a wide variety of memory devices, including but not limited to, SDRAMs, SLDRAMs, RDRAMs and other DRAMs and SRAMs, VRAMs and EEPROMs, may be used in the implementation of embodiments of the present invention. The DRAM implementation described herein is illustrative only and not intended to be exclusive or limiting.
A dielectric film containing atomic layer deposited lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable dielectric film having an equivalent oxide thickness thinner than attainable using SiO2. Dielectric films containing atomic layer deposited lanthanide doped TiOx formed using the methods described herein are thermodynamically stable such that the dielectric films formed will have minimal reactions with a silicon substrate or other structures during processing.
Lanthanide doped TiOx films formed by atomic layer deposition can be amorphous and possess smooth surfaces. Such lanthanide doped TiOx films can provide enhanced electrical properties due to their smoother surface resulting in reduced leakage current. Furthermore, doping with a lanthanide such as Nd, Tb, and Dy provide for increased breakdown electric fields and decreased leakage currents than can be attained with an undoped TiOx film. Additionally, formation of the lanthanide doped TiOx films by atomic layer deposition allows for the engineering of the relative concentrations of the lanthanide dopant and the limited occurrence of an unwanted SiO2 interfacial layer. These properties of layers containing atomic layer deposited lanthanide doped TiOx films allow for application as dielectric layers in numerous electronic devices and systems.
Capacitors, transistors, higher level ICs or devices, and electronic systems are constructed utilizing the novel process for forming a dielectric film having an ultra thin equivalent oxide thickness, teq. Gate dielectric layers or films containing atomic layer deposited lanthanide doped TiOx are formed having a dielectric constant (κ) substantially higher than that of silicon oxide, where the dielectric films are capable of a teq thinner than 10 Å, thinner than the expected limit for SiO2 gate dielectrics. At the same time, the physical thickness of the atomic layer deposited lanthanide doped TiOx dielectric film is much larger than the SiO2 thickness associated with the teq limit of SiO2. Forming the relatively larger thickness provides advantages in processing gate dielectrics and other dielectric layers. Further, a lanthanide doped TiOx film processed in relatively low temperatures allowed by atomic layer deposition can provide amorphous dielectric films having relatively low leakage current for use as dielectric layers in electronic devices and systems.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
| Patent | Priority | Assignee | Title |
| 7554161, | Jun 05 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | HfAlO3 films for gate dielectrics |
| 7560793, | May 02 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposition and conversion |
| 7572695, | May 27 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Hafnium titanium oxide films |
| 7589029, | May 02 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposition and conversion |
| 7595604, | Jun 28 2006 | Sanyo Electric Co., Ltd. | Motor control device |
| 7601649, | Aug 02 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Zirconium-doped tantalum oxide films |
| 7611959, | Dec 04 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Zr-Sn-Ti-O films |
| 7625794, | Mar 31 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods of forming zirconium aluminum oxide |
| 7662729, | Apr 28 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
| 7670646, | May 02 2002 | Micron Technology, Inc. | Methods for atomic-layer deposition |
| 7679308, | Jun 28 2006 | Sanyo Electric Co., Ltd. | Motor control device |
| 7687409, | Mar 29 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposited titanium silicon oxide films |
| 7727905, | Aug 02 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Zirconium-doped tantalum oxide films |
| 7754618, | Feb 10 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method of forming an apparatus having a dielectric containing cerium oxide and aluminum oxide |
| 7776762, | Aug 02 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Zirconium-doped tantalum oxide films |
| 7804144, | Dec 20 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
| 7867919, | Aug 31 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer |
| 7915174, | Dec 13 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Dielectric stack containing lanthanum and hafnium |
| 7972974, | Jan 10 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Gallium lanthanide oxide films |
| 8076249, | Mar 29 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Structures containing titanium silicon oxide |
| 8102013, | Mar 29 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanide doped TiOx films |
| 8110469, | Aug 30 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Graded dielectric layers |
| 8125038, | Jul 30 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Nanolaminates of hafnium oxide and zirconium oxide |
| 8154066, | Aug 31 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Titanium aluminum oxide films |
| 8178413, | Dec 20 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
| 8237216, | Aug 31 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Apparatus having a lanthanum-metal oxide semiconductor device |
| 8288809, | Aug 02 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Zirconium-doped tantalum oxide films |
| 8399365, | Mar 29 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods of forming titanium silicon oxide |
| 8445952, | Dec 04 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Zr-Sn-Ti-O films |
| 8501563, | Jul 20 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Devices with nanocrystals and methods of formation |
| 8541276, | Aug 31 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods of forming an insulating metal oxide |
| 8765616, | Aug 02 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Zirconium-doped tantalum oxide films |
| 8921914, | Jul 20 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Devices with nanocrystals and methods of formation |
| 8951903, | Aug 30 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Graded dielectric structures |
| 9129961, | Jan 10 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Gallium lathanide oxide films |
| 9583334, | Jan 10 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Gallium lanthanide oxide films |
| 9627501, | Aug 30 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Graded dielectric structures |
| Patent | Priority | Assignee | Title |
| 2501563, | |||
| 4058430, | Nov 29 1974 | PLANAR INTERNATIONAL OY A CORP OF FINLAND | Method for producing compound thin films |
| 4333808, | Oct 30 1979 | International Business Machines Corporation | Method for manufacture of ultra-thin film capacitor |
| 4413022, | Feb 28 1979 | PLANAR INTERNATIONAL OY A CORP OF FINLAND | Method for performing growth of compound thin films |
| 5049516, | Dec 02 1987 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor memory device |
| 5055319, | Apr 02 1990 | REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE, A CORP OF CA | Controlled high rate deposition of metal oxide films |
| 5426603, | Jan 25 1993 | Hitachi, Ltd. | Dynamic RAM and information processing system using the same |
| 5439524, | Apr 05 1993 | VLSI Technology, Inc | Plasma processing apparatus |
| 5572052, | Jul 24 1992 | Mitsubishi Denki Kabushiki Kaisha | Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer |
| 5674563, | Sep 14 1993 | Nissan Motor Co., Ltd.; Sharp Kabushiki Kaisha; Yasuo, Tarui | Method for ferroelectric thin film production |
| 5698022, | Aug 14 1996 | Advanced Technology Materials, Inc.; Advanced Technology Materials, Inc | Lanthanide/phosphorus precursor compositions for MOCVD of lanthanide/phosphorus oxide films |
| 5714336, | Aug 05 1986 | Siemens Healthcare Diagnostics Products GmbH | Process and test kit for determining free active compounds in biological fluids |
| 5714766, | Sep 29 1995 | GLOBALFOUNDRIES Inc | Nano-structure memory device |
| 5739524, | Jul 13 1994 | European Gas Turbines SA | Dynamic distance and position sensor and method of measuring the distance and the position of a surface using a sensor of this kind |
| 5795808, | Nov 13 1995 | Hyundai Electronics Industries C., Ltd. | Method for forming shallow junction for semiconductor device |
| 5801105, | Aug 04 1995 | TDK Corporation | Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film |
| 5810923, | Aug 17 1994 | TDK Corporation | Method for forming oxide thin film and the treatment of silicon substrate |
| 5828080, | Aug 17 1994 | TDK Corporation | Oxide thin film, electronic device substrate and electronic device |
| 5840897, | Jul 06 1990 | Entegris, Inc | Metal complex source reagents for chemical vapor deposition |
| 5879459, | Aug 29 1997 | EUGENUS, INC | Vertically-stacked process reactor and cluster tool system for atomic layer deposition |
| 5912797, | Sep 24 1997 | Bell Semiconductor, LLC | Dielectric materials of amorphous compositions and devices employing same |
| 5916365, | Aug 16 1996 | ASM INTERNATIONAL N V | Sequential chemical vapor deposition |
| 5923056, | Oct 10 1996 | Bell Semiconductor, LLC | Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials |
| 5958140, | Jul 27 1995 | Tokyo Electron Limited | One-by-one type heat-processing apparatus |
| 6020024, | Aug 04 1997 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method for forming high dielectric constant metal oxides |
| 6025627, | May 29 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Alternate method and structure for improved floating gate tunneling devices |
| 6034015, | May 14 1997 | Georgia Tech Research Corporation | Ceramic compositions for microwave wireless communication |
| 6060755, | Jul 19 1999 | Sharp Kabushiki Kaisha | Aluminum-doped zirconium dielectric film transistor structure and deposition method for same |
| 6063705, | Aug 27 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Precursor chemistries for chemical vapor deposition of ruthenium and ruthenium oxide |
| 6093944, | Jun 04 1998 | Bell Semiconductor, LLC | Dielectric materials of amorphous compositions of TI-O2 doped with rare earth elements and devices employing same |
| 6110529, | Jul 06 1990 | Entegris, Inc | Method of forming metal films on a substrate by chemical vapor deposition |
| 6162712, | Jun 30 1995 | Entegris, Inc | Platinum source compositions for chemical vapor deposition of platinum |
| 6174809, | Dec 31 1997 | Samsung Electronics, Co., Ltd. | Method for forming metal layer using atomic layer deposition |
| 6194237, | Dec 16 1997 | HYUNDAI ELECTRONICS INDUSTRIES CO , LTD | Method for forming quantum dot in semiconductor device and a semiconductor device resulting therefrom |
| 6200893, | Mar 11 1999 | AIXTRON, INC | Radical-assisted sequential CVD |
| 6203613, | Oct 19 1999 | International Business Machines Corporation | Atomic layer deposition with nitrate containing precursors |
| 6207589, | Jul 19 1999 | Sharp Laboratories of America, Inc. | Method of forming a doped metal oxide dielectric film |
| 6211035, | Sep 09 1998 | Texas Instruments Incorporated | Integrated circuit and method |
| 6225168, | Jun 04 1998 | GLOBALFOUNDRIES Inc | Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof |
| 6274937, | Feb 01 1999 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Silicon multi-chip module packaging with integrated passive components and method of making |
| 6281042, | Aug 31 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Structure and method for a high performance electronic packaging assembly |
| 6289842, | Jun 02 1998 | Structured Materials Industries Inc. | Plasma enhanced chemical vapor deposition system |
| 6291341, | Feb 12 1999 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method for PECVD deposition of selected material films |
| 6294813, | May 29 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Information handling system having improved floating gate tunneling devices |
| 6297103, | Feb 28 2000 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
| 6297539, | Feb 29 2000 | Sharp Kabushiki Kaisha | Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same |
| 6331465, | May 29 1998 | Micron Technology, Inc. | Alternate method and structure for improved floating gate tunneling devices using textured surface |
| 6346477, | Jan 09 2001 | ARKLES, BARRY | Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt |
| 6350704, | Oct 14 1997 | NANYA TECHNOLOGY CORP | Porous silicon oxycarbide integrated circuit insulator |
| 6387712, | Jun 26 1996 | TDK Corporation | Process for preparing ferroelectric thin films |
| 6391769, | Aug 19 1998 | Samsung Electronics Co., Ltd. | Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby |
| 6420230, | Aug 31 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Capacitor fabrication methods and capacitor constructions |
| 6432779, | May 18 2000 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Selective removal of a metal oxide dielectric |
| 6441417, | Mar 28 2001 | Sharp Laboratories of America, Inc.; Sharp Laboratories of America, Inc | Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same |
| 6444592, | Jun 20 2000 | GLOBALFOUNDRIES Inc | Interfacial oxidation process for high-k gate dielectric process integration |
| 6448192, | Apr 16 2001 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method for forming a high dielectric constant material |
| 6451641, | Feb 27 2002 | GLOBALFOUNDRIES U S INC | Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material |
| 6451695, | Mar 11 1999 | AIXTRON, INC | Radical-assisted sequential CVD |
| 6454912, | Mar 15 2001 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | Method and apparatus for the fabrication of ferroelectric films |
| 6458701, | Oct 20 1999 | Samsung Electronics Co., Ltd. | Method for forming metal layer of semiconductor device using metal halide gas |
| 6461436, | Oct 15 2001 | Micron Technology, Inc. | Apparatus and process of improving atomic layer deposition chamber performance |
| 6465334, | Oct 05 2000 | GLOBALFOUNDRIES U S INC | Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors |
| 6465853, | May 08 2001 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method for making semiconductor device |
| 6495436, | Feb 09 2001 | Micron Technology, Inc. | Formation of metal oxide gate dielectric |
| 6509280, | Feb 22 2001 | Samsung Electronics Co., Ltd. | Method for forming a dielectric layer of a semiconductor device |
| 6514820, | Aug 27 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method for forming single electron resistor memory |
| 6521911, | Jul 20 2000 | North Carolina State University | High dielectric constant metal silicates formed by controlled metal-surface reactions |
| 6527866, | Feb 09 2000 | SUPERCONDUCTOR TECHNOLOGIES, INC | Apparatus and method for deposition of thin films |
| 6531354, | Jan 19 2000 | North Carolina State University | Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors |
| 6534357, | Nov 09 2000 | Micron Technology, Inc. | Methods for forming conductive structures and structures regarding same |
| 6534420, | Jul 18 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for forming dielectric materials and methods for forming semiconductor devices |
| 6537613, | Apr 10 2000 | VERSUM MATERIALS US, LLC | Process for metal metalloid oxides and nitrides with compositional gradients |
| 6538330, | Aug 04 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Multilevel semiconductor-on-insulator structures and circuits |
| 6541079, | Oct 25 1999 | International Business Machines Corporation | Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique |
| 6541280, | Mar 20 2001 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | High K dielectric film |
| 6541353, | Aug 31 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer doping apparatus and method |
| 6544846, | Aug 27 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method of manufacturing a single electron resistor memory device |
| 6551893, | Nov 27 2001 | Round Rock Research, LLC | Atomic layer deposition of capacitor dielectric |
| 6551929, | Jun 28 2000 | Applied Materials, Inc | Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques |
| 6552383, | May 11 2001 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | Integrated decoupling capacitors |
| 6559472, | Nov 21 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Film composition |
| 6570248, | Aug 31 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Structure and method for a high-performance electronic packaging assembly |
| 6586349, | Feb 21 2002 | Advanced Micro Devices, Inc. | Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices |
| 6586792, | Mar 15 2001 | Micron Technology, Inc. | Structures, methods, and systems for ferroelectric memory transistors |
| 6592942, | Jul 07 2000 | ASM International N.V. | Method for vapour deposition of a film onto a substrate |
| 6596636, | Nov 21 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | ALD method to improve surface coverage |
| 6602338, | Sep 18 2000 | National Science Council | Titanium dioxide film co-doped with yttrium and erbium and method for producing the same |
| 6608378, | Feb 09 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Formation of metal oxide gate dielectric |
| 6613656, | Feb 13 2001 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | Sequential pulse deposition |
| 6613695, | Nov 24 2000 | ASM IP HOLDING B V | Surface preparation prior to deposition |
| 6617639, | Jun 21 2002 | MONTEREY RESEARCH, LLC | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling |
| 6620670, | Jan 18 2002 | Applied Materials, Inc.; Applied Materials, Inc | Process conditions and precursors for atomic layer deposition (ALD) of AL2O3 |
| 6627260, | Jul 19 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Deposition methods |
| 6627503, | Feb 11 2000 | Sharp Laboratories of America, Inc. | Method of forming a multilayer dielectric stack |
| 6632279, | Oct 14 1999 | ASM INTERNATIONAL N V | Method for growing thin oxide films |
| 6638859, | Dec 22 1999 | EUGENUS, INC | Apparatus and method to achieve continuous interface and ultrathin film during atomic layer deposition |
| 6642567, | Aug 31 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Devices containing zirconium-platinum-containing materials and methods for preparing such materials and devices |
| 6645882, | Jan 17 2002 | GLOBALFOUNDRIES U S INC | Preparation of composite high-K/standard-K dielectrics for semiconductor devices |
| 6652924, | Aug 16 1996 | ASM INTERNATIONAL N V | Sequential chemical vapor deposition |
| 6660660, | Oct 10 2000 | ASM INTERNATIONAL N V | Methods for making a dielectric stack in an integrated circuit |
| 6661058, | Apr 20 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Highly reliable gate oxide and method of fabrication |
| 6673701, | Aug 27 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposition methods |
| 6674138, | Dec 31 2001 | MONTEREY RESEARCH, LLC | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
| 6696332, | Dec 26 2001 | Texas Instruments Incorporated | Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing |
| 6699747, | Feb 29 2000 | Qimonda AG | Method for increasing the capacitance in a storage trench |
| 6709989, | Jun 21 2001 | Apple Inc | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
| 6710538, | Aug 26 1998 | Micron Technology, Inc. | Field emission display having reduced power requirements and method |
| 6713329, | May 10 1999 | The Trustees of Princeton University | Inverter made of complementary p and n channel transistors using a single directly-deposited microcrystalline silicon film |
| 6713846, | Jan 26 2001 | AVIZA TECHNOLOGY, INC | Multilayer high κ dielectric films |
| 6720221, | Feb 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Structure and method for dual gate oxide thicknesses |
| 6730575, | Aug 30 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure |
| 6750066, | Apr 08 2002 | Infineon Technologies LLC | Precision high-K intergate dielectric layer |
| 6754108, | Aug 30 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
| 6756298, | Jan 18 2000 | Round Rock Research, LLC | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
| 6759081, | May 11 2001 | ASM INTERNATIONAL N V | Method of depositing thin films for magnetic heads |
| 6767582, | Oct 15 1999 | ASM INTERNATIONAL N V | Method of modifying source chemicals in an ald process |
| 6767795, | Jan 17 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Highly reliable amorphous high-k gate dielectric ZrOXNY |
| 6770923, | Mar 20 2001 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | High K dielectric film |
| 6774050, | Feb 23 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Doped aluminum oxide dielectrics |
| 6777353, | Apr 14 2000 | ASM IP HOLDING B V | Process for producing oxide thin films |
| 6778441, | Aug 30 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Integrated circuit memory device and method |
| 6780704, | Dec 03 1999 | ASM INTERNATIONAL N V | Conformal thin films over textured capacitor electrodes |
| 6784101, | May 16 2002 | GLOBALFOUNDRIES U S INC | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation |
| 6787370, | Aug 26 1999 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method of forming a weak ferroelectric transistor |
| 6787413, | Jun 13 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Capacitor structure forming methods |
| 6790791, | Aug 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanide doped TiOx dielectric films |
| 6794709, | Feb 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Structure and method for dual gate oxide thicknesses |
| 6800567, | Aug 27 2001 | Hynix Semiconductor Inc. | Method for forming polyatomic layers |
| 6803326, | Oct 14 1997 | NANYA TECHNOLOGY CORP | Porous silicon oxycarbide integrated circuit insulator |
| 6804136, | Jun 21 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Write once read only memory employing charge trapping in insulators |
| 6812100, | Mar 13 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Evaporation of Y-Si-O films for medium-k dielectrics |
| 6812157, | Jun 24 1999 | ATOMIC PRECISION SYSTEMS, INC | Apparatus for atomic layer chemical vapor deposition |
| 6821862, | Jun 27 2000 | Samsung Electronics Co., Ltd. | METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES THAT INCLUDE A METAL OXIDE LAYER DISPOSED ON ANOTHER LAYER TO PROTECT THE OTHER LAYER FROM DIFFUSION OF IMPURITIES AND INTEGRATED CIRCUIT DEVICES MANUFACTURED USING SAME |
| 6821873, | Jan 10 2002 | Texas Instruments Incorporated | Anneal sequence for high-κ film property optimization |
| 6828632, | Jul 18 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Stable PD-SOI devices and methods |
| 6831315, | Dec 03 1999 | ASM INTERNATIONAL N V | Conformal thin films over textured capacitor electrodes |
| 6833285, | Feb 01 1999 | Micron Technology, Inc. | Method of making a chip packaging device having an interposer |
| 6833308, | Feb 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Structure and method for dual gate oxide thicknesses |
| 6835111, | Aug 26 1998 | Micron Technology, Inc. | Field emission display having porous silicon dioxide layer |
| 6844203, | Aug 30 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Gate oxides, and methods of forming |
| 6852167, | Mar 01 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods, systems, and apparatus for uniform chemical-vapor depositions |
| 6858120, | Mar 15 2001 | CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC | Method and apparatus for the fabrication of ferroelectric films |
| 6858444, | Mar 15 2001 | Micron Technology, Inc. | Method for making a ferroelectric memory transistor |
| 6858865, | Feb 23 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Doped aluminum oxide dielectrics |
| 6884719, | Mar 20 2001 | Regents of the University of California, The | Method for depositing a coating having a relatively high dielectric constant onto a substrate |
| 6884739, | Aug 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanide doped TiOx dielectric films by plasma oxidation |
| 6888739, | Jun 21 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Nanocrystal write once read only memory for archival storage |
| 6893984, | Feb 20 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Evaporated LaA1O3 films for gate dielectrics |
| 6900122, | Dec 20 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics |
| 6914800, | Mar 15 2001 | Micron Technology, Inc. | Structures, methods, and systems for ferroelectric memory transistors |
| 6919266, | Jul 24 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Copper technology for ULSI metallization |
| 6921702, | Jul 30 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
| 6930346, | Mar 13 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Evaporation of Y-Si-O films for medium-K dielectrics |
| 6953730, | Dec 20 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
| 6958302, | Dec 04 2002 | Micron Technology, Inc. | Atomic layer deposited Zr-Sn-Ti-O films using TiI4 |
| 6960538, | Aug 21 2002 | Micron Technology, Inc. | Composite dielectric forming methods and composite dielectrics |
| 6989573, | Oct 10 2003 | Micron Technology, Inc. | Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics |
| 7037574, | May 23 2001 | CVC PRODUCTS, INC | Atomic layer deposition for fabricating thin films |
| 7068544, | Aug 30 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Flash memory with low tunnel barrier interpoly insulators |
| 7081421, | Aug 26 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanide oxide dielectric layer |
| 7084078, | Aug 29 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposited lanthanide doped TiOx dielectric films |
| 7101813, | Dec 04 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposited Zr-Sn-Ti-O films |
| 7129553, | Jun 24 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanide oxide/hafnium oxide dielectrics |
| 7138336, | Aug 06 2001 | ASM KOREA LTD | Plasma enhanced atomic layer deposition (PEALD) equipment and method of forming a conducting thin film using the same thereof |
| 7160577, | May 02 2002 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
| 7160817, | Aug 30 2001 | Mosaid Technologies Incorporated | Dielectric material forming methods |
| 7169673, | Jul 30 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
| 7183186, | Apr 22 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Atomic layer deposited ZrTiO4 films |
| 7192824, | Jun 24 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanide oxide / hafnium oxide dielectric layers |
| 7192892, | Mar 04 2003 | Round Rock Research, LLC | Atomic layer deposited dielectric layers |
| 7195999, | Jul 07 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Metal-substituted transistor gates |
| 7199023, | Aug 28 2002 | Round Rock Research, LLC | Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed |
| 7205218, | Jun 05 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method including forming gate dielectrics having multiple lanthanide oxide layers |
| 7205620, | Jan 17 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Highly reliable amorphous high-k gate dielectric ZrOxNy |
| 7208804, | Aug 30 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Crystalline or amorphous medium-K gate oxides, Y203 and Gd203 |
| 7211492, | Jul 07 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Self aligned metal gates on high-k dielectrics |
| 7214994, | Aug 31 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Self aligned metal gates on high-k dielectrics |
| 7235501, | Dec 13 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanum hafnium oxide dielectrics |
| 7235854, | Aug 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Lanthanide doped TiOx dielectric films |
| 7259434, | Aug 30 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Highly reliable amorphous high-k gate oxide ZrO2 |
| 20010002280, | |||
| 20010005625, | |||
| 20010009695, | |||
| 20010012698, | |||
| 20010014526, | |||
| 20010019876, | |||
| 20010030352, | |||
| 20010034117, | |||
| 20010042505, | |||
| 20010050438, | |||
| 20020001971, | |||
| 20020004276, | |||
| 20020004277, | |||
| 20020013052, | |||
| 20020019125, | |||
| 20020024080, | |||
| 20020025628, | |||
| 20020037603, | |||
| 20020046705, | |||
| 20020053869, | |||
| 20020068466, | |||
| 20020086507, | |||
| 20020100418, | |||
| 20020102818, | |||
| 20020110991, | |||
| 20020117704, | |||
| 20020122885, | |||
| 20020135048, | |||
| 20020142536, | |||
| 20020146916, | |||
| 20020155688, | |||
| 20020155689, | |||
| 20020164420, | |||
| 20020167057, | |||
| 20020170671, | |||
| 20020177244, | |||
| 20020192974, | |||
| 20020192975, | |||
| 20020192979, | |||
| 20020195056, | |||
| 20020197793, | |||
| 20020197881, | |||
| 20030001190, | |||
| 20030001241, | |||
| 20030003722, | |||
| 20030003730, | |||
| 20030017717, | |||
| 20030027360, | |||
| 20030042526, | |||
| 20030043637, | |||
| 20030045060, | |||
| 20030045078, | |||
| 20030045082, | |||
| 20030048666, | |||
| 20030049942, | |||
| 20030052358, | |||
| 20030059535, | |||
| 20030104666, | |||
| 20030119246, | |||
| 20030119291, | |||
| 20030119313, | |||
| 20030132491, | |||
| 20030139039, | |||
| 20030143801, | |||
| 20030157764, | |||
| 20030170389, | |||
| 20030170403, | |||
| 20030181039, | |||
| 20030183156, | |||
| 20030193061, | |||
| 20030194861, | |||
| 20030194862, | |||
| 20030203626, | |||
| 20030207032, | |||
| 20030207540, | |||
| 20030207593, | |||
| 20030222300, | |||
| 20030224600, | |||
| 20030227033, | |||
| 20030228747, | |||
| 20030232511, | |||
| 20030235961, | |||
| 20040004244, | |||
| 20040004245, | |||
| 20040004247, | |||
| 20040004859, | |||
| 20040007171, | |||
| 20040009679, | |||
| 20040016944, | |||
| 20040023461, | |||
| 20040033681, | |||
| 20040033701, | |||
| 20040038525, | |||
| 20040038554, | |||
| 20040043541, | |||
| 20040043569, | |||
| 20040043635, | |||
| 20040065255, | |||
| 20040110348, | |||
| 20040110391, | |||
| 20040144980, | |||
| 20040156578, | |||
| 20040159863, | |||
| 20040161899, | |||
| 20040164357, | |||
| 20040164365, | |||
| 20040169453, | |||
| 20040175882, | |||
| 20040178439, | |||
| 20040183108, | |||
| 20040185654, | |||
| 20040189175, | |||
| 20040214399, | |||
| 20040219783, | |||
| 20040222476, | |||
| 20040248398, | |||
| 20040262700, | |||
| 20050009335, | |||
| 20050009370, | |||
| 20050020017, | |||
| 20050023574, | |||
| 20050023584, | |||
| 20050023594, | |||
| 20050023595, | |||
| 20050023602, | |||
| 20050023603, | |||
| 20050023624, | |||
| 20050023625, | |||
| 20050023626, | |||
| 20050023627, | |||
| 20050026349, | |||
| 20050026374, | |||
| 20050029547, | |||
| 20050029604, | |||
| 20050029605, | |||
| 20050030825, | |||
| 20050032292, | |||
| 20050034662, | |||
| 20050054165, | |||
| 20050077519, | |||
| 20050087134, | |||
| 20050124174, | |||
| 20050138262, | |||
| 20050145957, | |||
| 20050145959, | |||
| 20050158973, | |||
| 20050227442, | |||
| 20050260357, | |||
| 20050285225, | |||
| 20060028867, | |||
| 20060028869, | |||
| 20060125030, | |||
| 20060128168, | |||
| 20060148180, | |||
| 20060176645, | |||
| 20060177975, | |||
| 20060189154, | |||
| 20060223337, | |||
| 20060228868, | |||
| 20060245984, | |||
| 20060261397, | |||
| 20060263972, | |||
| 20060264064, | |||
| 20060270147, | |||
| 20060281330, | |||
| 20070007560, | |||
| 20070007635, | |||
| 20070010060, | |||
| 20070010061, | |||
| 20070018214, | |||
| 20070037415, | |||
| 20070045676, | |||
| 20070045752, | |||
| 20070048926, | |||
| 20070049023, | |||
| 20070049051, | |||
| 20070049054, | |||
| 20070059881, | |||
| 20070087563, | |||
| 20070090439, | |||
| 20070090440, | |||
| 20070090441, | |||
| 20070092989, | |||
| 20070099366, | |||
| 20070101929, | |||
| 20070107661, | |||
| 20070111544, | |||
| 20070131169, | |||
| 20070134931, | |||
| 20070134942, | |||
| 20070158765, | |||
| 20070181931, | |||
| 20070187772, | |||
| 20070187831, | |||
| 20070234949, | |||
| EP540993, | |||
| EP1096042, | |||
| WO197257, | |||
| WO231875, | |||
| WO243115, |
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