A controller comprises a host interface section and a processing circuit. The host interface section receives a command sequence outputted from a host apparatus to a first nonvolatile semiconductor memory. The processing circuit processes the command sequence outputted from the host apparatus to the first nonvolatile semiconductor memory, and controls writing, reading and erase of data to a second nonvolatile semiconductor memory, according to the command sequence.
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1. A memory card configured to be coupled to a host apparatus and to receive a command sequence outputted from the host apparatus and intended for a first nonvolatile semiconductor memory, comprising:
a second nonvolatile semiconductor memory having a different configuration than the first nonvolatile semiconductor memory; and
a controller which processes the command sequence outputted from the host apparatus, and controls writing, reading and erasing of data to the second nonvolatile semiconductor memory, in response to the command sequence;
wherein the controller processes the command sequence outputted from the host apparatus by the following control procedure comprising,
determining whether a command included in the command sequence is a writing or reading command;
determining whether an address of first predetermined bytes has been input, when the command is determined to be a writing or reading command;
performing said writing or reading when the address of the first predetermined bytes has been input;
determining whether the command is an erase command when the command is not a writing or reading command;
determining whether an address of second predetermined bytes has been input when the command is an erase command;
performing said erasing when the address of the second predetermined bytes has been input;
determining whether the command is an id read or a status read command when the command is not a writing, reading or erasing command; and
performing said id read or status read, when the command is an id read or status read command.
5. A method of controlling a memory card coupled to a host apparatus and accessed by the host apparatus, comprising:
determining, using a controller included in the memory card, whether a command input from the host apparatus to the memory card is a writing or reading command;
determining, using a controller, whether an address of first predetermined bytes has been input from the host apparatus to the memory card, when the command is a writing or reading command;
performing, using a controller, said writing or reading to a nonvolatile semiconductor memory included in the memory card when the address of the first predetermined bytes has been input to the memory card;
determining, using a controller, whether the command is an erase command when the command determined by the controller is not a writing or reading command;
determining, using a controller, whether an address of second predetermined bytes has been input from the host apparatus to the memory card when the command is determined by the controller to be an erase command;
performing, using a controller, said erase command on the nonvolatile semiconductor memory when the address of the second predetermined bytes has been input to the memory card;
determining, using a controller, whether the command is an id read or a status read command when the command is not a writing, reading, or erasing command; and
performing, using a controller, said id read or status read on the nonvolatile semiconductor memory, in dependence on whether the command determined by the controller is said id read or status read command, respectively.
3. A memory card configured to be coupled to a host apparatus and to receive a command sequence outputted from the host apparatus and intended for a first nonvolatile semiconductor memory, comprising:
a second nonvolatile semiconductor memory having a different configuration than the first nonvolatile semiconductor memory; and
a controller which processes the command sequence outputted from the host apparatus, and controls writing, reading and erasing of data to the second nonvolatile semiconductor memory, in response to the command sequence;
wherein the controller processes the command sequence outputted from the host apparatus by the following control procedure comprising,
determining whether a command included in the command sequence is a writing or reading command;
determining whether an address of first predetermined bytes has been input, when the command is a writing or reading command;
performing said writing or reading, when the address of the first predetermined bytes has been input;
determining whether a command has been input from the host apparatus, when the address of the first predetermined bytes has not been input;
returning to the determining whether the command is a writing or reading command step, when the command has been input;
returning to the determining whether the address of the first predetermined bytes has been input step, when the command has not been input;
determining whether the command is an erase command when the command is not a writing or reading command;
determining whether an address of second predetermined bytes has been input, when the command is determined to be an erase command;
performing the erase when the address of the second predetermined bytes has been input;
determining whether a command has been input from the host apparatus, when the address of the second predetermined bytes has not been input;
returning to the determining whether the command is a writing or reading command step, when the command has been input;
returning to the determining whether the address of the second predetermined bytes has been input step, when the command has not been input;
determining whether the command is an id read or a status read command when the command is not a writing, reading or erasing command; and
performing said id read or status read, when the command is an id read or status read command.
6. A method of controlling a memory card coupled to a host apparatus and accessed by the host apparatus, comprising:
determining, using a controller included in the memory card, whether a command input from the host apparatus to the memory card is a writing command or a reading command;
determining, using the controller, whether an address of first predetermined bytes has been input from the host apparatus to the memory card, when the command determined by the controller is a writing or reading command;
performing, using the controller, said writing or reading to a nonvolatile semiconductor memory included in the memory card, when the address of the first predetermined bytes has been input to the memory card;
determining, using the controller, whether a command has been input from the host apparatus to the memory card, when the address of the first predetermined bytes has not been input to the memory card;
returning, using the controller, to the determining whether the command is a writing or reading step, when the command has been input to the memory card;
returning, using the controller, to the determining whether the address of the first predetermined bytes has been input step, when the command has not been input to the memory card;
determining, using the controller, whether the command is an erase command when the command is not a writing or reading command;
determining, using the controller, whether an address of second predetermined bytes has been input from the host apparatus to the memory card, when the command is determined to be an erase command;
performing, using the controller, the erase to the nonvolatile semiconductor memory when the address of the second predetermined bytes has been input to the memory card;
determining, using the controller, whether a command has been input from the host apparatus to the memory card, when the address of the second predetermined bytes has not been input to the memory card;
returning, using the controller, to the determining whether the command is a writing or reading command step, when the command has been input to the memory card;
returning, using the controller, to the determining whether the address of the second predetermined bytes has been input step, when the command has not been input to the memory card;
determining, using the controller, whether the command is an id read or a status read command when the command is not a writing, reading, or erasing command; and
performing, using the controller, said id read or status read, in dependence on whether the command is said id read or status read command, respectively.
2. The memory card according to
4. The memory card according to
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This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-273895, filed Sep. 21, 2004, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a memory card having a controller and storage cells, and a method of controlling the memory card. For example, it relates to a memory card which performs writing, reading and erase of data by access from a host apparatus, a controller mounted on the memory card, and a method of controlling the memory card.
2. Description of the Related Art
Recently, in various portable electronic apparatuses such as personal computers, PDAs, cameras, and mobile phones, memory cards which are one kind of removable memory devices are widely used. Among memory cards, there are cards which do not have a controller but only have a NAND type flash memory. The conventional NAND type flash memory generally has a small erase block size in erase set to, for example, 16 kbytes.
In the meantime, as NAND type flash memory mounted on memory cards, inexpensive NAND type flash memories having a large capacity and a large erase block size in erase have been used. In the NAND type flash memories, the erase block size is set to, for example, 256 kbytes. Therefore, if the host apparatus accesses the memory card on the assumption that the memory is a NAND type flash memory having a small erase block size, the memory card having a NAND type flash memory having a large erase block size cannot properly respond to the access, and this causes a malfunction. The term “erase block size” indicates a data size which is erased at once in erase in a NAND type flash memory.
Jpn. Pat. Appln. KOKAI Pub. No. 2002-259322 discloses a memory system having a plurality of kinds of memory chips and a memory controller that controls the memory chips, wherein one memory controller enables access to the plurality of kinds of memory chips.
A controller according to an aspect of the present invention comprises: a host interface section which receives a command sequence outputted from a host apparatus to a first nonvolatile semiconductor memory; and a processing circuit which processes the command sequence outputted from the host apparatus to the first nonvolatile semiconductor memory, and controls writing, reading and erase of data to a second nonvolatile semiconductor memory, in response to the command sequence.
A method of controlling a memory card according to an aspect of the present invention is a method of controlling a memory card mounted on a host apparatus and accessed by the host apparatus, comprising: determining whether a command input from the host apparatus is writing, reading, erase, ID read, or status read; determining whether an address of predetermined bytes has been input, if the command is any one of writing, reading, and erase; performing the one of writing, reading and erase, if the address of the predetermined bytes is input; determining whether a command has been input from the host apparatus, if the address of the predetermined bytes is not input; and performing one of ID read and status read, if the command is the one of the ID read and status read.
An embodiment of the present invention will now be described with reference to drawings. In explanation, like reference numerals denote like constituent elements through all the drawings.
As shown in
Further, although not shown, the NAND type flash memory 3 and the controller 4 may be arranged on a PCB (Printed Circuit Board) substrate, or may be formed in the same LSI (Large-Scale Integration).
The terms “logical block address” and “physical block address” used in the following explanation indicate a logical address and a physical address, respectively, of a block itself. Further, although the terms “logical address” and “physical address” mainly indicate a logical address and a physical address, respectively, of the block address, they may also indicate addresses corresponding to a resolution unit smaller than the block unit.
The host apparatus 20 has hardware and software (system) for performing access to the memory card 1 to be connected. The host apparatus 20 is configured to manage a physical state (which physical block address includes logical sector address data and which ordinal number the logical sector address data has, or which block is in an erased state) inside the memory card, and directly control the NAND type flash memory 3 in the memory card 1.
Further, the host apparatus 20 performs assignments of logical addresses and physical addresses in 16 kbytes, on the assumption of using a NAND type flash memory having an erase block size in erase fixed to 16 kbytes. In many cases, the host apparatus 20 performs a sequential write access or a sequential read access for 16 kbytes of logical addresses (issues a corresponding command).
The memory card 1 operates in response to power supply when it is connected to the host apparatus 20, and performs processing in accordance with access from the host apparatus 20. The memory card 1 has the NAND type flash memory 3 and the controller 4 as described above.
The NAND type flash memory 3 is a non-volatile memory having an erase block size in erase (erase unit block size) fixed to 256 kbytes, and performs write and read of data in 16 kbytes, for example. The NAND type flash memory 3 is manufactured by using, for example, a 0.09 mm process technique. Specifically, the design rule of the NAND type flash memory is less than 0.1 μm.
The controller 4 has a memory interface section 5, a host interface section 6, a buffer 7, and a RAM (Random Access Memory) 10, in addition to the CPU 8 and the ROM 9 described above.
The memory interface section 5 performs interface processing between the controller 4 and the NAND type flash memory 3. The host interface section 6 performs interface processing between the controller 4 and the host apparatus 20.
The buffer 7 temporarily stores data of a predetermined amount (for 1 page, for example) when data transmitted from the host apparatus 20 is written in the NAND type flash memory 3, and when data read from the NAND type flash memory 3 is sent to the host apparatus 20.
The CPU 8 controls the operation of the whole memory card 1. The ROM 9 is a memory that stores a control program used by the CPU 8, and the like. The RAM 10 is a volatile memory that is used as work area of the CPU 8, and stores a control program and various tables. For example, when the memory card 1 receives power supply, the CPU 8 loads firmware (control program) stored in the ROM 9 into the RAM 10 and performs a predetermined processing. Thereby, the CPU 8 prepares various tables in the RAM 10, performs access to a relevant region in the NAND type flash memory 3 in response to a write command, a read command, or an erase command from the host apparatus 20, and controls data transmission through the buffer 7.
First, the CPU 8 determines whether a command has been input from the host apparatus 20 (step S1). Thereafter, when a command is input, the CPU 8 determines whether the command is a write command or a read command (step S2). When the CPU 8 determines in step S1 that a command is not input, it returns to step S1 again.
Next, when the CPU 8 determines that the input command is a write command or a read command, it determines whether an address of predetermined bytes, 4 bytes in this example, has been input (step S3). When an address of 4 bytes is input, the CPU performs writing or reading (step S4), and returns to step S1. In the meantime, in step S3, when an address of 4 bytes is not input within a predetermined time, the CPU determines again whether a command has been input (step S5). When the CPU 8 determines that a command has been input in step S5, it returns to step S2 and repeats the processing of step S2 and later steps. In the meantime, when a command is not input, the CPU returns to step S3 and repeats the processing of step S3 and later steps.
Further, in step S2, when the CPU 8 determines that the input command is not a write command or a read command, the CPU 8 determines whether the command is an erase command or not (step S6). When the CPU determines that the input command is an erase command, the CPU determines whether an address of predetermined bytes, 3 bytes in this example, has been input (step S7). When the CPU 8 determines in step S7 that an address of 3 bytes is input, the CPU 8 performs erase (step S8), and returns to step S1. In the meantime, in step S7, if a 3 bytes of address is not input within a predetermined time, the CPU 8 determines again whether a command has been input or not (step S9). If a command is input, the CPU 8 returns to step S2, and repeats the processing of step S2 and later steps. In the meantime, if a command is not input, the CPU 8 returns to step S7, and repeats the processing of step S7 and later steps.
Further, in step S6, when the CPU 8 determines that the input command is not an erase command, the CPU 8 determines whether the command is an ID read command or a status read command (step S10). When the CPU 8 determines that the input command is an ID read command or a status read command, the CPU 8 performs ID read or status read (step S11), and returns to step S1. In the meantime, if the CPU 8 determines that the input command is not an ID read command or a status read command, the CPU 8 does not perform any processing, and only returns to step S1.
In the command sequence shown in
When the command latch enable signal CLE is “high level (hereinafter referred to as “H”)”, the card enable signal -CE is “low level (hereinafter referred to as “L”)” and the address latch enable signal ALE is “L”, an ID read command COM is latched from the pins D0 to D7 to the controller 4 at a rising edge of the write enable signal -WE. Next, when the command latch enable signal CLE is “L”, the card enable signal -CE is “L” and the address latch enable signal ALE is “H”, an address “00 (hexadecimal number)” is latched from the pins D0 to D7 to the controller 4, at a rising edge of the write enable signal -WE. Further, when the command latch enable signal CLE is “L”, the card enable signal -CE is “L”, and the address latch enable signal ALE is “L”, data 0 to data 3 are latched from the pins D0 to D7 to the host apparatus 20 at a rising edge of the read enable signal -RE.
Further, in the command sequence shown in
When the command latch enable signal CLE is “H”, the card enable signal -CE is “L”, and the address latch enable signal ALE is “L”, the ID read command COM I is latched from the pins D0 to D7 to the controller 4 at a rising edge of the command enable signal -WE. Next, when the command latch enable signal CLE is “L”, the card enable signal -CE is “L”, and the address latch enable signal ALE is “H”, addresses adr1 to adr3 are latched from the pins D0 to D7 to the controller 4, at a rising edge of the write enable signal -WE. Further, when the command latch enable signal CLE is “L”, the card enable signal -CE is “L”, and the address latch enable signal ALE is “L”, data 0 to data 3 are latched from the pins D0 to D7 to the host apparatus 20, at a rising edge of the read enable signal -RE.
In the command sequence of an ID read command shown in
Therefore, the memory card 1 of the embodiment processes the command sequence shown in
In this embodiment, although 4 cycles of addresses are input after input of an ID read command, the present invention is not limited to it. Also in other cases where a command sequence according to the specifications is not input from the host apparatus 20, the memory card of the present invention can perform proper processing without malfunction. Further, although the embodiment discloses an example in which the control procedure shown in
In the flash memory assumed by the host apparatus 20, each page has 528 bytes (a data storing portion of 512 bytes+a redundant portion of 16 bytes), and 32 pages constitute an erase unit (that is, 16 kbytes+0.5 kbytes (k is 1024)). A card having such a flash memory is sometimes referred to as “small block card” below.
In the meantime, in the flash memory 3 that is actually used, each page has 2112 bytes (for example, a data storing portion of 512 bytes×4+a redundancy portion of 10 bytes×4+a management data storing portion of 24 bytes), and 128 pages constitute an erase unit (specifically, 256 kbytes+8 kbytes). A card 1 having such a flash memory 3 is sometimes referred to as “large block card” below. In the following explanation, the erase unit of small block cards is referred to as “16 kbytes”, and the erase unit of large block cards is referred to as “256 kbytes”, for convenience' sake.
Each of the flash memory assumed by the host apparatus 20 and the flash memory 3 that is actually used has a page buffer for performing data input/output to the flash memory. A storage capacity of the page buffer provided to the flash memory assumed by the host apparatus 20 is 528 bytes (512 bytes+16 bytes). In the meantime, a storage capacity of the page buffer provided to the flash memory that is actually used is 2112 bytes (2048 bytes+64 bytes). In data writing and the like, each of the page buffers executes data input/output to the flash memory in the unit for 1 page that corresponds to its storage capacity.
The example shown in
To make large block cards practically useful products, it is desirable that the flash memory 3 shown in
Further, although the example shown in
The system of the host apparatus 20 side has application software 21, a file system 22, driver software 23, and a small block card physical access layer 24. In the meantime, the memory card 1 (large block card) has a small block card physical access layer 11, a small block card physical/small block card logical conversion layer 12, a small block card logical/large block card physical conversion layer 13, and a large block card physical access layer 14.
For example, when the application software 21 of the host apparatus 20 side makes a request of writing in a file to the file system 22, the file system 22 instructs the driver software 23 to perform sequential sector writing on the basis of the logical block address of the small block card. In response to the instruction, the driver software 23 performs logical/physical block conversion when performing sequential writing for each 16 kbyte blocks based on the logical block address of the small block card, and issues a random write command according to the physical block address of the small block card to the large block card through the small card physical access layer 24, to perform data transfer.
In write accesses, both in the small block card and the large block card, there is the precondition that information is transmitted and received in the order of (1) command, (2) page address (row address), (3) column address, (4) data, and (5) program verification command, on the protocol.
When the small block card physical access layer 11 on the large block card side receives a write command based on the physical block address of the small block card from the host apparatus 20, the layer 11 acquires the physical block address and data, and in addition a logical block address included in associated data associated with them.
The small block card physical/small block card logical conversion layer 12 has a first table for performing conversion, in data reading or the like, from a physical block address (corresponding to a 16 kbyte block) of the small block card into a logical block address (corresponding to a 16 kbyte block) of the small block card. When the small block card access layer 11 acquires a logical block address of the small block card in response to a write command, the conversion layer 12 reflects the logical address on the first table. The conversion layer 12 also reflects the physical block address on the first table.
The small block card logical/large block card physical conversion layer 13 has a second table for performing conversion, in data reading or the like, from logical block addresses (corresponding to 16 of sequential 16 kbyte blocks) of the small block card to a physical block address (corresponding to a 256 kbyte physical block) of the large block card. When the small block card physical access layer 11 acquires logical block addresses of the small block card in response to a write command, the conversion layer 12 reflects the logical block address on the second table.
The large block card physical access layer 14 determines data arrangement in the flash memory 3, based on the logical block address of the small block card which the small block card physical access layer 1 has acquired from the received write command, and sequentially write data of 16 kbytes in 2 kbytes (1 page) in a 256 kbyte physical block. Further, the large block card access layer 14 stores the acquired logical block address and physical block address of the small block card in a predetermined region in a management data region in the flash memory 3.
As described above, since the host apparatus 20 issues a command based on a physical block address of the small block card, the large block card side performs management such that it is clear which 256 kbyte physical block includes data corresponding to the physical block address of the small block card. Specifically, the large block card side manages the correlation between the logical and physical block addresses of the small block card for each 16 kbyte block, and performs management such that it is clear which 256 kbyte physical block in the large block card stores sequential data corresponding to logical block addresses of the small block card for a 256 kbyte block.
A packet of a command transmitted from the host apparatus 20 includes various information, such as command type information (“Write” in this example), an address (physical block address) and data (substantial data such as contents and associated data (512 bytes+16 bytes)), as shown in
In a packet having the above format, a “logical block address” (logical address corresponding to a 16 kbyte block to be accessed) of the small block card is arranged in a predetermined position of the associated data 16 bytes, as shown in
The host apparatus 20 side (the left side in
In the meantime, when the large block card side (the right side in
As described above, the host apparatus 20 performs a random write operation in 16 byte blocks according to the physical addresses of the small block. In such random write operations, generally, processing for rewriting only a part of a large block (256 kbytes) occurs frequently. Since erase can be only performed in blocks in NAND type flash memories, if only a part of a block is to be rewritten, it is necessary to write new data for rewrite in an erased new block, and copy the other data which is not to be rewritten in the new block from the old block including the old data to be rewritten to the new data. As described above, processing to rewrite only a part of a block involves a copy operation of the data not to be rewritten (involved data copy). If processing to rewrite only a part of a block frequently occurs, overhead greatly increases. Therefore, in this embodiment, according to the order of the logical addresses obtained from the host apparatus 20 side, the physical addresses are assigned again on the large block card side. This reduces occurrence of writing for only a part of a block, and suppresses increase of overhead.
In the large block card, each 256 kbyte physical block being the erase unit includes 16 blocks (hereinafter referred to as “host management block”) for writing data corresponding to a 16 kbyte block being a unit by which the host apparatus 20 manages data. In data writing, individual data items are arranged in the order of logical block addresses in the small block card.
Each host management block is constituted by 8 pages. Each page includes 4 data regions each having 512 bytes, and 10 byte ECC regions corresponding to the respective data regions. Further, a 24 byte management data region is provided after the last 512 byte data region (the fourth 512 byte data region) in each page. Therefore, the last 10 byte ECC region in each page is configured to deal with both the fourth 12 byte data region and the 24 byte management data region.
Among 128 management data regions each having 24 byte and included in a 256 kbyte physical block being the erase unit, the last 24 byte management data region, for example, is configured to store an address information item corresponding to the physical block address acquired from a command transmitted from the host apparatus 20 side, and an address information item corresponding to the logical block address together. These address information items are used in preparation of the first table of the small block card physical/small block card logical conversion layer 12 and the second table of the small block card logical/large block card physical conversion layer 13, explained with reference to
The block format shown in
The host apparatus 20 controls the memory card on the assumption that the memory card 1 is a nonvolatile memory having an erase block size of 16 kbytes. For example, when performing writing of data in the memory card 1, the host apparatus 20 inputs a serial data input command “80H (H denotes a hexadecimal system)” to the I/O pins (pin 10 to pin 17). Next, the host apparatus 20 input a column address “C/A” and a page address “P/A” to the I/O pins. The column address “C/A” and the page address “P/A” are a column address and a page address, respectively, in a virtual physical address space which the host apparatus 20 assumes that the memory card 1 has.
Further, the host apparatus 20 inputs write data 528 times to each of the I/O pins (pin 10 to pin 17). Specifically, the host apparatus 20 successively inputs (shift-in) data of 528 bits for each I/O pin (the total is 528 bytes for all the I/O pins), while clocking the input signal to the write enable pin 528 times. When the shift-in of the data is completed, the host apparatus 20 inputs a program command “10H” to the I/O pins. In response to the command, the memory card 1 outputs a signal “L” to the R/-B pin to indicate that the memory card 1 is in the busy state. Thereafter, the memory card 1 outputs a signal “H” to the R/-B pin after a predetermined period of time to indicate that the memory card has become the ready state.
However, the state of the R/-B pin in
The controller 4 recognizes the NAND type flash memory 3 as a nonvolatile memory having an erase block size of 256 kbytes. For example, in writing data in the NAND type flash memory 3, the controller 4 inputs a serial data input command “80H (H denotes hexadecimal number system)” to the I/O pins 1-8. Next, the controller 4 inputs a column address “C/A” and a page address “P/A” to the I/O pins 1-8. The column address “C/A” and the page address “P/A” are a column address and a page address, respectively, in a real physical address space which the controller 4 assumes that the NAND type flash memory 3 has. Therefore, they do not always correspond to the column address “C/A” and the page address “P/A” shown in
Further, the controller 4 inputs write data 2112 times to each of the I/O pins 1-8. Specifically, the controller 4 successively inputs (shift-in) data of 2112 bits for each I/O pin (the total is 2112 bytes for all the I/O pins), while clocking the input signal to the write enable pin 2112 times. When the shift-in of the data is completed, the controller 4 inputs a program command “10H” to the I/O pins 1-8. In response to the command, the memory card 1 outputs a signal “L” to the R/-B pin to indicate that the memory card 1 is in the busy state. Thereafter, the memory card 1 outputs a signal “H” to the R/-B pin after a predetermined period of time to indicate that the memory card has become the ready state. The state of the R/-B pin in
In
According to the memory card and the method of controlling the same of the embodiment of the present invention, it is possible to make a proper response to a host apparatus issuing commands having sequences which are neither defined nor prohibited in the specifications of the NAND type flash memory mounted on the memory card. Specifically, according to embodiments of the present invention, it is possible to provide a controller, a memory card and a method of controlling the same, which can properly respond to a host apparatus issuing commands with sequences which do not meet the specifications of the nonvolatile semiconductor memory mounted on the memory card.
The above embodiment is not the only embodiment of the present invention, but various embodiments can be made by changing the above structure or adding various constituent elements.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
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