A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an ic substrate, particularly ldd region in an mos transistor, is disclosed. dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the ic substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the ic substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both nldd and pldd regions.
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33. A process of a diffused region in an ic substrate, comprising the steps of:
forming a source dielectric layer on a top surface of said substrate;
forming an implanted region in a top region of said source dielectric layer by a process of implanting a set of dopant atoms into said source dielectric layer such that less than 10 percent of said dopant atoms pass through said source dielectric layer into said substrate; and
forming said diffused regions by a process of heating said substrate such that a portion of said dopant atoms diffuse from said implanted region into a top region of said substrate. #10#
1. A process of forming an integrated circuit (ic) containing a metal oxide semiconductor (mos) transistor further containing lightly doped drain (ldd) diffused regions, comprising the steps of:
forming an ldd source dielectric layer on a top surface of a well and an mos gate formed on a top surface of an mos gate dielectric layer formed on said top surface of said well;
forming an ldd implanted region in a top region of said ldd source dielectric layer by a process of implanting an ldd set of dopant atoms into said ldd source dielectric layer such that less than 10 percent of said ldd dopant atoms pass through said ldd source dielectric layer into said well; and
forming said ldd diffused regions by a process of heating said ic such that a portion of said ldd dopant atoms diffuse from said ldd implanted region into top regions of said well adjacent to said mos gate. #10#
14. A process of forming an ic containing an mos transistor further containing source and drain (S/D) diffused regions, comprising the steps of:
forming an S/D source dielectric layer on a top surface of a well, an mos gate formed on a top surface of an mos gate dielectric layer formed on said top surface of said well and gate sidewall spacers formed on lateral surfaces of said mos gate;
forming an S/D implanted region in a top region of said S/D source dielectric layer by a process of implanting an S/D set of dopant atoms into said S/D source dielectric layer such that less than 10 percent of said S/D dopant atoms pass through said S/D source dielectric layer into in said well; and
forming said S/D diffused regions by a process of heating said ic such that a portion of said S/D dopant atoms diffuse from said S/D implanted region into top regions of said well adjacent to said mos gate sidewall spacers. #10#
27. A process of forming an ic containing an n-channel metal oxide semiconductor (nmos) transistor and a p-channel metal oxide semiconductor (pmos) transistor, comprising the steps of:
forming an n-type lightly doped drain (nldd) source dielectric layer on a top surface of a p-well and an nmos gate formed on a top surface of an nmos gate dielectric layer formed on said top surface of said p-well;
forming an nldd implanted region in a top region of said nldd source dielectric layer by a process of implanting an nldd set of n-type dopant atoms into said nldd source dielectric layer such that less than 10 percent of said nldd dopant atoms pass through said nldd source dielectric layer into said p-well;
forming nldd diffused regions by a process of heating said ic such that a portion of said nldd dopant atoms diffuse from said nldd implanted region into top regions of said p-well adjacent to said nmos gate; #10#
forming a p-type lightly doped drain (pldd) source dielectric layer on a top surface of an n-well and a pmos gate formed on a top surface of a pmos gate dielectric layer formed on said top surface of said n-well;
forming a pldd implanted region in a top region of said pldd source dielectric layer by a process of implanting a pldd set of p-type dopant atoms into said pldd source dielectric layer such that less than 10 percent of said pldd dopant atoms pass through said pldd source dielectric layer into said n-well; and
forming pldd diffused regions by a process of heating said ic such that a portion of said pldd dopant atoms diffuse from said pldd implanted region into top regions of said n-well adjacent to said pmos gate.
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said step of forming an nldd source dielectric layer and said step of forming a pldd source dielectric layer are performed concurrently; and
said step of forming nldd diffused regions and said step of forming pldd diffused regions are performed concurrently.
30. The process of
forming an n-type source and drain (NSD) source dielectric layer on a top surface of said p-well, said nmos gate, and nmos gate sidewall spacers formed on lateral surfaces of said nmos gate;
forming an NSD implanted region in a top region of said NSD source dielectric layer by a process of implanting an NSD set of n-type dopant atoms into said NSD source dielectric layer such that less than 10 percent of said NSD dopant atoms pass through said NSD source dielectric layer into in said p-well;
forming NSD diffused regions by a process of heating said ic such that a portion of said NSD dopant atoms diffuse from said NSD implanted region into top regions of said p-well adjacent to said nmos gate sidewall spacers; #10#
forming a p-type source and drain (PSD) source dielectric layer on a top surface of said n-well, said pmos gate, and pmos gate sidewall spacers formed on lateral surfaces of said pmos gate;
forming a PSD implanted region in a top region of said PSD source dielectric layer by a process of implanting a PSD set of p-type dopant atoms into said PSD source dielectric layer such that less than 10 percent of said PSD dopant atoms pass through said PSD source dielectric layer into in said n-well; and
forming PSD diffused regions by a process of heating said ic such that a portion of said PSD dopant atoms diffuse from said PSD implanted region into top regions of said n-well adjacent to said pmos gate sidewall spacers.
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said step of forming an NSD source dielectric layer and said step of forming a PSD source dielectric layer are performed concurrently; and
said step of forming NSD diffused regions and said step of forming PSD diffused regions are performed concurrently.
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This invention relates to the field of integrated circuits. More particularly, this invention relates to methods to form shallow junctions in integrated circuits.
It is well known that transistors in advanced integrated circuits (ICs) are shrinking with each new fabrication technology node, as articulated by Moore's Law. For example, at the 32 nanometer technology node, it is desired to form doped regions in transistors such as source and drain extensions which are less than 10 nanometers deep with average doping densities above 1021 cm−3. Formation of heavily doped shallow regions is problematic because anneals sufficient to repair damage to the IC substrate cause dopants to diffuse deeper than desired.
This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
The instant invention provides a process for forming diffused regions in an integrated circuit (IC) less than 20 nanometers deep with an average doping dose above 1014 cm−2, in particular lightly doped drain (LDD) regions in metal oxide semiconductor (MOS) transistors. A source dielectric layer is formed on an existing surface of the IC. Dopants are implanted into the source dielectric layer in a region above the region of the IC to be doped, using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation. The majority of the dopants are deposited in the source dielectric layer, so that negligible damage is generated in the IC substrate. A rapid thermal drive process such as a spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate to attain a desired depth and average doping density in the doped region. The inventive process may also be applied to forming source and drain (S/D) regions in p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors. One source dielectric layer may be used for forming both NLDD and PLDD regions. Similarly, one source dielectric layer may be used for forming both NSD and PSD regions.
The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
The instant invention provides a process for forming a doped region in an integrated circuit (IC) less than 20 nanometers deep with an average doping dose above 1014 cm−2. A source dielectric layer is formed on an existing surface of the IC. Dopants are implanted into the source dielectric layer in a region above the region of the IC to be doped, using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation. The majority of the dopants are deposited in the source dielectric layer, so that negligible damage is generated in the IC substrate. A thermal drive process diffuses the implanted dopants into the IC substrate to attain a desired depth and average doping density in the doped region. The inventive process may be applied to forming lightly doped drain (LDD) regions in both p-channel metal oxide semiconductor (PMOS) transistors and n-channel metal oxide semiconductor (NMOS) transistors, and to forming source and drain (S/D) regions in PMOS and NMOS transistors.
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A GCIB process may be performed by pressurizing a gas mixture of a carrier gas, such a helium and/or argon, and a dopant containing gas such as diborane, phosphine or arsine, at a ratio between 90%:10% and 98%:2%, releasing the gas mixture through a 100 to 500 micron diameter nozzle so that the gas mixture condenses into clusters of a few hundred to a few thousand atoms, ionizing the clusters such that each cluster typically has one electron unit of charge, approximately 1.6·10−19 coulomb, and accelerating the clusters toward an IC, commonly at an acceleration energy between 3 and 30 keV. Each cluster typically contains between 10 and 3000 dopant atoms. The clusters break up upon impact with a top surface of a source dielectric layer and dopant atoms in the clusters penetrate the source dielectric layer to a depth of a few nanometers. A majority of the carrier gas atoms in the clusters escape immediately after impact of the clusters. The acceleration energy of each cluster is divided among the atoms in each cluster, so that a very low fraction, much less than 1 percent, of dopant atoms have sufficient energy to penetrate the source dielectric layer and displace a silicon atom in a substrate of the IC. Doses greater than 1015 atoms/cm2 of embedded dopant atoms in the source dielectric layer may be attained in GCIB processes. The GCIB processes desirably provide a method of attaining useful doses without the amount of silicon crystal lattice damage that would be expected in conventional ion implantation processes without source dielectric layers providing equivalent doses. GCIB processes may be performed in commercially available semiconductor processing equipment, for example GCIB tools made by TEL-Epion.
Alternatively, a molecular ion process may be performed by accelerating molecules such as carborane (C2B10H12), phosphorus dimers (P2) or tetramers (P4), or arsenic dimers (As2) or tetramers (As4), containing boron, phosphorus or arsenic dopant atoms, respectively, toward an IC at acceleration energies between 3 and 30 keV. The acceleration energy of each molecule is divided among the atoms in each molecule, so that a low fraction, less than 5 percent, of dopant atoms have sufficient energy to penetrate a source dielectric layer and displace a silicon atom in a substrate of the IC. Doses greater than 1015 atoms/cm2 of embedded dopant atoms in the source dielectric layer may be attained in molecular ion implantation processes. The molecular ion implantation processes desirably provide a method of attaining useful doses without the amount of silicon crystal lattice damage that would be expected in conventional ion implantation processes without source dielectric layers providing equivalent doses. Molecular ion implantation processes may be performed in commercially available semiconductor ion implanters.
Alternatively, an atomic ion implantation process may be performed by accelerating individual dopant atoms such as boron, phosphorus or arsenic toward an IC at acceleration energies between 2 and 10 keV. In a preferred embodiment, over 90 percent of the dopant atoms are absorbed in a source dielectric layer, so that less than 10 percent of the dopant atoms impact a single crystal silicon substrate below the source dielectric layer, desirably reducing an amount of silicon crystal lattice damage that would be expected in conventional ion implantation processes without source dielectric layers providing equivalent doses. Atomic ion implantation processes may be performed in commercially available semiconductor ion implanters.
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It will be recognized by those familiar with IC fabrication that the advantages of the instant embodiment may be applied to formation of NLDD diffused regions, PSD diffused region and NSD diffused regions.
It will be recognized by those familiar with IC fabrication that an extension of an LDD region toward or under a gate may be varied by adjusting an amount of source dielectric material deposited on lateral surfaces of the gate. A deposition process for a source dielectric layer may be adjusted from totally conformal to totally anisotropic, advantageously providing a means for providing a desired extension of the LDD region independently of a dose or depth of the LDD region.
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