A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.
|
1. A mounted planar semiconductor device, comprising:
a heat sink having a flat surface, a submount having two opposing first and second flat surfaces, and a planar semiconductor device having a flat mounting surface, wherein the flat surface of the heat sink is soldered to the first flat surface of the submount using a first solder film, and the second flat surface of the submount is soldered to the flat mounting surface of the planar semiconductor device using a second solder film, so as to form a stack;
wherein the planar semiconductor device, the submount, and the heat sink have first, second, and third coefficients of thermal expansion CTE1, CTE2, and CTE3, respectively, wherein said coefficients of thermal expansion are measured in a direction parallel to said flat surfaces, and wherein CTE3>CTE1>CTE2 or CTE3<CTE1<CTE2.
2. A mounted planar semiconductor device of
3. A mounted planar semiconductor device of
4. A mounted planar semiconductor device of
5. A mounted planar semiconductor device of
6. A mounted planar semiconductor device of
7. A mounted planar semiconductor device of
8. A mounted planar semiconductor device of
11. A mounted planar semiconductor device of
12. A mounted planar semiconductor device of
|
The present application is a divisional application of U.S. patent application Ser. No. 12/167,125, filed on Jul. 2, 2008 now U.S. Pat. No. 7,816,155, entitled “A Mounted Semiconductor Device And A Method For Making The Same”, which claims priority from U.S. Provisional Patent Application No. 60/948,300 filed Jul. 6, 2007, entitled “A Cost Effective Method Of Mounting High Power Optical Devices On Mismatched Substrates”, each of which are incorporated herein by reference for all purposes.
The present invention is related to mounting of planar semiconductor devices, and in particular to low-stress mounting of semiconductor laser diodes onto thermally mismatched heat sinks.
Planar semiconductor devices including patterned thin film structures formed on a semiconductor substrate can generate a considerable amount of heat during normal operation. For example, a single emitter laser diode chip rated at 5 W of output radiation at an efficiency of 40%, will generate 3 W of heat during operation at full rated power. This heat needs to be removed to prevent overheating and failure of the device.
Heat removal is achieved by mounting a semiconductor device onto a heat sink made of a material having a good thermal conductivity, e.g. copper. Once the heat is transferred to the copper heat sink, it can be removed by cooling the heat sink with, for example, a Peltier cooler. It is therefore essential to ensure a good thermal contact between a semiconductor device and a heat sink. In order to provide such a contact, and also to ensure that the device is mounted in a reliable and stable fashion, soldering is often used.
Soldering a semiconductor device, especially a radiation-emitting semiconductor device such as a laser diode, to a copper heat sink has a serious drawback. A laser diode chip has to be mounted at a certain position relative to a collimating lens. A shift of the chip relative to the lens degrades a laser performance and should be avoided. To avoid creeping of laser diode chip during operation or storage at varying temperatures, a hard solder is frequently used. However, soldering of a semiconductor device on a GaAs or a silicon substrate, having relatively small coefficient of thermal expansion, to copper having a large coefficient of thermal expansion, with a hard solder creates a significant amount of residual stress in the semiconductor device, which greatly reduces reliability of the latter. A material with a coefficient of thermal expansion matching that of the semiconductor device can be used to reduce the stress to a low enough value. For example, copper-tungsten (CuW) alloy is used in prior art to match the coefficient of thermal expansion of gallium arsenide (GaAs). However, thermally matching alloys are often expensive to make and difficult to process.
An alternative approach established in the prior art is based on employing a submount, placed between a semiconductor device and a heat sink, for better thermal matching between the semiconductor device and the surface it is mounted on. To reduce the residual stress in a semiconductor device mounted on a submount, Mochida et al., in US20050127144A1 which is incorporated herein by reference, describe various techniques using pressure bonding and, or creating temperature gradients, to offset the residual stresses generated upon cooling the compound heat sink. Further, Moriya et al., in U.S. Pat. No. 6,961,357 which is incorporated herein by reference, optimize a shape of a submount to reduce residual stress at a particular point, corresponding to the light emitting region of a mounted laser diode chip, to a value lower than 20 MPa, which is considered in U.S. Pat. No. 6,961,357 to be a threshold value of stress above which a defect rate increases considerably (see FIG. 5 of said Patent document). Still yet further, Yamane et al., in US20040201029A1 which is incorporated herein by reference, describe various methods of applying soldering compounds aiming at minimizing the melting point of compound solder films, to lower soldering temperature, and to lower the residual mechanical stresses correspondingly.
The abovementioned approaches utilizing a submount for relieving the stress in a semiconductor device share common problems. Mounting methods employing a submount require an extra process step of mounting the submount on a heat sink, or mounting the semiconductor device to the submount, whichever step is done first. A special mounting equipment needs to be developed, for example, in case of US20050127144A1 by Mochida et al., a heated mounting chuck (collet) needed to be developed. More complicated mounting process and utilization of special materials for precise thermal matching of submount to the semiconductor device increase manufacturing time and cost, as compared to mounting of semiconductor devices directly onto a copper heat sink.
It is therefore an object of the present invention to provide a method for mounting a semiconductor device allowing one to considerably lower the levels of residual mechanical stress in a mounted semiconductor device without having to use expensive or difficult to machine submount materials or adding new major steps in the manufacturing process. Further, it is an object of the present invention to provide a mounted semiconductor device having low levels of the residual mechanical stress, lower than 20 MPa and, preferably, lower than 10 MPa.
The device and method of present invention meet the above stated objectives. Not only that, but the method of the present invention allows one to use a hard solder having relatively high melting point, to ensure a high mechanical stability and reliability of a mounted device.
In accordance with the invention there is provided a method for low-stress mounting of a planar semiconductor device, comprising:
providing a heat sink having a flat surface and a submount having two opposing first and second flat surfaces, wherein two of three said surfaces have solder films adhered thereon;
cold contacting the flat surface of the heat sink to the first flat surface of the submount, and cold contacting the second flat surface of the submount to a flat surface of the planar semiconductor device, so as to form a stack, wherein the solder films are disposed on both sides of the submount;
melting the solder films on both sides of the submount; and
allowing the solder films to cool and solidify;
wherein the planar semiconductor device, the submount, and the heat sink have first, second, and third coefficients of thermal expansion CTE1, CTE2, and CTE3, respectively, wherein said coefficients of thermal expansion are measured in a direction parallel to said flat surfaces, and wherein the value of CTE1 is in between the values of CTE2 and CTE3.
In accordance with another aspect of the invention there is further provided a mounted semiconductor device, comprising:
a heat sink having a flat surface, a submount having two opposing first and second flat surfaces, and a planar semiconductor device having a flat mounting surface, wherein the flat surface of the heat sink is soldered to the first flat surface of the submount using a first solder film, and the second flat surface of the submount is soldered to the flat mounting surface of the planar semiconductor device using a second solder film, so as to form a stack;
wherein the planar semiconductor device, the submount, and the heat sink have first, second, and third coefficients of thermal expansion CTE1, CTE2, and CTE3, respectively, wherein said coefficients of thermal expansion are measured in a direction parallel to said flat surfaces, and wherein CTE3>CTE1>CTE2 or CTE3<CTE1<CTE2.
Exemplary embodiments will now be described in conjunction with the drawings in which:
While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives, modifications and equivalents, as will be appreciated by those of skill in the art.
Referring to
The method of the present invention advantageously differs from the method of
Turning now to
CTE3>CTE1>CTE2 (1)
or, for heat sinks with the coefficient of thermal expansion smaller than that of the semiconductor device,
CTE3<CTE1<CTE2 (2)
Referring now to
(c′−c)/c=(b′−b)/b, (3)
wherein, according to condition (1) above,
(b′−b)/b<(a′−a)/a (4)
Turning now to
In contrast to the method of soldering of
Turning now to
The method of the present invention allows one to minimize residual stress in a semiconductor device being mounted by adjusting the thickness of a submount, as opposed to the prior art method of matching the bulk thermal expansion coefficients which often requires one to use customized expensive alloys such as copper-tungsten (CuW) alloy with a customized percentage of copper and tungsten. As a result, the present method can be advantageously used to mount semiconductor devices, such as GaAs laser diodes onto inexpensive ceramic substrates with the mismatch of thermal coefficient of expansion exceeding 2*10−6/° C. At the same time, unexpectedly and advantageously, an inexpensive heat sink material having a high thermal expansion coefficient of over 15*10−6/° C., such as copper, can be used.
An important aspect of the present invention is that the mounting be performed in a single soldering step. Single-step soldering allows one to further leverage the residual stress levels reduction by making sure that the submount and the semiconductor device are flat when the solder begins to solidify as a result of cooling the stack. When a single-step soldering is used, both normal and tangential components of residual stress of the semiconductor device are much lower than the value of an acceptable residual stress level of 20 MPa. GaAs laser diode chips having a thickness of 0.1 mm have been mounted onto a 0.24 mm thick SiC submount mounted onto a 1 mm thick copper heat sink using a single-step soldering, and manufacturing cost savings combined with excellent reliability of the mounted laser diodes have been demonstrated.
Turning now to
In
A top view microphotograph of a mounted laser diode stack 800 in
The method of the present invention for mounting of a semiconductor device onto a substrate can be used to mount laser diodes, light emitting diodes, or any other planar semiconductor devices which generate heat during operation. Various materials can be used for a heat sink and a submount, for as long as conditions (1) or (2) above are fulfilled, together with condition (3). To reduce residual stress in a mounted semiconductor device according to a method of the present invention, the coefficient of thermal expansion of the semiconductor element has to have a value in between of the values of coefficients of thermal expansion of the heat sink and the submount. For example, when copper is used as a heat sink for a gallium arsenide semiconductor device, the coefficient of thermal expansion of the heat sink is larger than that of the semiconductor device. Therefore, a low-expansion submount, such as silicon carbide submount, should be used. On the other hand, when a low-expansion material, such as aluminum nitride, is used as a heat sink for a gallium arsenide device, a high-expansion submount can be used. In either case, the thickness of the submount is chosen so that the condition (3) above is fulfilled.
Patent | Priority | Assignee | Title |
10297276, | Oct 28 2014 | Western Digital Technologies, INC | Systems and devices for acheiving high throughput attachment and sub-micron alignment of components |
8890194, | Aug 14 2012 | ALPAD CORPORATION | Semiconductor light emitting device |
8908349, | Mar 31 2011 | NGK Insulators, Ltd | Member for semiconductor manufacturing apparatus |
9902023, | Oct 28 2014 | Western Digital Technologies, INC | Systems and devices for achieving high throughput attachment and sub-micron alignment of components |
Patent | Priority | Assignee | Title |
3593070, | |||
6335863, | Jan 16 1998 | Sumitomo Electric Industries, Ltd. | Package for semiconductors, and semiconductor module that employs the package |
6895027, | Jan 29 2002 | Spectra-Physics | CTE compensation of semiconductor laser bars |
7811903, | Dec 06 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Thin flip-chip method |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 31 2015 | JDS Uniphase Corporation | Lumentum Operations LLC | CORRECTIVE ASSIGNMENT TO CORRECT INCORRECT PATENTS 7,868,247 AND 6,476,312 ON PAGE A-A33 PREVIOUSLY RECORDED ON REEL 036420 FRAME 0340 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT | 037562 | /0513 | |
Jul 31 2015 | JDS Uniphase Corporation | Lumentum Operations LLC | CORRECTIVE ASSIGNMENT TO CORRECT PATENTS 7,868,247 AND 6,476,312 LISTED ON PAGE A-A33 PREVIOUSLY RECORDED ON REEL 036420 FRAME 0340 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT | 037627 | /0641 | |
Jul 31 2015 | JDS Uniphase Corporation | Lumentum Operations LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036420 | /0340 | |
Dec 10 2018 | Lumentum Operations LLC | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | PATENT SECURITY AGREEMENT | 047788 | /0511 | |
Dec 10 2018 | OCLARO FIBER OPTICS, INC | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | PATENT SECURITY AGREEMENT | 047788 | /0511 | |
Dec 10 2018 | OCLARO, INC | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | PATENT SECURITY AGREEMENT | 047788 | /0511 | |
Dec 12 2019 | DEUTSCHE AG NEW YORK BRANCH | Lumentum Operations LLC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 051287 | /0556 | |
Dec 12 2019 | DEUTSCHE AG NEW YORK BRANCH | OCLARO FIBER OPTICS, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 051287 | /0556 | |
Dec 12 2019 | DEUTSCHE AG NEW YORK BRANCH | OCLARO, INC | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 051287 | /0556 |
Date | Maintenance Fee Events |
Nov 24 2015 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Jul 14 2016 | ASPN: Payor Number Assigned. |
Apr 25 2017 | ASPN: Payor Number Assigned. |
Apr 25 2017 | RMPN: Payer Number De-assigned. |
Nov 27 2019 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Jan 22 2024 | REM: Maintenance Fee Reminder Mailed. |
Jul 08 2024 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
Jun 05 2015 | 4 years fee payment window open |
Dec 05 2015 | 6 months grace period start (w surcharge) |
Jun 05 2016 | patent expiry (for year 4) |
Jun 05 2018 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jun 05 2019 | 8 years fee payment window open |
Dec 05 2019 | 6 months grace period start (w surcharge) |
Jun 05 2020 | patent expiry (for year 8) |
Jun 05 2022 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jun 05 2023 | 12 years fee payment window open |
Dec 05 2023 | 6 months grace period start (w surcharge) |
Jun 05 2024 | patent expiry (for year 12) |
Jun 05 2026 | 2 years to revive unintentionally abandoned end. (for year 12) |