A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.
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1. A semiconductor signal processing device comprising:
a plurality of unit operator cells arranged in rows and columns and being divided into operation unit blocks in a row direction, each for storing data in a nonvolatile manner and passing a current of a different amount according to the storage data;
a write circuit for expanding each bit of multi-bit numerical data to a number of bits corresponding to a bit position in the numerical data to produce internal write data in each operation unit block, for concurrently selecting unit operator cells in the operation unit block, and for concurrently writing bits of said internal write data corresponding to said multi-bit numerical data in corresponding unit operator cells in the operation unit block;
a plurality of global read data lines arranged corresponding to the columns of said plurality of unit operator cells;
a read circuit for concurrently selecting the unit operator cells of a plurality of rows in said plurality of unit operator cells in data reading, and for passing a current corresponding to data stored in each selected selection unit operator cell through a corresponding global read data line; and
a conversion circuit for adding currents supplied through the global read data lines in an analog manner in each operation unit block, and converting a result of the adding into a digital signal.
8. A semiconductor signal processing device comprising:
a plurality of unit operator cells arranged in rows and columns, each for storing data in a nonvolatile manner, each unit operator cell including a storage element causing a current flow of an amount depending on storage data, said plurality of unit operator cells being divided into a plurality of operation unit blocks in a row direction and being divided into a plurality of sub-array blocks in a column direction, a bit position of multi-bit numerical data of an operation target being previously allocated to each of said plurality of sub-array blocks;
a write circuit for concurrently writing corresponding bits of said multi-bit numerical data in sub-array blocks previously allocated according to weights of bit positions of the corresponding bits in said multi-bit numerical data in said plurality of sub-array blocks, said write circuit writing data of an identical bit position in a set of plurality of operation target data in the unit operator cells being aligned in said column direction in one sub-array block;
a plurality of global read data lines arranged corresponding to the operation unit blocks of the unit operator cells and commonly to the sub-array blocks of each respective operation unit block;
a read circuit for passing a current through a corresponding global read line according to data stored in a selected unit operator cell in each sub-array block in which said set of operation target data is stored, said read circuit connecting the sub-array block and said corresponding global read data line for a time period being set according to said bit position allocated to each sub-array block; and
a conversion circuit for adding the currents passed through the corresponding global read data line in the operation unit block in analog manner, to convert a result of the adding into a digital signal.
2. The semiconductor signal processing device according to
a plurality of global write data lines arranged corresponding to the columns of the unit operator cells and extending in a column direction in each operation unit block, each for transferring said internal write data; and
a plurality of global write drivers arranged corresponding to the global write data lines, for concurrently transferring corresponding bits of said multi-bit numerical data to corresponding global write data lines to produce internal write data, said plurality of global write drivers being provided such that each bit of said multi-bit numerical data are transferred to the global write data lines corresponding in number to a weight of a bit position of each respective bit in said multi-bit numerical data.
3. The semiconductor signal processing device according to
said write circuit writes first internal write data produced from first multi-bit numerical data in the first SOI transistor of a selected unit operator cell, and writes second internal write data produced from second multi-bit numerical data in the second SOI transistor of the selected unit operator cell, and writes said first internal write data and said second internal write data in different rows of the unit operator cells while sequentially shifting bit locations of said first internal write data and said second internal write data, and
said read circuit passes a current through the corresponding global read data line according to an amount of current flowing through said first and second SOI transistors.
4. The semiconductor signal processing device according to
5. The semiconductor signal processing device according to
said plurality of rows are selected one for each different sub-array block.
6. The semiconductor signal processing device according to
said write circuit includes:
a plurality of global write data lines provided commonly to each operation unit block, and arranged corresponding to the rows of the unit operator cells, for transferring the internal write data; and
a plurality of global write drivers arranged corresponding to the respective global write data lines, for concurrently transferring corresponding bits of said multi-bit numerical data to corresponding global write data lines to produce internal write data, said plurality of global write drivers being arranged such that each bit of the multi-bit numerical data is transferred to the global write data lines of the number corresponding to a weight of a bit location of each bit in said multi-bit numerical data; and
a write cell selection circuit arranged corresponding to the columns of the unit operator cells in each sub-array block, for concurrently selecting unit operator cells of corresponding columns of the unit operator cells to write the data on the global write data lines in corresponding unit operator cells,
the global read data lines are arranged commonly to said plurality of sub-array blocks, and
said read circuit selects unit operator cells in units of columns in a sub-array block in which operation target data is written, for passing currents through the global read data line arranged corresponding to a selected column according to the data stored in the unit operator cells of the selected column.
7. The semiconductor signal processing device according to
said read circuit includes read gate circuits for sequentially selecting different columns of the unit operator cells, and
said conversion circuit includes:
a current addition line arranged corresponding to each operation unit block and commonly to the global read data lines of a corresponding operation unit block; and
an analog-digital converter arranged corresponding to each current addition line, for converting an analog voltage value of a corresponding current addition line into a digital signal, to produce a conversion result for each of the different unit operator cell columns.
9. The semiconductor signal processing device according to
a write word line selection circuit for concurrently selecting unit operator cells aligned in the column direction in each sub-array block of write target of the numerical data;
a data line drive circuit provided corresponding to each sub-array block, for receiving data bits of the allocated bit position of different multi-bit numerical data, for concurrently writing corresponding bits of the different multi-bit numerical data into different unit operator cells selected by said write word line selection circuit.
10. The semiconductor signal processing device according to
each unit operator cell includes:
first and second SOI transistors formed on an insulating layer, each for storing data according to charges accumulated in a body region thereof, said first and second SOI transistors being connected in series between a reference power supply and a corresponding bit line; and
third and fourth SOI transistors arranged being separated from the bit line, for transferring write data to the body regions of said first and second SOI transistors in data writing, respectively.
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This application is a Divisional of U.S. application Ser. No. 12/390,213, filed on Feb. 20, 2009, now U.S. Pat. No. 8,130,582 claiming priority of Japanese Application Nos. 2008-039107, filed on Feb. 20, 2008, 2008-050484, filed on Feb, 29, 2008, 2008-052868, filed Mar. 4, 2008, 2008-84276, filed on Mar. 27, 2008, 2008-08776, filed Mar. 28, 2008, 2008-08777, filed on Mar. 28, 2008, 2008-236668, filed on Sep. 16, 2008, the entire contents of each of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor signal processing device, and particularly to a configuration of a semiconductor signal processing device including an operational circuit in which a semiconductor memory is used.
2. Description of the Background Art
A system LSI (Large Scale Integration) called SoC (System on Chip) is widely used to achieve down-sizing, weight-lighting and speed-up of a processing system. In SoC, a memory and a logic (processing device) are integrated on a common semiconductor substrate. In the system LSI, because the memory and the logic are connected by on-chip interconnections, a large amount of data can be transferred at high speed to allow the high-speed processing. In an article by K. Arimoto et, al., titled “A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory,” 2006 Symposium on VLSI Circuits, Digest of Technical Papers, June 2006 (hereinafter referred to as Non-Patent Document 1), TTRAM (Twin Transistor Random Access Memory) is proposed as a semiconductor memory suitable for embedding in the system LSI.
In Non-Patent Document 1, a transistor having an SOI (Silicon On Insulator) structure is utilized to store data in a nonvolatile manner. A threshold voltage of a data storage transistor is changed by accumulating charges in a body region of the data storage SOI transistor, and the storage data is converted into threshold voltage information. In data reading, an access transistor is set in an on-state, and the data storage transistor is connected between a source line and a bit line. Because an amount of current flowing through the bit line depends on the threshold voltage of the data storage transistor, the data is read by sensing the bit line current.
In the configuration of Non-Patent Document 1, the charges are accumulated in the body region of the transistor having the SOI structure, so that the data can be stored in the nonvolatile manner. Because the charges are retained in the body region, data can be read in a nondestructive manner, a restoring operation in which the storage data is re-written is not required unlike DRAM (Dynamic Random Access Memory), and a read cycle time can be shortened. Data is read by sensing the current, so that the data can be read at high speed even under a low power supply voltage condition.
A memory cell is formed of two transistors, so that an occupied area by the memory cell can be reduced so that the memory cells re arranged in high density. The charges are accumulated in the body region of the transistor of the SOI structure, so that the data can stably be retained even under the low power supply voltage condition.
A need for high-speed digital signal processing for processing large amount of data such as audio and image at high speed is increased in a mobile application such as a mobile terminal equipment. In conventional software-based processing with CPU (Central Processing Unit) and DSP (Digital Signal Processor), a performance required in current multi-media processing cannot be achieved. Therefore, usually the processing with hardware logic is performed.
However, as miniaturization of the semiconductor manufacturing process and complexity of system advance, such problems are caused as cost increase of semiconductor process, and prolonged design and verification periods and resultant cost increase. Therefore, there is a strong demand to perform various kinds of large-scale data processing at high speed through replacement by software. Naturally, from the viewpoint of built-in application, there is a strong demand for high processing capability with low power consumption, that is, high-energy processing capability.
As a configuration for satisfying such demand, Japanese Patent Laying-Open No. 2006-099232, for example, discloses the one, in which an operational processing unit is disposed corresponding to each memory cell column of a semiconductor memory array and operational processing is concurrently performed in plural operational processing units. In the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, operation processing contents can be set by changing micro program contents. In the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, a sense amplifier and a write driver are disposed for each memory cell column as a data transfer circuit at a data transfer section between the memory array and the operational processing units. The memory cell is used to store operation target data and operation result data.
In the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, the SIMD (Single Instruction Multiple Data Stream) operational processing unit and the memory are closely coupled to solve a data transfer bottle neck between a memory and a processor, and operation performance close to hardware is achieved by massive parallel operation.
The configuration disclosed in Japanese Patent Laying-Open No. 2006-099232 is characterized in that fine granularity processing element of one bit or two bits is utilized and the operational processing unit performs the operation based on bit-by-bit data from the memory. That is, in the configuration disclosed in Japanese Patent Laying-Open No. 2006-099232, a plurality of operational processing units concurrently perform the operation in a bit serial fashion, thereby achieving the high-performance operation processing.
Japanese Patent Laying-Open No. 2004-264896 discloses a configuration, in which a memory cell is provided with an operation function without the use of an operational processing unit. In the configuration disclosed in Japanese Patent Laying-Open No. 2004-264896, a storage capacitor storing data and a load capacitor are connected in series between a bit line pair. A reference voltage and operation data are applied at both ends of the series-connected ferroelectric capacitors, and operation result is supplied from a connection node of the ferroelectric capacitors. In Japanese Patent Laying-Open No. 2004-264896, using a hysteresis in polarization of the ferroelectric capacitor, dependency of a moving amount of charges on match/mismatch of logical values of the storage data and operation data is utilized.
Japanese Patent Laying-Open No. 2007-213747 discloses a configuration, in which an operation of the storage data and write data is performed using one ferroelectric capacitor. In the configuration disclosed in Japanese Patent Laying-Open No. 2007-213747, a one-shot pulse signal is applied to a bit line of a bit line pair according to a logical value of the operation data, and a potential at the other of the bit line pair is amplified by a sense amplifier. In Japanese Patent Laying-Open No. 2007-213747, the dependency of the moving amount of charges of the ferroelectric capacitor on match/mismatch of logical values of the storage data and operation data is also utilized.
Japanese Patent Laying-Open No. 07-249290 discloses a configuration, in which an SRAM (Static Random Access Memory) cell is provided with an operation function. In the configuration disclosed in Japanese Patent Laying-Open No. 07-249290, access transistors of the SRAM cell have on-off control made independently of each other, and a high-side cell power supply voltage and a low-side cell power supply voltage are also controlled in a unit of a memory cell row. The bit line connection, the on-off control of the access transistors, and the control of the high-side and low-side cell power supply voltages are combined to perform various logic operations.
Japanese Patent Laying-Open No. 08-031168 discloses a configuration, in which a sense amplifier performs an operation processing of the storage data of a memory cell with the use of a DRAM (Dynamic Random Access Memory) cell. In the configuration disclosed in Japanese Patent Laying-Open No. 08-031168, plural memory cells and plural dummy cells are connected to bit lines of the bit line pair, respectively. A logic operation is performed on storage data of the plural memory cells by setting the respective storage data of the plural dummy cells at one of an intermediate value, “1” and “0”.
Japanese Patent Laying-Open No. 07-182874 discloses a configuration, in which an operation is performed with the memory cell. In the configuration disclosed in Japanese Patent Laying-Open No. 07-182874, an operational circuit is connected to a bit line and a static storage circuit, and includes an operation result output terminal. The operational circuit performs a one-bit arithmetic or logic operation on the input data received from the bit line and the data stored in the storage circuit, and supplies the operation result through the operation result output terminal.
Japanese Patent Laying-Open No. 2000-284943 discloses a configuration, in which an operation is performed using a memory cell. In the configuration disclosed in Japanese Patent Laying-Open No. 2000-284943, a semiconductor memory includes plural memory cells, a word line corresponding to an X-address, and a pair of bit lines corresponding to a Y-address. A logic operational circuit is provided for each pair of bit lines, and the plural logic operational circuits are simultaneously activated in response to a logic selection signal. The operation result of the logic operational circuit is simultaneously written in all the Y-addresses on at least one selected X-address. The logic operational circuit is provided for each pair of bit lines, so that data on all the pairs of bit lines can simultaneously be operated and thus the operation can be performed in a short time for a large amount of data.
FPGA (Field Programmable Gate Array) with an LUT (Look Up Table) mounted thereon is a logic device that can implement various logic circuits by programming a logic specification. For example, a memory having a storage capacity of N bits by M bits can implement an LUT operational unit having a function of a logic function, which outputs M-bit data for N-bit input data. A programmable LUT operational processing unit can be implemented with the use of FPGA as the memory. However, in the conventional LUT operational processing unit, the implementable logic function is directly restricted by the memory capacity.
Japanese Patent Laying-Open No. 2007-226944 discloses an LUT (Look Up Table) operational processing unit that realizes plural functions. In the configuration disclosed in Japanese Patent Laying-Open No. 2007-226944, when a control signal line connected to a memory cell is activated, the memory cell performs one of the data read and write and the output of a predetermined value constituting an operation result of the operation target data in response to a mode control signal. An address decoder receives a data write address, a data read address, or operation target data, and activates the control signal line corresponding to the received address/data based on which the mode control signal designates, the data write, the data read, or the operation processing. Therefore, a circuit scale is maintained without preparing the memory cells for storing data of a truth table, and the LUT operational processing unit having two independent operation functions is implemented.
In T. Tsuji, et al., “A 1.2V 1 Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture,” 2004 Symposium on VLSI Circuits Digest of Technical Papers, June 2004, pp. 450-453 (hereinafter referred to as Non-Patent Document 2), a configuration in which MRAM is utilized is described as an example of a nonvolatile memory suitable for the built-in application. In Non-Patent Document 2, a magnetic field is induced by a current flowing through a bit line and a write word line, a magnetization direction of a free layer of an MTJ (Magnetic Tunnel Junction) element is set by the magnetic field, and a resistance value is changed due to a magneto-resistance effect. The resistance value of the MTJ element is correlated with the storage data.
In the configurations disclosed in the above-described Japanese Patent Laying-Open Nos. 2004-264896, 2007-213747, 07-249290, 08-031168, 07-182874, and 2000-284943, the logic operation is performed with the memory cell or the sense amplifier. Accordingly, there is no need to read the data stored in the memory cell outside the memory for performing the operation processing with a separately provided operational processing unit, achieving speed-up of a operation processing.
In the configurations disclosed in Japanese Patent Laying-Open Nos. 2004-264896, 2007-213747, 07-249290, and 08-031168, the operation is performed in each memory cell column, so that the operation of a fine granularity can be realized without largely adding hardware.
However, in the configuration where two series-connected ferroelectric capacitors are used as the configuration of Japanese Patent Laying-Open No. 2004-264896, although it is described that the nondestructive data read can be performed, the restoring operation is performed by writing the reverse data of the operation data after the operational processing, in order to avoid a distortion of a hysteresis characteristic of the ferroelectric capacitor during the operational processing. Accordingly, the operation data transfer, the operation, and the restoring are required during the operation. The operation cycle cannot be shortened due to the restoring, and the high-speed processing is hardly realized.
In the configuration disclosed in Japanese Patent Laying-Open No. 2007-213747, although one ferroelectric capacitor and two transfer gates are used as one operator cell, the data stored in the ferroelectric capacitor is destructively read during the operation. Accordingly, the operational processing cannot be performed by combining different operation data with the same data.
Where the ferroelectric capacitor is used as in Japanese Patent Laying-Open Nos. 2004-264896 and 2007-213747, the charge movement is utilized depending on a polarization state of the ferroelectric capacitor. Accordingly, in order to sense the moving amount of charges with the sense amplifier, it is necessary to move some charge amount. Therefore, in order to move the sufficient amount of charges, the capacitor needs to have a significant size, which becomes an obstacle against a high integration.
In Japanese Patent Laying-Open Nos. 07-249290 and 07-182874, because of the use of the SRAM cell, the number of transistor elements is increased and the cell size becomes larger than those of the MRAM cell and DRAM cell. Therefore, the large-capacity memory array is hardly realized in the small occupation area, and the configuration of Japanese Patent Laying-Open Nos. 07-249290 and 07-182874 is difficult to apply to the application in which a large amount of data are processed in a mobile equipment.
In the configuration disclosed in Japanese Patent Laying-Open No. 08-031168, the DRAM cell is used, and therefore, the cell size can be reduced. However, the data is destructively read in the DRAM cell. Particularly the storage data is completely destroyed in cases where plural memory cells are connected in parallel to one bit line as in Japanese Patent Laying-Open No. 08-031168. Accordingly, similarly to the configuration of Japanese Patent Laying-Open No. 2007-213747, the operation cannot be performed by repeatedly utilizing the data stored in the memory cell.
In the configuration disclosed in Japanese Patent Laying-Open No. 2000-284943, when the logic operational circuit is provided for each pair of bit lines, it is difficult to implement a large-capacity memory array in a small occupation area.
In the method for achieving the multifunctional memory cell as in the configuration disclosed in Japanese Patent Laying-Open No. 2007-226944, the occupation area of the memory array is significantly enlarged with the increase in storage capacity.
Where the ferroelectric capacitor and the DRAM cell are used, because a voltage sensing type sense amplifier is used as the sense amplifier that senses and amplifies the data, the sensing operation cannot be performed until a difference in voltage is sufficiently developed between the sense nodes of the sense amplifier. Accordingly, in the voltage sensing type sense amplifier, because the sensing operation is slower than that of a current sensing type sense amplifier, the operation result cannot be produced at high speed, and it is difficult to implement a high-speed operation processing.
The mobile equipment is required to operate under a low power supply voltage condition. Accordingly, where an operational processing is performed by moving the charges through the use of the capacitor, the sufficient amount of charges cannot be moved at a low power supply voltage, which results in a problem that the correct operational processing cannot be ensured.
Non-Patent Document 1 describes that a DFV (Dynamic Frequency and Voltage) control system is applied in system power supply management. However, in Non-Patent Document 1, there is no description on the configuration in which the operation is performed using a memory cell.
In Japanese Patent Laying-Open Nos. 2006-099232, 2004-264896, 2007-213747, 07-249290, and 08-031168 and Non-Patent Document 1, the operation is digitally performed. For example, when addition is digitally performed, the operation of the upper-order bit cannot be performed until a lower-order carry is ascertained. Therefore, the digital arithmetic operation cannot be performed at high speed. In Japanese Patent Laying-Open Nos. 2006-099232, 2004-264896, 2007-213747, 07-249290, and 08-031168 and Non-Patent Document 1, there is no description on a circuit-wise measure for performing the arithmetic operation such as addition and subtraction at high speed.
In Japanese Patent Laying-Open Nos. 2006-099232, 2004-264896, 2007-213747, 07-249290, and 08-031168 and Non-Patent Document 1, an address space of the storage device is uniquely determined, and there is no consideration on the configuration for expanding the address space.
Non-Patent Document 2 merely describes the configuration of the MRAM cell and the configuration of the data read, and fails to describe an internal operational processing of storage data.
An object of the present invention is to provide a semiconductor signal processing device having a small occupation area, in which the operational processing can be performed at high speed even in the low power supply voltage.
Another object of the invention is to provide a high-density semiconductor signal processing device having an operational function.
Briefly stating, in a semiconductor signal processing device according to the present invention, a nonvolatile memory cell having an amount of current that can be passed set according to storage data, is used to produce internal read data according to the current, and internally necessary processing is performed on the internal read data.
In accordance with a first aspect of the present invention, a semiconductor signal processing device includes a memory array having a plurality of memory cells arranged in rows and columns each being formed on an insulating layer and for storing information in a nonvolatile manner. The plurality of memory cells are disposed such that at least two memory cells constitute one unit operator cell. The unit operator cell includes at least first to fourth SOI transistors. The first SOI transistor has a first gate electrode and is selectively put into a conductive state according to a potential at the first gate electrode to transfer first write data of a first write port when made conductive. The second SOI transistor has a second gate electrode and is selectively put into the conductive state according to a potential at the second gate electrode, to transfer second write data of a second write port when in the conductive state. The third SOI transistor has a third gate electrode and a first body region receiving the first write data transferred through the first SOI transistor. The third SOI transistor is connected between a reference voltage supply and a first read port, and has an amount of current that it can pass set according to a potential at the third gate electrode and an amount of charge accumulated in the first body region. The fourth SOI transistor has a fourth gate electrode and a second body region receiving the second write data transferred through the second SOI transistor. The fourth SOI transistor is connected between the third SOI transistor and a second read port and has an amount of current that it can pass set according to a potential at the fourth gate electrode and an amount of charge accumulated in the second body region. Each of the first and second SOI transistors is a first conductivity type SOI transistor, and each of the third and fourth SOI transistors is a second conductivity type SOI transistor.
In accordance with the first aspect of the present invention, the semiconductor signal processing device further includes a plurality of dummy cells arranged corresponding to columns of the unit operator cells, each for supplying a reference current when data stored in a selected unit operator cell is read, and a plurality of read lines arranged corresponding to the columns of the unit operator cells and each connecting to the unit operator cells of a corresponding column. Each read line includes a first read bit line and a second read bit line. The first read bit line is connected to the first read port of each unit operator cell of the corresponding column, and the second read bit line is connected to the second read port of each unit operator cell of the corresponding column. The semiconductor signal processing device further includes a plurality of dummy read lines arranged corresponding to the columns of the unit operator cells and each connecting to the dummy cell of a corresponding column. The plurality of read lines and dummy read lines are divided into operation unit groups by each predetermined number.
In accordance with the first aspect of the present invention, the semiconductor signal processing device further includes a plurality of sense read bit lines arranged corresponding to the respective columns of the unit operator cells, a port selection/switch circuit for connecting one of the first and second read bit lines to a sense read bit line of a corresponding column according to an operation instruction, a plurality of amplifying circuits arranged corresponding to the respective columns of the unit operator cells, each for producing a signal corresponding to a difference between currents passing through the sense read bit line and the dummy read line of a corresponding column, and a plurality of unit operation processing circuits arranged corresponding to the operation unit groups, each for producing the first and second write data to the unit operator cells of a corresponding operation unit group according to received data in data writing, and for performing operation processing specified by the operation instruction on an output signal of a corresponding amplifying circuit in data reading.
In accordance with a second aspect of the present invention, a semiconductor signal processing device includes a memory array including a plurality of unit cells arranged in rows and columns, each for storing information in a nonvolatile manner, and a plurality of read lines arranged corresponding to the columns of the unit cells and each connecting to the unit cells of a corresponding column. A current passes through the read line according to data stored in the unit cell of a corresponding column in data reading. The memory array is divided into a plurality of entries along a row direction. The semiconductor signal processing device further includes a read operation processing circuit for reading data stored in the unit cells of the addressed entry according to an operation instruction and an address specifying the entry in the memory array, to perform an operation specified by the operation instruction on the read out data in units of unit cell columns, and to supply the operational result as storage information to an entry that is different from the addressed entry. The read operation processing circuit includes a plurality of sense read amplifying circuits arranged corresponding to the columns of the unit cells and each producing internal read data according to a current passing through the read line of a corresponding column when made active.
In accordance with a third aspect of the present invention, a semiconductor signal processing device includes a plurality of unit operator cells arranged in rows and columns and each for storing data in a nonvolatile manner. Each unit operator cell can pass a current of a differ amount according to the storage data. The plurality of unit operator cells are divided into operation unit blocks in a row direction.
In accordance with the third aspect of the present invention, the semiconductor signal processing device further includes a write circuit for expanding each bit of multi-bit numerical data to a number of bits corresponding to a bit position of each bit in the numerical data to produce internal write data for the operation unit block, for concurrently selecting the unit operator cells in the operation unit block, and for concurrently writing bits of the internal write data corresponding to the multi-bit numerical data in corresponding unit operator cells, a plurality of global read data lines arranged corresponding to the columns of the plurality of unit operator cells, a read circuit for concurrently selecting the unit operator cells of a plurality of rows among the plurality of unit operator cells in data reading, to pass a current corresponding to data stored in each selected selection unit operator cell through the corresponding global read data line, and a conversion circuit for adding currents passing through the global read data lines in an analog manner in each operation unit block, and to convert the addition result into a digital signal.
In the semiconductor signal processing device according to the first aspect of the present invention, the unit operator cell is formed by the SOI element, so that the number of components of each cell can be decreased to reduce the layout area of the memory cell compared with an SRAM. The amplifying circuit performs the current sensing operation, so that the amplifying behavior can be performed at high speed to produce the operational result data.
The amplifying circuit can amplify the operational result of the data stored in the unit operator cells by selectively utilizing the first and second read ports. Therefore, not only the data can be stored, but also the AND, OR, and NOT logic operation functions can be implemented. Accordingly, the fine granularity operation can be achieved without separately disposing a computing unit.
In the semiconductor signal processing device according to the second aspect of the present invention, the read operation processing circuit reads the internal data in each column, and the read operation processing circuit has the operational function of performing an operation on the read out data. The selected entry can be converted into another entry by performing the operation to the data stored in the unit operator cells in units of entry columns, and the virtual entry space larger than the real entry space can be produced. Therefore, high-density and large-capacity LUT calculating unit can be implemented.
In the semiconductor signal processing device according to the third aspect of the present invention, the addition and subtraction are performed on the current that is weighted according to the bit position of the bits in the multi-bit numerical data. Accordingly, the addition and subtraction can be performed without waiting for the settlement of the carry/borrow, and the addition and subtraction processing can be achieved at speed. Similarly to the addition and subtraction, the partial product addition can be performed to implement the high-speed multiplication processing.
The current addition is internally performed without transferring the added current to the outside of the device, so that the current addition result can be produced at high speed with the small current even in the low power supply voltage.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
[First Embodiment]
SOI transistor NQ1 is connected between a source line SL and a read port RPRTA, and a gate of SOI transistor NQ1 is connected to a read word line RWLA. SOI transistor NQ2 is connected between SOI transistor NQ1 and a read port RPRTB, and a gate of SOI transistor NQ2 is connected to a read word line RWLB.
Potentials at the body regions of SOI transistors NQ1 and NQ are set according to write data DINA and DINB from write ports WPRTA and WPRTB. In the SOI transistor, a threshold voltage depends on the potential at the body region. Specifically, in SOI transistors NQ1 and NQ2 each, when the body region has a high potential, back gate-source in each of SOI transistors NQ1 and NQ2 is biased in a positive direction at a voltage level that is not higher than a built-in voltage of a PN junction, and the threshold voltages of SOT transistors NQ1 and NQ2 are lowered. When the body region has a low potential, the threshold voltages of SOT transistors NQ1 and NQ are raised. Accordingly, SOT transistors NQ1 and NQ2 can store information according to the potentials at the respective body regions. The body regions of SOT transistors NQ1 and NQ2 are isolated from other regions, so that data can be stored during power-off.
Voltage levels at body regions or storage nodes SNA and SNB can be set, by adjusting a power supply voltage of a write driver or the like, precisely to a level not higher than the built-in voltage of the PN junction, and the threshold voltage of the SOT transistor can reliably be set according to the storage data.
Similarly, high-concentration P-type regions 1c and 1d are arranged in alignment along the Y-direction. An N-type region 2b is arranged between P-type regions 1c and 1d. A P-type region 4a is arranged in alignment in the Y-direction with P-type region ld.
In the outside of the P-type transistor forming region, high-concentration N-type regions 3a, 3b, and 3c are disposed adjacent to P-type regions 1d and 4a and in alignment with each other in the Y-direction.
P-type region 4a is disposed, between N-type regions 3a and 3b, extending from the P-type transistor forming region, and P-type region 4b is disposed, between N-type regions 3b and 3c, extending from the P-type transistor forming region.
A gate electrode interconnection line 5a is disposed, above N-type regions 2a and 2b, extending in an X-direction, and a gate electrode interconnection line 5b is disposed above P-type region 4a. A gate electrode interconnection line 5c is disposed, above P-type region 4b, extending in the X-direction. In
A first metal interconnection line 6a is disposed in alignment with gate electrode interconnection line 5a, and first metal interconnection line 6a is formed continuously extending in the X-direction. A first metal interconnection line 6d is disposed in alignment with gate electrode interconnection line 5c, and first metal interconnection line 6d is arranged continuously extending in the X-direction. First metal interconnection lines 6b and 6c are disposed, between first metal interconnection lines 6a and 6d, being isolated from each other, and first metal interconnection lines 6b and 6c are formed continuously extending in the X-direction. First metal interconnection line 6a is electrically connected to gate electrode interconnection line 5a in a region (not shown) to constitute a write word line WWL. First metal interconnection line 6b is electrically connected to high-concentration N-type region 3a of a lower layer through a via/contact 8c, and first metal interconnection line 6b constitutes a source line SL. First metal interconnection line 6c disposed adjacent to gate electrode interconnection line 5b is electrically connected to gate electrode interconnection line 4a in a region (not shown) to constitute a read word line RWLA. First metal interconnection line 6d is electrically connected to gate electrode interconnection line 5c in a region (not shown) to constitute read word line RWLB.
In a boundary region between active regions (region where the transistor is formed), second metal interconnection lines 7a to 7d are disposed continuously extending along the Y-direction. Second metal interconnection line 7a is electrically connected to N-type region 3c through a via/contact 8e and an intermediate first interconnection line. Second metal interconnection line 7b is electrically connected to N-type region 3b through a via/contact 8d and an intermediate first interconnection line. Second metal interconnection line 7c is electrically connected to P-type region 1c through a via/contact 8b and an intermediate first interconnection line. Second metal interconnection line 7d is electrically connected to P-type region 1a through a via/contact 8a and an intermediate first interconnection line.
Second metal interconnection lines 7a and 7b transmit output data DOUTB and DOUTA through read ports, respectively. Second metal interconnection lines 7c and 7d transmit input data DINA and DINB through write ports, respectively. That is, second metal interconnection lines 7c and 7d are connected to write ports WPRTA and WPRTB of
In the planar layout of
As shown in
In SOI transistor PQ1, a channel is formed at a surface of body region (N-type region) 2b, charges transmitted from write port WPRTA are transmitted through P-type region 1d to and accumulated in P-type region 4a. The voltage at the body region of SOI transistor NQ1 is set at a voltage level according to write data, and the threshold voltage is set at a level corresponding to storage data. N-type region 3b constitutes a pre-charge node, and is maintained at a voltage level not causing the PN junction between the regions 4a and 3b to be conductive, irrespective of the voltage level of P-type region 4a. Usually, source line SL is maintained at a power supply voltage VCC level to prevent the PN junction between the body region and the source line from being conductive.
During data read, a high-level voltage is applied to the gate electrode interconnection line formed above the body region of SOI transistor NQ1. The channel is selectively formed at the surface of P-type region 4a according to the storage data by the voltage applied to the gate electrode, and a current flows from source line SL to read port RPRTA according to the storage data. The data is read by sensing the current. The charges accumulated in body region (P-type region) 4a are retained, so that the data can be stored in a nonvolatile manner.
The data read can be performed at high speed since a current amount from source line SL according to the threshold voltages of SOI transistors NQ1 and NQ2 is merely sensed.
In operator cell sub-array blocks OAR0 to OAR31, unit operator cells (UOE) are arranged in rows and columns, and a dummy cell is disposed corresponding to each unit operator cell column. A current supplied from the dummy cell is used as a reference current to read the storage data of a unit operator cell.
A row selection driving circuit 22 is provided for operator cell array 20. Row selection driving circuit 22 includes row drive circuits XDR0 to XDR31 provided corresponding to operator cell sub-array blocks OAR0 to OAR31, respectively. Each of row drive circuits XDR0 to XDR31 selects a unit operator cell row in a corresponding operator cell sub-array block. Each of row drive circuits XDR0 to XDR31 includes a row address decode circuit that decodes a row address signal, a read word line drive circuit that drives a read word line in a selected state in the data read, and a write word line drive circuit that drives a write word line in a selected state in the data write.
Processing of concurrently driving both read word lines RWLA and RWLB of
A main amplifier circuit 24, a combination logic operational circuit 26, and a data path 28 are provided in a data input and output path of operator cell array 20. Main amplifier circuit 24 includes a main amplifier that is provided corresponding to a unit operator cell column of each operator cell sub-array blocks OAR0 to OAR31. In main amplifier circuit 24, main amplifiers concurrently amplify data read from the operator cell sub-array block selected in operator cell array 20. Therefore, data of an entry (formed by unit operator cells on one row) of the operator cell sub-array block selected in operator cell array 20 are concurrently amplified for each selected unit operator cell.
Combination logic operational circuit 26 further performs designated logic or arithmetic operation processing on the data of the selected unit operator cell transferred from main amplifier circuit 24. The combination logic operations such as an OR operation, an XOR operation, and an XNOR operation are prepared as the logic operation, and addition and subtraction are prepared as the arithmetic operation processing. Further, combination logic operational circuit 26 can receive the storage data of the selected unit operator cell through the main amplifier to externally supply the received output signal from the main amplifier through a register without changing logic thereof.
Data path 28 sets a path of the transfer data from main amplifier circuit 14 and/or combination logic operational circuit 26. Data path 28 sets a path for supplying data DOUT[m:0] to the outside, and sets a path for producing the write data from input data DINA<m:0> and DINB<m:0> to the unit operator cells, and sets a write data transfer path.
Input data DINA<m:0> and DINB<m:0> are transferred from the outside of the device and are written in the body regions of SOI transistors NQ1 and NQ2 of each unit operator cell after the path is set in the data path. The transfer path setting for the write data and data inversion/non-inversion are selectively performed in data path 28. Therefore, operational processing contents on the external input data, which utilizes the unit operator cells of a selected operator cell sub-array block, is set.
In the semiconductor signal processing device, a control circuit 30 performs setting of internal operation processing, and setting and operation timing control of a data transfer path. Control circuit 30 includes an instruction memory storing program instructions, and produces internal operation designation and internal timing according to the program in the instruction memory. Alternatively, control circuit 30 may performs the setting of the internal data transfer path and generation of internal operation timings in response to an external command.
Referring to
A bit line pair BLP is disposed corresponding to a unit operator cell row. As described above, unit operator cell UOE includes read ports RPRTA and RPRTB, and each bit line pair BLP includes read bit lines BLA and BLB (BLA/B) and a complementary read bit line ZBL. Read bit lines BLA and BLB (BLA/B) are connected to read ports RPRTA and RPRTB of the unit operator cell of corresponding row, respectively. Dummy cell DMC is connected to complementary read bit line ZBL. Read port selection circuit 36 selects one of read bit lines BLA and BLB.
Each sense amplifier SA of sense amplifier band 38 senses an amount of current flowing through bit line BLAB and complementary bit line ZBL selected by read port selection circuit 36, and produces a signal according to the sensing result.
Each sense amplifier SA of sense amplifier band 38 is connected to a global read data line pair RGLP. Global read data line pair RGLP is commonly disposed for plural operator cell sub-array blocks, and is disposed corresponding to the sense amplifier of each operator cell sub-array block. An output of sense amplifier SA of the selected operator cell sub-array block is transmitted to a main amplifier MA of main amplifier circuit 24 through global read data line pair RGLP.
A global write data line pair WGLP is commonly disposed for operator cell sub-array blocks OAR (OAR0 to OAR31). Global write data line pair WGLP includes global write data lines WGLA and WGLB, and write data lines WGLA and WGLB are connected to write ports WPRTA and WPRTB of the unit operator cell of a selected operator cell sub-array block. Accordingly, the global write data line pair is disposed corresponding to a unit operator cell column of each operator cell sub-array block.
In main amplifier circuit 24, main amplifier MA is provided for each of global read data line pair RGLP.
A dummy cell DMC0 is disposed for unit operator cell UOE0. Dummy cell DMC0 includes a dummy transistor DTA and dummy transistors DTB0 and DTB1. Dummy transistor DTA is connected between a complementary read bit line ZRBL0 and a reference voltage source supplying a reference voltage Vref. Dummy transistors DTB0 and DTB1 are connected in series between complementary read bit line ZRBL0 and the reference voltage source. Dummy transistor DTA is made conductive in response to a dummy cell selection signal DCLA, to supply a current to complementary read bit line ZRBL0 from reference voltage source Vref. Dummy transistors DTB0 and DTB1 are made conductive in response to a dummy cell selection signal DCLB, to supply a current to complementary read bit line ZRBL0 from reference voltage source Vref. Each of dummy transistors DTA, DTB0, and DTB1 is formed by an N-channel SOI transistor having a low threshold voltage.
In dummy cells DMC0 and DMC1, dummy transistor DTA is made conductive in selecting port A, and dummy transistors DTB0 and DTB1 are used when port B is selected. The is because, in unit operator cell UOE, each of dummy transistor DTA and dummy transistors DTB0 and DTB1 produces a reference current depending on whether one N-channel SOI transistor or two series-connected SOI transistors are used.
Reference voltage Vref (power supply and supply voltage are designated by the same reference symbol) supplied from reference voltage source Vref supplies a current at a magnitude intermediate between currents supplied in a state of a high-threshold voltage and in a state of a low-threshold voltage of SOI transistors NQ1 and NQ2 included in unit operator cell UOE0. A port connection circuit PRSW0 is provided for read bit lines RBLA0 and RBLB0. Port connection circuit PRSW0 connects one of read bit lines RBLA0 and RBLB0 to a sense read bit line RBL0 in response to a port selection signal PRMX. Complementary read bit line ZRBL0 is connected to sense amplifier SA.
A sense amplifier SA0, a bit line pre-charge/equalize circuit BLEQ0, and a read gate CSG0 are provided between sense read bit lines RBL0 and ZRBL0. Sense amplifier SA0 includes a cross-coupled N-channel SOI transistors, a cross-coupled P-channel SOI transistors, a sense activation P-channel SOI transistor, and a sense activation N-channel SOI transistor. The sense activation P-channel SOI transistor and the sense activation N-channel SOI transistor are selectively turned conductive in response to sense amplifier activation signals /SOP and SON, to supply a sense power supply voltage VBL and a ground voltage to sense power supply nodes (power supply node to which the cross-coupled SOI transistors are connected), respectively. Sense power supply voltage VBL may have a level of power supply voltage VCC or a level of an intermediate voltage. It is only necessary that sense power supply voltage VBL have a voltage level on a selected read word line at lowest.
Sense amplifier SA0 is a cross-coupled sense amplifier that amplifies a potential difference between read bit lines RBL0 and ZRBL0 differentially. Alternatively, as shown in Non-Patent Document 1, sense amplifier SA0 may be formed by the SOI transistors having the gate and the body region connected together. A current sensing type sense amplifier may be used for sense amplifier SA. The current sensing type sense amplifier may be used that performs a current-mirror operation for producing a mirror current of currents flowing through sense read bit lines RBL and ZRBL.
Bit line pre-charge/equalize circuit BLEQ0 supplies a bit line pre-charge voltage VPC to read bit lines ZRBL0 and RBL0 in response to a bit line pre-charge instruction signal BLPE. Bit line pre-charge voltage VPC has a voltage level at which the PN junction between the read port and the body region of N-channel SOI transistors NQ1 and NQ2 in unit operator cell UOE is maintained in a non-conductive state irrespective of a voltage level of the body region.
Read gate CSG0 connects sense read bit lines RBL0 and ZRBL0 to global read data lines RGL0 and ZRGL0 in response to a read gate selection signal (operator cell sub-array block selection signal) CSL.
The transistors constituting sense amplifier SA0, bit line pre-charge/equalize circuits BLEQ0, and read gate CSG0 that are included in sense amplifier band 38 may be formed by not the SOI transistors but usual bulk MOS transistors formed at a surface of a semiconductor substrate region.
Dummy cell DMC1 and a port connection circuit PRSW1 are also provided for unit operator cell UOE1. A sense amplifier SA1, a bit line pre-charge/equalize circuit BLEQ1, and a read gate CSG1 are provided for unit operator cell UOE1. Sense amplifiers SA0 and SA1 are commonly selectively activated in response to sense amplifier activation signals /SOP and SON, and bit line pre-charge/equalize circuits BLEQ0 and BLEQ1 are activated when the bit line pre-charge instruction signal BLPE is activated. Similarly to read gate CSG0, read gate CSG1 is also brought into conductive state in response to read gate selection signal CSL.
As shown in
Port selection signal PRMX is a multi-bit signal, and the connection of the bit lines can be set for each bit line pair. As described later, an operation is performed by a four-bit line pair. Usually, because the same operation is performed in each operation unit, it is only necessary to prepare a four-bit control signal at the minimum (one-bit selection control signal is prepared per one-bit line pair) for port selection signal PRMX.
Data path unit block DPUB0 also includes a multiplexer (MUXA) 56, a multiplexer (MUXB) 57, and global write drivers 58 and 59. Multiplexer (MUXA) 56 selects one of the storage data of register 50, the output values of inverters 52 and 53, and external one-bit write data DINA0 in response to a switching control signal MXAS. Multiplexer (MUXB) 57 selects one of the storage data of register 50, the output values of inverters 52 and 53, and external one-bit write data DINB0 in response to a switching control signal MXBS. Global write drivers 58 and 59 drive write data lines WGLA and WGLB of global write data line pair GLP0 according to the data selected by multiplexers 56 and 57.
Data path unit block DPUB0 selects one of an inverted value of the external write data bit, a non-inverted value of the external write data bit, and a corresponding output bit Q0 from a combination logic operational circuit to transmit the selected bit to write data line WGLA. Data path unit block DPUB0 selects one of the data bit from register 50, the inverted value of external write data bit DLB0, the non-inverted value of write data bit DLB0 to transmit the selected bit to global write data line WGLB.
Data path unit blocks DPUB1 to DPUB3 have the configuration similar to that of data path unit block DPUB0. However, in data path unit blocks DPUB1 to DPUB3, buffer 51 is not provided at an output of register 50. That is, data bits Q1 to Q3 from the corresponding combination logic operational circuits are not supplied as the data to the outside. Register 50 may be removed in data path unit blocks DPUB1 to DPUB3. The storage value of register 50 of data path unit block DPUB0 is transferred to data path unit blocks DPUB1 to DPUB3.
External one-bit write data DINA0 and DINB0 are commonly supplied to data path unit blocks DPUB0 to DPUB3. The storage value of register 50 is commonly supplied to data path unit blocks DPUB1 to DPUB3.
Switching control signals MXAS and MXBS are applied for each data path unit block, and selection manner of multiplexers 56 and 57 are individually set in each data path unit block. In cases where a common operation is performed in each data path operation unit group 44, it is necessary to prepare four kinds of switching control signals for switching control signals MXAS and MXBS (one kind is allocated to one data path unit block).
External data bits DINA<0> and DINB<0> are supplied to data path operation unit group 44<0> to produce one-bit output data DOUT<0>. In
Multiplexer MUXA/B<3:0> (multiplexers 56 and 57) determines a data propagation/conversion path of each of data path unit blocks DPUB0 to DPUB3 in data path operation unit group 44<0>, and internal data bits DP<0> to DP<3> are transmitted to corresponding global write data line through global write drivers 58 and 59.
Similarly, external write data bits DINA<1>, DINB<1>, . . . , and DINA<m> and DIMB<m> are applied to data path operation unit groups 44<1>, . . . , and 44<m>, and write data DP<4> to DP<7>, DP<4m> to DP<4m+3> are produced by each of the internal multiplexer (MUXA and MLTXB) and transmitted to the corresponding global write data line pairs through the corresponding global write drivers (58 and 59).
In data path 28, the data bit from combination logic operational circuit 26 is transmitted to data path unit blocks DPUB0 to DPUB3 of each data path operation unit group. However, in each of data path operation unit groups 44<0> to 44<m>, one data path unit block DPUB4i (i=0 to m) supplies output data bits DOUT<0> to DOUT<m> as data bits DOUT<0> to DOUT<m> externally.
Accordingly, in each data path operation unit group, the four-bit data is produced according to the external write data bit, and the operational processing is performed based on storage data of the for unit operator cells per one operation unit group at the maximum, thereby implementing various combination logic operations and arithmetic operations.
In
Unit operation block UCL4k also includes a two-input OR gate OG0, a three-input OR gate OG1, and a four-input OR gate OG2. Two-input OR gate OG0 receives output signals P<4k> and P<4k+1> of the main amplifiers. Three-input OR gate OG1 receives output signals P<4k>, P<4k+1>, and P<4k+2> of the main amplifiers. Four-input OR gate OG2 receives output signals P<4k> to P<4k+3> of the main amplifiers.
Unit operation block UCL4k further includes a five-input multiplexer 60a, two-input multiplexers 62a to 62d, and a demultiplexer 63. Multiplexer 60a receives output signals of buffer BFF0, inverter IV0, and OR gates OG0 to OG2, and selects one of the output signals in response to a logic path instruction signal LGPS.
Multiplexer 62a selects one of output signals of buffer BFF1 and inverter IV1 to produce a bit Q<4k>. Multiplexer 62b selects one of output signals of buffer BFF2 and inverter IV2 to produce a bit Q<4k+1>. Multiplexer 62c selects one of output signals of buffer BFF3 and inverter IV3 to produce a bit Q<4k+3>. The selection manner of multiplexers 62a to 62c are also set in response to logical path instruction signal LGPS.
Demultiplexer 63 transmits the output signal (data) of multiplexer 60a to one of a four-bit addition/subtraction processing circuit 64 and multiplexer 62d in response, to logical path instruction signal LGPS. Multiplexer 62d selects one of output bits supplied from demultiplexer 63 and four-bit addition/subtraction processing circuit 64, and supplies the selected one bit as output bit Q<4k>.
Four-bit addition/subtraction processing circuit 64 performs addition or subtraction on output bits G<4k> to G<4(k+7)> applied from demultiplexer 63 of the eight unit operation blocks, to produce an five-bit output including carry/borrow in four-bit addition/subtraction. In the configuration of
In the following description, for SOI transistors NQ1 and NQ2, a high-threshold voltage state corresponds to a state in which data “0” is stored, and a low-threshold voltage corresponds to a state in which data “1” is stored.
In a pre-charge period, read bit line RBL and complementary read bit line ZRBL are pre-charged to a level of a pre-charge voltage VPC by bit line pre-charge/equalize circuit BLEQ of
When a read cycle is started, read word lines RWLA and RWLB and dummy cell selection signal DCLB are driven to the selected state. A voltage at source line SL has a level of power supply voltage VCC, and is higher than reference voltage Vref supplied to dummy cell DMC. In cases where the data “0” is stored in one of SOI transistors NQ1 and NQ2, the threshold voltage is high and the current amount is small. On the other hand, where the data “1” are stored in both SOI transistors NQ1 and NQ2, the threshold voltage is low and the large amount of current flows.
Accordingly, in cases where the data “1” is stored in both SOI transistors NQ1 and NQ2, the large amount of current is passed from source line SL to sense read bit line RBL through read port RPRTB. In dummy cell DMC, the current is passed from reference voltage source Vref to complementary sense read bit line ZRBL through dummy transistors DTB0 and DTB1. Reference voltage Vref (voltage source and voltage at the voltage source are designated by the same reference symbol) has a voltage level between bit line pre-charge voltage VPC and the voltage (level of power supply voltage VCC) supplied to source line SL. In this case, the amount of current supplied from unit operator cell UOE is larger than the amount of current supplied from dummy cell DMC, and a potential at sense read bit line RBL is higher than a potential at complementary sense read bit line ZRBL.
On the other hand, where the data “0” is stored in at least one of SOI transistors NQ1 and NQ2, the amount of current supplied to complementary sense read bit line ZRBL from dummy cell DMC becomes larger than the amount of current supplied from unit operator cell UOE. The potential at sense read bit line RBL becomes lower than the potential at complementary sense read bit line ZRBL due to the difference in current amount.
At this point, sense amplifier SA is activated by changing sense amplifier active signals /SOP and SON between the L level and the H level. Sense amplifier SA amplifies the data (potential or current amount) read on sense read bit lines RBL and ZRBL differentially.
A high-level output voltage of sense amplifier SA is a voltage level of a sense high-side power supply voltage VBC, and is double the pre-charge voltage VPC in the waveform diagram of
Therefore, even if the voltage level of high-side power supply voltage VBC of sense amplifier SA is transmitted to one of sense read bit lines RBL and ZRBL, the forward bias of the PN junction of each of the body regions of SOI transistors NQ1 and NQ2 and dummy transistor DTB is prevented to prevent the charges from flowing into the body region, and the sensing operation can correctly be performed without causing the destruction of the storage data.
Then read gate CSG of
The data read is nondestructive read, a restoring period in which the storage data is re-written is not required. Accordingly, read word lines RWLA and RWLB may be driven to the non-selected state before the sense amplifier operation. The elimination of the restoring period can shorten the read cycle.
As shown in
Thus, the logic operation on the storage data is performed to obtain the operational result without reading the data externally, only by internally reading the storage data of the unit operator cell.
Referring to
In the arrangement of
Accordingly, in this case, output signal SOUT of sense amplifier SA becomes an H level (“1”).
Accordingly, as shown in
Data A0 and B0 taken in at the rising edge of clock signal CLK are taken into data path 28 of
The internal write data is transmitted from data path 28 to the global write data lines through global write drivers 58 and 59 of
When the data writing into SOI transistors NQ1 and NQ2 is completed, read word lines RWLA and RWLB or read word line RWLA is driven to the selected state. Referring to
In performing the AND operation, read word lines RWLA and RWLB are concurrently driven to the selected state. In performing the NOT operation, read word line RWLA is driven to the selected state and read word line RWLB is maintained in the non-selected state. Before the read word line is driven to the selected state, port selection signal PRMX is set, a port connection switch PRSW (PRSW0 and PRSW1) of read port selection circuit 36 of
Dummy cell selection signal DCLA/DCLB is also driven to the selected state when read word line RWLA/RWLB is driven to the selected state. Therefore, the current corresponding to the storage data of the unit operator cell and the reference current of the selected dummy cell are passed through read bit lines RBL and ZRBL connected to the sense amplifier, and the potentials at read bit lines RBL and ZRBL are changed. After read word lines RWLA and RWLB are driven to the selected state, sense amplifier activation signals /SOP and SON are activated at a predetermined timing. The voltage levels of read bit lines RBL and ZRBL are changed by the sensing operation of the sense amplifier. The data sensed and amplified by sense amplifier SA is transmitted to corresponding main amplifier MA.
When sense result of sense amplifier SA (see
In the next cycle, data A1 and B1 are taken in as input data DINA and DINB along with the operation command again, and the operational processing is performed in response to the operation command. Accordingly, when input data DINA and DINB is imparted, data DQ1, DQ2, . . . indicating the operational result in one clock cycle are produced as output data DOUT by successively performing the data writing and reading, and the operational processing can be performed in one clock cycle.
Accordingly, the operational processing time can be shortened compared with the configuration in which the data is read externally to perform the operational processing by using a separately and externally provided logic gate.
As shown in
Command decoder 70 takes in command CMD for specifying operation contents externally applied at the rising edge of clock signal CLK (not shown), and produces operation processing instruction OPLOG for specifying operational processing contents.
Connection control circuit 72 produces switching control signals MXAS and MXBS for the data path and logical path instruction signal LGPS for the combination logic operational circuit according to operational processing instruction OPLOG. The data transfer path of the data path is set by switching control signals MXAS and MXBS, and operational contents in the combination logic operational circuit are set according to logical path instruction signal LGPS.
When operational processing instruction OPLOG is applied, write control circuit 74 activates write activation signal WREN and write word line enable signal WWLEN. The circuits related to the data write, such as the global write driver and the write word line decode circuit, which are included in the data path, are activated in response to write activation signal WREN. Write word line enable signal WWLEN provides the timing at which the write word line is driven to the selected state.
Read word control circuit 76 produces a read activation signal RREN, read word line enable signals RWLENA and RWLENB, and main port selection signal PRMXM according to operational processing instruction OPLOG. The operation of the portion related to the data read is performed in a selected operator cell sub-array block in response to those signals. Operation starting timing of read word control circuit 76 is set after write activation signal WREN is activated in write control circuit 74. The circuits such as a read word line decode circuit are activated according to the activation of read activation signal RREN.
Data read control circuit 78 activates a sense amplifier activation signal SAEN (/SOP and SON), main amplifier activation signal MAEN, and a read gate selection timing signal CLEN according to read activation signal RREN from read word control circuit 76 and operational processing instruction OPLOG. Read gate selection timing signal CLEN provides read gate path connection timing at which the sense amplifier and the corresponding global read data lines are connected.
The signals that are produced by write control circuit 74, write word control circuit 76 and data write control circuit 78 are applied to row selection driving circuit (22) that is provided for each operator cell sub-array block. The activation of the read word line and write word line and dummy cell selection, the connection of the bit line and the sense amplifier, the transfer of the output signal of the sense amplifier to the main amplifier are performed in each addressed operator cell sub-array block.
Row drive circuit XDRi includes a read word line drive circuit 80 that drives a read word line, a dummy cell selection circuit 82 that selects the dummy cell, and a write word line drive circuit 84 that selects a write word line.
Read word line drive circuit 80 is enabled by read activation signal RREN, and drives read word lines RWLA and RWLB arranged for an addressed unit operator cell row to the selected state according to read word line enable signals RWLENA and RWLENB from read word control circuit 76, an address signal AD, and a block address BAD for specifying an operator cell sub-array block. In read word line drive circuit 80, the selection mode of read word lines RWLA and RWLB is set by read word line enable signals RWLENA and RWLENB, thereby performing the setting in which data is read through which one of read ports RPRTA and RPRTB.
Dummy cell selection circuit 82 is enabled by read activation signal RREN, and drives dummy cell selection signals DCLA and DCLB to the selected state according to block address signal BAD for specifying an operator cell sub-array block and read word line enable signals RWLENA and RWLENB. The selection mode of dummy cell selection signals DCLA and DCLB is set according to the selection mode of read word line enable signals RWLENA and RWLENB. When both read word line enable signals RWLENA and RWLENB are activated, dummy cell selection signal DCLB is driven to the selected state. When read word line enable signal RWLEN is in the active state while read word line enable signal RWLENB is in the inactive state, dummy cell selection signal DCLA is driven to the selected state.
Write word line drive circuit 84 is enabled by write activation signal WREN and block address signal BAD, and drives the write word line arranged for the unit operator cell row specified by address signal AD to the selected state in response to write word line enable signal WWLEN.
Block selection circuit 90 includes a read gate selection circuit 92 that selects the read gate and a port connection control circuit 94 that controls a read bit line connection path. Read gate selection circuit 92 drives read gate selection signal CSL to the selected state in response to read gate selection timing signal CLEN when block address signal BAD specifies the corresponding operator cell sub-array block in activation of read activation signal RREN. Here, for the selection mode of the read gate (CSG), it is assumed that all the columns are concurrently selected in a selected operator sub-array block. Where the sense amplifier group including a predetermined number of sense amplifiers is selected in the sub-array block, the read column selection signal is produced in response to the address signal, and is combined with read gate selection signal CSL.
Port connection control circuit 94 selectively inactivates port selection signals /PRMXA and /PRMXB in response to main port selection signal PRMXM when block address signal BAD specifies a corresponding operator cell sub-array block in the activation of read activation signal RREN. Port selection signals /PRMXA and /PRMXB correspond to port selection signal PRMX. Main port selection signal PRMXM includes port specifying information, and port connection control circuit 94 connects read bit line (RBLA/RBLB) corresponding to the port specified by main port selection signal PRMXM to sense read bit line RBL. In a standby state, port connection control circuit 94 maintains port selection signals /PRMXA and /PRMXB in the active state to connect sense read bit line RBL to read bit lines RBLA and RBLB, which in turn are pre-charged and equalized to a predetermined potential (VPC) level by the bit line pre-charge/equalize circuit of
Transistors NT1 and NT2 are made non-conductive when port selection signals /PRMXB and /PRMXA are activated at the L level. That is, port selection signals /PRMXA and /PRMXB are set at the L level of the active state when read ports RPRTA and RPRTB are specified, respectively. Accordingly, when read port RPRTA is specified, port selection signal /PRMXA becomes the L level, transistor NT2 is put into the non-conductive state, and transistor NT1 is put into the conductive state. When read port RPRTB is specified, port selection signal /PRMXA becomes the inactive state of the H level, and port selection signal /PRMXB becomes the L level of the active state. Accordingly, transistor NT2 connects B-port read bit line RBLB to sense read bit line RBL.
A transmission gate may be used instead of transistors NT1 and NT2.
A specific operation processing mode of the semiconductor signal processing device of the first embodiment of the present invention will be described below.
(NOT Operation)
Dummy cell selection signal DCLA is applied to (activate) dummy cell DMC to bring dummy transistor DTA into the conductive state. In read port selection circuit 36, port connection circuit (PRSW) is set in the state in which read port RPRTA (hereinafter arbitrarily referred to as port A or A port) is selected, and read bit line RBLA is connected to sense amplifier SA.
Accordingly, the output data of sense amplifier SA is inverted data /A of data A stored in unit operator cell UOE, and inverted data /A is transmitted from corresponding main amplifier MA in main amplifier circuit 24.
In combination logic operational circuit 26, because buffer BUFF0 is selected, data DOUT supplied externally through register 50 is inverted data /A. Therefore, the NOT operation can be performed.
Alternatively, input data A may be selected, and written into and read from unit operator cell UOE in data path 28, and inverter (INV0) may be selected to produce external data DOUT through register 50 in combination logic operational circuit 26. In this case, non-inverted data A is supplied from sense amplifier SA and is then inverted, and similarly, the NOT operational result is obtained for the input data.
(AND Operation)
In read port selection circuit 36, read port RPRTB (hereinafter arbitrarily referred to as port B or B port) is selected and read bit line RBLB is connected to sense amplifier SA. In dummy cell DMC, dummy transistor DTB0/1 (DTB0 and DTB1) are selected in response to dummy cell selection signal DCLB. Accordingly, as shown in
In combination logic operational circuit 26, buffer BFF0 is selected in response to the logical path instruction signal. Accordingly, output data DOUT transmitted from buffer BFF0 through register 50 is data A·B. Therefore, the logical product operational result (AND operation result) can be obtained for input data A and B.
(OR Operation)
In read port selection circuit 36, port B (read port RPRTB) is selected and read bit line RBLB is connected to sense amplifier SA. Dummy cell selection signal DCLB is applied to dummy cell DMC to select dummy transistors DTB0 and DTB1. Accordingly, because sense amplifier SA performs the AND operation, the output data of corresponding main amplifier MA in main amplifier circuit 24 becomes data /A·/B.
In combination logic operational circuit 26, inverter IV0 is selected to invert the output data of main amplifier MA. Accordingly, data DOUT supplied through register 50 becomes data /(/A·/B) that is equivalent to data (A+B), thereby obtaining the OR (logical addition) operational result of input data A and B.
(XOR Operation)
In data path unit block DPUB1, multiplexer 56 selects the inverted value of the input data A, and multiplexer 57 selects input data B. The inverted value of the input data A is supplied from inverter 52. Accordingly, data /A and B are transmitted onto corresponding global write data lines WGLA1 and WGLB1, respectively and stored in corresponding a unit operator cell UOE1.
In operator cell sub-array block OARi, dummy cell selection signal DCLB is applied to dummy cell DMC for selecting two series-connected dummy transistors DTB0 and DTB1. In read port selection circuit 36, port B (read port RPRTB) is selected, and therefore read bit lines RBLB0 and RBLB1 are connected to corresponding sense amplifiers SA0 and SA1. In the connection manner of the dummy cell and unit operator cell, sense amplifiers SA0 and SA1 each supply the AND operational results. Accordingly, main amplifier MAO of main amplifier circuit 24 supplies data A·/B, and main amplifier MA1 produces data /A·B.
In combination logic operational circuit 26, two-input OR gate OG0 is selected to perform the logical addition of the output signals of main amplifiers MA0 and MA1. Accordingly, register 50 supplies output data DOUT of (/A·B+A·/B), and the XOR operational result of input data A and B can be obtained as the output data DOUT.
(XNOR Operation)
In data path unit block DPUB1, multiplexers 56 and 57 select input data A and B. Accordingly, data A and B are transmitted onto corresponding global write data lines WGLA1 and WGLB1 and stored in corresponding unit operator cell UOE1. In memory cell array 34, dummy cell selection signal DCLB is applied to dummy cell DMC for selecting series-connected dummy transistors DTB0 and DTB1. In read port selection circuit 36, port B (read port RPTRB) is selected. Accordingly, read bit lines RBLB0 and RBLB1 are connected to corresponding sense amplifiers SA0 and SA1, respectively.
In this connection manner, each of sense amplifiers SA0 and SA1 perform the AND operation of storage data of unit operator cell UOE0 and of unit operator cell UOE1 to transmit the data indicating the AND operational result to corresponding main amplifies MA0 and MA1 included in main amplifier circuit 20. Accordingly, main amplifier MAO produces data /A·/B, and main amplifier MA1 produces data A·B.
In combination logic operational circuit 26, two-input OR gate OG0 is selected. Two-input OR gate OG0 receives output data of main amplifiers MA0 and MA1. Accordingly, data DOUT supplied from OR gate OG0 through register 50 becomes data A·B+/A·/B that is equal to the XNOR operational result of input data A and B.
Thus, the data transfer paths in data path 28 and combination logic operational circuit 26 are set according to the operational contents, so that the operational results for input data can be obtained in one clock cycle.
The device waits for an external operation instruction (Step S1). When the operation instruction is supplied, data A and B are supplied, the paths of the data path and logical path are set according to operator op1 based on the operational contents (specified by OPLOG) instructed by the operation instruction (Step S2). Here, the logical path indicates the combination logic operational circuit. In this case, in data path unit block (DPUB), data A and B are selected when operator op1 is the AND operation. Data /A and /B are selected when operator op1 is the OR operation. A set of data (A,/B) and (/A,B) is selected when operator op1 is the XOR operation. Data (/A,/B) and (A,B) are selected when operator op1 is the XNOR operation. That is, as described above, in the case of the XOR operation and XNOR operation, the operation is performed using two data path unit blocks DPUB.
When the data propagation path of the data path is set (at this time point, the path of the logical path is also set), write access to the operator cell sub-array block is made, and the set data is written in the unit operator cell(s) (Step S3).
The data is read from the operator cell sub-array block at the same time as the data is written in the operator cell sub-array block (Step S4). At this time, for example, port B is selected in the case where operator op1 is any one of the AND operation, OR operation, XOR operation, and XNOR operation. That is, dummy cell selection signal DCLB is driven to the selected state, and read word lines RWLA and RWLB are driven to the selected state, to implement the selection manner of the dummy cells and ports for the data connection paths of
When the data is read from the operator cell sub-array block and the output data of main amplifier MA turns definite, the data is transferred through the path of the logical path (combination logic operational circuit) that is determined according to operator op1 (Step S5). At this point, in the logical path (combination logic operational circuit), an output signal MA of the main amplifier and an inverted signal /MA of the output signal MA are selected when operator op1 is one of the AND operation and OR operation, and two-input OR gate (OG0) is selected when operator op1 is one of the XOR operation and XNOR operation. The data transferred through the route in the logical path is stored in register (50) in the data path. Therefore, the operational result (A.op1.B) is stored as data Reg (Step S6). One clock cycle is consumed for the data write and read to complete one operation cycle in which the operation is performed for operator op1.
Here, it is assumed that the AND operation and OR operation are performed by the use of the outputs of the sense amplifiers. The NAND operation and NOR operation can be performed in a similar manner. The term of logical product operation is used to refer to both the AND operation and NAND operation, and the term of logical sum operation will is used to refer to both the NOR operation and OR operation in the following description.
Then, the operation sequence enters the next operation cycle, data C is supplied, and the routes of the data path and logic path are set according to operator op2 (Step S7). In data path (DPUB), external data C and data Reg stored in register (50) in the data path are selected when operator op2 is the AND operation. Inverted data /C of the external data and inverted value /Reg of the data stored in the register are selected when operator op2 is the OR operation. A set of data of (C, /Reg) and (/C, Reg) is selected when operator op2 is the XOR operation. A set of data of (/C, /Reg) and (C, Reg) is selected when operator op2 is the XNOR operation.
Then, similarly to Steps S2 to S4, the write access and the read access to the operator cell sub-array block are made. In this case, port B is also selected, and dummy transistors (DTB0 and DTB1) for selection of port B are selected as dummy cell DMC. Then, the output of the main amplifier is decided according to the output of the sense amplifier (Step S8).
The sense amplifier output in the definite state is transferred through the logic path route that is determined according to operator op2 in the combination logic operational circuit (Step S9). The data path setting manner of the combination logic operational circuit is similar to that in the case of operator op1.
The operational result data is obtained from the data transferred through the data propagation route set in the combination logic circuit in Step S9, and final operational result data DOUT is supplied through the register (Step S10). The second operation cycle is completed.
In the composite operation, it is necessary to perform the operational processing after the result of operation (A.op1.B) is decided, and it is necessary to sequentially make the access to the operator cell sub-array twice. That is, the data write and read are performed in one clock cycle for operator op1, and the data write and read are also performed in one clock cycle for operator op2. Accordingly, the operation can be performed in the total of two clock cycles for the operators op1 and op2.
In the processing sequence, operator op2 is issued along with data C to perform the operational processing after one clock cycle elapses since operator op1 is issued along with data A and B. Therefore, the composite operational processing can easily be implemented only by switching the data transfer paths of the internal configuration.
The write cycle for data C can be started when the output signal of the internal main amplifier, that is, the value stored in the register of the data path is settled. Accordingly, the write access timing can internally be set at a faster timing for data C (the write data is supplied in the continuous clock cycle and timing of the write driver for data C is adjusted to data decided timing of the register in the data path).
In accordance with the first embodiment of the present invention, in the unit operator cell, the two SOI transistors are used to store the data according to the accumulated charge amount in the body regions of the SOI transistors, the SOI transistors are/is selected according to the operational contents, and the write data and read data are set according to the operational contents.
Accordingly, for the unit operator cell, magnitude of the amount of current flowing through the bit line is sensed to read the storage data, so that the read operation r can be performed at high speed unlike the data read that is performed through the charge movement using a capacitor or the like. The large change in current amount can be generated, and the data can securely be sensed even under the low power supply voltage. Further, the data is not read externally for performing an operational processing by a separately provided logic gate, so that the operational processing can be performed at high speed. Additionally, the unit operator cell is formed by the four SOI transistors, so that the layout area can be reduced to prevent the increase in area of the memory cell array.
[Second Embodiment]
When an input carry Cin is “0”, word gate circuit 100 transmits the signals on write word line WWL and read word line pair RWLA/B of to a local word line group LWLG0. When input carry Cin is “1”, word gate circuit 100 maintains local word line group LWLG0 in the non-selected state.
Read word line pair RWLA/B includes read word lines RWLA and RWLB. Local word line group LWLG0 includes a local write word line LWWL0 and local read word lines LRWLA0 and LRWLB0. In the configuration of
In the case of input carry Cin being “1”, word gate circuit 102 transmits the signal potential on write word line WWL and the signal potential on read word line pair RWLA/B to a corresponding local word line group LWLG1. In the case of input carry Cin being “0”, word gate circuit 102 maintains corresponding local word line group LWLG1 in the non-selected state.
Accordingly, unit operator cells UOE0 and UOE1 are set in the non-selected state in the case of input carry Cin being “1”, and unit operator cells UOE2 and UOE3 are set in the non-selected state in the case of input carry Cin being “0”. That is, the data is selectively written in and read from the unit operator cell according to the logical value of input carry Cin.
In the one-bit addition, dummy cell selection signal DCLB is supplied to dummy cell DMC to select two series-connected dummy transistors (DTB0 and DTB1). In read port selection circuit 36, port B (read port RPRTB) is selected to connect read bit lines RBLB to corresponding sense amplifiers SA0 to SA3. Sense amplifiers SA0 to SA3 supply AND operational results for data stored in corresponding unit operator cells UOE0 to UOE3 (when the unit operator cell is in the selected state), respectively.
In the addition operation, the following route setting is performed in data path operation unit group 44. In data path unit block DPUB0, multiplexer 56 selects input data DINA (=A), multiplexer 57 selects the inverted value of input data DINB (=B). The inverted value of input data DINB (=B) is supplied from inverter 54. Accordingly, data A and /B are transmitted to corresponding global write data lines WGLA0 and WGLB0 through global write drivers (not shown), respectively.
In data path unit block DPUB1, multiplexer 56 selects the inverted value of input data A, which is supplied from inverter 52. Multiplexer 57 selects input data B. Accordingly, data /A and B are transmitted to corresponding global write data lines WGLA1 and WGLB1, respectively.
In data path unit block DPUB2, multiplexers 56 and 57 select the inverted values of input data A and B, which are supplied from inverters 52 and 54. Accordingly, data /A and /B are transmitted to corresponding global write data lines WGLA2 and WGLB2, respectively.
In data path unit block DPUB3, multiplexers 56 and 57 select input data A and B, and data A and B are transmitted to global write data lines WGLA3 and WGLB3 through not shown write drivers, respectively.
For dummy cell DMC, two series-connected dummy transistors (DTB0 and DTB1) are selected according to dummy cell selection signal DCLB.
In combination logic operational circuit 26, four-input OR gate OG1 that receives outputs of main amplifiers MAO (not shown) to MA3 included in main amplifier circuit 24 is selected according to logical passage instruction signal LGPS. In read port selection circuit 36, combination logic operational circuit 26, and data path 28, routes are set in response to control signals /PRMXB, LGPS, MXAS, and MXBS.
On the other hand, in the case of input carry Cin being “1”, sum SUM becomes “1” when data (A,B) is data (0,0) or (1,1). That is, sum SUM becomes “1” when one of operational results /A·/B and A·B is “1”.
The selection/non-selection of the word line (including write word line and read word line) is set according to input carry Cin, by utilizing the relationship of
Word gate circuit 100 includes an inverter 114 that inverts input carry Cin and AND gates 116a to 116c that are provided corresponding to local word lines LWWL0, LRWLA0, and LRWLB0. Inverted input carry /Cin is commonly imparted from inverter 114 to AND gates 116a to 116c. In the case of input carry Cin being “1”, AND gates 116a to 116c set all corresponding local word lines LWWL0, LRWLA0, and LRWLB0 at the L level of the non-selected state. In the case of input carry Cin being “0”, AND gates 116a to 116c transmit the signals on corresponding word lines WWL, RWLA, and RWLB to corresponding local word lines LWWL0, LRWLA0, and LRWLB0.
Referring to
(1) In the Case of Input Carry Cin being “0”:
Word gate circuit 100 drives local word line group LWLG0 in response to the signals of write word line WWL and read word lines RWLA and RWLB. Therefore, in data writing, data (A,/B) and (/A,B) are stored in unit operator cells UOE0 and UOE1, respectively. In data reading, data (A·/B) is supplied from sense amplifier SA0, and data (/A·B) is supplied from sense amplifier SA1.
Because word gate circuit 102 maintains unit operator cells UOE2 and UOE3 in the non-selected state, no current flows through corresponding read bit line RBLB. The dummy cell DMC is selected, and the amount of current flowing through complementary read bit line ZRBL is larger than the amount of current flowing through corresponding read bit line RBLB. Accordingly, irrespective of the logical value of the data stored in unit operator cells UOE2 and UOE3, it is determined that unit operator cells UOE2 and UOE3 are equivalently in the state of storing data “0”, and the output signals of sense amplifiers SA2 and SA3 becomes “0” (L level).
Output data of sense amplifiers SA0 to SA3 are transmitted to four-input OR gate OG1 through corresponding main amplifiers MAO (not shown) and MA1 to MA3. When one of the output data, that is, (A·/B) and (/A·B) is at the H level, the output signal of four-input OR gate OG1 attains H level (“1”). When both data (A·/B) and (/A·B) are at the L level, the output signal of four-input OR gate OG1 attains the L level (“0”). The output signal of four-input OR gate OG1 satisfies the logical value table of
(II) In the Case of Input Carry Cin being “1”:
In the case of input carry Cin being “1”, word gate circuit 100 maintains unit operator cells UOE0 and UOE1 in the non-selected state, and sense amplifiers SA0 and SA1 produce the output signals at the L level. Word gate circuit 102 drives corresponding local word line group LWLG1 into the selected state in response to the signals on write word line WWL and read word lines RWLA and RWLB. Accordingly, data (/A,/B) and (A,B) are stored in unit operator cells UOE2 and UOE3 and read therefrom. In the data reading, the output signals of sense amplifiers SA2 and SA3 assume AND operational results (/A·/B) and (A·B) of storage data, respectively. Accordingly, OR gate OG1 supplies the signal of the H level (“1”) when data /A·/B or A·B are “1”, and therefore sum SUM from register 50 is set to “1”.
When both data /A·/B and A·B are “0” (L level), four-input OR gate OG1 supplies the signal of the L level. Accordingly, sum SUM from register 50 is set to “0”.
As shown in a logical value table of
Therefore, the input and output relationship shown in the logical value table of
In the configuration of
In the case where word gate circuits 100 and 102 are used, in performing the operations except the addition, that is, in performing the AND, OR, XOR, or XNOR operation, the configuration for setting both input carries Cin and /Cin to H level is used. For example, for inverter 114, a NAND gate is used to receive input carry Cin and the control signal. The control signal is set at the L level in performing the operational processing except the addition operation, and the control signal is set at the H level in performing the addition processing. Other configurations other than such configuration may be utilized. Gate word circuits 100 and 102 have no adverse effect on the word line selection, so that various kinds of logic operational processing specified as described above can be performed.
[Configuration of Carry Producing Unit]
Following setting of the data propagation path is performed in the carry producing section of
In data path unit block DPUB1, multiplexer 56 selects the inverted value of input data A supplied from inverter 52, and multiplexer 57 selects input data B. Accordingly, data /A and B are transmitted to corresponding global write data lines WGLA1 and WGLB1.
In data path unit block DPUB2, multiplexer 56 selects input data A, and multiplexer 57 selects the inverted value of input data B supplied from inverter 54. Accordingly, data A and /B are transmitted to corresponding global write data lines WGLA2 and WGLB2.
Data path unit block DPUB3 is set in the input selection manner of “don't care,” and corresponding unit operator cell UOE3 is not used for the carry production.
In operator cell sub-array block, a word gate circuit 120 is provided for unit operator cell UOE0, and a word gate circuit 122 is provided for unit operator cells UOE1 to UOE3. Word gate circuit 120 receives power supply voltage VCC as the input carry, and transmits the signals on write word line WWL and read word line group RWLA/B to local word line group LWLG0 on corresponding unit operator cells UOE0 irrespective of the logical value of input carry Cin. The configurations of read word line pair RWLA/B and local word line group LWLG are similar to those of
According to the logical value of input carry Cin, word gate circuit 122 selectively transmits the signal potentials on write word line WWL and read word line pair RWLA/B to local word line group LWLG1 disposed for unit operator cells UOE1 to UOE3. That is, word gate circuit 122 maintains all unit operator cells UOE1 to UOE3 in the non-selected state in the case of input carry Cin being “0”. In the case of input carry Cin being “1”, word gate circuit 122 transmits the signal potentials on write word line WWL and read word line pair RWLA/B to local word line group LWLG1.
Dummy cell selection signal DCLB is applied to dummy cell DMC to select the series-connected dummy transistors. In read port selection circuit 36, port B is selected to connect read bit lines RBLB to corresponding sense amplifiers SA0 to SA3.
In combination logic operational circuit 26, three-input OR gate OG1 is selected to receive main amplifiers MA1 and MA2 included in main amplifier circuit 24 and the output signal (not shown) of main amplifier MAO. OR gate OG1 supplies a carry CY through register 50.
Referring to
Word gate circuit 122 includes AND gates 126a to 126c that are provided corresponding to local write word line LWWL1 and local read word lines LRWLA1 and LRWLB1. Input carry Cin is commonly applied to the first inputs of AND gates 126a to 126c, and the signals on write word line WWL and read word lines RWLA and RWLB are applied to the second inputs of AND gates 126a to 126c. The output signals of word gate circuits 122 are applied to unit operator cells UOE1 to UOE3 of
Accordingly, as is clear from the configurations of word gate circuits 120 and 122 of
Referring to
Word gate circuit 120 drives corresponding unit operator cell UOE0 to the selected state according to the signal of write word line WWL irrespective of the logical value of input carry Cin, and data A and B transferred to global write data lines WGLA0 and WGLB0 are written in unit operator cell UOE0. In the data reading, word gate circuit 120 drives local read word lines LRWLA0 and LRWLB0 of corresponding unit operator cell UOE0 in response to the signals on read word lines RWLA and RWLB, and the current flows through read bit line RBLB according to the logical values of data A and B. Two series-connected dummy transistors (DTB0 and DTB1) of dummy cell DMC are connected to complementary read bit line ZRBL, and the current flows through complementary read bit line ZRBL according to the voltage level of reference voltage Vref. Accordingly, the output data of sense amplifier SA0 is the AND operation result of the data stored in unit operator cell UOE0, sense amplifier SA0 produces data A·B, and the data A·B is transmitted to three-input OR gate OG1 through the corresponding main amplifier (not shown).
On the other hand, word gate circuit 122 selectively drives unit operator cells UOE1 to UOE3 to the selected state according to the logical value of input carry Cin. In the case of input carry Cin being “0”, unit operator cells UOE1 to UOE3 are in the non-selected state, and the data write and read are not performed. Accordingly, the amount of current flowing through complementary read bit line ZRBL is larger than the amount of current flowing through corresponding read bit line RBLB, and the output signals of sense amplifiers SA1 to SA3 attain “0”. That is, in the case of input carry Cin being “0”, the output signal of three-input OR gate OG1 becomes the voltage level corresponding to output data A·B of sense amplifier SA0, and carry CY outputted from register 50 becomes the logical value corresponding to the logical value of data A·B. Accordingly, as shown in
In the case of input carry Cin of “1”, the data writing and reading are also performed on unit operator cells UOE1 to UOE3. Data /A and B transmitted to corresponding global write data lines WGLA1 and WGLB1 are stored in unit operator cell UOE1, and data A and /B transmitted to corresponding global write data lines WGLA2 and WGLB2 are stored in unit operator cell UOE2.
Port B is selected, and sense amplifiers SA1 and SA2 output the AND operation results of data stored in corresponding unit operator cells UOE1 and UOE2, or data /A·B and A·/B. The output signals of sense amplifiers SA0 to SA2 are applied to three-input OR gate OG1 through corresponding main amplifiers MA0 to MA2. Thus, three-input OR gate OG1 outputs data (A·B+A·/B+A·/B). As is clear from the logical value table of
Thus, the one-bit full addition operation can be performed in one clock cycle by concurrently operating the adder and carry producing section of
(Configuration of One-Bit Subtracter)
In the case of input borrow BRin being “1”, subtraction value DIFF becomes “1” when data (A,B) is (0,0) or (1,1). Accordingly, if the configuration in which output value becomes “1” when one of operational results /A·/B and A·B is “1” is realized, subtraction value DIFF can be produced in the case of input borrow BRin being “1”. The one-bit subtracter is implemented by establishing the set of data selected according to the logical value of input borrow BRin in data path 28.
In the case of input borrow BRin of “1”, word gate circuit 130 maintains unit operator cells UOE0 and UOE1 in the non-selected state. On the other hand, in the case of input borrow BRin being “1”, word gate circuit 130 transmits signal potentials on write word line WWL and read word line pair RWLA/B to corresponding local word line group LWLG0. Similarly to the configuration of
In the case of input borrow BRin being “1”, word gate circuit 132 drives local word line group LWLG1 to the selected state according to the signal potentials on write word line WWL and read word lines RWLA and RWLB. Local word line group LWLG1 is arranged for unit operator cells UOE2 and UOE3. In the case of input borrow BRin being “0”, word gate circuit 132 maintains local word line group LWG1 for unit operator cells UOE2 and UOE3 in the non-selected state to prohibit the data from being written in and read from unit operator cells UOE2 and UOE3.
For example, word gate circuits 130 and 132 can be implemented by utilizing the configurations of word gate circuits 100 and 102 of
Dummy cell selection signal DCLB is applied to dummy cell DMC to select two series-connected dummy transistors (DTB0 and DTB1) in dummy cell DMC.
In read port selection circuit 36, port B (read port RPRTB) is selected to connect read bit lines RBLB to corresponding sense amplifiers SA0 to SA3.
In combination logic operational circuit 26, four-input OR gate OG2 is selected, and the output signals of main amplifiers MA0 to MA3 included in main amplifier circuit 24 are applied to four-input OR gate OG2. The output signal of four-input OR gate OG2 is outputted as subtraction value DIFF externally through register 50.
As shown in
Referring appropriately to
In the case of input borrow BRin being “0”, word gate circuit 132 maintains unit operator cells UOE2 and UOE3 in the non-selected state, and make the data write/read access to unit operator cells UOE0 and UOE1. Accordingly, data A and /B on global write data lines WGLA0 and WGLB0 are stored into and read from unit operator cell UOE0. Similarly, data /A and B on global write data lines WGLA1 and WGLB1 are written in and read from unit operator cell UOE1.
Dummy cell selection signal DCLB is applied to dummy memory cell DMC, and port B is selected. Accordingly, sense amplifiers SA0 and SA1 output AND operation results A·/B and /A·B of data stored in corresponding unit operator cells UOE0 and UOE1.
In sense amplifiers SA2 and SA3, unit operator cells UOE2 and UOE3 are in the non-selected state, substantially no current flows through read bit line RBLB, and dummy cell DMC supplies the current to complementary read bit line ZRBL. In this state, sense amplifiers SA2 and SA3 thus output the data “0”. Sense amplifiers SA0 to SA3 supply the data to four-input OR gate OG1 through corresponding main amplifiers MA0 to MA3. Accordingly, the data (A·/B)+(/A·B) is generated through register 50. As shown in the logical value table of
In the case of input borrow BRin being “1”, word gate circuit 130 maintains unit operator cells UOE0 and UOE1 in the non-selected state. Word gate circuit 132 drives local word line group LWG1 of unit operator cells UOE2 and UOE3 to the selected state according to the signal potentials on write word line WWL and read word lines RWLA and RWLB, and the data write/read access is made. Accordingly, data /A and /B on corresponding global write data lines WGLA2 and WGLB2 are stored in and read from unit operator cell UOE2, and data A and B on corresponding global write data lines WGLA3 and WGLB3 are stored in and read from unit operator cell UOE3.
Port B is selected, two series-connected dummy transistors are selected in dummy cell DMC in response to dummy cell selection signal DCLB, sense amplifiers SA2 and SA3 produce AND operation results (/A·/B) and (A·B) of data stored in unit operator cells UOE2 and UOE3. Main amplifiers MA0 and MA1 output data “0” received from sense amplifiers SA0 and SA1. Accordingly, OR gate OG2 supplies data (/A·/B+A·B) through register 50.
As can be seen from the logic table of
(Configuration of Borrow Producing Section)
In the case of input borrow BRin being “1”, output borrow BRout becomes “1” when data (A,B) is (0,0), (0,1), or (1,1). Accordingly, in the case of input borrow BRin being “1”, output borrow BRout becomes “1” when data (/A·/B+/A·B+A·B) is “1”. In this case, output borrow BRout becomes “1” irrespective the value of input borrow BRin when AND operation result /A·B is “1”. Accordingly, similarly to the case in which output carry CY is produced, output borrow BRout can be produced using the set of three kinds of data also in the portion in which output borrow BRout is produced.
In data path unit block DPUB0, multiplexer 56 selects the inverted value of input data DINA (=A) received from inverter 52, and multiplexer 57 selects input data INB (=B). Accordingly, data /A and B are transmitted to corresponding global write data lines WGLA0 and WGLB0.
In data path unit block DPUB1, multiplexers 56 and 57 select pieces of input data A and B, respectively. Accordingly, pieces of data A and B are transmitted to global write data lines WGLA1 and WGLB1.
In data path unit block DPUB2, multiplexers 56 and 57 select inverted values /A and /B of input data A and B received from inverters 52 and 54, respectively. Accordingly, data /A and /B are transmitted to corresponding global write data lines WGLA2 and WGLB2.
A word gate circuit 140 is provided for unit operator cell UOE0 that is arranged for data path unit block DPUB0, and a word gate circuit 142 is commonly provided for unit operator cells UOE1 to UOE3 that are arranged for data path unit blocks DPUB1 to DPUB3. Word gate circuit 140 transmits the signals on write word line WWL and read word line pair RWLA/B to write local word line group LWLG0 of unit operator cell UOE0 irrespective of the logical value of input borrow BRin. Word gate circuit 142 selectively transmits the signal potentials on write word line WWL and read word line pair RWLA/B to local word line group LWLG1 according to the logical value of input borrow BRin. The configurations of local word line group LWLG and read word line pair are identical to that of the carry producing section of the one-bit adder.
In the configurations of word gate circuits 140 and 142 shown in
In unit operator cell UOE0, corresponding local write word line LWWL0 and local read word lines LRWLA0 and LRWLB0 are driven to the selected state according to the signal potentials on write word line WWL and read word lines RWLA and RWLB irrespective of the value of input borrow BRin, and data writing and reading are performed. Referring to the logical value table of
As described above, in the case of input borrow BRin being “0”, word gate circuit 142 maintains all unit operator cells UOE1 to UOE3 in the non-selected state. In this case, data /A and B transmitted to global write data lines WGLA0 and WGLB0 are stored in and read from unit operator cell UOE0. Port B is selected, and the series-connected dummy transistors are selected in dummy cell DMC in response to dummy cell selection signal DCLB. Accordingly, sense amplifier SA0 supplies AND operation result /A·B of the transferred data. Sense amplifiers SA1 to SA3 supply the data “0” because all unit operator cells UOE1 to UOE3 are in the non-selected state.
The output signals (data) of sense amplifiers SA0 to SA2 are applied to three-input OR gate OG1 through corresponding main amplifiers MA0 to MA2. Accordingly, OR gate OG1 supplies the data corresponding to the output data of sense amplifier SA0, and the output data from register 50 becomes equal to data /A·B. The data satisfies the logical value relationship in the case of input borrow BRin being “0” in the logical value table of
In the case of input borrow BRin being “0”, word gate circuit 142 drives local word line group LWLG1 arranged for unit operator cells UOE1 to UOE3 to the selected state according to the signal potential on write word line WWL and read word line pair RWLA/B. Accordingly, data A and B on global write data lines WGLA1 and WGLB1 are written in and read from unit operator cell UOE1, and data /A and /B are written in and read from unit operator cell UOE2. Unit operator cell UOE3 is not used. Corresponding sense amplifiers SA1 and SA2 produce data A·B and /A·/B, respectively.
Because data /A−B, A−B, and /A·/B supplied from sense amplifiers SA0 to SA2 are applied to three-input OR gate OG1, OR gate OG1 supplies data (/A·B+A·B+/A·/B) through register 50. The data satisfies the logical value relationship of
Accordingly, irrespective of the logical value of input borrow BRin, the output data satisfying the logical value relationship of
The one-bit subtracter can be implemented by concurrently operating the one-bit subtracter of
In the subtraction operation, similarly to the combination logic operation, only the connection manner of the internal data propagation route is changed, and the arithmetic operation of the subtraction can be performed without changing the internal configuration.
Even in the subtracter, the port connection, the gate selection in the input of the combination logic operational circuit, and the selection of the data propagation route in the data path are set based on specified operational processing contents in response to the corresponding control signals. For the control signals, in the data path, it is necessary to produce four individual sets of system switching control signals for the four data path unit blocks of the carry/borrow producing section and four individual sets of switching control signals for the four data path unit blocks of the addition/subtraction unit. The same holds for the logical path instruction signal in the combination logic operational circuit.
(First Modification)
Referring to
A carry input CIN of one-bit full adder FA0 receives input carry Cin. For each of one-bit full adders FA1, FA3, and FA5, switching elements SWN and NTX are arranged in parallel with each other for carry input CIN. For each of one-bit full adders FA2, FA4, and FA6, switching elements SWN and PTX are arranged in parallel with each other for carry input CIN.
Switching elements SWN are made conductive when a one-bit addition operation instruction BIT1 is set (turns H level), and transmit input carry Cin to carry inputs CIN of corresponding one-bit full adders FA1 to FA6. Switching elements NTX are made conductive when a four-bit addition operation instruction BIT4 is activated (set to H level), and transmit ground voltage GND to carry inputs CIN of one-bit full adders FA1, FA3, and FA5. Switching elements PTX are made conductive when an inverted four-bit addition operation instruction /BIT4 is activated (set to L level), and transmit power supply voltage VCC to carry inputs CIN of corresponding one-bit full adders FA2, FA4, and FA6. That is, switching element NTX forcedly sets input carry Cin at “0” when made conductive, and switching element PTX forcedly sets input carry Cin at “1” when made conductive.
Carry input CIN is connected to a node that receives input carry Cin for each respective word gate circuit. The selection/non-selection of the unit operator cell of the word gate circuit included in each of one-bit full adders FA0 to FA6 is set by forcedly setting the input carry. Input carries Cin are forcedly set to one-bit full adders FA0 to FA6, whereby the addition operations are concurrently performed in one-bit full adders FA1 to FA6 for the case where the input carry supplied from the one-bit preceding full adder is “0” and for the case of the input carry being “1”.
Demultiplexers (DEMUX) DX0 to DX6 are provided for one-bit full adders FA0 to FA6 in the data path. Demultiplexers DX0 to DX6 correspond to demultiplexers 63 of
Demultiplexer DX0 produces sum S<0> and carry CY<0> of the least significant bit. Demultiplexers DX1, DX3, and DX5 supply sums S0<1> to S0<3> and carries CY0<1> to CY0<3> when input-carry CY from a preceding stage is “0”. Demultiplexers DX2, DX4, and DX6 supply sums S1<1> to S1<3> and carries CY1<1> to CY1<3> when the output carry of one-bit full adder of each respective preceding stage is “1”.
A four-bit addition processing circuit 145 is arranged in combination logic operational circuit 26, and includes multiplexers 147a to 147f that are provided for demultiplexers DX1 to DX6. Demultiplexer DX0 produces sum S<0> as least significant addition bit S<0>. Multiplexer 147a selects one of sums S0<1> and S1<1> according to intermediate carry bit CY<0> to produce addition bit S<1>. Multiplexer 147b selects one of carries CY0<1> and CY1<1> according to intermediate carry bit CY<0> to produce intermediate carry bit CY<1>.
Multiplexer 147c selects one of sums S0<2> and S1<2> according to intermediate carry bit CY<1> to produce addition bit S<2>. Multiplexer 147d selects one of intermediate carry bits CY0<2> and CY1<2> according to intermediate carry bit CY<1> to produce intermediate carry bit CY<2>. Multiplexer 147e selects one of sums S0<3> and S1<3> according to intermediate carry bit CY<2> to produce most significant addition bit S<3>. Multiplexer 147f selects one of intermediate carry bits CY0<3> and CY1<3> according to intermediate carry bit CY<2> to produce output carry COUT.
That is, the carries and sums are produced in parallel for the cases of “0” and “1” of the input carry in advance, and multiplexers 147a to 147f select the final sum and carry according to the actually produced intermediate carry bits CY<0> to CY<2> in four-bit addition processing circuit 145.
In performing the four-bit addition operation, the four-bit addition instructions BIT4 and BIT4 are set in the active state, and the four-bit addition processing can be performed in one clock cycle by activating the four-bit addition operational processing. In each of one-bit full adders FA0 to FA6, one-bit full addition is performed. When the addition result is to be produced, the one-bit addition instruction BIT1 is activated, and input carry Cin is coupled to carry input CIN. In this case, input carry Cin is individually set to each of one-bit full adders FA0 to FA6 (transmission bus of input carry Cin of
In cases where the full addition is performed in bit serial and data parallel in each of one-bit full adders FA0 to FA6, produced carry is fed back to carry input CIN of corresponding one-bit full adder. Here, the term “bit serial and data parallel” 1 means a fashion in which an operation is concurrently performed to plural multi-bit data while performed on each data in a bit-by-bit manner.
In the configuration of the four-bit full adder shown in
Four-bit addition processing circuit 145 of
(Second Modification of Four-Bit Adder)
Input carry Cin is fixed to “0” and is transmitted to eight-cell groups GP00 to GP06, and input carry Cin is fixed to “1” and is transmitted to eight-cell groups GP10 to GP16. Compared with the configuration in which different input carries Cin are transmitted to the unit operator cells aligned in one row, the value of input carry Cin is fixed in each unit operator cell row, thereby facilitating the layout of the transmission lines of input carry Cin.
In row ROW<0>, four-bit addition instruction BIT4 is applied to eight-cell groups GP00, GP01, GP03, and GP05, and complementary four-bit addition instruction /BIT4 is applied to eight-cell groups GP02, GP04, and GP06.
In row ROW<1>, four-bit addition instruction /BIT4 is applied to eight-cell groups GP10, GP11, GP13, and GP15, and four-bit addition instruction BIT4 is applied to eight-cell groups GP12, GP14, and GP16.
In each of eight-cell group GP00 to GP06 and GP10 to GP16, word gate circuits (100 and 102) are provided as shown in
Sense amplifier (SA) groups SAG0 to SAG6 are provided for eight cell groups GP00 to GP06 and GP10 to GP16. Each of sense amplifier groups SAG0 to SAG6 includes eight sense amplifiers, and output data of sense amplifier groups SAG0 to SAG6 are applied to combination logic operational circuit through main amplifiers. In the combination logic operational circuit, as shown in
In the configuration of
The configuration in which rows ROW<0> and ROW<1> are concurrently driven to the selected state can easily be realized by simply setting the least significant bit of the word line address in a degenerated state (don't care state) according to four-bit addition operation instruction BIT4.
Similarly, the four-bit addition processing can be realized in one clock cycle in the bit parallel fashion by utilizing the configuration of
One of the eight-cell groups in the same column is in the active state while the other is in the inactive state (unit operator cell is in the non-selected state), so that the collision of the write data and read data is not caused. Even in the addition operation processing, the data is read from one operator cell sub-array block while the data is written in another operator cell sub-array block, so that the four-bit addition processing can be performed in a pipeline manner and the four-bit addition processing can be performed in one clock cycle quivalently.
Rows ROW<0> and ROW<1> may be unit operator cell rows included in different operator cell sub-array blocks. The data writing path differs from the data reading path in the unit operator cell in which the SOI transistors are used. Accordingly, when the data is read to perform the addition on a unit operator cell group, the data may concurrently be written in another unit operator cell group.
In the arrangement of
Thus, according to the second embodiment of the present invention, in the combination logic operational circuit, the combination logic operation processing is performed to the values stored in the unit operator cells, so that the arithmetic operations of the addition and subtraction can be performed at high speed without changing the internal configuration.
The addition/subtraction result is preliminarily obtained while the value of carry/borrow is fixed, and one of the preliminary addition/subtraction results is selected according to the actual carry/borrow output of the preceding-stage circuit in the final stage, so that the addition/subtraction processing of the plural bits can be performed at high speed in the bit parallel fashion.
[Third Embodiment]
Where unit operator cell UOE shown in
A P-type region 154a is disposed adjacent to P-type region 150b in the Y-direction. A P-type region 154b is disposed in alignment with P-type region 154a in the Y-direction, and P-type region 154b and P-type region 154a are separated from each other. A high-concentration P-type region 150c is disposed in alignment with and in contact with P-type region 154b in the Y-direction. A high-concentration P-type region 150d is disposed in alignment with P-type region 150c in the Y-direction. An N-type region 152b is disposed between P-type regions 150c and 150d. N-type region 152b constitutes the body region of SOI transistor PQ2. A P-type region 154c is disposed extending in the X-direction, and is in contact with P-type region 150d.
A high-concentration N-type region 156a is disposed adjacent to P-type region 150h and outside the P-channel SOI transistor forming region. High-concentration N-type regions 156b and 156c are disposed in alignment with N-type region 156a in the Y-direction, and are separated from each other. P-type region 154a is disposed extending in the X-direction between N-type regions 156a and 156b, and P-type region 154b is disposed extending in the X-direction between N-type regions 156b and 156c.
A gate electrode interconnection line 158a is disposed continuously extending in the X-direction on N-type region 152a. A gate electrode interconnection line 158b is continuously provided on P-type region 154a along the X-direction so as to traverse a region between N-type regions 156a and 156b. A gate electrode interconnection line 158c is continuously provided on P-type region 154b along the X-direction so as to traverse a region between N-type regions 156b and 156c.
Second metal interconnection lines 160a to 160e are provided continuously extending in the X-direction, and are separated from each other. A second metal interconnection line 162a is disposed in alignment with gate electrode interconnection line 158a, and is electrically connected to gate electrode interconnection line 158a (contact portion is not shown) to constitute write word line WWLA. Second metal interconnection line 160b is electrically connected to N-type region 156a through a contact/via CVb and intermediate interconnection line to constitute source line SL. Second metal interconnection line 160c is provided in parallel with gate electrode interconnection line 158b provided in a lower layer thereof, and is electrically connected to gate electrode interconnection line 158b (contact portion is not shown) to constitute read word line RWLA. Second metal interconnection line 160d is disposed in alignment with gate electrode interconnection line 158c, and is electrically connected to gate electrode interconnection line 158c to constitute read word line RWLB. Second metal interconnection line 160e is disposed in alignment with gate electrode interconnection line 158d, and is electrically connected to gate electrode interconnection line 158d to constitute write word line WWLB.
First metal interconnection lines 162a to 162d are disposed continuously extending along the Y-direction, and are separated from one another. The first metal interconnection line is located below the second metal interconnection line.
First metal interconnection line 162a is electrically connected to N-type region 156c through a contact/via CVd. First metal interconnection line 162b is electrically connected to N-type region 156b through a contact/via CVb. First metal interconnection line 162c is electrically connected to P-type region 150a through a contact/via CVa. First metal interconnection line 162d is electrically connected to P-type region 150c through a contact/via CVe.
First metal interconnection lines 162a and 162b constitute read bit lines that transmit data DOUTB and DOUTA through port B and port A, respectively. First metal interconnection lines 162c and 162d each constitute a write port and a global write data line for transmitting input data DINA and DINB.
Write word lines WWL and WWLB are disposed sandwiching read word lines RWLA and RWLB in between, so that the gates of SOI transistors PQ1 and PQ2 are electrically connected to different write word lines WWLA and WWLB without largely changing the layout of unit operator cell UOE shown in
In data path 28, a match line ML is disposed commonly to data path operational unit blocks 44<0> to 40<m>. In each of data path operational unit groups 44<0> to 44<m>, a discharging transistor TQ1 is provided for data path unit block DPUB0. Discharging transistor TQ1 is formed by an N-channel MOS or SOI transistor, is connected to match line ML, and discharges match line ML in response to the output signal of the corresponding two-input OR gate. A P-channel pre-charging transistor PQ0 and an amplifying circuit AMP are provided for match line ML. P-channel pre-charging transistor PQ0 charges match line ML to a power supply voltage level in response to a pre-charge instruction signal /PRE. Amplifying circuit AMP amplifies a signal potential on match line ML.
In operator cell array 20, input data B and inverted data /B are stored as entry data in storage nodes SNB of the unit operator cells that are disposed for data path unit blocks DPUB0 and DPUB1.
After the search is started, in data path unit blocks DPUB0 and DPUB1, inverted data /A of data A and non-inverted data A are selected and stored in and then read out from storage nodes SNA of the corresponding unit operator cells. The data (/A,B) and (A,/B) are read in the corresponding unit operator cells.
The sense amplifiers of operator cell array 20 produces AND operational results A·/B and /A·B to two-input OR gate OG0 through the corresponding main amplifiers. In the case where data A and B are matched with each other, AND operational results A·/B and /A·B become “0” and the output signal of OR gate OG0 becomes “0”. On the other hand, in the case where data A and B are not matched with each other, one of data A·/B and /A·B becomes “1” and the output signal of corresponding OR gate OG0 becomes “1”.
Accordingly, the output signal of OR gate OG0 that detects the mismatch becomes “1”, and a corresponding discharging transistor TQ1 turns on to discharge match line ML. The voltage level of match line ML becomes a voltage level pre-charged by pre-charging transistor PQ0 in the case where data A and B are matched with each other, and voltage level of match line ML becomes lower than a pre-charge voltage through discharging by discharging transistor TQ1 in the case where data A and B are not matched with each other. The voltage level of match line ML is amplified by amplifying circuit AMP, whereby the voltage level of match line ML can be determined according to a logic level of an output signal SRSLT, and therefore the match/mismatch between search data A and previously stored search target data (entry data) B can be determined.
Data B is supplied as the search target data, and data B and inverted data /B are stored in unit operator cells (UOE0 and UOE1) of entry ERY by path selection processing in data path 28 (Step SP1). In such operation, only write word line WWLB is selected to store the data in the body region of SOI transistor NQ2 shown in
Then address counter 170 is sequentially updated in response to a clock signal (not shown), and the entry of operator cell array 20 is sequentially updated to store the search target data (Step SP2).
After all the search target data necessary for operator cell array 20 are stored, the searching operation is started for data A (Step SP3). In starting the searching operation, address counter 170 is reset to the initial value. In data path 28, using input data (search data) A, inverted data /A and data A are produced for data path unit blocks DPUB0 and DPUB1 and transmitted to the corresponding unit operator cells. In writing the search data, write word line WWLB is maintained in the non-selected state, and only write word line WWLA is driven to the selected state. Then row selection driving circuit 22 concurrently selects read word lines RWLA and RWLB of the selected entry to read the data through port B.
Sense amplifiers SA produce data A·/B and A·/B to corresponding two-input OR gate OG0 through the corresponding main amplifiers. Discharging transistor TQ1 selectively discharges match line ML in response to the output signal of two-input OR gate OG0. The control circuit (30, not shown) determines whether the match is generated in response to output signal SRSLT of amplifying circuit AMP that amplifies the voltage on match line ML (Step SP4).
When the match is detected, address counter 170 stops the counting operation, and retains and supplies the current count value (Step SP5). Processing, which is appropriately defined depending on the application of the semiconductor signal processing device, is performed using the count value of address counter 170 as an address index.
When the data stored in the selected entry is not matched with search data A, a determination whether the search is completed for all the entries is made (Step SP6). When the search is not completed for all the entries, the address counter 170 has the count value updated (Step SP8), and row selection driving circuit 22 selects the next entry to perform the searching (Step SP9).
On the other hand, when a determination that the search is completed for all the entries is made in Step SP6, because the search target data stored in operator cell array 20 are not matched with search data A, necessary processing in generation of the mismatch is performed (Step SP7).
In searching processing, each entry is sequentially selected to perform the search. Accordingly, although the processing speed becomes slower than that of a usual parallel searching operation as done in a TCAM (Three-value CAM), the layout area of the unit operator cell can largely be reduced, compared with TCAM in which the usual SRAM cell is used.
In the TCAM, usually an XOR circuit that determines the match/mismatch is arranged in each cell, a match line is disposed for each entry, and each match line is discharged by the corresponding XOR circuit. Accordingly, there is caused a problem that current dissipation is increased due to the charging and discharging of the match line.
In the third embodiment, because data path 28 and combination logic operational circuit 26 are commonly provided for a plurality of entries, the charging and discharging current of the match line is largely reduced, and the layout area of the portion for providing the components that determine the match/mismatch can largely be reduced.
When command decoder 70 provides operation processing instruction OPLOG to write the search target data in each entry, similarly to the XOR operation, connection control circuit 272 sets switching control signals MXAS and MXBS to the states of forming the connection path through which the adjacent data path unit blocks generate the complementary data, and sets logical path instruction signal LGPS to the state of selecting the two-input OR gate.
When command decoder 70 supplies operation processing instruction OPLOG instructing the writing of search target data in each entry, write control circuit 274 activates a write word line enable signal WWLENB and write activation signal WREN while maintaining a write word line enable signal WWLENA in the inactive state. When operation processing instruction OPLOG instructs the start of searching, write control circuit 274 sets write word line enable signal WWLENB to the inactive state while driving write activation signal WREN and write word line enable signal WWLENA to the active state.
When operation processing instruction OPLOG instructs the writing of search target data, read word control circuit 276 sets read activation signal RREN and read word line enable signals RWLENA and RLENB at the inactive state and sets main port selection signal PRMXM to the inactive state. When operation processing instruction OPLOG instructs the start of searching, read word control circuit 276 activates write word line enable signal WWLENA, and then drives read activation signal RREN and read word line enable signals RWLENA and RWLENB to the active state at a predetermined timing.
When operation processing instruction OPLOG instructs the writing of the search target data, data read control circuit 278 maintains sense amplifier activation signal SAEN, main amplifier activation signal MAEN, and read block selection activation signal CLEN in the inactive state. When operation processing instruction OPLOG instructs the starting of search, before the read word line is activated, read word control circuit 276 sets main port selection signal PRMXM to the state of selecting port B (read port RPTB), drives sense amplifier activation signals SAEN (/SOP and SON) to the active state according to read word line selection timing of read word control circuit 276, and activates main amplifier activation signal MAEN. In this operation, read gate selection timing signal CLEN is activated before or after the sense amplifier is activated.
Row drive circuit XDRi includes a read word line drive circuit 280 that drives a read word line, a dummy cell selection circuit 282 that selects a dummy cell, and a write word line drive circuit 284 that drives a write word line.
Read word line drive circuit 280 is enabled in activation of read activation signal RREN, receives and decodes the count value from address counter (170) as address signal AD and block address signal BAD, and drives read word lines RWLA and RWLB that are arranged for the specified entry to the selected state at timing defined by read word line enable signals RWLENA and RWLENB.
Dummy cell selection circuit 282 is enabled in activation of read activation signal RREN, receives and decodes block address signal BAD from address counter 170, and drives one of dummy cell selection signals DCLA and DCLB to the selected state in response to read word line enable signals RWLENA and RWLENB. Dummy cell selection circuit 282 drives dummy cell selection signal DCLA to the selected state when only read word line enable signal RWLENA is activated, and dummy cell selection circuit 282 drives dummy cell selection signal DCLB to the selected state when both read word line enable signals RWLENA and RWEANB are activated.
Write word line drive circuit 284 is enabled in activation of write activation signal WREN, decodes address signals AD and BAD from address counter 170, and drives write word lines WWLA and WWLB to the selected state at activation timing of write word line enable signals WWLENA and WWLENB.
A sub-array selection driving circuit 290 includes a read gate selection circuit 292 that selects a read gate and a port connection control circuit 294 that performs the port connection control. Read gate selection circuit 292 is enabled in activated read activation signal RREN, decodes block address signal BAD from address counter 170, and drives read gate selection signal CSL for the corresponding operator sub-array block to the selected state at activation timing of read gate selection timing signal CLEN according to the decoding result.
Port connection control circuit 294 is enabled in activation of read active signal RREN, and sets port selection signals /PRMXA and /PRMXB to the state of setting the port connection of the corresponding operator cell sub-array block in accordance with main port selection signals PRMXM and block address signals BAD. Port selection signals /PRMXA and /PRMXB correspond to previously-described port selection signal PRMX. In the searching operation, port connection control circuit 294 drives port-B selection signal /PRMXB of port selection signals /PRMXA and /PRMXB to the L level such that port B is selected.
Using the control circuit and row selection driving circuit shown in
In the case where block address BAD and address AD are produced with address counter 170 in the configurations shown in
The following configuration can be utilized to implement the data processing in the pipeline manner by way of example. Address signals BAD and AD are applied to read word line drive circuit 280, dummy cell selection circuit 282, and port connection control circuit 290 while being delayed by one clock cycle later than the application of these address signals to write word line drive circuit 284. Therefore, the data read access can be made in the next cycle to the operator cell sub-array block in which the data is written. In data path 28, because the data writing path differs from the data reading path, there is caused no problem even if the data transfer path in the data write and the data transfer path in the data read are set in parallel. This enables the high-speed processing to be performed in the pipeline manner.
In the same operator cell sub-array block, the data can concurrently be written and read to the different entries. In this behavior, the application of the word line address in the data write is delayed by one clock cycle behind that in the data read. The data read is performed in the next cycle to the entry in which the data is written. This configuration can also be implemented using the configurations shown in
Thus, in semiconductor signal processing device according to the third embodiment of the present invention, the match/mismatch determination section is provided commonly to a plurality of entries, the search target data is stored in each entry, and then the complementary data are produced through the data path according to the search data for writing and reading data. Accordingly, the searching operation can be performed in one clock cycle for one entry, and the layout area of the memory cell array and the consumed current can be reduced.
[Fourth Embodiment]
Operation data input and output processing circuit 300 is divided into operation unit blocks 302a, 302b, . . . . Each of operation unit blocks 302a, 302b, . . . includes unit operation block (UCL) and data path operation unit group (44) of the combination logic operational circuit.
Data words A, B, C, and D are supplied to operation data input and output processing circuit 300 in a bit serial fashion, and resultant data DOUT of operational processing (*) of the data is supplied externally in the bit serial manner.
In the bit serial and data word parallel manner, a data string conversion circuit 310 applies the data string. Data words A, B, C, . . . applied in bit parallel and data serial are sequentially stored in data string conversion circuit 310, and data string conversion circuit 310 transfers the storage data in the bit serial and data word parallel manner.
Here, “bit serial and data word parallel” transfer means a manner, in which bits constituting a data word are sequentially transferred and the data words are transferred in parallel. “Bit parallel and data word serial” transfer means a manner, in which the data words are transferred in serial and a plurality of bits constituting a data word are transferred in parallel.
The configuration of data string conversion circuit 310 can easily be implemented using a usual orthogonal transformation circuit. Although data string conversion circuit 310 is provided outside the semiconductor signal processing device in
Row selection driving circuit 22 selects an entry, and the specified operation processing is performed in the bit serial and data word parallel manner.
A two-input OR gate OG10 that receives output bits P<4k+1> and <4k+2> of the corresponding main amplifiers is also provided for multiplexer 62a. Two-input OR gate OG10 produces a sum SUM in the bit serial manner.
Other configuration of unit operation block UCL4k shown in
Multiplexer 320 selects one of bits Q0 from AND/OR complex gate AOCT1 and the corresponding unit operation block in response to an operation switching signal OPAX, and supplies the output signal to register 50. The output signal of register 50 is supplied as external data DOUT<0> through buffer 51, and is also fed back to data path unit blocks DPUB0 to DPUB3 in the same data path operation unit group.
Because the configuration of the data path unit block shown in
Even in the case where the bit-serial addition or subtraction is performed, the one-bit addition or subtraction is also performed using the carry producing unit and the sum producing unit that are arranged for each data path operation unit group (44).
For the selections of the read word line and write word line for the unit operator cell, the word gate circuit that selectively transmits the signal according to the carry/borrow value is not used in the addition/subtraction processing in the bit serial manner. Similarly to the execution of the XOR operation or XNOR operation, the selection of the unit operator cell and the write/read access to the unit operator cell are executed.
In data path unit block DPUB1, multiplexer 56 selects inverted value /A of input data A, and multiplexer 57 selects inverted value /B of input data B. Inverted value /A is supplied from inverter 52, and inverted value /B is supplied from inverter 54. Data /A and /B are transferred through corresponding global write data line pair WGLA1 and WGLB1 and stored in corresponding unit operator cell UOE1.
In data path unit block DPUB2, multiplexers 56 and 57 select carry CY transferred from register 50. Accordingly, data CY is transferred through corresponding global write data line pair WGLA2 and WGLB2 and stored in corresponding unit operator cell UOE2.
In data path unit block DPUB3, multiplexers 56 and 57 select inverted value /CY of carry CY transferred from register 50. Inverted value /CY of carry CY is supplied from inverters 53 and 55. Accordingly, data CY is transferred through corresponding global write data line pair WGLA3 and WGLB3 and stored in corresponding unit operator cell UOE3.
Carry CY transmitted from register 50 is a carry that is produced by performing the operational processing in the preceding cycle and based on the one-bit lower-order addition result, and is equivalent to input carry Cin in the current cycle. Carry CY is written in and read from the unit operator cell again, whereby a new carry can be produced with the carry produced in the preceding cycle used as input carry Cin (=CY_old).
In the operator cell array, dummy cell selection signal DCLB is applied to dummy cell DMC, and two series-connected dummy transistors (DTB0 and DTB1) are selected. The arrangement of the read and write word lines for unit operator cells UOE0 to UOE3 is similar to that of the first embodiment, the data transmitted to corresponding global write data lines WGLA and WGLB are written in and read from unit operator cells UOE0 to UOE3.
In read port selection circuit 36, port switching signal PRMXB is set in the state of selecting port B, and the output signals of sense amplifiers SA0 to SA3 indicate the AND operational results of data stored in corresponding unit operator cells UOE0 to UOE3. That is, sense amplifier SA0 produces data A·B, and sense amplifier SA1 produces data (/A·/B). Sense amplifier SA2 supplies data CY·CY=CY, and sense amplifier SA3 produces data (/CY·/CY)=/CY.
That is, sense amplifiers SA2 and SA3 produce the values according to the intermediate carry CY produced in the preceding cycle. The output bits of sense amplifiers SA2 and SA3 are applied through buffers BFF2 and BFF3 to a sum producing data path operation unit group arranged adjacently, and the sum producing data path operation unit group produces the sum with the carry produced in the preceding cycle, that is, the carry produced through the operation on the one-bit lower-order bits being used as input carry Cin (=CY_old).
Output bits P0 and P2 are applied to AND/OR composite gate AOCT0 from the main amplifiers (not shown) that are disposed for sense amplifiers SA0 to SA2.
Accordingly, carry CY expressed by the following equation is produced from AND/OR composite gate AOCT0:
wherein carry CY_old is an intermediate carry produced in the preceding cycle and becomes input carry (Cin) in the current cycle.
As is clear from the logic table shown in
In the operator cell array, dummy cell selection signal DCLB is applied to dummy cell DMC to select the series-connected dummy transistors. Similarly to the first embodiment, for unit operator cells UOE4 to UOE7, the read word lines and write word lines are sequentially selected to perform the data write and read to two storage nodes (SNA and SNB).
In data path unit block DPLTB4 of data path operation unit group 44, multiplexer (MUXA) 56 selects input data DINA (=A), and multiplexer (MUXB) 57 selects inverted value /B of input data DINB (=B). Inverted value /B is produced from inverter 54. Accordingly, data A and /B are transmitted to corresponding global write data lines WGLA4 and WGLB4 and stored in corresponding unit operator cell UOE4.
In data path unit block DPUB5, multiplexer 56 selects inverted value /A of input data A, and multiplexer 57 selects input data B. Inverted value /A is supplied from inverter 52. Accordingly, data /A and B are transmitted to corresponding global write data lines WGLA5 and WGLB5 and stored in corresponding unit operator cell UOE5.
In data path unit block DPUB6, multiplexers 56 and 57 select inverted values /A and /B of input data A and B, respectively, which are applied from inverters 52 and 54. Accordingly, data /A and /B are transmitted to corresponding global write data lines WGLA6 and WGLB6 and stored in corresponding unit operator cell UOE6.
In data path unit block DPUB7, multiplexers 56 and 57 select input data A and B. Accordingly, the data on corresponding global write data lines WGLA7 and WGLB7 are data A and B and are stored in corresponding unit operator cell UOE7.
In the data reading, in read port selection circuit 36, port B is selected and the read bit line (RBLB) of port B is selected. Accordingly, sense amplifiers SA4 to SA7 produce the AND operation result of two data stored in the corresponding unit operator cells, respectively. The output data of sense amplifiers SA4 to SA7 are transmitted through the main amplifiers (not shown) to combination logic operational circuit 26.
In combination logic operational circuit 26, two-input OR gates OG0 and OG10 are selected. Two-input OR gate OG0 produces the logical sum operational result of output signals P<4> and P<5> of the main amplifiers arranged for sense amplifiers SA4 and SA5. Two-input OR gate OG10 produces the logical sum operation result of output signals P<6> and P<7> of the main amplifiers provided for sense amplifiers SA6 and SA7. The output bits of two-input OR gates OG0 and OG10 and intermediate carries CY_old and /CY_old produced in the preceding cycle from the corresponding carry producing unit are applied to AND/OR composite gate AOCT1 arranged in the data path, and the output data of AND/OR composite gate AOCT1 is supplied through register 50 and the buffer (not shown). The output from buffer (51) is equal to sum SUM, and sum SUM is expressed by the following equation.
SUM=(A·(/B)+(/A)·(B))·(/CY_old)+(A·B+(/A)·(/B))·CY_old
Referring to the logical value table of sum SUM shown in
As described above, in the case where the one-bit serial addition is performed, the operational processing is performed with the carry produced by the carry producing unit being used as the input carry, which allows sum SUM to be produced as in the XOR operation (or XNOR operation).
In the case where the data bit is written and read, a time delay until decision of carry bit CY is caused because carry bit CY produced in the preceding cycle is used as input carry bit CY_old. However, if carry bit CY is made definite in a half clock cycle, the addition processing can be performed in the pipeline manner in the bit serial manner with the time delay of the half clock cycle.
The four unit operator cells are used to produce carry CY, and the four unit operator cells are used to produce sum SUM. Accordingly, 128 pairs of data can concurrently be processed when the entry has the bit width of 1024 bits, and 128 data words can be processed in 2·m cycles when the data word has the bit width of m bit (one clock cycle is required to perform each of the data writing and reading). In the case where m-bit addition is performed in one clock cycle with an m-bit adder of a usual hardware, 128 clock cycles are required to process the 128 data. In the fourth embodiment, when the data has the bit width of 32 bits, the addition processing can be performed at higher speed. The number of sets of data processed in parallel can be increased by increasing the bit width of the entry, and the addition processing can be performed at higher speed.
(Configuration of Bit Serial Subtracter)
In data path unit block DPUB0, multiplexer (MUXA) 56 selects inverted value /A supplied from inverter 52 receiving input data DINA (=A), and multiplexer (MUXB) 57 selects input data DINB (=B). Accordingly, data /A and B are transmitted to corresponding global write data lines WGLA0 and WGLB0 and stored in corresponding unit operator cell UOE0.
In data path unit block DPUB1, multiplexer 56 selects input data A, and multiplexer 57 selects inverted value /B of input data B supplied from inverter 54. Accordingly, data A and /B are transmitted to corresponding global write data lines WGLA1 and WGLB1 and are stored in corresponding unit operator cell UOE1.
In data path unit block DPUB2, multiplexers 56 and 57 select the data transmitted from register 50. Because register 50 transfers borrow BR in the preceding cycle, borrows BR (=BR_old) and BR are transmitted to corresponding global write data lines WGLA2 and WGLB2 and stored in corresponding unit operator cell UOE2.
In data path unit block DPUB3, multiplexers 56 and 57 select the inverted value, supplied from inverters 53 and 55, of the value stored in corresponding registers 50. Accordingly, inverted values /BR (=BR_old) and /BR of borrow BR are transmitted to corresponding global write data lines WGLA3 and WGLB3 and stored in corresponding unit operator cell UOE3.
In combination logic operational circuit 26, AND/OR composite gate AOCT0 is selected and buffers BFF2 and BFF3 are selected. In AND/OR composite gate AOCT0, output bit P<1> of the main amplifier that is provided for sense amplifier SA1 is applied to a negative input of the AND gate, and output bit P<2> of the main amplifier that is provided for sense amplifier SA2 is applied to a non-inverting input of the AND gate. The logical sum operation is performed on the output bit of the AND gate and output bit P<0> of the main amplifier that is provided for sense amplifier SA0. Accordingly, the data supplied from composite gate AOCT0 through register 50 is expressed as follows:
(/A·B)+/((A)·(/B))·BR_old
As can be seen from the logical value relationship of output borrow BRout shown in
Accordingly, data BR supplied from register 50 shown in
Borrows BR·BR=BR and /BR·/BR=/BR from buffers BFF2 and BFF3 are transmitted as the borrow of the preceding cycle, that is, input borrows BR_old and /BR_old to adjacent data path operation unit group constituting the subtracter.
(Configuration of One-Bit Serial Subtracter)
The configurations of unit operator cells UOE4 to UOE7 are similar to those of the first embodiment, the data on the corresponding global write data lines are written in parallel in two storage nodes (SNA and SNB), and the data stored in series-connected storage nodes SNA and SNB are read. Accordingly, in performing the subtraction, the output signal of each sense amplifier is the AND operation result of the data stored in the corresponding unit operator cell.
In data path unit block DPUB4 of data path operation unit block 44, multiplexer (MUXA) 56 selects input data DINA (=A), and multiplexer (MUXB) 57 selects inverted value /B of input data DINB (=B), supplied from inverter 54. Accordingly, data A and /B are transmitted to corresponding global write data lines WGLA4 and WGLB4 and stored in corresponding unit operator cell UOE4.
In data path unit block DPUB5, multiplexer 56 selects inverted value /A of input data A supplied from inverter 52, and multiplexer 57 selects input data B. Accordingly, data /A and B are transmitted to corresponding global write data lines WGLA5 and WGLB5 and stored in corresponding unit operator cell UOE5.
In data path unit block DPUB6, multiplexers 56 and 57 select inverted values /A and /B of input data A and B, which are supplied from inverters 52 and 54, respectively. Accordingly, data /A and /B are transmitted to corresponding global write data lines WGLA6 and WGLB6 and stored in corresponding unit operator cell UOE6.
In data path unit block DPUB7, multiplexers 56 and 57 select input data A and B, and data A and B are transmitted to corresponding global write data lines WGLA7 and WGLA7 and stored in corresponding unit operator cell UOE7.
In combination logic operational circuit 28, two-input OR gates OG0 and OG10 are selected. Two-input OR gate OG0 receives the output signals of the main amplifiers arranged for sense amplifiers SA4 and SA5. Two-input OR gate OG10 receives the output signals of the main amplifiers arranged for sense amplifiers SA6 and SA7.
The output signals of sense amplifiers SA4 to SA7 indicate the AND operation result of the values stored in corresponding unit operator cells UOE4 to UOE7, and two-input OR gate OG0 produces data (A·/B)+(/A·B), and two-input OR gate OG10 produces data (/A·/B)+(A·B).
In the reading path of the data path, AND/OR composite gate AOCT1 is selected and the output signals of two-input OR gates OG0 and OG10 are applied to AND/OR composite gate AOCT1. AND/OR composite gate AOCT1 receives input borrows BR_old and /BR_old corresponding to bits P<2> and P<3> from the borrow producing section shown in
(A·(/B)+(/A)·(B))·/BR_old+((A·B)+(/A)·(/B)·BR_old.
Referring to the logical value table of subtraction value DIFF shown in
In the case of input borrow BRin (=BR_old) being “1”, as is clear from the logical value table shown in
In performing the subtraction in the one-bit serial manner, borrow BR_old produced in the preceding cycle is transferred with delay by one clock cycle through the unit operator cell, so that the subtraction processing can be performed with the borrow produced in the preceding cycle being used as input borrow.
In performing the bit serial addition/subtraction, the input carry is set at “0” when the operation is performed on the least significant bit. This is implemented by resetting the value stored in register 50 to “0”. Although the time until the borrow is made definite is required, the subtraction processing can be performed in the pipeline manner in the bit serial fashion as in the addition.
In the fourth embodiment, the addition and subtraction can be performed in the bit serial manner. In the case where one entry includes 512 bit line pairs, the addition and subtraction can be performed in the bit serial manner and in data parallel for 64 data. When the data has the bit width of 32 bits, the addition and subtraction can be performed on the set of 64 data in 32 clock cycles. Accordingly, the processing time can be greatly shortened compared with the 64 clock cycles that is necessary for sequentially performing the addition processing and subtraction processing on the set of data to in data serial and in bit parallel. It is only necessary to internally write and read the data in and from the unit operator cells, so that the addition and subtraction can be implemented at high speed.
(Modification)
The combination logic operational circuit and the data path (not shown) are arranged outside operator cell array 20. The configurations of the data path and combination logic operational circuit are identical to those shown in
In performing the bit serial addition, the connections of the data propagation routes of the data path and the combination logic operational circuit are established as the manner shown in
In the data path, the carry (input carry) stored in the carry producing register is written in next entry ERY1 along with next upper data bits A<1> and B<1> and then read therefrom. Then the bit serial addition described with reference to
Therefore, the one-bit addition can be performed at high speed in the bit serial manner. The malfunction or defect caused by the continuous use of the local region can be avoided because the regions used for the operation are disposed being dispersed in the operator cell array.
It is merely required to arrange the carry producing unit and the sum producing unit in the operator cell array in correspondence to the sets of data. Entries ERY0 to ERYn may be arranged being dispersed over the different operator cell sub-array blocks.
In the configuration shown in
The entire configuration of the semiconductor signal processing device according to the fourth embodiment and configuration of the control circuit can be formed similar to that of the first embodiment.
According to the fourth embodiment of the present invention, the data propagation routes of the operator cell array, combination logic operational circuit and data path are switched to perform the bit slice operation, and the addition processing and subtraction processing is internally performed to perform the high-speed bit slice operational processing, so that the bit slice operation cycle can be largely reduced. In the case where the bit width of the operation target data is changed, it is merely required to change the operation cycle according to the data bit width. Thus, the semiconductor signal processing device according to the fourth embodiment can deal with a plurality of kinds of data bit widths without changing the internal configuration.
[Fifth Embodiment]
For common source line SLC, switching circuits SWT0, SWT1, . . . are provided corresponding to B-port read bit lines RBLB0 and RBLB1, respectively. Switching circuits SWT0, SWT1, . . . selectively connect corresponding B-port read bit lines RBLB0 and RBLB1 to common source line SLC in response to a mode setting signal MDSEL. In this operation, in response to port selection signal PRMX, port connection circuits PRSW0 and PRSW1 connect A-port bit lines RBLA0, RBLA1, to read bit lines RBL0, RBL1, . . . for corresponding sense amplifiers SA0, SA1, . . . .
In
In the voltage applying manner shown in
Here, the connection manner between B-port read bit line RBLB and the common source line is arbitrary in
A-port read word line RWLA is maintained in the L level of the non-selected state, while B-port read word line RWLB is driven to the H level of the selected state. B-port read bit line RBLB is connected to common source line SLC through switching circuit (SWT). A voltage at the same level is applied to common source line SLC and to source line SL. Accordingly, in the voltage applying manner shown in
As shown in
In
Mode setting circuit 352 sets mode setting signal MDSEL and port selection signal PRMX at the specified state according to operational processing instruction OPLOG applied from command decoder 350. That is, in the case where operation manipulation instruction OPLOG instructs execution of the one-bit read, mode setting circuit 352 sets port selection signal PRMX at the state of connecting port A, that is, read bit line RBLA to the sense amplifier. Mode setting circuit 352 sets mode setting signal MDSEL at the mode of connecting common source line SLC and B-port bit line RBLB with each other.
In the case where operational processing instruction OPLOG instructs a normal operational processing, mode setting circuit 352 sets port selection signal PRMX according to the specified operational processing such that one of port A and port B is connected to the sense amplifier, and mode setting circuit 352 maintains mode selection signal MDSEL in the non-selected state (B port is selected during the operational processing except for the NOT operation).
Read word line control circuit 354 produces dummy cell selection enable signals DCLAEN and DCLBEN and read word line enable signals RWLAEN and RWLBEN according to operational processing instruction OPLOG. In the case where one-bit data read is specified according to processing contents instructed by operational processing instruction OPLOG, read word line control circuit 354 activates dummy cell selection enable signal DCLAEN to maintain dummy cell selection enable signal DCLBEN in the inactive state. Read word line control circuit 354 drives one of read word line enable signals RWLAEN and RWLBEN to the selected state according to port indication information included in operational processing instruction OPLOG. Therefore, one-bit read mode is specified, and the connection manner can be set when operational processing instruction OPLOG instructs the mode in which each bit of each two-bit information included in the unit operator cells is read to the outside. In the one-bit read mode, the combination logic circuit and the data path perform inversion or non-inversion processing on the output signal of the sense amplifier and output the inverted or non-inverted signal.
In the case where a normal operational processing is performed, according to operational contents specified by operational processing instruction OPLOG, read word line control circuit 354 activates read word line enable signal RWLAEN and read word line enable signals RWLAEN and RWLBEN and selectively activates dummy cell selection enable signals DCLAEN and DCLBEN. Therefore, in performing a combination logic operation or an arithmetic operation, B port can be selected to perform the operation of the two data stored in the unit operator cell.
The entire configuration of the semiconductor signal processing device according to the fifth embodiment is similar to that of the first embodiment shown in
According to the fifth embodiment of the present invention, data of the storage nodes of the SOI transistors constituting the unit operator cell are individually read out, so that the semiconductor signal processing device can be used as a memory device, in addition to the combination logic operation and arithmetic operation functions.
[Sixth Embodiment]
Other configuration of the unit operator cell shown in
In the configuration of the unit operator cell shown in
Outside the P-type transistor forming region, high-concentration N-type regions 3d and 3e are arranged in alignment along the Y-direction, and a P-type region 4c is arranged between N-type regions 3d and 3e. P-type region 4c is electrically connected to P-type region 1f. N-type region 3d is electrically connected to N-type region 3b through the N-type region extending in the X-direction, and is electrically connected to first metal interconnection line 7b through an intermediate interconnect and a contact/via 8d.
N-type region 3e is electrically connected to first metal interconnection line 7a through a contact/via 8f and an intermediate interconnect. P-type region 1e is electrically connected through a contact/via 8g and an intermediate interconnect to a first metal interconnection line 7e that continuously extends in the Y-direction. SOI transistor PQ3 is formed by P-type regions 1e and if and N-type region 2c, and SOI transistor NQ3 is formed by N-type regions 3d and 3e and P-type region 4c. A source/drain node of SOI transistor PQ3 is connected to the body region (P-type region 4c) of SOI transistor NQ3 by P-type regions 1f and 4c. Input data DINC is transmitted through first layer metal interconnection line 7e.
In
As shown in
An AND gate 408 is provided for multiplexer 57 and receives the output signal of inverter 404 and external input data bit DINB<0>. An inverter 410 is provided for multiplexer 56 and inverts data C (corresponding to carry/borrow). The connection paths of multiplexers 56, 57, and 400 are set in accordance with switching control signals MXAS and MXBS. Other configuration of data path unit block BPUB0 is similar to that of data path unit block BPUB0 in the data path shown in
The configuration similar to that of data path unit block DPUB0 is provided in data path unit block DPUB1, but register 50 is not provided in data path unit block DPUB1.
Data path unit blocks DPUB0 and DPUB1 produce internal write data to drive global write data line sets WGLS0 and WGLS1, and a specified operational processing is performed.
The configuration of the combination logic operational circuit is similar to that of the first embodiment (see
Referring to
In data path unit block DPUB1, multiplexer 400 selects carry CY supplied from register 50, and multiplexer 57 selects input data DINB. Multiplexer 56 selects input data A. Accordingly, the data CY_old, B and A are transferred to corresponding global write data lines WGLC1, WGLB1 and WGLA1 and stored in storage nodes SNC, SNB, and SNA of corresponding unit operator cell UOE1.
In memory cell array 32, dummy cell selection signal DCLB is applied to dummy cell DMC, and two series-connected dummy cell transistors (DTB0 and DTB1) are connected to complementary read bit lines ZRBL0 and ZRBL1.
In read port selection circuit 36, port B is selected, and read bit lines RBLB0 and RBLB1 are connected to corresponding sense amplifiers SA0 and SA1 of sense amplifier band 38.
In combination logic operational circuit 26, there is selected two-input OR gate OG1 receiving the output signals of the main amplifiers provided for sense amplifiers SA0 and SA1 in main amplifier circuit 24. Sense amplifiers SA0 and SA1 produce operation results of (SNB+SNC)·SNA, respectively. Here, the storage node and the data stored therein are designated by the same reference symbol.
Accordingly, carry CY transmitted from two-input OR gate OG1 through register 50 is represented by (A+B)·CY_old+(CY_old+B)·A.
According to a formula of Boolean algebra, the above-described expression can be transformed into the following equation because of A+A=A:
CY=(A+B)·CY_old+A·B
As can be seen from the logical value table of carry CY shown in
In data path unit block DPUB3, multiplexer (MUXC) 400 selects the output signal of AND gate 406. AND gate 406 receives input data A and inverted value /B of input data B supplied from inverter 54. Multiplexer 57 receives the output signal of AND gate 408 receiving inverted value /A of input data A received from inverter 404 and input data B. Multiplexer (MUXA) 56 receives inverted value /CY of carry CY supplied from inverter 410. Accordingly, data A·/B, /A·B, and /CY_old are transmitted to global write data lines WGLC3, WGLB3, and WGLA3 and stored in storage nodes SNC, SNB, and SNA of unit operator cell UOE3.
In data path unit block DPUB4, multiplexer 400 selects the output signal of AND gate 411 receiving input data A and B. Multiplexer (MUXB) 57 selects the output signal of AND gate 412 receiving inverted value /B of input data B from inverter 54 and inverted value /CY of carry CY from inverter 404. Multiplexer (MUXA) 56 selects carry CY. Accordingly, data A·B, /A·B, and CY_old are transmitted to corresponding global write data lines WGLC4, WGLB4, and WGLA4 and stored in storage nodes SNC, SNB, and SNA of corresponding unit operator cell UOE4.
Similarly to the production of the carry, dummy cell selection signal DCLB is applied to dummy cell DMC. In read port selection circuit 36, port B is selected, and read bit lines RBLB3 and RBLB4 are connected to corresponding sense amplifiers SA3 and SA4 in sense amplifier band 38. Accordingly, sense amplifier SA3 produces data (A·/B+/A·B)·/CY_old according to the data stored in unit operator cell UOE3, and sense amplifier SA4 produces data (A·B+/A·/B)·CY_old.
Sense amplifiers SA3 and SA4 apply OR/AND operation results to two-input OR gate OG1 of combination logic operational circuit 26 through the corresponding main amplifiers included in main amplifier circuit 24. Data SUM supplied to the outside of the device through register 50 from two-input OR gate OG1 is expressed as follows:
SUM=((A·/B)+(/A·B))·/CY_old+((A·B)+(/A·/B))·CY_old
The above-described equation of sum SUM is identical to the equation of sum SUM shown in
Using the configuration of the adder shown in
As shown in
(Modification)
The configurations of the read port selection circuit, sense amplifier band, and main amplifier circuit that are provided for operator cell array 20 are similar to those in the first embodiment, and the configuration of data path 28 is similar to that shown in
In the configuration shown in
Similarly, carries CY<0> to CY<m−1> are applied together with input data A<0>, B<0> to A<m>, and B<m> to two-cell/sum producing units SUG1 to SUGm from two-cell/carry producing units CYG0 to CYG(m−1) at the one-bit lower-order sides. Sum bits S<0> to S<m> are produced from two-cell/sum producing units SUG0 to SUGm, and carry CY is supplied from final-stage two-cell/carry producing unit CYGm.
The input carry is set at “0” for two-cell/carry producing unit CYG0 and two-cell/sum producing unit SUG0 each at the least significant bit location.
When an addition start instruction is supplied (Step SP10), the control circuit retains input data A and B of the operation target in the input register (not shown) such that input data A and B are supplied in bit parallel to the data path as needed (Step SP11).
In the data path provided for two-cell/carry producing units CYG0 to CYGm, the path is set according to the addition start instruction such that the output carry from the preceding-stage (one-bit lower-order side) is selected (Step SP12). In the arrangement shown in
In the addition operation, carry CY<0> of two-cell/carry producing unit CYG0 provided for the least significant bit is made definite according to input data bits A<0> and B<0>. In the next access cycle, two-cell/carry producing unit CYG1 produces corresponding carry CY<1> according to produced and decided carry CY<0> and data bits A<1> and B<1>. Carry CY<1> produced by two-cell/carry producing unit CYG1 is stored in the corresponding register. The carry sequentially becomes the definite state starting from the lower-order bit side. All carries CY<0> to CY<m> are set at the definite state by repeating the carry producing operation (m+1) times, and definite carries CY<0> to CY<m> are stored in corresponding registers (50).
After the carry producing manipulation is repeated (m+1) times, two-cell/sum producing units SUG0 to SUGm perform the sum producing processing according to the carries applied from the one-bit lower-order sides and input data bits A<0>, B<0> to A<m>, and B<m> (
In the addition operational processing, all the carries from the lower-order bit sides are definite, the one-bit addition is concurrently performed on bits A<0>, B<0> to A<m>, and B<m>, and sum bits S<0> to S<m> indicating the addition result are produced along with final carry CY (Step SP14). Then, the addition result is output (Step SP15).
The full addition can be performed on the (m+1)-bit data by repeating the addition operation (m+2) times to one entry. The value of sum bit SUM<i> is decided in each clock cycle for sum SUM from the lower-order bit side by concurrently operating sum producing units SUG and carry producing units CYG, highest-order sum bit SUM<m> can concurrently be produced in producing final carry CY, and the addition result can be obtained in (m+1) cycles
Even if the bit parallel addition is performed in a unit of entry in the operator cell array, the bit parallel addition can be performed only by switching the data bus connection routes. The addition is performed while switching the entries, so that the localized access concentration can be avoided to prevent the malfunction.
In the configuration shown in
Thus, according to the sixth embodiment of the present invention, three storage transistors are arranged in one unit operator cell, the OR and AND composite operation can be performed on the storage data, and the addition and subtraction operational processing can be performed at high speed using the small number of unit operator cells.
[Seventh Embodiment]
In order to select SOI transistor PQ2 by using write word line WWLB, high-concentration P-type regions 1g and 1h are arranged in alignment with P-type region 4b in the Y-direction. An N-type region 2d is disposed between P-type regions 1g and 1h. A gate electrode interconnection line 5e extending in the X-direction is provided on N-type region 2d. Gate electrode interconnection line 5e is electrically connected to first metal interconnection line 6e of an upper layer (contact portion is not shown).
A high-concentration P-type region 1i extending in the X-direction is provided adjacent to P-type region 1h, and is electrically connected to upper-layer second metal interconnection line 7d through a contact/via 8h. That is, unlike the layout shown in
Other arrangement of the planar layout shown in
In the case where three data storage SOI transistors are arranged in unit operator cell UOE, the data write can be performed separately to storage node SNB and storage nodes SNA and SNC without largely changing the layout.
In the case where unit operator cell shown in
Similarly to the third embodiment, pre-charging transistor PQ0 and amplifying circuit AMP that amplifies the search result are provided for match line ML. The configurations of data path 28 and combination logic operational circuit 26 are similar to those shown in
In the seventh embodiment, in operator cell array 20, data can be individually written in storage nodes SNA and SNB of the unit operator cell in response to the signals on write word lines WWLA and WWLB. For example, in performing the searching operation, data bit A can be set at the “don't-care” state by storing flag FLG in storage node SNC. When flag FLG is set at “1”, operational result data A·(B+FLG) and /A·(/B+FLG) supplied from the sense amplifiers assume A and /A, and the output signal of two-input OR gate OG0 assumes “1 (=A+/A)”. When flag FLG is set at “0”, output data of sense amplifiers SA0 and SA1 assume data A·B and /A·/B, the output signal of two-input OR gate OG0 becomes data (A·B+/A·/B) to indicate the match result of data A and B. Accordingly, the search can be performed while data bit A is masked with flag FLG. The searching operation will specifically be described.
An instruction to store the search target data in the operator cell array is supplied according to an operation start instruction (Step SP20). The data path is set according to the search target data storage instruction (Step SP21). Inverted value /B of data B is selected in data path unit block DPUB0, and the path is set so as to select data B (=DINB) in data path unit block DPUB 1. After the setting of the propagation path, write word line WWLB is selected, and the search target data is written in storage nodes (body region) SNB of SOI transistors NQ2 of corresponding unit operator cells UOE0 and UOE1 (Step SP22).
Then, a determination whether all the search target data are written is made (Step SP23). When all the search target data are not written yet, the entry address is updated (Step SP24), and write word line WWLB of selected entry is selected to write the next search target data.
When a determination that all the search target data are written is made in Step SP23, the semiconductor signal processing device waits for a search instruction supplied externally (Step SP24).
When the search instruction is supplied, the data path and the logical path (the data propagation path of the combination logic operational circuit) are set, and the entry address is initialized (Step SP25).
In the data path, the transfer paths are set for search data A (=DINA) and flag FLG. The propagation path is set for data A such that non-inverted data A is transferred to unit operator cell (UOE0) in which data B is stored while inverted data /A is transferred to unit operator cell (UOE1) in which data /B is stored. The propagation path is set for flag FLG such that the non-inverted value of flag FLG is transferred to storage node SNC.
The search data and flag are written in and read from the specified entry (Step SP26). Write word line WWLA is driven to the selected state to write the data and flag in storage nodes SNA and SNC. Accordingly, to unit operator cell UE0 in which data B is stored, data A is stored at storage node SNA and flag FLG is stored at storage node SNC. For unit operator cell UE1 in which inverted data /B is stored, data A is written in storage node SNA and flag FLG is stored at storage node SNC. Then, read word lines RWLA and WRLB are concurrently driven to the selected state to read the data stored in unit operator cells UE0 and UE1. In the read port selection circuit (not shown), B port is selected, and sense amplifiers produce data A·(FLG+B) and /A·(FLG+/B), which in turn are transmitted to corresponding two-input OR gate OG0 through the corresponding main amplifiers.
When flag FLG is “1”, the output data of two-input OR gate OG0 becomes A+/A=“1”, and the output signal (data bit) of two-input OR gate OG0 is inverted by inverter 420, and the output signal of inverter 420 becomes “0” indicating the match state. On the other hand, when flag FLG is “0”, the output data of two-input OR gate OG0 becomes A·B+/A·/B. In the case where data A and B are equal to each other, the output signal of two-input OR gate OG0 becomes “1” (H level), and accordingly, the output signal of inverter 420 becomes “0” (L level). Accordingly, the search data (bit) for which flag FLG is set at “1” has no influence on the potential at match line ML. In the case where data A and B are not matched with each other, the output signal of two-input OR gate becomes “0”, the output signal of inverter 420 becomes “1”, and corresponding discharging transistor TQ1 turns into the on-state to discharge match line ML. Accordingly, match line ML is discharged when any bit of search data A (DINA<m:0>) is not matched with that of search target data B(DINB<m:0>).
Therefore, the match state is indicated when match line ML is maintained at the pre-charged state, and the mismatch state is indicated when match line ML is discharged. The potential at match line ML is amplified by amplifying circuit AMP, and search result indication SRSLT is set at “0” or “1”, whereby the match/mismatch between search data A and search target data B is identified (Step SP27).
A determination whether the search is made to the final entry according to the address counter when the mismatch is detected (Step SP29). When the final entry is not searched yet, the entry address is updated (Step SP30), and the search data and flag are written and read in Step SP26.
When a determination that the final entry has been searched and match is not detected is made, necessary processing for mismatch is performed (Step SP31). The processing for the generated mismatch is appropriately defined depending on an application of the semiconductor integrated device. When match is detected in Step SP27, the matching address (entry address) at that time is retained and supplied externally (Step SP28). Here, the entry address (address index) is supplied externally, and the necessary information may be read according to the externally supplied entry address, or predetermined processing may be performed irrespective of the value of the entry address when the match is detected.
As shown in
The entire configuration of the semiconductor signal processing device according to the seventh embodiment of the present invention is similar to that of the third embodiment, and the ternary CAM behavior can be implemented with address counter 170 shown in
Referring to
For example, the semiconductor signal processing device according to the seventh embodiment can be applied to a next-address search for a data packet of an IP address (Internet Protocol address) in data communication, and character string search can be performed in a pay load.
[Eighth Embodiment]
Unit operator cell UOE having three storage nodes SNA, SNB, and SNC of the fifth embodiment is used in AND operation array OARA. Write ports WA, WB, and WC may concurrently be driven to the selected state, or write port WB may be driven to the selected state independently of write ports WA and WC as in the seventh embodiment. Write ports WA, WB, and WC are write port WPRT that is connected to storage nodes SNA, SNB, and SNC. In the AND operation array, data bit “0” is always transmitted to one of write ports WB and WC or the same data is transmitted to write ports WC and WB.
In sense amplifier band 38 of AND operation array OARA, sense amplifier is provided for each bit line pair of memory cell array 32. In AND operation array OARA, because the operating manner in the AND operational processing is similar to that of the first embodiment, read port B (RPRPB) is selected, and the logical product operation (for example, A·B) is performed to the data bits stored in the unit operator cells.
On the other hand, in full addition array OARF, the carry producing unit (shown as the carry in
Unit operator cells UOEk and UOE(k+1) are arranged each for producing the sum in each of two data path unit blocks DPUBa and DPUBb included in one full addition operation unit MUB1. Data path unit blocks DPUBa and DPUBb in an adjacent full addition operation unit MUB(1+1) produce the carry for the sum producing section constituted by upper-bit full addition operation unit MUB(1+2). Carry C for full addition operation unit MUB1 is transferred from the lower-bit location (not shown), and the output carry is produced according to input data bits DINA<1> and DINB<1>.
Data path unit blocks DPUBa and DPUBb shown in
In each of write data path unit blocks DPUBa and DPUBb, inverters 456, 457, and 458 are provided for the output value of temporary register 450 of upper-bit full addition operation unit MUB(1+2). The output data bits of inverters 456, 457, and 458 are applied to multiplexers 400, 57, and 56, respectively. Accordingly, the shifted-down data bit can be transferred from temporary register 450 to corresponding bit operator cells UOEk and/or UOE(k+1) by using full addition operation unit MUB1.
Because other configurations of data path unit blocks DPUBa and DPUBb are similar to those of the data path unit block shown in
Using the full addition operation unit in the data bus shown in
In a normal parallel multiplier, a multiplication cell array is provided to produce each partial product, and such operational processing is implemented using AND operation array OARA and full addition array OARF shown in
As shown in
For the AND operation, the non-inverted data of the input data A and B are selected such that the AND operation is performed in the full addition operation unit in a corresponding data path (not shown). Multiplicand bits X<0> to X<3> are applied as input data A to AND cells LPC4 to LPC7, respectively. Multiplier bit Y<0> is applied as write data B to AND cells LPC4 to LPC7. Data “0” is applied as data A to AND cells LPC0 to LPC3. Data “0” may be applied as external write data B to AND cells LPC0 to LPC3.
In each of AND cells LPC4 to LPC7, the AND operational result of multiplicand bits X<0> to X<3> and multiplier bit Y<0> is produced by the corresponding sense amplifier and stored in register 50 of the corresponding data path unit block. On the other hand, the AND operational result becomes “0” in each of AND cells LPC0 to LPC3, and data “0” is stored in corresponding register 50. Thus, each bit of partial product PP1 is produced as shown in
Then, as shown in
Similarly to the AND cell, full addition (FADD) cells FDC0 to FDC7 are used in full addition array OARF. Full addition cell FADD includes the carry producing unit operator cell and the sum producing unit operator cell in order to perform the one-bit full addition. In full addition cell FADD, addition operation unit MUB shown in FIG. 73 is provided for each full addition cell in order to produce the carry and sum. The unit block of the data path is shared by the AND cell and the full addition cell, and therefore, AND cells LPC0 to LPC7 and full addition (FADD) cells FDC0 to FDC7 are arranged in alignment in the column direction.
For FADD cells FDC0 to FDC7, the data stored in one-bit upper side temporary register 450 is selected as write data B, and the output data of register 50 included in the corresponding data path unit block is selected as write data A. The shift down to the one-bit lower side direction realizes the bit location alignment in addition of the partial products.
Then, in full addition array OARF, the access to FADD (full addition) cells FDC0 to FDC7 is made to produce the carry and sum of the full addition (see sixth embodiment). Therefore, as shown in
Then, as shown in
In AND cells LPC0 to LPC3, input data A is “0”, and the data “0” is stored in corresponding register 50.
Then, as shown in
As the stored data of registers are shown in
Then, as shown in
Then, as shown in
The access to full addition array OARF is made again, and the full addition operation is performed in FADD cells FDC0 to FDC7 (the carry and sum are generated). As a result, the final addition result of partial products PP0 to PP3 is stored in registers 50 corresponding to FADD cells FDC1 to FDC7. Multiplication bits P<0> to P<7> of the multiplication result of data A and B can be produced by taking out the output data externally from registers 50 of FADD cells FDC1 to FDC7 through the buffers. The data stored in register 50 corresponding to FADD cell FDC0 is not used as the external product bit. Therefore, the four-bit multiplication can be performed in five clock cycles.
The three-input unit operator cell is used in the operator cell array, and four unit operator cells are provided in each of AND cells and FADD cells FDC0 to FDC7. It is not necessary to provide the multiplication cell that performs the AND operation and addition and the carry shift in each bit of each partial product, and the multiplication of the multi-bit data can be performed with the small occupation area.
The semiconductor signal processing device waits for the multiplication instruction (Step SP40). When the multiplication is instructed, the multiplication data X and Y are retained (Step SP41).
Then, a count value i of the counter is set to zero, and the setting is performed in data path (28) such that the AND operation is performed. In such case, multiplexers 56 and 57 shown in
Multiplicand data X and multiplier bit Y<i> are supplied, the access to the AND operation array is made to produce the AND operation result (Step SP43).
A determination whether the count value i of the counter is zero is made (Step SP44). When the count value i of the counter is zero, because only the first partial product is formed, the count value i of the counter is incremented by one (Step SP45), and the processing is performed from Step SP43.
When the count value i of the counter is not zero in Step SP44, at least the two partial products are produced, and the full addition operation is performed. In this case, in each data path unit block, multiplexers 452 and 56 select the data stored in register (50) as write data A, and the bit value from upper-bit side temporary register (450) is selected as write data B (by multiplexer 57). When the path of the data path and logical path (combination logic operational circuit) is set for the purpose of the full addition, the access to the full addition array is made, and the full addition operation is performed to produce the carry and the sum (Step SP46).
A determination whether the count value i of the counter reaches a maximum value MAX is made after the full addition operation is completed (Step SP47). When the count value i of the counter reaches maximum value MAX, the full addition of the partial products is performed to the most significant bit Y<MAX> of multiplier Y, and the full addition result is output as the multiplication result (Step SP48).
When the count value i of the counter does not reach maximum value MAX, the process returns to Step SP45, the count value i of the counter is incremented by one, and the operational processing is performed again from Step SP43.
Accordingly, the two partial products are produced first, the full addition of the partial products is performed, and then the AND operation and full addition operation are repeatedly performed. In the case where the multiplication is performed on the data of the N-bit width, the multiplication result can be obtained in (2·N+1) clock cycles.
Thus, to the data path, latch circuit 472 always supplies multiplicand data X<m:0> to the write target operation unit, and the multiplicand data can be supplied through bit-by-bit shifting out.
In the multiplication, control circuit 30 shown in
Thus, according to the eighth embodiment of the present invention, the operator cell array is divided into the AND operation array (operator cell sub-array block) that performs the AND operation and the full addition array (operator cell sub-array block) that performs the full addition operation, and the data path and the data propagation route of the combination logic operational circuit are switched according to the operational contents to perform the full addition and the AND operation. Therefore, the multiplication of the multi-bit data can be performed using the small-area array.
[Ninth Embodiment]
Unit operator cell UOEA includes P-channel SOI transistors PQA1 and PQA2 and N-channel SOI transistors NQA1 and NQA2, and unit operator cell UOEB includes P-channel SOI transistors PQB1 and PQB2 and N-channel SOI transistors NQB1 and NQB2.
P-channel SOI transistors PQA1 and PQB1 transmit data /DINB and DINB on global write data lines to body regions (storage node) SNB of N-channel SOI transistors NQA2 and NQB2 according to the signal potential on write word line WWLB. P-channel SOI transistors PQA2 and PQB2 transmit data DINA and /DINA on the write data lines to the body regions (storage node SNA) of SOI transistors NQA1 and NQB2 in response to the signal potential on local write word lines WWLA and SWWLA.
First local write word line WWLA is arranged in the direction orthogonal to write word line WWLB. Second local write word line SWWLA is arranged in the direction orthogonal to first local write word line WWLA, and is electrically connected to first local write word line WWLA. Second local write word line SWWLA is electrically connected to the gates of MOS transistors PQA2 and PQB2 in unit operator cells UOEA and UOEB that are arranged in alignment in the row direction. Local write word lines WWLA and SWWLA are arranged extending within the corresponding operator cell sub-array block. A hierarchical architecture of the local write word lines will be described later.
The sources of SOI transistors NQA1 and NQB1 are connected to source line SL. In unit operator cells UOEA and UOEB, the connection manner of the SOI transistors of the reading section is similar to that of the unit operator cell shown in
In response to the signal potential at read word line RWLA, SOI transistors NQA1 and NQB1 are selectively put into the conductive state according to the storage data on read word line RWLA. In response to the signal potential on read word line RWLB, SOI transistors NQA2 and NQB2 are selectively put into the conductive state according to the storage data.
In each of unit operator cells UOEA and UOEB, data DOUTA is used in the case where the NOT operation is performed, and data DOUTB is used in the case where the AND operation result is outputted. The different read bit lines are connected to unit operator cells UOEA and UOEB, respectively. Accordingly, the data read is performed in parallel for unit operator cells UOEA and UOEB.
In P-type transistor forming region, high-concentration P-type regions 500a and 500b are arranged in alignment in the Y-direction. An N-type region 502a is arranged between P-type regions 500a and 500b. A P-type region 504a is disposed adjacent to P-type region 500b in alignment with P-type region 500b in the Y-direction.
P-type region 504b and high-concentration P-type regions 500c and 500d are disposed in alignment with P-type regions 500a, 500b, and 504a in the Y-direction. An N-type region 502b is disposed between P-type regions 500c and 500d.
Outside the P-type transistor forming region, an N-type region 506a is disposed adjacent to P-type region 500b, and high-concentration N-type regions 506b and 506c are disposed in alignment with N-type region 506a in the Y-direction. P-type region 504a is disposed, between N-type regions 506a and 506b, continuously extending in the X-direction. A P-type region 504b is disposed, between N-type regions 506b and 506c, continuously extending in the X-direction.
In the P-type transistor forming region, high-concentration P-type regions 500e and 500f are arranged in the Y-direction. An N-type region c is disposed between P-type regions 500e and 500f. A P-type region 504c is disposed adjacent to P-type region 500f and in alignment with P-type region 500f in the Y-direction.
P-type region 504d and high-concentration P-type regions 500g and 500h are disposed in alignment with P-type regions 500e, 500f, and 504e in the Y-direction. N-type region 502d is disposed between high-concentration P-type regions 500g and 500h.
Outside the P-type transistor forming region, a high-concentration N-type region 506d is disposed adjacent to P-type region 500f, and high-concentration N-type regions 506e and 506f are disposed in alignment with N-type region 506d in the Y-direction. P-type region 504c is disposed, between N-type regions 506d and 506e, continuously extending in the X-direction from the P-type transistor forming region. P-type region 504d is disposed, between N-type regions 506e and 506f, continuously extending in the X-direction from the P-type transistor forming region.
A gate electrode interconnection line 508a is continuously extending in the X-direction, and is disposed so as to overlap with N-type regions 502a and 502c. A gate electrode interconnection line 508b continuously extends in the X-direction, so as to overlap with P-type regions 504a and 504c. A gate electrode interconnection line 508c continuously extends in the X-direction, so as to overlap with P-type regions 504b and 504d. A gate electrode interconnection line 508d continuously extends in the X-direction, so as to overlap with N-type regions 502b and 502d.
First metal interconnection lines 510a to 510g continuously extending in the Y-direction are disposed being separated from one another. First metal interconnection line 510a is electrically connected to N-type region 506f through a contact/via VV11. First metal interconnection line 510b is electrically connected to N-type region 506e through a contact/via VV10. First metal interconnection line 510c is electrically connected to N-type region 506h through a contact/via VV8.
First metal interconnection line 510d is electrically connected to a second metal interconnection line 512g through a contact/via VV6. Second metal interconnection line 512g is disposed extending in the X-direction. Second metal interconnection line 512g is electrically connected to gate electrode interconnection line 508a in a not shown region. Gate electrode interconnection line 508a is disposed in the lower layer in parallel with second metal interconnection line 512g. In
First metal interconnection line 510e is electrically connected to P-type region 500d through a contact/via VV5. First metal interconnection line 510f is electrically connected to N-type region 506b through a contact/via VV3. First intermediate interconnection line 510g is electrically connected to N-type region 506c through a contact/via VV.
First metal interconnection lines 510a and 510b constitute the B-port and A-port bit lines, respectively. First metal interconnection line 510c constitutes the write port through which write data DINB is transmitted. First metal interconnection line 501d constitutes local write word line WWLA, and first metal interconnection line 510e transmits write data DINB. First metal interconnection line 510f constitutes the A-port read bit line, and transmits data DOUTA. First metal interconnection line 510g constitutes the B-port read bit line, and transmits data DOUTB.
Second metal interconnection lines 512a to 512g continuously extending in the X-direction are disposed being separated from one another. Second metal interconnection line 512a is electrically connected to P-type region 500a through a contact/via VV1 and an intermediate interconnect. Second metal interconnection 512b is electrically connected to P-type region 500e through a contact/via VV7 and an intermediate interconnect. Second metal interconnection line 512c is electrically connected to N-type region 506d through a contact/via VV9 and an intermediate interconnect, and is electrically connected to N-type region 506a through a contact/via VV2. Second metal interconnection line 512d is disposed in parallel with gate electrode interconnection line 508b continuously extending in the X-direction, and is electrically connected to gate electrode interconnection line 508b in a not shown portion.
Second metal interconnection line 512e is disposed so as to overlap with gate electrode interconnection line 508c, and is electrically connected to gate electrode interconnection line 508c in a not shown portion. Second metal interconnection line 512f is disposed so as to overlap with gate electrode interconnection line 508d, and is electrically connected to gate electrode interconnection line 508d in a not shown portion.
Second metal interconnection lines 512a and 512b transmit input data /DINA and DINA, respectively. Second metal interconnection line 512c constitutes source line SL, and second metal interconnection line 512d constitutes read word line RWLA along with lower-layer gate electrode interconnection line 508b. Second metal interconnection line 512e constitutes read word line RWLB along with lower-layer gate electrode interconnection line 508c. Second metal interconnection line 512f constitutes write word line WWLB along with lower-layer gate electrode interconnection line 508d. Second metal interconnection line 512g constitutes second local write word line SWWLA.
A-port local write word line WWLA is arranged continuously extending in the Y-direction, and second local write word line SWWLA is arranged extending in the X-direction and is connected to the gate electrode interconnection line in the corresponding memory cell row of each operator cell sub-array block. Thus, in the searching operation, the same rows are concurrently selected in the operator cell sub-array blocks selected in a plurality of operator cell sub-array blocks, and the searching operation is performed. As described later, the reason why local write word lines WWLA and SWWLA are used is that, in the searching operation, a row in the sub-array blocks is specified by the global write word line and to adjust the number of selected operator cell sub-array blocks according to the search data bit width.
In sense amplifier band 38, the sense amplifier circuit is provided for the unit operator cell column. Although the arrangement of the port selecting switching circuit and the read gate is similar to that of the previously-described embodiments, the output portion of the sense amplifier circuit differs from that of the previously-described embodiments in that the global read data line is driven such that the current is selectively supplied in the one-way direction to the global read data line according to the sense data (the output portion is described later).
An A-port write word line decoder 520 is shared by operator cell sub-array blocks OAR0 to OAR31. A-port write word line decoder 520 includes an A-port write word line driver 522 for driving an addressed global write word line WWLA<0>, WWLA<1>, . . . according to an A-port word line address for reading the data. In the searching operation, the selected global word line is sequentially updated in each search cycle.
A sub-decoder band 525 is provided for each of operator cell sub-array blocks OAR0 to OAR31. In sub-decoder band 525, a sub-decoder 523 is provided corresponding to each of global write word lines WWLA<0> to WLLA<m>. Sub-decoder 523 drives corresponding local write word line WWLAi to the selected state in response to the signal on the corresponding global write word line WWLA<i> and block selection signal BSk supplied from row selection driving circuit 22, and sub-decoder 523 drives the unit operator cells of one row to the selected state. The unit operator cells of one row are connected to a corresponding second local write word line SWWLAi.
Second local write word lines SWWLA in the same row are driven to the selected state in the operator cell sub-array blocks that are selected in operator cell sub-array blocks OAR0 to OAR31 in response to block selection signal BS. A-port write word line is formed into a hierarchical structure of the global and local word lines, and the match detection can be performed while selecting the search target data pattern according to the search data bit width even if the search data bit width is changed in each clock cycle.
Main amplifier circuit 24, combination logic circuit 26, and data path 28 are similar to those of the first to fourth embodiments. In data path 28, the non-inverted data of external data DINB is produced. Data path 28 includes global write drivers 524 and 526 that transmit data /DINB and DINE to global write data lines WGLZ and WGL, respectively. Data DINB<m:0> and output data DOUT<m:0> each having the (m+1)-bit width are transferred through data path 28.
In row selection driving circuit 22, row/data line selection driving circuits XXDR0 to XXDR31 are provided corresponding to operator cell sub-array blocks OAR0 to OAR31. The bit-width variable search data DINA#x are applied to row/data line selection driving circuits XXDR0 to DDXR31.
A bit width w of bit-width variable search data DINA#x (x is a number of the search data) is described in a packet header in the use of data communication application, and bit width w of search data DINA<1:0> is detected by analyzing the header in each search cycle. The search data bits are transferred to operator cell sub-array blocks OAR31 to OAR(31−1) in a distributed manner. Block selection signal BS that is driven to the selected state by control circuit 600 is determined according to information w on the detected search data bit width, and the one-row unit operator cells are selected based on the number of operator cell sub-arrays according to the search data bit width, and the match searching is performed.
Each of row/data line selection driving circuit XXDR0 to XXDR31 includes a word line drive circuit 530 and a data line drive circuit 534. Word line drive circuit 530 drives read word lines RWLA and RWLB and write word line WWLB to the selected state in response to an address signal (not shown). Data line drive circuit 534 produces complementary data DINA and /DINA according to corresponding bit DINAx<i> of the received search data.
Word line drive circuit 530 is arranged for each unit operator cell row of the corresponding operator cell sub-array block. In operator cell sub-array blocks OAR0 to OAR31, read word lines RWLA and RWLB and write word line WWLB can individually and concurrently be driven to the selected state.
A flag register 540 is provided corresponding to data path 28. As will be described later, in data path 28, a match detecting circuit is provided, and the match detecting result is stored in the registers of flag register 540 in each searching operation.
When the corresponding enable signals are activated, driving circuits 541, 542, and 544 are enabled to decode address signal AD, and drive corresponding word lines WWLB, RWLA, and RWLB to the selected state according to the decoding results.
Data line drive circuit 534 includes a gate circuit 546 for receiving data bit DINA<i>, read enable signal REN and address signal AD to produce inverted data bit /DINA, and an inverter 548 for inverting an output signal of gate circuit 546 to produce data bit DINA.
Read enable signal REN is activated when both A-port read enable signal RENA and B port read enable signal RENB are in the active state. Gate circuit 546 is a NAND-type decode circuit and is enabled to decode address signal AD when read enable signal REN is activated, and acts as the inverter to invert data bit DINA<i> when the corresponding row is selected.
A first local write word line WWLAj is arranged in the direction orthogonal to B-port write word line WWLB and read word lines RWLA and RWLB, and first local write word line WWLAj transmits the A-port write word line selection signal supplied from sub-decoder 523 of sub-decoder band 525 shown in
By forming the A-port write word line into the hierarchical structure, second local write word lines SWWLA in the same row are concurrently driven to the selected state in each of the operator cell sub-array blocks that are selected according to the search data bit width in operator cell sub-array block OAR0 to OAR31.
The configuration shown in
P-channel transistor 550 is selectively put into the conductive state in response to an output signal /SOUT of sense amplifier SA, and transmits a power supply voltage when made conductive. N-channel transistor 552 is put into the conductive state in response to an output signal SOUT of sense amplifier SA, and transmits a ground voltage when in the conductive state. Global read data lines RGL and ZRGL are pre-charged to the ground voltage, for example, In such case, in the conductive state, transistor 552 simply maintains corresponding global read data line ZRGL at a pre-charge voltage level. In this state, transistor 550 is put into the conductive state to supply the current to global read data line RGL, complementary global read data line ZRGL acts as a shielding line for global read data line RGL. However, global read data lines RGL and ZRGL may be pre-charged at an intermediate voltage level, and the main amplifier may produce the signal corresponding to the output signal voltage level of sense amplifier SA according to voltage levels of global read data lines RGL and ZRGL.
Sense amplifier SA drives output signal SOUT to the H level (“1”) when data /A·B or A·/B from the corresponding unit operator cell is “1”, that is, when data A and B are not matched with each other. In such case, transistors 550 and 552 are turned conductive and the current is supplied through read gate CSG to global read data line RGL to raise the voltage level of global read data line RGL.
When data A·/B and /A·B is “0”, that is, when data A and B are matched with each other, output signals SOUT and /SOUT of sense amplifier SA become the L level and H level, respectively, and transistors 550 and 552 are in the off-state. Accordingly, sense amplifier SA equivalently enters an output high-impedance state, and has no influence on the potentials at global read data lines RGL and ZRGL.
The search target data pattern are disposed in line, and the match detecting result for each bit is read on corresponding global read data line RGL. Accordingly, when the data pattern matched with applied search data is stored, corresponding sense amplifier circuits 560 in all the operator cell array blocks enter the output high-impedance state, and corresponding global read data lines RGL are maintained at the pre-charge voltage level. On the other hand, the potential at corresponding global read data line RGL attains the H level when any bit of the search data is not matched with that of the corresponding search target data.
In combination logic operational circuit 26, two-input OR gate is selected to perform the logical sum operation of output signals P<4i> and P<4i+1> of the main amplifiers. Accordingly, when corresponding mask bit MASK<i> is “1” while one of output signals P<4i> and P<4i+1> of the corresponding main amplifiers is “1”, that is, when data A and B are not matched with each other, the output signal of inverter 420 attains the L level, and match line ML is not discharged. When both output signals P<4i> and P<4i+1> of the main amplifiers are “0”, that is, when the patterns of data A and B are matched with each other, the output signal of inverter 420 attains the H level and match line ML is discharged. When mask bit MASK<i> is “0”, transistor TQ10 is in the off-state, and the match determination is masked to exert no influence on the voltage level of match line ML.
In
The main amplifiers that produce data bits P<0> and P<1> are also shown as main amplifier MA included in the main amplifier circuit. Each of main amplifiers MA compares a reference voltage VREF to the potential at corresponding global read data line RGL (RGL<0>, RGL<1>, . . . ). Because complementary global read data line ZRGL is not used in the main amplifier MA, complementary global read data line ZRGL is not shown in the main amplifier MA shown in
Sense amplifier circuit 560 in each of operator cell sub-array blocks OAR31 to OAR24 includes sense amplifier SA and transistors 550 and 552 shown in
The search target data pattern is stored in operator cell sub-array blocks OAR31 to OAR0 in advance before the searching operation. Complementary data bits (DINB and /DINB) of one-bit search target data B are stored in unit operator cells UOEA and UOEB, respectively. One search target data pattern is formed by unit operator cell pairs at the same position (same row and same column) of operator cell sub-array blocks OAR31 to OAR24.
In the searching operation, global write data line WWLA<i> is driven to the selected state, and eight operator cell sub-arrays OAR31 to OAR24 are selected by block selection signals BS31 to BS24 according to the bit width of search data DINA<7:0>. Data bits DINA<0> to DINA<7> and /DINA<7> are transmitted to the selected rows (selected by local word lines WWLA and WWLA) of selected operator cell sub-arrays OAR31 to OAR24 by data line drive circuit 534, and data transmitted to the selected unit operator cells are written by the corresponding second local sub-word lines. After the search data is written, in operator cell sub-array blocks OAR31, and OAR24, read word lines RWLA and RWLB concurrently drive unit operator cells UOEA and UOEB in the same row to the selected state to read the data stored in the unit operator cells in the selected row.
Read port selection circuit (36) selects B port. Data A is written in unit operator cell UOEA and data A and /B are read out, while data /A is written in unit operator cell UOEB and data A and B are read out. The corresponding sense amplifiers supply AND operational result data A·/B and /A·B through the write and read access to unit operator cells UOEA and UOEB (in
All read gate selection signals CSL#31 to CSL#24 are driven to the selected state for read gates CSG31 to CSG24 of operator cell sub-array blocks OAR31 to OAR24.
When data A and B are not matched with each other, one of data A·/B and /A·B attains “1”, output signal /SOUT of corresponding sense amplifier SA attains the L level, and currents (i#31 to i#24) are transmitted to corresponding global read data line RGL from sense amplifier circuit 560 arranged for the one of unit operator cells UOEA and UOEB (through transistor 550 shown in
In main amplifier MA, when the voltage level of corresponding global read data line RGL<j> is higher than reference voltage VREF, corresponding output bit P<j> is driven to the H level. Accordingly, an output signal Q of two-input OR gate OG0 shown in
On the other hand, when data A and B are matched with each other, both the data A·/B and /A·B attain “0”, sense amplifier circuits 560 arranged to unit operator cells UOEA and UOEB do not supply the currents to corresponding global read data lines RGL<j> and RGL<j+1>, and global read data line RGL<j> is maintained at the ground voltage level. Accordingly, the output signal of main amplifier MA attains the L level, and thus the output signal of two-input OR gate OG0 attains the L level to put the output signal of inverter 420 into the H level. In this state, match line ML pre-charged by pre-charging transistor PQ0 is discharged when mask bit MSK<k> (j=0 to m) is at the H level (“1”).
When mask bit MASK<j> is “0”, match line ML is not discharged, and is maintained at the pre-charge voltage level.
Match line ML is discharged when one of the data patterns that are stored in unit operator cells UOEA and UOEB arranged for read data line pair RGL<j> and RGL<j+1> is matched with the pattern of input search data DINA<7:0>, and match line ML is not discharged when the data patterns stored in unit operator cells UOEA and UOEB are not matched with the pattern of input search data DINA<7:0>. Accordingly, in operator cell sub-array blocks OAR31 to OAR24, the determination can concurrently be made for the data patterns stored in the unit operator cells connected to read word lines RWLA and RWLB.
That is, the determination of the match/mismatch is concurrently made for the data bits stored in the one-row unit operator cells in each operator cell sub-array block, match line ML is discharged when at least one of the data patterns is matched with the search target data pattern, and match line ML is maintained at the pre-charge voltage level when the search data pattern is not matched with any of the search target data patterns. Accordingly, the searching operation can be performed in one cycle for a plurality of search target data patterns. The search result is amplified by amplifying circuit AMP shown in
Two unit operator cells UOEA and UOEB are used for the data of one bit, and the complementary data bits are stored in the unit operator cells UOEA and UOEB. Accordingly, each of global read data lines RGL1 to RGLm shown in
In the searching operation, the operator cell sub-arrays are selected in response to the block selection signal according to the bit width of search data DINA in operator cell sub-array blocks OAR0 to OARk, one-row unit operator cells are selected in each selected operator cell sub-array, and the search is performed on a plurality of search target data patterns.
The bit width of transferred search data DINA is variable in each search cycle. When the operator cell sub-arrays are selected according to the bit width, the data bit string, for example, {a11, b11, . . . } that is disposed for the same global read line of the selected operator cell sub-arrays are selected as the search target data for input search data DINA and the match search is performed.
The search target data bits are previously stored in the unit operator cells, respectively. First, a searching operation instruction is supplied (Step SP50). The searching operation instruction may be a command, or the searching operation instruction may be produced by analytical result of the data packet header in the data communication application. In the description below, the search data is not limited to, but by way of example, is described as the data pattern used to discriminate between access permission and access rejection included in the packet transferred in a communication network.
The address (word line address) and flag register are initialized according to the searching operation instruction (Step SP51). The route is set in the data path and the combination logic operational circuit, and the selected port is set to B port in the memory (operator) cell array.
When the searching operation is started, the bit width (w1+1) of the search data is identified in the first cycle through the header analysis, and the first search data string DINA#1<w1:0> is transferred along with bit width information w indicating the bit width (w1+1). Here, the numeral (w1+1) is a bit width in the first search cycle, and the bit width indicated by bit width information w is variable for each search cycle. In the configuration shown in
In the selected operator cell sub-array blocks OAR0 to OARw1, write word lines WWLA and SWWLA are driven to the selected state, the complementary bits are produced from each bit of search data string DINA#1<w1:0> and transferred to unit operator cells (UOEA and UOEB) of the selected row of the corresponding operator cell sub-array blocks, and the data are written and read (Step SP52). Therefore, the unit operator cells at the same position (first row) of operator cell sub-array blocks OAR0 to OARw1 are concurrently selected, and the data are written and read.
In response to the output signals of the sense amplifier circuits, the current selectively flows through each of global read data lines RGL1 to RGLm according to the results of pattern matching determination of input search data string DINA#1<w1:0> to (w1+1)-bit data patterns <a11, b11, . . . >, <a12, b12, . . . >, . . . , <a1m, b1m, . . . >, the voltage levels of global read data lines RGL1 to RGLm are raised higher than the reference voltage (in mismatching) or maintained at the pre-charged ground voltage level (in matching).
When one of global read data lines RGL1 to RGLm is at the L level of the pre-charge voltage level, one of the search target data patterns is matched with the pattern of input search data string DINA#1<x:0>. In this state, match line ML is discharged from the pre-charge voltage of the power supply voltage level by two-input OR gate OG0, register 50 and inverter 420. That the data pattern matched with search data string DINA#1<w1:0> is stored in operator cell sub-array blocks OAR0 to OARw1 is indicated by flag SRSLT at L level, for example, supplied from amplifying circuit AMP that amplifies the voltage on match line ML.
When each of global read data lines RGL1 to RGLm is not lower than the reference voltage level, every search target data pattern is not matched with the pattern of input search data string DINA#1<w1:0>, and the output signal of the two-input OR gate OG0 attains the H level. Accordingly, the output signal of inverter 420 attains the L level, and the match line is maintained at the power supply voltage level of the pre-charge voltage. Output flag SRSLT of amplifying circuit AMP is, for example, at the H level that is different from that in the match, and output flag SRSLT indicates the mismatch.
When mask bit MASK<1> is “0”, for the corresponding search target data pattern, the searching operation is stopped and removed from a search candidate. The pattern of the search target candidate, that is, the searching range can be set by mask bit MASK<m:0>.
In the case where the match is detected in the current cycle, a match flag is set in flag register 540 according to search result flag SRSLT from amplifying circuit AMP (Step SP53).
Then, it is determined whether the search is completed for the final search data (Step SP54). When the search is not completed for the final search data, the word line address is updated (Step SP55), and the searching operation is repeated from Step SP52. Because the final search is not completed, when the another search data string DINA#2<w2:0> is transferred along with bit width information w in the next clock cycle, write word line WWLA and read word lines RWLA and RWLB of the next row are selected in the selected (w2+1) operator cell sub-arrays, and the pattern search is performed to (w2+1)-bit search target data patterns {a21, b21, . . . }, . . . , {a2m, . . . }.
The operation is repeatedly performed, and the match flag is set in flag register 540 shown in
When it is determined that the search is completed for all the input search data in Step SP54, that is when the pattern search is completed for search data patterns {a11, b11, . . . }, . . . , {a1m, b1m, . . . } in the first search cycle, the determination of the state of the match flags of flag register 540 is made (Step SP56). When the match is detected for all the input search data strings while all the match flags allocated to the search cycles of flag register (540) are in the set state (for example, “1”), all transferred search data strings DINA#1<w1:0> to DINA1<w1:0> are matched with search target data patterns stored in operator cell sub-array blocks OAR0 to OARk. According to the match/mismatch detection result, the necessary action is performed depending on the system to which the semiconductor signal processing device is applied (Steps SP57 and SP58).
In such case, for example, an identification whether the data string for which the access is prohibited is transferred can be made in an NIDS (Network Intrusion Detection System).
In the ninth embodiment, the bit width of the data pattern string of the search target is variable for each search cycle. Alternatively, search data DINA may be the data having a fixed bit width. In this case, the bit width may appropriately be defined according to the application of the device. The configuration of control circuit 600 shown in
[Tenth Embodiment]
The configuration of the unit operator cell shown in
Control circuit 30 performs a specified operational processing and a predetermined control operation to operator cell sub-array according to a command CMD and an address ADD. Address ADD includes a block address for specifying an operator cell sub-array block and a row address AD for specifying a row of the unit operator cells.
Referring to
Bit lines RBLA0 and RBLB0 and global write data lines WGLA0 and WGLB0 are provided for unit operator cells UOEI0, UOEJ0, and UOEK0, or unit operator cell column <0>. Global write data lines WGLA0 and WGLB0 are connected to write ports WPRTA and WPRTB of each of unit operator cells UOEI0, UOEJ0, and UOEK0. Bit lines RBLA0 and RBLB0 are connected to read ports RPRTA and RPRTB of each of unit operator cells UOEI0, UOEJ0, and UOEK0.
Dummy cells DMC0 and DMC1 are provided for each unit operator cell column. The configuration of dummy cells DMC0 and DMC1 is the same as that of the first embodiment shown in
A switch DMSW1 is provided to transmit the reference voltage to dummy cells DMC0 and DMC1. Switch DMSW1 supplies one of reference voltage VREF1 from a reference voltage source VREF1 (the power supply and the supply voltage are designated by the same reference symbol) and a reference voltage VREF2 from a reference voltage source VREF2 to dummy cells DMC0 and DMC1 according to an operation mode.
Reference voltage source VREF1 supplies the current of an amount intermediate the current amounts that are supplied from SOI transistors NQ1 and NQ2 included in unit operator cell UOEI0 when in the high threshold voltage and low threshold voltage. For example, reference voltage VREF1 is set lower than a half of power supply voltage VCC. Reference voltage VREF2 supplies the current that is larger than the current supplied to the bit line when one of series transistors NQ1 and NQ2 of the unit operator cell is in the high threshold voltage and that is smaller than the current amount supplied to the bit line when both series transistors NQ1 and NQ2 are in the low threshold voltage.
Read port selection circuit 36 includes a plurality of switch circuits PRSWC that are provided corresponding to the unit operator cell rows. For example, a switch circuit PRSWC0 is provided for bit lines RBLA0 and RBLB0. Switching circuit PRSWC0 includes switches PRSWA and PRSWB. Switch PRSWA connects one of bit lines RBLA0 and RBLB0 to sense bit line RBL0 in response to a port selection signal PRMX. Complementary bit line ZRBL0 connected to the dummy cell is connected to sense amplifier SA0.
Switch PRSWB selectively connects bit line RBLB0 and common source line SLC in response to a port selection signal PRMX. Therefore, in unit operator cell UOE, the data stored in SOI transistor NQ1, the data stored in SOI transistor NQ2, and the logic-operation result of data stored in SOI transistors NQ1 and NQ2 can selectively be read as described later.
Dummy cells DMC1 and switching circuits PRSWC1 are also provided corresponding to unit operator cells UOEI1, UOEJ1, and UOEK1, or unit operator cell column <1>, and the similar connection control is performed.
Port selection signal PRMX is a multi-bit signal, the connection of port selection signal PRMX can be set for each bit line pair.
The configuration of sense amplifier band 38 is similar to that of the first embodiment shown in
Row drive circuit XDR concurrently drives one or a plurality of unit operator cell rows to the selected state. Row drive circuit XDR also concurrently drives a plurality of dummy cells DMC corresponding to one or a plurality of concurrently-selected unit operator cell rows. One or a plurality of selected dummy cells DMC supply one of the two kinds of reference currents to corresponding complementary bit lines ZRBL in response to which is selected between dummy cell selection signals DCLA and DCLB. Accordingly, in memory (operator) cell array MLA, the data stored in the plurality of unit operator cells UOE corresponding to one or a plurality of entries are concurrently read and written.
In the data read, the operation waveform is similar to that shown in
Switching circuit DMSW selects reference voltage VREF1. reference voltage VREF1 is at a level between the voltage (power supply voltage VCC level) supplied to source line SL and bit line pre-charge voltage VPC.
For example, source line SL is at the voltage level of power supply voltage VCC level, and the voltage at source line SL is higher than reference voltage VREF1 supplied to dummy cell DMC.
When the data “0” is stored in at least one of SOI transistors NQ1 and NQ2 (state S(1,0), state S(0,1), and state S(0,0)), because the at least one SOI transistor is in the high threshold voltage, the amount of current flowing through the unit operator cell is smaller than the amount of current flowing through dummy cell DMC.
On the other hand, when the data “1” is stored in SOI transistors NQ1 and NQ2 (state S(1,1)), because both SOI transistors NQ1 and NQ2 is in the low threshold voltage, the amount of current flowing to the bit line through the unit operator cell is larger than the amount of current flowing through dummy cell DMC.
Sense amplifier activation signals /SOP and SON are set at a logical low level (L level) and a logical high level (H level) to activate sense amplifier SA. The data (potential or current amount) are read onto bit lines RBL and ZRBL and sense amplifier SA differentially amplifies the data.
Then, read gate CSG shown in
Accordingly, as shown in
In such case, in
In
Accordingly, the output signal of sense amplifier SA assumes the data of the same logical value as that of the data stored in SOI transistor NQ1. When the output signal of sense amplifier SA is inverted, or when the inverted value of the write data is stored in SOI transistor NQ1 and read therefrom, the NOT operational result of the write data can be obtained as the output of sense amplifier SA.
Therefore, similarly to the manner when SOI transistor NQ1 shown in
In the connection manner, the output signal of sense amplifier SA also becomes the data of the same logical value as that of the data stored in SOI transistor NQ2. When the output signal of sense amplifier SA is inverted, or when the inverted value of the write data is stored in SOT transistor NQ2 and read therefrom, the NOT operational result of the write data can be obtained as the output of sense amplifier SA. Accordingly, in the SOI transistor selection manner shown in
The read operation in the case where two unit operator cell rows <i> and <j> are selected in semiconductor signal processing device 101 will be described below.
In unit operator cell UOEI, SOI transistor NQ1 is selected through read word line RWLi and connected to sense bit line RBL through port RPRTA. In unit operator cell UOEJ, SOI transistor NQ2 is selected through read word line RWLBj. Switch PRSWB of corresponding switching circuit PRSWC connects common source line SLC to bit line RBLB. SOI transistor NQ2 connects sense amplifier SA through port RPRTA. That is, SOI transistors NQ1 and NQ2 are connected in parallel with each other to sense bit line RBL.
For dummy cell DMC, dummy transistor DTA or series dummy transistors DTB0 and DTB1 are selected according to an operation mode. In
As shown in
In writing the data, a plurality of unit operator cells UOEI corresponding to unit operator cell row <i> and a plurality of unit operator cells UOEJ corresponding to unit operator cell row <j> are individually selected, the threshold voltages of SOI transistors NQ1 and NQ2 are set in the plurality of selected unit operator cells UOE. That is, in writing the data, write word lines WWL<i> and WWL<1> are sequentially selected, and the voltages are applied to global write data line pair WGLP according to the write data using the write drivers (not shown).
In reading the data, the plurality of unit operator cells UOEI corresponding to unit operator cell row <i> and the plurality of unit operator cells UOEJ corresponding to unit operator cell row <j> are selected in parallel, and SOI transistors NQ are concurrently connected to bit lines RBL in the plurality of selected unit operator cells UOE. Accordingly, in reading the data, the currents passed through SOI transistors NQ connected to the same bit line RBL are combined to flow through each bit line RBL.
For example, A-port read word line RWLA is selected for the odd-numbered row read word line, and B-port read word line RWLB is driven to the selected state for the even-numbered row read word line.
Alternatively, SOI transistor NQ1 may be selected in unit operator cells UOEI and UOEJ. It is only necessary to select one SOI transistor in each of two unit operator cells and connect the selected SOI transistors in parallel to the sense amplifier.
In dummy cell DMC of each unit operator cell column, one of dummy transistor DTA and series dummy transistors DTB0 and DTB1 is selected in reading the data. That is, one of dummy cell selection signals DCLA and DCLB is driven to the selected state. The amount of current passed through dummy cell DMC is adjusted by selecting one of reference voltages VREF1 and VREF2. The case will be described, in which dummy cell selection signal DCLA is driven to the selected state to select dummy transistor DTA and dummy transistor DTA is connected to reference voltage source VREF1 as shown in
In
On the other hand, in the state S(1,1), because SOI transistors NQ1 (UOEI) and NQ2 (UOEJ) have the low threshold voltage, the amount of current flowing from unit operator cells UOEI and UOEJ to sense amplifier SA through sense bit line RBL becomes the maximum.
In the states S(1,0) and S(0,1), the low threshold voltage and the high threshold voltage are combined, and the current intermediate between the bit line currents of states S(0,0) and S(1,1) flows. Accordingly, in the cases of the states S(1,0) and S(0,1), the bit line attains the read potential between bit line read potentials at the states S(0,0) and S(1,1).
Reference voltage VREF1 is selected as reference voltage VREF, and reference voltage VREF1 is set at voltage level that is lower than a half of power supply voltage VCC. In this state, the current flowing through dummy transistor DTA can be set larger than the current flowing through bit line RBL in state S(0,0) and smaller than the current flowing through bit line RBL in states S(0,1) and S(1,0). Accordingly, in selecting dummy transistor DTA, the potential at complementary bit line ZRBL can be set between the potential in state S(0,0) and the potentials in states S(1,0) and S(0,1). In such case, current Id1 flowing through dummy transistor DTA can be expressed as follows.
I1>Id1>1h,
2×Ih<Id1<Ih+I1
Here, Ih is a current flowing through SOI transistor NQ in the high threshold voltage state and I1 is a current flowing through SOI transistor NQ in the low threshold voltage state.
The operation in the case where reference voltage VREF2 is selected as reference voltage VREF in the connection and arrangement shown in
Reference voltage VREF2 is higher than reference voltage VREF1 by a predetermined value. In the condition of reference voltage VREF2, the current that is smaller than the current flowing through read bit line RBL when two SOI transistors NQ1 and NQ2 has the low threshold voltages and larger than the current flowing through unit operator cell UOE when one SOI transistor NQ has the low threshold voltage can be passed to complementary bit line ZRBL. Accordingly, in selecting dummy transistor DTA, the potential at complementary bit line ZRBL can be set between the potential in states S(1,0) and S(0,1) and the potential in state S(1,1). In such case, current Id2 flowing through dummy transistor DTA can be expressed as follows.
I1<Id2,
2×I1>Id2>1h+I1.
Sense amplifier SA differentially amplifies the potentials or currents of bit line RBL and ZRBL to read the data stored in unit operator cells UOEI and UOEJ. In sense amplifier SA, binary determination of the bit line potential or bit line current is made using the potential at dummy cell DMC or the current passed through dummy cell DMC as the reference value. Accordingly, the output of sense amplifier SA indicates one of two classifications into which the combination of the one-bit data stored in each of unit operator cells UOEI and UOEJ is classified on the basis of the voltage level of reference voltage VREF, so that the logic operation can be performed to the data stored in unit operator cells UOEI and UOEJ by sense amplifier SA.
As shown in
In the state S(1,0) and the state S(0,1), one of SOI transistors NQ1 (UOEI) and NQ2 (UOEJ) is in the high threshold voltage state and the other is in the low threshold voltage state. Accordingly, in the case where the reference voltage VREF1 is selected, the current flowing through bit line RBL is larger than the current flowing through complementary bit line ZRBL, and the potential at bit line RBL is higher than the potential at complementary bit line ZRBL. Therefore, the output signal of the sense amplifier attains “1”. In the case where reference voltage VREF2 is selected, the current flowing through bit line RBL is smaller than the current flowing through complementary bit line ZRBL, and the potential at bit line RBL is lower than the potential at complementary bit line ZRBL. Therefore, the output signal of the sense amplifier attains “0”.
In the state S(1,1), both SOI transistors NQ1 (UOEI) and NQ2 (UOEJ) are in the low threshold voltage state, and the data “1” is stored in SOI transistors NQ1 (UOEI) and NQ2 (UOEJ). In this condition, even if any of reference voltage VREF1 and reference voltage VREF2 is selected, as shown in
As shown in
Preferably, the current sensing type sense amplifier is used as the sense amplifier, because current sensing type sense amplifier has the sensing operation faster than that of the voltage sensing type sense amplifier. As described later, a current-mirror type sense amplifier is used as sense amplifier SA instead of the cross-coupled latch type sense amplifier shown in
(First Modification)
One SOI transistor is selected in each of the three unit operator cells on unit operator cell rows <i>, <j>, and <k> and on the same unit operator cell column.
N-channel SOI transistor NQ1 (UOEI), N-channel SOI transistor NQ1 (UOEJ), and N-channel SOI transistor NQ1 (UOEK) are selected in
As shown in
In writing the data, a plurality of unit operator cells UOEI corresponding to unit operator cell row <i>, a plurality of unit operator cells UOEJ corresponding to unit operator cell row <j>, and a plurality unit operator cells UOEK corresponding to unit operator cell row <k> are individually selected, and the threshold voltage of SOI transistor NQ1 (and NQ2) is (are) set in the plurality of selected unit operator cells UOE. That is, in writing the data, write word lines WWL<i>, WWL<j>, and WWL<k> are sequentially selected, and the write driver (not shown) applies the voltage to each global write data line pair WGLP according to the write data.
In reading the data, the plurality of unit operator cells UOEI corresponding to unit operator cell row <i>, the plurality of unit operator cells UOEJ corresponding to unit operator cell row <j>, and the plurality of unit operator cells UOEK corresponding to unit operator cell row <k> are selected in parallel, and SOI transistors NQ1 are connected in parallel with each other to sense bit lines RBL in the plurality of selected unit operator cells UOE. Accordingly, in reading the data, the currents flowing through SOI transistors NQ1 connected to the same bit line RBL are combined and flow through each bit line RBL.
The following configuration can be used as the configuration for concurrently driving read word lines RWLi, RWLj, and RWLk to the selected state. That is, a latch circuit is provided at an output portion of the read word line driver. For example, the read word line address is produced by a counter, and the three read word lines are sequentially specified in the activated period of time of read word line enable signal RWLEN. When read word line enable signal RWLEN is inactivated, the latch circuit of the output portion of the read word line driver is reset, and the read word line in the selected state is driven to the non-selected state. Therefore, the three read word lines can concurrently be set at the selected state starting at an arbitrary address without utilizing a complicated circuit configuration.
In dummy cell DMC of each unit operator cell column, either of dummy transistor DTA and dummy transistors DTB0 and DTB1 is selected in reading the data. That is, one of dummy cell selection signals DCLA and DCLB is selected. The amount of current flowing through dummy cell DMC is adjusted by selecting one of reference voltages VREF1 and VREF2. The case will be described, in which dummy cell selection signal DCLA is driven to the selected state to select dummy transistor DTA and reference voltage VREF1 is selected as reference voltage VREF.
As shown in
On the other hand, in a state S(1,1,1), because SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK) have the low threshold voltage, the amount of current flowing through sense bit line RBL becomes the maximum.
In states S(1,0,0), S(0,1,0), and S(0,0,1), two of SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK) have the high threshold voltages and the other one of SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK) has the low threshold voltage. In this state, the current flows in an amount between the bit line currents in the states S(0,0,0) and S(1,1,1). Accordingly, in states S(1,0,0), S(0,1,0), and S(0,0,1), the bit line read potential is located between those in the states S(0,0,0) and S(1,1,1).
In states S(1,1,0), S(1,0,1), and S(0,1,1), two of SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK) have the low threshold voltages and the other one of SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK) has the high threshold voltage. In this state, the current flows in an amount between the bit line currents flowing in the states S(0,0,0) and S(1,1,1), and the bit line current becomes larger than those in the states S(1,0,0), S(0,1,0), and S(0,0,1). Accordingly, in states S(1,1,0), S(1,0,1), and S(0,1,1), the bit line read potential is located between those in the states S(1,0,0), (0,1,0), and S(0,0,1) and state S(1,1,1).
Reference voltage VREF1 is selected as reference voltage VREF, and reference voltage VREF1 is set at voltage level that is lower than half a power supply voltage VCC. In this state, the current flowing through dummy transistor DTA can be set larger than the current flowing through bit line RBL in state S(0,0,0) and smaller than the current flowing through bit line RBL in states S(1,0,0), S(0,1,0), and S(0,0,1). Accordingly, in selecting dummy transistor DTA, the potential at complementary bit line ZRBL can be set to a level between the potential in state S(0,0,0) and the potentials in states S(1,0,0), S(0,1,0), and S(0,0,1). In such case, current Id1 flowing through dummy transistor DTA can be expressed as follows.
I1>Id1>Ih,
3×1h<Id1<2Ih+I1.
Here, Ih is a current flowing through SOI transistor NQ in the high threshold voltage state and I1 is a current flowing through SOI transistor NQ in the low threshold voltage state.
When reference voltage source VREF2 is selected as reference voltage VREF and dummy cell selection signal DCLA is driven to the selected state to select dummy transistor DTA, the output signal of the sense amplifier becomes the states shown in the column of reference voltage source VREF2 shown in
Reference voltage VREF2 is higher than reference voltage VREF1 by a predetermined value. With the use of reference voltage VREF2, when one SOI transistor NQ is selected in unit operator cell UOE and the SOI transistor NQ has the low threshold voltage, the current that is larger than the current flowing through unit operator cell UOE can be passed through complementary bit line ZRBL. Accordingly, in selecting dummy transistor DTA, the potential at complementary bit line ZRBL can be set at a level between the potentials in states S(1,1,0), S(1,0,1), and S(0,1,1) and the potential in state S(1,1,1). In such case, current Id2 flowing through dummy transistor DTA can be expressed as follows.
I1<Id2,
3×1h>Id2>Ih+2×I1.
Sense amplifier SA differentially amplifies the potentials or currents of bit lines RBL and ZRBL to read the data stored in unit operator cells UOEI, UOEJ, and UOEK. In sense amplifier SA, the binary determination of the bit line potential or bit line current is made using the potential at dummy cell DMC or the current passed through dummy cell DMC as the standard value. Accordingly, the output of sense amplifier SA indicates one of two classifications into which the combination of the one-bit data stored in each of unit operator cells UOEI, UOEJ, and UOEK is bi-classified according to the voltage level of reference voltage VREF, so that the logic operation can be performed to the data stored in three unit operator cells UOEI, UOEJ, and UOEK by sense amplifier SA.
As shown in
In the states S(1,0,0), S(0,1,0), S(0,0,1), S(1,1,0), S(1,0,1), and S(0,1,1), at least one of SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK) is in the low threshold voltage state. Accordingly, in the case where reference voltage VREF1 is selected, the current flowing through bit line RBL is larger than the current flowing through complementary bit line ZRBL, and the potential at bit line RBL is higher than the potential at complementary bit line ZRBL. Therefore, the output signal of the sense amplifier attains “1”. In the case where reference voltage VREF2 is selected, the current flowing through bit line RBL is smaller than the current flowing through complementary bit line ZRBL, and the potential at bit line RBL is lower than the potential at complementary bit line ZRBL. Therefore, the output signal of the sense amplifier attains “0”.
In state S(1,1,1), SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK) are in the low threshold voltage state, and the data “1” is stored in SOI transistors NQ1 (UOEI), NQ1 (UOEJ), and NQ1 (UOEK). In this state, even if any of reference voltage VREF1 and reference voltage VREF2 is selected, as shown in
Accordingly, as shown in
(Modification of Sense Amplifier)
MOS transistors PP1 to PP6 and N-channel MOS transistors NN1 to NN9 are each formed by the SOI transistor. Alternatively, MOS transistors PP1 to PP6 and N-channel MOS transistors NN1 to NN9 may be each formed by a bulk transistor at periphery of the operator cell array.
MOS transistor NN8 has the gate and the drain interconnected together to convert cell current Icell supplied through read bit line RBL into the voltage. MOS transistor NN1 has a source connected to the ground node and a gate connected to a gate and drain of MOS transistor NN8. MOS transistor NN1 and MOS transistor NN8 constitute the current-mirror stage to extract the mirror current of cell current Icell from MOS transistor PP1 in operation of the sense amplifier. MOS transistor PP1 is connected between a node ND 1 and MOS transistor NN1.
MOS transistor PP1 has a gate and a drain interconnected together to serve as a master of the current-mirror stage. MOS transistor PP1 passes the mirror current of cell current Icell during the sensing operation.
MOS transistor NN9 has a gate and drain interconnected together to convert dummy cell current Idummy supplied through complementary read bit line ZRBL into the voltage. MOS transistor NN6 has a gate connected to a gate and drain of MOS transistor NN9. MOS transistor NN6 and MOS transistor NN9 constitute the current-mirror stage to pass the mirror current of dummy cell current Idummy during the sensing operation.
MOS transistors PP6 and NN6 are connected in series between node ND1 and ground node. MOS transistor PP6 has a gate and a drain interconnected together to act as a master of the current-mirror stage. MOS transistor PP6 passes the mirror current of dummy cell current Idummy during the sensing operation. MOS transistors PP2 to PP5 each has a source node connected to the power supply node.
Sense amplifier SA further includes N-channel MOS transistors NN2 and NN3 constituting a current-mirror stage and N-channel MOS transistors NN4 and NN5 constituting another current-mirror stage.
MOS transistor NN2 is connected between MOS transistor PP2 and node ND, and has a gate and drain interconnected to each other. MOS transistor NN3 is connected between MOS transistor PP4 and node ND2, and has a gate connected to the gate of MOS transistor NN2. MOS transistor NN4 is connected between MOS transistor PP3 and node ND2, and has a gate connected to a gate of MOS transistor NN5. MOS transistor NN5 is connected between MOS transistor PP5 and node ND2, and has a gate and drain interconnected to each other.
The signals current/voltage-converted by MOS transistors NN2 and NN5 are produced as intermediate sense signals SOT and /SOT.
Sense amplifier SA further includes a P-channel MOS transistor PP7 and an N-channel MOS transistor NN7. When sense amplifier activation signal /SE is activated, P-channel MOS transistor PP7 is put into a conductive state to connect node ND1 to the power supply node. When sense amplifier activation signal SE is activated, N-channel MOS transistor NN7 turns conductive to connect node ND2 to ground node GND. Sense amplifier activation signals /SE and SE are set at the L level and H level in the active state, respectively.
Sense amplifier SA furthermore includes a final amplifying circuit SMP. Final amplifying circuit SMP amplifies intermediate sense output signals SOT and/SOT current-voltage converted by MOS transistors NN2 and NN5, to produce final sense output signals SOUT and /SOUT. Final amplifying circuit SMP is in the output high-impedance state when sense amplifier activation signal /SE is inactivated. The operation of sense amplifier SA shown in
MOS transistors PP7 and NN7 are in the off-state when sense amplifier activation signals /SE and SE are inactive. In this state, MOS transistors PP2 and PP5 maintain intermediate sense output signals SOT and /SOT at the level of power supply voltage VCC. MOS transistors PP1, NN1, PP6, and NN1 in combination maintain node ND1 at the ground voltage level. Final sense output signals SOUT and /SOUT are also maintained at the pre-charge level (for example, H level) of the output high-impedance state.
In the sensing operation, before the read word line selection, sense amplifier activation signal /SE is activated to set MOS transistors PP7 and NN7 into the on-state. Accordingly, node ND1 is connected to the power supply node and MOS transistors PP1 and PP6 are made operative to establish the state of capable of sensing the currents on bit lines RBL and ZRBL. In such case, sense amplifier activation signal SE may be activated in parallel. The activation of sense amplifier activation signal SE may be delayed until the sensing operation is started. Read word line RWL is still in the non-selected state, and bit lines RBL and ZRBL are pre-charged to a predetermined voltage level by a bit line equalize circuit (BLEQ).
When the bit line pre-charging operation is completed, the read word line is driven to the selected state. Sense amplifier activation signal SE is activated before the read word line is driven to the selected state. Therefore, cell current Icell is supplied through the selected unit operator cell and bit line RBL according to the storage data. On the other hand, dummy cell current Idummy flows through complementary bit line ZRBL from the dummy cell.
MOS transistors NN1 and NN8 produce the mirror current of cell current Icell, and MOS transistors NN6 and NN9 produce the mirror current of dummy cell current Idummy. The mirror currents of currents Icell and Idummy flow through MOS transistors PP1 and PP6. The mirror current of the current flowing through MOS transistor PP1 flows through MOS transistors PP2 and PP3, and the mirror current of the current passed through MOS transistor PP6 flows through MOS transistors PP4 and PP5. Accordingly, the mirror currents of cell currents Icell and dummy cell current Idummy, flowing through bit lines RBL and ZRBL, flow through MOS transistors NN2 and NN5.
Through the current-voltage conversion operation by MOS transistors NN2 and NN5, when cell current Icell is larger than dummy cell current Idummy, intermediate sense output signal /SOT attains the voltage level higher than that of intermediate sense output signal SOT. In the case where cell current Icell is smaller than dummy cell current Idummy, intermediate sense output signal /SOT attains the voltage level lower than that of intermediate sense output signal SOT. Final amplifying circuit SMP in the subsequent stage further amplifies intermediate sense output signals SOT and /SOT to produce final sense output signals SOUT and /SOUT at the power supply voltage level and ground voltage level.
MOS transistors NN3 and NN4 behave as follows. MOS transistor NN2 discharges the current supplied from MOS transistor PP2, and MOS transistor NN3 discharges the mirror current of MOS transistor NN2. Similarly, the mirror current of the current flowing through MOS transistor PP5 flows through MOS transistor NN5, and MOS transistor NN4 can discharge the mirror current of the current supplied through MOS transistor NN5.
Accordingly, the smaller one of cell current Icell and dummy cell current Idummy flows through MOS transistors PP3 and NN4, and also the smaller one of cell current Icell and dummy cell current Idummy passes through MOS transistors PP4 and NN3. The sum of the combined current of cell current Icell and dummy cell current Idummy and the current that is double the smaller one of cell current Icell and dummy cell current Idummy always passes through MOS transistor NN7. In the case where the one-bit cell data is read to make the binary determination, MOS transistors PP3, PP4, NN3, and NN4 have the function of keeping the amount of current flowing through MOS transistor NN7 constant in order to stabilize the sensing operation.
However, MOS transistors PP3, NN4, NN3, and NN4 need not to be particularly provided. Alternatively, sense output signals SOUT and /SOUT may be extracted from the connection node of MOS transistors PP3 and NN4 and the connection node of MOS transistors PP4 and NN3.
As described above, sense amplifier SA produces the signals indicating the OR operational result and AND operational result of the data stored in a plurality of unit operator cells. In the case where the logical value of the data stored in the unit operator cell is inverted and read, and in the case where the sense amplifier produces the NOR operational result and NAND operational result, it is sufficient for main amplifier circuit 14 or data path 28 to invert the sense output signal shown in
Through adjustment of a current level of dummy cell current Idummy by reference voltages VREF1 and VREF2, the OR operation and AND operation can be selectively performed. That is, the connection path of switching circuit DMSW is set according to the performing operational contents, which allows the logic operations to be selectively performed. The data read and the operation can be performed at high speed with a low power supply voltage using the current sensing type sense amplifier.
In
In
The storage data string of SOI transistors NQ1 of the unit operator cells is “1100110011001” in entry (Entry) j-A, that is, in unit operator cell row <j>, and the storage data string of SOI transistors NQ2 of the unit operator cells is “0011001100110” in entry (Entry) j-B, that is, in unit operator cell row <j>.
The storage data string of SOI transistors NQ1 of the unit operator cells is “0001110001110” in entry k-A, that is, in unit operator cell row <k>, and the storage data string of SOI transistors NQ2 of the unit operator cells is “1110001110001” in entry k-B, that is, in unit operator cell row <k>.
When entry i-A is selected to perform buffering processing as the operational processing, output data DOUT becomes “1010101010101” (OP1). When entries i-A and i-B are select to perform the AND operation, data DOUT becomes “0000000000000” (OP2). When entries i-A and j-A are selected to perform the OR operation, data DOUT becomes “1110111011101” (OP3).
Assuming that m is the number of operator cell sub-array blocks OAR in operator cell array 20 and n is the number of entries in each operator cell sub-array block OAR, the number of produced data strings is obtained as follows:
m×n×2+m×n×(n−1)÷2×2+m×n×(n−1)×(n−2)÷(3×2)×2.
In the above expression, the first term is the number of combinations in the case where one entry is selected from the n entries in one operator cell sub-array block OAR and one of SOI transistors NQ1 and NQ2 is selected. The second term is the number of combinations in the case where two entries are selected from the n entries and one of SOI transistors NQ1 and NQ2 is selected to perform the AND or OR operation on the selected entries. The third term is the number of combinations in the case where three entries are selected from the n entries and one of SOI transistors NQ1 and NQ2 is selected to perform the AND or OR operation on the selected entries.
A main usage example of the semiconductor signal processing device according to the tenth embodiment of the present invention is as follows. Although the data stored in the unit operator cells of operator cell array 20 are changed depending on the system into which the semiconductor signal processing device is incorporated, the data stored in the unit operator cells are not dynamically changed. In the system, the different address signals and operation flags are successively applied to the semiconductor signal processing device externally, and the operational processing result is received from the semiconductor signal processing device. The entry is specified by the address signal, and the operation contents to be performed, the entry and SOI transistor to be concurrently selected are specified by the operation flag. Accordingly, for the processing results, the number of reference results that is greater than the number of internal operational results and the number of entries (unit operator cell rows) prepared in operator cell array 20 can be produced, and the number of entries can equivalently be increased to implement the high-density LUT.
Thus, in the semiconductor signal processing device according to the tenth embodiment of the present invention, row selection driving circuit 22 concurrently selects a plurality of unit operator cells UOE and a plurality of dummy cells DMC corresponding to one or the plurality of rows of unit operator cells based on the received address signal. Sense amplifier SA compares the current flowing through corresponding read bit line RBL and the current flowing through corresponding complementary read bit line ZRBL to supply the signal indicating the comparison result. Therefore, the storage data string of the selected unit operator cell row (entry) can directly be read out to the outside of the semiconductor signal processing device. A plurality of unit operator cell rows are concurrently selected to perform the addition of the currents based on the data stored in unit operator cell rows. Therefore, the sense amplifier performs the logic operation of the storage data strings of the unit operator cell rows, and the operational result can be read from the outside of semiconductor signal processing device 101.
By performing a logic operation of the data strings stored in the unit operator cell rows, a virtual entry space can be created which is larger than the real entry space made of physical true-value data strings from the true-value data strings stored in operator cell array 20. That is, the LUT calculating unit in which a further higher-density logic information is stored can be implemented compared with the conventional LUT calculating unit. Thus, the LUT calculating unit having a small occupying area and high density can be implemented by the semiconductor signal processing device according to the tenth embodiment of the present invention.
In the semiconductor signal processing device according to the tenth embodiment of the present invention, the transistor having the SOI structure is used as the memory element in unit operator cell UOE. Therefore, the data stored in the unit operator cell can be read without destructing the storage data, an operation can be performed while the data stored in the unit operator cell is repeatedly used.
The unit operator cell includes the four SOI transistors, the layout area is reduced, and the increase in area can be prevented in the memory cell array.
In the semiconductor signal processing device according to the tenth embodiment of the present invention, as shown in
In operator cell array 20, unit operator cell row <i>, unit operator cell row <j>, and unit operator cell row <k> may be provided being adjacent to each other, or unit operator cell row <i>, unit operator cell row <j>, and unit operator cell row <k> may be provided such that at least one unit operator cell row is located between any two of unit operator cell row <i>, unit operator cell row <j>, and unit operator cell row <k>.
[Eleventh Embodiment]
Combination logic operational circuit 600 performs a specified logic operation or arithmetic operation processing to the data stored in the unit operator cells, and combination logic operational circuit 600 produces different operational processing result such as the XOR operational processing result from the OR operational result or AND operational result that is the sense amplifier output. The data stored in the unit operator cells are transferred from sense amplifier band 38. Combination logic operational circuit 600 can also invert the logic level of an output signal of a sense amplifier in sense amplifier band 38 to supply the inverted output signal to main amplifier circuit 24.
In
The configurations and arrangements of unit operator cell UOE and dummy cell DMC in memory cell array MLA are similar to those of the cells shown in
Referring to
Transistor SAT1 transfers the data stored in the unit operator cell and dummy cell to sense amplifier SA1 in response to the output signal of sense amplifier selection driver SADV1. Transistor SAT2 transfers the data stored in the unit operator cell and dummy cell to sense amplifier SA2 in response to the output signal of sense amplifier selection driver SADV2. Sense amplifier selection drivers SADV1 and SADV2 are selectively activated in response to sense amplifier activation signal SAEN and a control signal specifying the operational contents.
Combination logic operational circuit 600 includes an AND gate G1, a multiplexer G2, buffers BUF1 and BUF2, and a transistor TR1.
Buffer BUF1 receives and buffers the signal from sense amplifier SA1 through signal line SAL1, and supplies the buffered signal to multiplexer G2. Buffer BUF2 receives and buffers the signal from sense amplifier SA1 through signal line ZSAL1, and supplies the buffered signal to multiplexer G2.
Multiplexer G2 selects one of the output signal of AND gate G1, the output signal of buffer BUF1 and the output signal of buffer BUF2, based on the control signal applied from operation selection driver OPSELDV in control circuit 30. Transistor TR1 is selectively turned conductive in response to an output signal of sub-array block selection driver MLASELDV, and transistor TR1 transfers the output signal of multiplexer G2 to main amplifier circuit 24 through global bit line GBL when made conductive.
The operation will be described below by way of example, in the case where the exclusive logical product (XOR) operation of the data stored in unit operator cells UOEI and UOEJ in the semiconductor signal processing device according to the eleventh embodiment of the present invention.
Reference voltage source VREF1 and dummy cell selection signal DCLA are selected by switch DMSW1. In dummy cell DMC, dummy transistor DTA passes the current from reference voltage source VREF1 to complementary bit line ZRBL. One transistor (NQ1) is selected in each of unit operator cells UOEI and UOEJ, and the current that is combined according to the data stored in unit operator cells UOEI and UOEJ flows through read bit line RBL.
Sense amplifier selection driver SADV1 is selected to activate sense amplifier SA1. Transistors SATA1 and ZSAT1 connect sense amplifier SA1 to read bit lines RBL and ZRBL, the current flowing through bit line RBL and the current flowing through complementary bit line ZRBL are differentially amplified, and the amplified signals are maintained and supplied to signal lines SAL1 and ZSAL1.
After sense amplifier SA1 amplifies and maintains the current difference, sense amplifier selection driver SADV1 is driven to the inactive state. In this state, sense amplifier SA1 is separated from read bit lines RBL and ZRBL, and retains the logical sum (OR operation) result of the data stored in unit operator cells UOEI and UOEJ.
Then, the connection path of switch DMSW1 is switched to select reference voltage source VREF2 and in addition, dummy cell selection signal DCLA is selected. In dummy cell DMC, one dummy transistor DTA is selected, and dummy transistor DTA passes the current from reference voltage source VREF2 to complementary bit line ZRBL. In each of unit operator cells UOEI and UOEJ, one SOI transistor is selected, the combined current of the currents corresponding to the data stored in the unit operator cells flows through read bit line RBL.
Sense amplifier selection driver SADV2 is selected according to the path switching of switch DMSW1 to put transistors SAT2 and ZSAT2 into the conductive state, thereby connecting read bit lines RBL and ZRBL to sense amplifier SA2.
Sense amplifier SA2 is activated after the data is read. Accordingly, sense amplifier SA2 amplifies the difference between the current flowing through bit line RBL and the current flowing through complementary bit line ZRBL, and sense amplifier SA2 retains the amplified signals and supplies the amplified signals to signal lines SAL2 and ZSAL2.
Sense amplifier selection driver SADV2 is turned off after sense amplifier SA2 amplifies and retains the current difference. In this state, sense amplifier SA2 retains the logical product (AND operation) result of the data stored in unit operator cells UOEI and UOEJ.
AND gate G1 supplies the signal indicating the logical product of the signal received through signal line SAL1 and the signal received through signal line ZSAL2. The signal indicating the logical sum operational result of the data stored in unit operator cells UOEI and UOEJ is transmitted from signal line SAL1, and the signal indicating the inverted value of the logical product operation, that is, the NAND operational result of the data stored in unit operator cells UOEI and UOEJ is transmitted from signal line ZSAL2.
Then, sub-array block selection driver MLASELDV is activated to turn on transistor TR1. Multiplexer G2 selects the output signal of AND gate G1 on the basis of the control signal received from operation selection driver OPSELDV, and multiplexer G2 transfers the selected signal to main amplifier circuit 24 through transistor TR1 and global bit line GBL. Main amplifier circuit 24 further amplifies the signal and supplies the amplified signal externally through the data path.
Referring to
As for the operation control, when the XOR operation is specified as the operational processing, the activation switching between sense amplifier selection drivers SADV1 and SADV2 is performed according to the path switching of switch DMSW1 while read word lines RWLi and RWLj are maintained in the selected state. Accordingly, the active timing of row drive circuit XDR of row selection driving circuit 22 and the activation timing of sense amplifier SA are set in the same way as in the tenth embodiment.
In the case where buffer BUF1 is selected, the LUT operation can be performed in the same way as in the tenth embodiment. In the case where buffer BUF2 is selected, the inverted value of the output data of sense amplifier SA1 can be produced. Accordingly, the NOT operation, the NOR operation, and the NAND operation can be achieved as the executable operational processing in addition to the OR operation, the AND operation, and the XOR operation. Control circuit 30 that receives command CMD and address ADD performs the operation control for these logical or arithmetic operations.
Referring to
In the case where one storage node SNA in entry i is selected, that is, in the case where the output signal of buffer BUF1 shown in
Assuming that m is the number of operator cell sub-array blocks OAR in operator cell array 10 and n is the number of entries in each operator cell sub-array block OAR in the semiconductor signal processing device, the number of produced data strings is obtained as follows:
m×n×2+m×n×(n−1)÷2×3+m×n×(n−1)×(n−2)÷(3×2)×3.
In the above expression, the first term is the number of combinations in the case where one entry is selected from the n entries in one operator cell sub-array block OAR. The second term is the number of combinations including the selection of the AND operation, OR operation and XOR operation in the case where two entries are selected from the n entries (storage node SNA is selected). The third term is the number of combinations including the selection of the AND operation, OR operation and XOR operation in the case where three entries are selected from the n entries (storage node SNA is selected).
According to the eleventh embodiment, combination logic operational circuit is provided corresponding to each operator sub-array block, and the additional logic operation processing is selectively performed on the output signals of the sense amplifiers. Accordingly, the virtual entry space can further be extended, in addition to the effect of the tenth embodiment.
[Twelfth Embodiment]
In the semiconductor signal processing device according to the twelfth embodiment, a hierarchical word line scheme is applied and any sub-block can be selected by the AND operation of the signals on read word lines RWLA<i>, RWLB<i>, RWLA<1>, RWLB<j>, RWLA<k>, and RWLB<k> and sub-block selection control signals p, q, r, and s.
Particularly, the semiconductor signal processing device shown in
AND gates G10 to G13, GJ0 to GJ3, and GK0 to GK3 are provided corresponding to entries (Entry) i, j, and k, respectively. The AND gates supply the logical product operational results of the signal on read word line RWLA and the signal on read word line RWLB and sub-block selection control signals p, q, r, and s.
Row selection driving circuit 22 activates read driver RWDV (RWADV and RWBDV) corresponding to the entry to be selected, and row selection driving circuit 22 drives the sub-block selection control signal corresponding to the sub-block to be selected in sub-block selection control signals p, q, r, and s to the H level of the selected state, thereby selecting unit operator cells UOE corresponding to the entry in the sub-block to be selected. Accordingly, the entries of the different sub-blocks can be selected in the four entries (Entry<0> to Entry<3>).
The entire configuration of the semiconductor signal processing device shown in
Referring to
Output data DOUT becomes “101010010101110011111000” in the case where entry i (Entry i-A<A>) in sub-block SBLA, entry j (Entry j-A<B>) in sub-block SBLB, entry k (Entry k-A<C>) in sub-block SBLC, and entry l (Entry l-A<D>) in sub-block SBLD are selected.
In the semiconductor signal processing device, it is now assumed that m is the number of operator cell sub-array blocks OAR in operator cell array 10, that n is the number of entries in each operator cell sub-array block OAR, and that the number of sub-blocks is set at four in each operator cell sub-array block OAR. In this condition, the number of produced data string becomes m×n×n×n×n even if the type of the operation such as the AND operation and OR operation is not considered.
For the configuration for selecting unit operator cells for each sub-block to read data from each entry in parallel, the following configuration may be utilized, for example. A latch unit (half latch) for latching the output signal of the H level is provided at the output portion of each of AND gates G10 to G13, GJ0 to GJ3, and GK0 to GK3. For example, the AND gate is formed by the series-connection of an NAND gate and an inverter, and the switching transistor of the input portion of the inverter is put into the on-state to hold the inverter input portion at the L level of the ground voltage (the H-level outputting transistor of the NAND gate is forcedly maintained in the off-state during the latching period) when the output signal of the inverter attains the H level. After the data is read, the input portion of the inverter is forcedly connected to the power supply node in response to a reset signal, the selected row is driven to the non-selected state, and the switching transistor is driven to the off-state.
Sub-block selection signals p, q, r, and s are sequentially activated for a predetermined period of time. During the sub-block activation period, the corresponding read word line is specified in response to the address signal. A sub-entry Entry <i> of the entry specified in each sub-block during the sub-block specified period is maintained in the selected state by the latching function of the sub-block selecting AND gate. Sense amplifiers SA may be driven in parallel to the active state in sub-blocks SBLA to SBLD, or sense amplifiers SA may sequentially be activated in each sub-block specifying period of time. The data of sub-blocks SBLA to SBLD can be supplied in parallel externally by concurrently activating the main amplifiers in the main amplifier circuits. The latching function of sub-block selecting AND gate is reset when the read period is ended. Thus, different unit operator cell rows can be selected for each sub-block.
The case in which the semiconductor signal processing device according to the twelfth embodiment is applied to LUT-based PWM (Pulse Width Modulation) will be described below.
A waveform W2 indicates fine data given by the table having discrete data of a minimum phase pitch Δφ. A waveform W1 indicates coarse data given by the table having discrete data of an appropriate integer multiple of a minimum phase pitch Δφ. In
The target PWM waveform data (waveform W3) can be produced by performing the addition of the fine data and the coarse data. The addition processing is performed outside the device. Accordingly, when the data stored in the entry (sub-block) is signed data, the addition and subtraction can externally be performed according to the sign bit.
The data strings stored in the first entries in sub-blocks SBLA, SBLB, SBLC, and SBLD of sub-memory array MLAI are read in this order and sequentially supplied as data DOUT1. At the same time, the data strings stored in the first entries in sub-blocks SBLA, SBLB, SBLC, and SBLD of sub-memory array MLAK are read at the same time and are supplied as data DOUT2. The data DOUT1 and DOUT2 are added inside or outside the semiconductor signal processing device to produce data P1 to P4 of waveform W3 that is of the PWM waveform.
During reading data DOUT1 in units of sub-blocks, in the non-selected sub-block, the corresponding read word line is in the non-selected state and the data “0” is read. Accordingly, the bit width of the data supplied in each sub-block selection is equal to that of data DOUT2. Alternatively, only in the selected sub-block, sense amplifiers SA and the main amplifiers are activated, and the output data bit positions may be located at the positions corresponding to the selected sub-block.
Then, the data strings stored in the second entries in sub-blocks SBLA, SBLB, SBLC, and SBLD of sub-memory array MLAI are read in this order and sequentially supplied as data DOUT1. At the same time, the data strings stored in the second entries in sub-blocks SBLA, SBLB, SBLC, and SBLD of sub-memory array MLAK are read at the same time and supplied as data DOUT2. The data DOUT1 and DOUT2 are added inside or outside semiconductor signal processing device 103 to produce data P5 to P8 of waveform W3 that is of the PWM waveform.
For the entries equal and subsequent to the third entry, similarly the storage data string is sequentially taken out to complete the PWM waveform data.
The fine data can sequentially be read by sequentially reading the data in units of sub-blocks using an address counter.
Thus, according to the twelfth embodiment of the present invention, the data is selected in units of sub-blocks in the operator cell array, so that the number of virtual entries can be increased. All the bits of the multi-bit PWM data can be produced at each minimum sampling period (Δφ) without increasing the storage capacity.
[Thirteenth Embodiment]
The semiconductor signal processing device shown in
In operator cell sub-array blocks OAR0 to OAR31, a plurality of sense amplifiers SA are arranged in rows and columns as a whole. In sense amplifier band 38, sense amplifier SA is disposed corresponding to bit line pair RBL and ZRBL of a corresponding operator cell sub-array block OAR.
Global bit line GBL is shared by operator cell sub-arrays OAR0 to OAR31, that is, global bit line GBL is provided corresponding to a sense amplifier column, and global bit line GBL is connected to the outputs of sense amplifiers SA of the corresponding column through switches SWOAR. That is, global bit line GBL is provided corresponding to each set of bit line RBL and complementary bit line ZRBL in operator cell sub-array blocks OAR0 to OAR31, and global bit line GBL is connected to the outputs of the plurality of sense amplifiers SA through switches SWOAR in operator cell sub-array blocks OAR0 to OAR31. Each sense amplifier SA is connected to corresponding bit line RBL and to corresponding complementary bit line ZRBL.
In reading the data, switch SWOAR is selectively put into the conductive state in response to the sub-array selection signal. When in the conductive state, switch SWOAR transmits the output signal of corresponding sense amplifier SA to corresponding global bit line RBL. The configuration shown in
Sense amplifier SA compares the current flowing through corresponding bit line RBL and the current flowing through corresponding complementary bit line ZRBL, and supplies the current to corresponding global bit line GBL through switch SWOAR on the basis of the comparison result.
Comparison and amplification circuit GRA senses the current flowing through corresponding global bit line GBL, and produces the signal based on the sensed current amount. That is, comparison and amplification circuit GRA compares the potential at global bit line GBL and a reference voltage VREF3 or VREF4 applied through switch MASW11, to produce the signal to data path 28 based on the comparison result.
In
The reading operation in the case where one operator cell sub-array block OAR0 is selected in the semiconductor signal processing device will be described.
Referring to
On the other hand, in the case where sense amplifier SA produce the output signal of “0” in operator cell sub-array block OAR0 (state ST2), the current flowing through global bit line GBL is decreased, and the potential at global bit line GBL becomes lower than reference voltage VREF3. In this state, comparison and amplification circuit GRA supplies the data “0”. Accordingly, when one operator cell sub-array is selected, the binary signal is produced according to the output signal of sense amplifier SA.
The reading operation in the case where two operator cell sub-array blocks OAR0 and OAR31 are selected in the semiconductor signal processing device will be described.
Referring to
In the case where sense amplifier SA supplies the output signal of “0” in both operator cell sub-array blocks OAR0 and OAR31 (state ST4), current I0+I1 flowing through global bit line GBL becomes the minimum.
In the case where sense amplifier SA supplies the output signal of “0” in one of operator cell sub-array blocks OAR0 and OAR31 while sense amplifier SA supplies the output signal of “1” in the other of operator cell sub-array blocks OAR0 and OAR31 (states ST2 and ST3), the current intermediate between the amount of current flowing through global bit line GBL in state ST1 and the amount of current flowing through global bit line GBL in state ST4 flows through global bit line GBL. Therefore, the potential at global bit line GBL is an intermediate level between the states ST1 and ST4.
Reference voltage VREF3 is set to a level between the potential at global bit line GBL in state ST1 and the potential at global bit line GBL in states ST2 and ST3, and switch MASW11 supplies reference voltage VREF3 to comparison and amplification circuit GRA.
In the state in which reference voltage VREF3 is selected, comparison and amplification circuit GRA supplies the data “1” for state ST1, and comparison and amplification circuit GRA supplies the data “0” for states ST2 to ST4. That is, comparison and amplification circuit GRA produces the AND operational result of the operational results in operator cell sub-array blocks OAR0 and OAR31.
On the other hand, reference voltage VREF4 is set between the potential at global bit line GBL in state ST4 and the potential at global bit line GBL in states ST2 and ST3, and switch MASW11 supplies reference voltage VREF4 to comparison and amplification circuit GRA.
In the state in which reference voltage VREF4 is selected, comparison and amplification circuit GRA produces the data “1” for state ST3, and comparison and amplification circuit GRA outputs the data “0” for state ST3. That is, comparison and amplification circuit GRA produces the OR operational result of the operational results in operator cell sub-array blocks OAR0 and OAR31.
Thus, in the semiconductor signal processing device of the thirteenth embodiment, the OR operation and the AND operation can be performed to the operational results in a plurality of operator cell sub-array blocks.
Entry i in operator cell sub-array block OAR31 and entry k in operator cell sub-array block OAR0 are selected, and reference voltage VREF4 is selected as the reference voltage to perform the AND operation. In such case, data DOUT becomes “0010001000100”.
In the semiconductor signal processing device, assuming that m is the number of operator cell sub-array blocks OAR in operator cell array 10 and n is the number of entries in each operator cell sub-array block OAR, the number of produced data string becomes m×n×2+m×n×2×(m−1)×n×2÷2×2 (one SOI transistor is selected in one unit operator cell UOE).
In the above expression, the first term is the number of combinations, in the case where one operator cell sub-array block OAR is selected from m operator cell sub-array blocks OAR, one entry is selected from the n entries in the selected operator cell sub-array block OAR, and one of SOI transistors NQ1 and NQ2 is selected. The second term is the number of combinations, in the case where two operator cell sub-array blocks OAR are selected from m operator cell sub-array blocks OAR, one entry is selected from the n entries in each of the selected two operator cell sub-array blocks OAR, one of SOI transistors NQ1 and NQ2 is selected, and the AND operation and OR operation on the selected operator cell sub-array blocks are to be selected.
According to the semiconductor signal processing device of the thirteenth embodiment, the combination logic operation can be performed by the potential at the global bit line and the reference voltage without providing the combination logic operational circuit. Therefore, similarly to the twelfth embodiment, the virtual entry space can be expanded without increasing the array area.
Control circuit 30 selects one of reference voltages VREF3 and VREF4 according to the operational contents specified by a command CMD. For the configuration in which the two operator cell sub-array blocks are driven to the selected state , the following configuration may be utilized, by way of example. That is, the least significant bit of the sub-array block address is set at a degenerated state, which allows the adjacent operator sub-array blocks to be concurrently driven to the selected state. In order to concurrently select any operator cell sub-array blocks, a latch circuit is provided for each sub-array block OAR, for latching an operator cell sub-array block selection signal received from a sub-array block decoder when the sub-array block selection signal is in the selected state. Sub-array block addresses are supplied at successive timings and are statically decoded by the sub-array block decoder. The configuration similar to a so-called bank configuration of a bank selection circuit of a memory is used.
[Fourteenth Embodiment]
Operator cell sub-array block OAR that is divided into control field 615a and data field 615b may be disposed at a particular position in operator cell array (20), or all the sub-array blocks may be divided into control field 615a and data field 615b. The configuration of control field 615a and data field 61b can appropriately be defined depending on the application of the device.
The semiconductor signal processing device shown in
Row selection driving circuit 22 selects an entry corresponding to the address signal to read the control flags and data in the selected entry. Based on the decoding result received from controlling decoder 613, row selection driving circuit 22 selectively performs the decoding operation to select one or a plurality of entries in operator cell sub-array block OAR. The operational processing is controlled by utilizing the control flags stored in control field 615a, thereby achieving the high-degree or complicated operational processing.
Other configuration of the semiconductor signal processing device of the fourteenth embodiment is similar to that of the semiconductor signal processing device shown in
Referring to
Referring to
The data having a predetermined pattern and control flags are written in sub-memory array MLA of each operator cell sub-array block OAR (Step SS2). A count value is supplied as the data, and a code for controlling a next behavior performed in the case of a predetermined count value is stored as the control flag. Control flag A specifies a successive counting operation (count-up) in the case of the data “1”. Control flag B specifies repetition of the counting operation from an initial value in the case of the data “1”. Control flag C indicates that the count value reaches a predetermined value. Control flag D is prepared for the counter expansion.
Then, the counting is started from a specified count value. That is, the entry corresponding to an initial address specified by the address signal is selected, and the data and control flag are read from the selected entry (Step SS3). The read data corresponds to the count value.
In the case where the read data reaches the predetermined count value, the corresponding control flag C is set at “1”, the data indicating that read control flag C is set at “1” is supplied to CPU (Central Processing Unit, not shown) (Step SS4) or the like. The external processing unit such as CPU receives control flag C to detect that the count value reaches the predetermined value. In the case where the read data does not reach the predetermined count value, the external processing unit is not informed of control flag C, but the next processing of Step SS5 is performed.
In Step SS5, a determination of the value of control flag B is made. That is, when control flag B in the currently selected entry is set at “0” (NO in Step SS5) and when control flag A is set at “1” (YES in Step SS6), the counter is incremented (Step SS7). The address is updated to select the entry next to the currently selected entry is selected.
When control flag B in the currently selected entry is set at “1” (YES in Step SS5), the count value is reset irrespective of the value of control flag A (Step SS8), and the flow returns to Step SS3 to perform the counting behavior again. The address is reset to the initial value, and the entry corresponding to the initial address is selected to repeat the counting operation.
On the other hand, when control flag B in the currently selected entry is set at “0” (NO in Step SS5), the value of control flag A is referred to (Step SS6). When control flag A is set at “0” (NO in Step SS6), the counting operation is ended.
Accordingly, the count range and counting time duration can be set by the value of the control flag, and the processing such as the monitoring of the number of clock cycles can internally be achieved. In the counting operation, controlling decoder 613 shown in
After the reset (Step SS1), the data and control flag shown in
Then, the counting is started from a specified count value. That is, row selection driving circuit 22 selects an entry corresponding to the specified initial address 0, and the information is read from the data field and control field of the selected entry (Step SS3). In the data string of the entry at the address 0, the data field is “00000001”, control flag A is set at “1”, control flag B is set at “0”, control flag C is set at “0”, and control flag D is set at “0”. For example, control flag D is used as a counting start trigger when an counter is added at the next stage.
Control flag B is set at “0” in the entry corresponding to the currently selected address 0 (NO in Step SS5), and control flag A is set at “1” (YES in Step SS6). Therefore, the count value is incremented (Step SS7). That is, the address corresponding to the address 1 next to the currently selected address 0 is selected to read corresponding contents.
The values of control flags A and B are set at “1” and “0” up to the address 253, and the count value is repeatedly incremented up to the address 254 (Steps SS3 to SS8). The data string is read from the entry specified by the address 254. In reading from the entry corresponding to the address 254, the data field is “11111111”, control flag A is set at “1”, control flag B is set at “1”, control flag C is set at “1”, and control flag D is set at “0”.
The count value is “11111111” that is the predetermined value, and control flag C is set at 1 in the currently selected entry. Therefore, the data indicating that the control flag C is set at 1 is supplied to CPU (not shown) (Step SS4).
Because control flag B is set at “1” in the currently selected entry (YES in Step SS5), the count value is reset (Step SS8). That is, the entry corresponding to the initial address 0 is selected again.
When control flag C is supplied to CPU (not shown) and a predetermined processing is completed in CPU, the address is set at the address 255 to stop the counting operation according to a command supplied from CPU. Entry contents of the address 255 are read. The counting operation is stopped according to the values “0” of control flags A and B in the entry of the address 255. Accordingly, the counting operation can repeatedly be performed to ensure flexibility of the processing according to the processing contents.
In the case where the processing sequence and processing time are determined in advance, control flags A and B of an entry at a certain count value (for example, address 254) are set at “0”, and control flag C is set at “1”. Therefore, the count value reaches the certain value (for example, address 254), the counting operation is stopped and control flag C is applied to inform the external CPU that the predetermined time period elapses. Such counter can be used as a watchdog timer.
Thus, in the semiconductor signal processing device of the fourteenth embodiment, the processing procedure (continuous counting operation and repetition and stop of counting operation) is stored in the LUT calculating unit, and the data reading operation is looped in the LUT calculating unit according to the processing procedure, so that a complicated operation function can be achieved by the counter behavior. Alternatively, when an access to a particular entry is made not through not the counter operation but according to the external address, subsequent processing operation may be stopped.
[Fifteenth Embodiment]
Write word line WWLA is provided corresponding to the unit operator cell column, and write word line WWLA is arranged extending in the Y-direction, that is, write word line WWLA is disposed in parallel to read bit line RBL. Write word line WWLB is provided corresponding to the unit operator cell row, and write word line WWLB is arranged extending in the X-direction, that is, write word line WWLB is arranged orthogonally to read bit line RBL.
In the case where the data is written through write port WPRTA, that is, in the case where the threshold voltage of SOI transistor NQ1 is set, write word line WWLA is driven to the selected state to put SOI transistor PQ1 into the conductive state. In the case where the data is written through write port WPRTB, that is, in the case where the threshold voltage of SOI transistor NQ2 is set, write word line WWLB is driven to the selected state to put SOI transistor PQ2 into the conductive state.
In
High-concentration P-type regions 651c and 651d are arranged in alignment in the Y-direction. An N-type region 652b is arranged between P-type regions 651c and 651d. A P-type region 654b is arranged in alignment with P-type region 651c in the Y-direction.
High-concentration N-type regions 653a, 653b, and 653c are arranged outside the P-type transistor forming region and adjacent to P-type regions 651b, 654a, 654b, and 651c. P-type region 654a is arranged, between N-type regions 653a and 653b, extending from the P-type transistor forming region, and P-type region 654b is arranged, between N-type regions 653b and 653c, extending from the P-type transistor forming region.
A gate electrode interconnection line 655a is arranged, on N-type region 652a, extending in the X-direction, and a gate electrode interconnection line 655b is arranged on P-type region 654a. A gate electrode interconnection 655d is arranged, on N-type region 652b, extending in the X-direction, and a gate electrode interconnection line 655c is arranged on P-type region 654b. In
A first metal interconnection line 656a is arranged continuously extending in the X-direction. A first metal interconnection line 656b is arranged continuously extending in the X-direction, and first metal interconnection line 656b is arranged adjacent to first metal interconnection line 656a and being separated from first metal interconnection line 656a. A first metal interconnection line 656c is arranged continuously extending in the X-direction, and first metal interconnection line 656c is arranged adjacent to first metal interconnection line 656b and being separated from first metal interconnection line 656b. A first metal interconnection line 656d is arranged continuously extending in the X-direction, first metal interconnection line 656d is arranged adjacent to first metal interconnection line 656c and being separated from first metal interconnection line 656c, and first metal interconnection 656d is arranged being aligned with gate electrode interconnection line 655c. A first metal interconnection line 656e is arranged continuously extending in the X-direction, first metal interconnection line 656e is arranged adjacent to first metal interconnection line 656d and being separated from first metal interconnection line 656d, and first metal interconnection line 656e is arranged being aligned with gate electrode interconnection line 655d.
First metal interconnection line 656a is connected to P-type region 651a through a via/contact 658b and an intermediate first interconnect. First metal interconnection line 656b is electrically connected to lower-layer N-type region 653a through a via/contact 658c to constitute source line SL. First metal interconnection line 656c arranged adjacent to gate electrode interconnection line 655b is electrically connected to gate electrode interconnection line 655b in a not shown region to constitute read word line RWLA. First metal interconnection line 656d is electrically connected to gate electrode interconnection line 655c in a not shown region to constitute read word line RWLB. First metal interconnection line 656e is electrically connected to gate electrode interconnection line 655d in a not shown region to constitute write word line WWLB.
Second metal interconnection lines 657a to 657d are arranged in a boundary region of each active region (region where a transistor is formed) and continuously extending along the Y-direction. Second metal interconnection line 657a is electrically connected to N-type region 653c through a via/contact 658e and the intermediate first metal interconnect. Second metal interconnection line 657b is electrically connected to N-type region 653b through a via/contact 658d and the intermediate first interconnect. Second metal interconnection line 657c is connected to P-type region 651d through a via/contact 658f and the intermediate first interconnect. Second metal interconnection line 657d is electrically connected to gate electrode interconnection line 655a through via/contact 658a and the intermediate first interconnect to constitute write word line WWLA.
Second metal interconnection lines 657a and 657b transmit the output data DOUTB and DOUTA through the read ports, respectively. First metal interconnection line 656a and second metal interconnection line 657c transmit input data DINA and DINB through the write ports, respectively. That is, second metal interconnection lines 657a and 657b constitute read ports RPRTB and RPRTA shown in
In the planar layout shown in
That is, P-type region 651c is connected to write port WPRTA, N-type region 653a is connected to source line SL, and N-type region 653b is connected to read port RPRTA. P-type region 654a placed between N-type regions 653a and 653b constitutes the body region of SOI transistor NQ1. P-type region 654a is arranged adjacent to high-concentration P-type region 651b, and P-type regions 651b and 654a are electrically connected to each other. N-type region 652a constitutes the body region of SOI transistor PQ1.
In SOI transistor PQ1, a channel is formed at a surface of body region (N-type region) 652a, whereby charges transmitted from write port WPRTA are transmitted through P-type region 651b to and accumulated in P-type region 654a. The voltage at the body region of SOI transistor NQ1 is set at a voltage level corresponding to the write data, and the threshold voltage of SOI transistor NQ1 is set at a level corresponding to the storage data. N-type region 653b constitutes the pre-charge node, and N-type region 653b is maintained at the voltage level at which the PN junction between regions 654a and 653b is kept non-conductive irrespective of the voltage level of P-type region 654a. Source line SL is usually maintained at the level of power supply voltage VCC to prevent the PN junction between the body region and the source line from being conductive.
In reading the data, the logical high level voltage is applied to the gate electrode interconnection line formed above the body region of SOI transistor NQ1. The voltage applied to the gate electrode selectively forms the channel at the surface of P-type region 654a according to the storage data, and the current flows from source line SL to read port RPRTA according to storage data. The data is read by sensing the current. The charges accumulated in body region (P-type region) 654a are still retained, and the data can be stored in the nonvolatile manner.
It is merely required to sense the amount of current supplied from source line SL according to the threshold voltages of SOI transistors NQ1 and NQ2, so that the data can be read at high speed.
Write driver WWADV drives, to the selected state, a global write word line WWLA<i> corresponding to the column to which unit operator cells UOE to be selected belongs. Write word line driver WWBDV drives, to the selected state, write word line WWLB corresponding to the row to which unit operator cell UOE to be selected belongs. Read driver RWADV and read driver RWBDV drive, to the selected state, read word lines RWLA and RWLB corresponding to the unit operator cell row to be selected.
Global write word line WWLA<i> is arranged for each unit operator cell column and being shared by operator cell sub-array OAR0 to OAR31. As described later, the sub-block selection circuit is arranged for operator cell sub-array OAR, and the data write is performed in the selected sub-array block.
In
AND gate GBS supplies the signal indicating a logical product operational result of the signal on write word line WWLA and the output signal on the sub-array block selection driver BSDV, to local write word line LCWWLA.
Row selection driving circuit 22 enables sub-array block selection driver BSDV corresponding to operator cell sub-array block OAR to be selected, and row selection driving circuit 22 drives local write word line LCWWLA to the selected state in operator cell sub-array block OAR to be selected. Therefore, any operator cell sub-array block can be selected.
In
Data DINB[n:0] is written as the word parallel data in operator cell array 10 using write word line WWLA and data line DINA. The word parallel data is data formed of the bits located at the same bit position of a plurality of words. Using global write word line WWLA and block selection signal, data DINA[n:0] is transferred to data lines DINA, and the data bits are concurrently written in transistors NQ1 of unit operator cells UOE that are aligned in the Y-direction (column direction) in selected sub-array block OARi. Accordingly, write word lines WWLA are sequentially driven to the selected state to write all the data DINA[n: 0], the bits of data word <0> are stored in unit operator cell row <0>, and the bits of data word <1> are stored in unit operator cell row <1>. For example, any data word <0> are written in bit serial manner in SOI transistors NQ1 in unit operator cell row <0> of operator cell sub-array block OAR31.
Read word lines RWLA<0> and RWLB<0> are driven to the selected state, SOI transistors NQ1 and NQ2 in unit operator cell row <0> of operator cell sub-array block OAR31 are selected as the read target, and the AND operation is also selected. In the storage state shown in
SOI transistors NQ1 and NQ2 in unit operator cell row <1> of operator cell sub-array block OAR31 are selected as the read target, and the AND operation is also selected. Therefore, the data string is read as data DOUT[m:0], while odd bits (the unit operator cells in which the mask data bit “0” is written) out of the data string written in the plurality of SOI transistors NQ1 in unit operator cell row <1> are masked.
Selected read word lines RWLA and RWLB are updated, SOI transistors NQ1 and NQ2 in unit operator cell row <2> of operator cell sub-array block OAR31 is selected as the read target, and the AND operation is also selected. The data string written in the plurality of SOI transistors NQ1 in unit operator cell row <2> b is read as data DOUT[m:0] with the upper four bits being masked by the mask bit “0”.
Thus, in the semiconductor signal processing device of the fifteenth embodiment, when the mask bit data string is supplied into the semiconductor signal processing device from the Y-direction while word-parallel data string (DINA[n:0]) is fed into the semiconductor signal processing device from the X-direction, bit-parallel data string (DOUTB[m:0]) is supplied with desired bits being masked in a word serial manner. Thus, in the semiconductor integrated circuit device, a predetermined bit can be masked while the orthogonal transform of the data string is performed.
[Sixteenth Embodiment]
An access transistor of memory cell MCI is formed by impurity regions 702I and 704I and gate electrode 705I. Gate electrode 705I constitutes read word line RWLi. In memory cell MCI, a variable magnetoresistive element (MTJ element) MTJI is provided as a variable resistive element corresponding to and in an upper layer of an access transistor.
Variable magnetoresistive element MTJI includes a fixed layer FXL in which a magnetization direction is fixed, a free layer FRL in which the magnetization direction is changed according to the storage data, and a tunnel burlier layer TBL that is located between fixed layer FXL and free layer FRL. Free layer FRL is connected to bit line BL through an upper electrode UELR. Fixed layer FXL is connected to a local interconnect LII through a lower electrode (not shown). Local interconnect LII is electrically connected to impurity region 702I by plugs 706I and 707I and an intermediate layer interconnect 708I. Below variable magneto-resistive element MTJI, a conductive line 709I is arranged in the same interconnection layer as intermediate layer interconnect 708I. Conductive line 709I constitutes write word line WWLi.
In memory cell MCJ, the access transistor is formed by impurity regions 702J and 704J and gate electrode 705J. Gate electrode 705J constitutes another read word line RWLj.
A variable magnetoresistive element MTJJ is provided above the access transistor forming region of memory cell MCJ. Because variable magnetoresistive element MTJJ has the same configuration as variable magnetoresistive element MTJI, the reference numerals are not allotted. Variable magnetoresistive element MTJJ is electrically connected to impurity region 702J through a local interconnect LIJ, plugs 706J and 707J, and an intermediate layer interconnect 708J.
Below variable magnetoresistive element MTJJ, a conductive line 709J is arranged in the same interconnection layer as an intermediate layer interconnect 708J. Conductive line 709J constitutes write word line WWLj.
In memory cell MCK, the access transistor is formed by impurity regions 702K and 704K and gate electrode 705K. Gate electrode 705K constitutes another read word line RWLk.
A variable magnetoresistive element MTJK is provided above the access transistor forming region of memory cell MCK. Because variable magnetoresistive element MTJK has the same configuration as variable magnetoresistive element MTJI, the reference numerals are not allotted. Variable magnetoresistive element MTJK is electrically connected to impurity region 702K through a local interconnect LIK, plugs 706K and 707K, and an intermediate layer interconnect 708K.
Below variable magnetoresistive element MTJK, a conductive line 709K is arranged in the same interconnection layer as intermediate layer interconnect 708K. Conductive line 709K constitutes write word line WWLk.
Access transistors ATI, ATJ, and ATK are selectively put into the on-state in response to the potentials on read word lines RWLi, RWLj, and RWLk, respectively. Write word lines WWLi, WWLj, and WWLk are physically separated from but magnetically connected to variable magnetoresistive elements MTJI, MTJJ, and MTJK variable magnetoresistive elements MTJI, MTJJ, and MTJK.
The magnetization directions in free layers FRL of variable magnetoresistive elements MTJI, MTJJ, and MTJK are set according to magnetic fields induced by the currents flowing through bit line BL and write word lines WWLi, WWL1, and WWLk.
On the other hand, as shown in
When access transistor AT (ATI, ATJ, and ATK) is in the on-state, the amount of current flowing through bit line BL and source line SL (SLI and SLJ) depends on the resistance values of variable magnetoresistive element MTJ (MTJI, MTJJ, and MTJK). The sense amplifier (not shown) senses the current amount, thereby reading the data stored in memory cell MC (MCI, MCJ, and MCK). For example, the high-resistance state of resistance value Rmax is correlated with the data “0”, and the low-resistance state of resistance value Rmin is correlated with the data “1”.
In writing the data, access transistors ATI, ATJ, and ATK shown in
The data of memory cell MC is set by the magnetization direction in the free layer of the variable magnetoresistive element. The magnetization direction in the free layer is not changed unless a factor inverting the magnetization direction in the free layer is applied externally. Accordingly, the data can be stored in memory cell MC in a nonvolatile manner. The magnetization direction in the free layer FRL is determined by the magnetic field induced by the bit line current and the write word line current, and the current does not flow through a tunnel insulating film or the like in writing the data unlike a flash memory. Accordingly, the problem such as the deterioration of the interlayer insulating film can be avoided, and the number of rewriting times substantially can be made infinite in the variable magnetoresistive element.
The magnetization direction in the free layer of the variable magnetoresistive element depends on the currents flowing through bit line BL and write word line WWL, so that the data can be written at high speed. The data is read according to the amount of current flowing through bit line BL, so that the data can be read at high speed. The data is read according to magnitude of the currents flowing through variable magnetoresistive elements MTJI, MTJJ, and MTJK, and the magnetization directions in the free layers of variable magnetoresistive elements MTJI, MTJJ, and MTJK are not inverted by the read currents. Accordingly, the data is read in a nondestructive manner, the restoring operation is eliminated unlike the DRAM cell and the ferroelectric capacitor, and a data read cycle can be shortened.
In the sixteenth embodiment, the characteristic feature of the MRAM cell is utilized to perform the operational processing using the data stored in the memory cells and the amplifying operation of a sense amplifier (not shown).
Read word line RWLi and write word line WWLi are provided corresponding to memory cells MCI1 and MCI2, read word line RWLj and write word line WWL1 are provided corresponding to memory cells MCJ1 and MCJ2, and read word line RWLk and write word line WWLk are provided corresponding to memory cells MCK1 and MCK2. A source line SLi extending in a row direction is provided for memory cells MCI1 and MCI2. A source line SLI extending in the row direction is provided corresponding to memory cells MCJ1 and MCJ2. A source line SLk extending in the row direction is provided corresponding to memory cells MCK1 and MCK2. Source lines SLi, SLj, and SLk are connected to the ground node through a common source line SLCM.
Bit line BL is arranged corresponding to a memory cell column, and two dummy cells DMCA and DMCB are provided corresponding to each memory cell column. That is, bit line BL1 is arranged for memory cells MCI1, MCJ1, and MCK1, and dummy cells DMCA1 and DMCB1 are connected to bit line ZBL1 paired with bit line BL1. Bit line BL2 is arranged for memory cells MCI2, MCJ2, and MCK2, and dummy cells DMCA2 and DMCB2 are connected to bit line ZBL2 paired with bit line BL2.
A dummy read word line DRWL1, a dummy write word line DWWL1, and a dummy source line DSL1 are provided corresponding to dummy cells DMCA1 and DMCA2. A dummy read word line DRWL2, a dummy write word line DWWL2, and a dummy source line DSL2 are provided corresponding to dummy cells DMCB1 and DMCB2
Dummy source line DSL1 for dummy cells DMCA1 and DMCA2 is connected through switch MSW1 to reference voltage node VREF1 to which reference voltage VREF1 is supplied or reference voltage node VREF3 to which reference voltage VREF3 is supplied.
Dummy source line DSL2 for dummy cells DMCB1 and DMCB2 is connected through switch MSW2 to reference voltage node VREF2 to which reference voltage VREF2 is supplied or reference voltage node VREF4 to which reference voltage VREF4 is supplied. Dummy cells DMCA1, DMCA2, DMCB1, and DMCB2 are set at the low-resistance state, and dummy cells DMCA1, DMCA2, DMCB1, and DMCB2 have the resistance value Rmin.
A determination on which of reference voltage nodes VREF1 and VREF3 is connected to dummy source line DSL1 and a determination on which of reference voltage nodes VREF2 and VREF4 is connected to dummy source line DSL2 are made based on the type of an operation to be performed on the data read from memory cell MC as described later. Because the MRAM cell is used as the memory cell, reference voltages VREF1 to VREF4 are set at voltage levels that are different from the reference voltage level of the unit operator cell in which a TTRAM cell is used. The voltage levels of reference voltages VREF1 to VREF4 in the sixteenth embodiment is described later along with a specific operation.
Bit lines BL and ZBL are provided corresponding to the column of dummy cells DMC and the column of memory cells MC. Memory cells MCI1, MCJ1, and MCK1 are connected to bit line BL1 in parallel, and dummy cells DMCA 1 and DMCB1 are connected to complementary bit line ZBL1. Memory cells MCI2, MCJ2, and MCK2 are connected to bit line BL2 in parallel, and dummy cells DMCA2 and DMCB2 are connected to complementary bit line ZBL2.
Read drivers RWDVI, RWDVJ, and RWDVK are provided at first ends of read word lines RWLi, RWLj, and RWLk, respectively. Read drivers DRWDV1 and DRWDV2 are provided at first ends of dummy word lines DRWL1 and DRWL2, respectively. Write drivers WWDVI, WWDVJ, and WWDVK are provided at first ends of write word lines WWLi, WWLj, and WWLk, respectively. Write drivers DWWDV1 and DWWDV2 are provided at first ends of dummy write word lines DWWL1 and DWWL2.
In reading data, read drivers RWDVI, RWDVJ, RWDVK, DRWDV1, and DRWDV2 drive the corresponding read word lines to the selected state. In writing data, write drivers WWDVI, WWDVJ, WWDVK, DWWDV1, and DWWDV2 drive the corresponding write word lines to the selected state.
Sense amplifier SA1 is provided at first ends of bit lines BL1 and ZBL1. Write drivers WDVA1 and WDVA2 are provided at both (first and second) ends of bit line BL1, and write drivers DWDVA1 and DWDVA2 are provided at first and second ends of complementary bit line ZBL1. In writing data, write drivers WDVA1 and WDVA2 bi-directionally pass the currents through bit line BL1 according to complementary data D and /D. Similarly, write drivers DWDVA1 and DWDVA2 bi-directionally pass the currents through complementary bit line ZBL1 according to complementary data DD and /DD. Write drivers WDVA1, WDVA2, DWDVA1, and DWDVA2 are each formed by a bi-directional driver, so that the currents can bi-directionally pass through bit lines BL1 and ZBL1 according to the write data, to write data in memory cells MCI1, MCJ1, and MCK1.
Similarly, sense amplifier SA2 is provided at first end of bit lines BL2 and ZBL2. Write drivers WDVB1 and WDVB2 are provided at first and second opposite ends of bit line BL2, and write drivers DWDVB1 and DWDVB2 are provided at first and second opposite ends of complementary bit line ZBL2. In data writing, write drivers WDVB1 and WDVB2 bi-directionally pass the currents through bit line BL2 according to complementary data D and /D. Similarly, write drivers DWDVB1 and DWDVB2 bi-directionally pass the currents through complementary bit line ZBL2 according to complementary data DD and /DD. Write drivers WDVA1, WDVA2, DWDVA1, and DWDVA2 are each formed by a bi-directional driver, so that the currents can bi-directionally flow through bit lines BL2 and ZBL2 according to the write data, to write data in memory cells MCI2, MCJ2, and MCK2.
However, because dummy cell DMC is set at the low-resistance state, the supplying direction of the current is fixed in write drivers DWDVA1, DWDVA2, DWDVB1, and DWDVB2 that are provided corresponding to complementary bit line ZBL, and it is not particularly required for write drivers DWDVA1, DWDVA2, DWDVB1, and DWDVB2 to bi-directionally supply the currents.
Sense amplifier SA, pair of write drivers WDV, and pair of write drivers DWDV are provided for each bit line pair. It is sufficient to use a write driver in a general MRAM as the write driver WDV. In the case where data are written for each memory cell row, it is not necessary to apply the column selection signal to the write drivers. In the case where data are sequentially written in each bit line, the write driver of the selected column is enabled by the column selection signal.
The reason why dummy source lines DSL1 and DSL2 of dummy cells DMCA1, DMCA2, DMCB1, and DMCB2 are connected to reference voltage nodes VREF1 to VREF4, not to the ground node will be described below. In data reading, in the case where the voltages VREF1 to VREF4 at the reference voltage nodes are set at desired values, the amounts of currents flowing through dummy cells DMCA1, DMCA2, DMCB1, and DMCB2 can be set to an intermediate value among the currents flowing through memory cells MCI, MCJ, and MCK or to a higher value than those.
During the operational processing, as described in detail later, memory cells MCI, MCJ, and MCK are concurrently selected, and the currents corresponding to the data stored in memory cells MCI, MCJ, and MCK flow through bit line BL. The voltage levels of reference voltages VREF1 to VREF4 are adjusted with respect to the combined current on bit line BL, to adjust the dummy cell current flowing through complementary bit line ZBL, for performing a necessary operation.
In writing data, memory cells MCI, MCJ, and MCK are sequentially selected, and the data is written by pair of write drivers WDV. In reading data, read word lines RWLi, RWLj, and RWLk are concurrently driven to the selected state, and variable magnetoresistive elements MTJI, MTJJ, and MTJK of memory cells MCI, MCJ, and MCK are concurrently connected to bit line BL.
The data reading operation in the case where one memory cell row <i> is selected in the semiconductor signal processing device shown in
In writing data, a plurality of memory cells MCI corresponding to memory cell row <i> are concurrently selected to set the resistance state of each variable magnetoresistive element MTJI. That is, in writing the data, write word line WWL<i> is selected, and the current is supplied in the direction corresponding to the write data through bit line BL of a selected column using a pair of write drivers WDV arranged at both ends of bit line BL of the selected column. In this operation, the current is passed in a constant direction in write word line WWLI irrespective of the logical value of the write data, and write word line WWLI is physically separated from memory cell. Therefore, data may concurrently be written in the memory cells of the selected row <i>.
In reading data, the plurality of memory cells MCI on memory cell row <i> are selected, and variable magnetoresistive elements MTJI are concurrently connected to corresponding bit lines BL. Sense amplifier SA supplies the current to each bit line. Accordingly, in reading the data, the read current of sense amplifier SA flows from bit line BL to source line SL through each variable magnetoresistive element MTJI according to the data stored in the memory cell.
In dummy cells DMCA and DMCB on each memory cell column, one dummy cell is selected in the data reading. That is, one of dummy read word lines DRWL1 and DRWL2 is selected. Dummy cells DMCA and DMCB are in the low-resistance state L (Rmin), and dummy cells DMCA and DMCB have the resistance value Rmin. The amount of current flowing through dummy cells DMCA and DMCB is adjusted by selecting the voltage levels of reference voltages VREF1 to VREF4. The case will be described below, in which dummy read word line DRWL1 is selected, dummy cell DMCA is selected, and dummy cell DMCA is connected to reference voltage node VREF1 by switch MSW.
When memory cell MCI is in state S(0), memory cell MCI (variable magnetoresistive element MTJI) is in the high-resistance state in which the current flowing through memory cell MCI becomes the minimum. In such case, the decreasing speed in potential at bit line BL is the slowest.
In state S(1), memory cell MCI (variable magnetoresistive element MTJI) is in the low-resistance state in which a large amount of current flows from bit line BL to source line SL. Accordingly, the potential at the bit line largely lowers at the fastest speed.
Dummy cell DMCA is in the low-resistance state L (Rmin), and the source line of memory cell MCI is maintained at the ground voltage level. Reference voltage VREF1 is set at the voltage level not lower than the ground voltage, whereby the current passing through dummy cell DMCA is larger than the current passing through bit line BL in state S(0) and smaller than the current passing through bit line BL in state S(1). Accordingly, in selecting dummy cell DMCA, the potential at complementary bit line ZBL can be set at the state between state S(0) and state S(1). In this state, current Id1 passing through dummy cell DMCA can be expressed as follows.
I1>Id1>Ih.
Here, Ih is a current passing through memory cell MC in the high-resistance state and I1 is a current passing through memory cell MC in the low-resistance state.
Sense amplifier SA differentially amplifies the currents of bit lines RBL and ZRBL to read the data stored in memory cells MCI. In sense amplifier SA, the binary determination of the bit line current is made with the current passing through dummy cell DMC being the reference value. Accordingly, the output of sense amplifier SA indicates the logical value of one-bit data stored in memory cells MCI.
As shown in
In a state S(1), memory cell MCI is in low-resistance state L (Rmin), and the data “1” is stored in memory cell MCI. As shown in
Accordingly, the sense amplifier outputs the NOT operational result of the data stored in memory cells MCI.
The read operation in the case where two memory cell rows <i> and <1> are selected concurrently in semiconductor signal processing device 101 will be described below.
In a state S(0,1), variable magnetoresistive elements MTJI and MTJJ are in high-resistance state H (Rmax) and low-resistance state L (Rmin), respectively. In a state S(1,1), both variable magnetoresistive elements MTJI and MTJJ are in low-resistance state L (Rmin).
In writing data, a plurality of memory cells MCI on memory cell row <i> and a plurality of memory cells MCJ corresponding to memory cell row <j> are separately selected to set the resistance state of each variable magnetoresistive element MTJI and the resistance state of each variable magnetoresistive element MTJJ. That is, in writing the data, write word lines WWL<i> and WWL<j> are sequentially selected, and the current is supplied through bit line BL in the direction corresponding to the write data using a pair of write drivers WDV arranged at both ends of each bit line BL shown in
In reading data, the plurality of memory cells MCI corresponding to memory cell row <i> and the plurality of memory cells MCJ corresponding to memory cell row <j> are concurrently selected, and a set of variable magnetoresistive elements MTJI and a set of variable magnetoresistive element MTJJ are concurrently connected to corresponding bit lines BL. Accordingly, in reading the data, combined currents of the current passing through the set of variable magnetoresistive element MTJI and the current passing through the set of variable magnetoresistive element MTJJ pass through the respective bit lines BL.
In dummy cells DMCA and DMCB of a memory cell column, one dummy cell is selected during the data reading. That is, one of dummy read word lines DRWL1 and DRWL2 is selected. Dummy cells DMCA and DMCB are in low-resistance state L (Rmin), and therefore have resistance value Rmin. The amounts of currents passing through dummy cells DMCA and DMCB are adjusted by selecting the voltage levels of reference voltages VREF1 to VREF4.
When memory cells MCI and MCJ are in a state S(0,0), both memory cells MCI and MCJ are in the high-resistance state, and the currents passing through memory cells MCI and MCJ become the minimum. In such case, the decreasing speed in potential at bit line BL becomes the slowest. In reading data, bit lines BL and ZBL are pre-charged to a predetermined voltage level (read voltage level) by the sense amplifier.
In a state S(1,1), both memory cells MCI and MTJJ are in the low-resistance state in which a large amount of current flows from bit line BL to source line SL. Accordingly, the potential at the bit line is largely decreased at the fastest speed.
States S(1,0) and S(0,1) are a combination of the high-resistance state and the low-resistance state, and the current intermediate between the currents passing through the bit line in states S(0,0) and S(1,1) flows. Accordingly, in states S(1,0) and S(0,1), the bit-line read potential lies between the potentials in states S(0,0) and S(1,1).
Both dummy cells DMCA and DMCB are in the low-resistance state L (Rmin), and the source lines of memory cells MCI and MCJ are maintained at the ground voltage level. Reference voltage VREF1 is selected as reference voltage VREF, and reference voltage VREF1 is set at the voltage level not lower than the ground voltage. Dummy cell DMCA is selected as the dummy cell. Therefore, the current passing through dummy cell DMCA is larger than the current passing through bit line BL in state S(0,0) and smaller than the current passing through bit line BL in states S(0,1) and S(1,0). Accordingly, in selecting dummy cell DMCA, the potential at complementary bit line ZBL can be set at a level between those in state S(0,0) and states S(0,1) and S(1,0). In this state, current Id1 passing through dummy cell DMCA can be expressed as follows.
I1>Id1>Ih,
2×Ih<Id1<Ih+I1
Where Ih is a current passing through memory cell MC in the high-resistance state and I1 is a current passing through memory cell MC in the low-resistance state.
The case will be described below, in which dummy read word line DRWL2 is selected, dummy cell DMCB is selected, and dummy cell DMCB is connected to reference voltage node VREF2 through switch MSW2.
In the case where dummy cell DMCB is selected and reference voltage VREF2 is set at a negative voltage, the current that is larger than the current passing through one memory cell MC in the low-resistance state can be caused to flow through complementary bit line ZBL. Accordingly, in selecting dummy cell DMCB, the potential at complementary bit line ZBL can be set at a level between those in states S(1,0) and S(0,1) and state S(1,1). In this state, current Id2 passing through dummy cell DMCB can be expressed as follows.
I1<Id2,
2×IL>Id2>Ih+I1
Sense amplifier SA differentially amplifies the currents of bit lines RBL and ZRBL to read the data stored in memory cells MCI and MCJ. In sense amplifier SA, the binary determination on the bit line current is made with the current passing through dummy cell DMC being the reference value. Accordingly, the output of sense amplifier SA indicates one of two classifications into which the combination of data of two bits stored in memory cells MCI and MCJ is bi-classified on the basis of the reference voltage, so that the logic operation can be performed on the data stored in memory cells MCI and MCJ by sense amplifier SA.
As shown in
In state S(1,0) and state S(0,1), one of memory cells MCI and MCJ is in high-resistance state H (Rmax) while the other is in low-resistance state L (Rmin). Accordingly, in the case where the reference voltage VREF1 is selected, the current passing through bit line BL is larger than the current passing through complementary bit line ZBL, and the potential at bit line BL is lower than the potential at complementary bit line ZBL. Therefore, the output signal of the sense amplifier attains “0”. In the case where reference voltage VREF2 is selected, the current passing through bit line BL is smaller than the current passing through complementary bit line BL, and the potential at bit line BL is higher than the potential at complementary bit line ZBL. Therefore, the output signal of the sense amplifier attains “1”.
In a state S(1,1), both memory cells MCI and MCJ are in low-resistance state L (Rmin), and the data “1” is stored in memory cells MCI and MCJ. In this state, even if any of reference voltage VREF1 and reference voltage VREF2 is selected, as shown in
As shown in
The cross-coupled latch sense amplifier may be used as the sense amplifier. However, the cross-coupled latch sense amplifier is a voltage sensing type sense amplifier, which amplifies the difference in potential between bit lines BL and ZBL. Accordingly, it is preferable to use the current sensing type sense amplifier as the sense amplifier in order to perform the sensing operation at high speed.
The behavior of sense amplifier SA shown in
During the sensing operation, before a read word line is selected, sense amplifier activation signal /SE is activated to set MOS transistors PP7 and NN7 at the on-state. Accordingly, node ND1 is connected to the power supply node to make MOS transistors PP1 and PP6 operative, and bit lines BL and ZBL are charged. In this operation, sense amplifier activation signal SE may concurrently be activated. The activation of sense amplifier activation signal SE may be delayed until the sensing operation is started. Read word line RWL is still in the non-selected state, and bit lines BL and ZBL are pre-charged to a predetermined voltage level according to the currents supplied from MOS transistors NN1 and NN6.
When the pre-charging operation is completed, the read word line is driven to the selected state. In this state, sense amplifier activation signal SE is already activated. Therefore, cell current Icell corresponding to the storage data passes from bit line BL to the source line through the selected memory cell. Dummy cell current Idummy is passed through complementary bit line ZBL by the dummy cell. Currents Icell and Idummy are supplied by MOS transistors PP1 and PP6, respectively, the mirror current of the current passing through MOS transistor PP1 passes through MOS transistors PP2 and PP3, and the mirror current of the current passing through MOS transistor PP6 passes through MOS transistors PP4 and PP5. Accordingly, the mirror currents of cell current Icell and dummy cell current Idummy passing through the bit lines flow through MOS transistors NN2 and NN5, respectively.
In the case where cell current Icell is larger than dummy cell current Idummy, intermediate sense output signal /SOT attains the logical high level (intermediate voltage level) while intermediate sense output signal SOT attains logical low level (intermediate voltage level) through the current-voltage conversion operation of MOS transistors NN2 and NN5. On the contrary, in the case where cell current Icell is smaller than dummy cell current Idummy, intermediate sense output signal /SOT attains the logical low level while intermediate sense output signal SOT attains the logical high level. Subsequent-stage final amplifying circuit SMP further amplifies the intermediate sense output signals SOT and /SOT to produce final sense output signals SOUT and /SOUT at the power supply voltage level and ground voltage level.
The smaller current between cell current Icell and dummy cell current Idummy flows through MOS transistors PP3 and NN4, and the smaller current between dummy cell current Idummy and cell current Icell also passes through MOS transistors PP4 and NN3. The sum of the total current of the cell current Icell and dummy cell current Idummy and the current that is double the smaller current between dummy cell current Idummy and cell current Icell always passes through MOS transistor NN7. Accordingly, in cases where one-bit cell data is read to make the binary determination, MOS transistors PP3, PP4, NN3, and NN4 have a function of keeping the current passing through MOS transistor NN7 constant in order to stabilize the sensing operation.
However, similarly to the configuration shown in
As described above, sense amplifier SA produces the signals indicating the NOR operational result and NAND operational result of the data stored in a plurality of memory cells. In the case where the data stored in the memory cell is read without changing the logical value of the data, and in the case where the sense amplifier produces the OR operational result and AND operational result, main amplifier circuit 24 or data path 28 may invert the sense output signal shown in
The level of dummy cell current Idummy is adjusted using reference voltages VREF1 to VREF4, which allows the NOR operation and NAND operation of two data to be selectively performed.
The reading operation in the case where three memory cell rows <i>, <j>, and <k> are selected in semiconductor signal processing device 101 will be described below.
In writing data, a plurality of memory cells MCI corresponding to memory cell row <i>, a plurality of memory cells MCJ corresponding to memory cell row <j>, and a plurality of memory cells MCK corresponding to memory cell row <k> are separately selected in units of rows or memory cells to set the resistance states of each variable magnetoresistive element MTJI, the resistance state of each variable magnetoresistive element MTJJ, and each variable magnetoresistive element MTJK. That is, in writing the data, write word lines WWL<i>, WWL<j>, and WWL<k> are sequentially selected, and the current is supplied through each bit line BL in the direction corresponding to the write data using a pair of write drivers WDV arranged at both ends of bit line BL shown in
In reading the data, the plurality of memory cells MCI corresponding to memory cell row <i>, the plurality of memory cells MCJ corresponding to memory cell row <j>, and the plurality of memory cells MCK corresponding to memory cell row <k> are concurrently selected, and sets of variable magnetoresistive elements MTJI, variable magnetoresistive element MTJJ, and variable magnetoresistive element MTJK are concurrently connected to the respective bit lines BL. Accordingly, in reading the data, a combined current of the currents passing through the set of variable magnetoresistive element MTJI, variable magnetoresistive element MTJJ and variable magnetoresistive element MTJK passes through a corresponding bit line BL.
In dummy cells DMCA and DMCB of the memory cell column, one dummy cell is selected during the data reading. That is, one of dummy read word lines DRWL1 and DRWL2 is selected. Dummy cells DMCA and DMCB are in low-resistance state L (Rmin), and dummy cells DMCA and DMCB have resistance value Rmin. The amounts of currents passing through dummy cells DMCA and DMCB are adjusted by selecting the voltage levels of reference voltages VREF1 to VREF4. The case will be described below, in which dummy read word line DRWL1 is select to select dummy cell DMCA connected to reference voltage node VREF3 through switch MSW1.
When memory cells MCI, MCJ, and MCK are in state S(0,0,0), variable magnetoresistive elements MCI, MCJ, and MCK are in high-resistance state, and the currents passing through memory cells MCI, MCJ, and MCK each become the minimum. In such case, the decreasing speed in potential at bit line BL becomes the slowest. In reading the data, bit lines BL and ZBL are pre-charged to a predetermined voltage level (read voltage level) by the sense amplifier.
In a state S(1,1,1), memory cells MCI, MCJ, and MCK are in the low-resistance state in which a large amount of current flows from bit line BL to source line SL. Accordingly, the potential at the bit line largely lowers at the fastest speed.
In states S(1,0,0), S(0,1,0), and S(0,0,1), two of memory cells MCI, MCJ, and MCK are in the high-resistance state and the other is in the low-resistance state. In such case, the current intermediate between the currents passing through the bit line in states S(0,0,0) and S(1,1,1) flows. Accordingly, in states S(1,0,0), S(0,1,0), and S(0,0,1), the bit-line read potential lies between the potentials in states S(0,0,0) and S(1,1,1).
In states S(1,1,0), S(1,0,1), and S(0,1,1), two of memory cells MCI, MCJ, and MCK are in the low-resistance state , and the other one is in the high-resistance state. In such case, the current intermediate between the currents passing through the bit line in states S(0,0,0) and S(1,1,1) flows, and the bit line current becomes larger than that in states S(1,0,0), S(0,1,0), and S(0,0,1). Accordingly, in states S(1,0,0), S(0,1,0), and S(0,0,1), the bit-line read potential lies between the potentials in states S(1,0,0), S(0,1,0), and S(0,0,1) and the potential in state S(1,1,1).
Both dummy cells DMCA and DMCB are in the low-resistance state L (Rmin), and the source lines of memory cells MCI, MCJ, and MCK are maintained at the ground voltage level. Reference voltage VREF1 is selected as reference voltage VREF, and is set at the voltage level not lower than the ground voltage. Because reference voltage VREF1 is at the voltage level not lower than the ground voltage, the current passing through dummy cell DMCA is larger than the current passing through bit line BL in state S(0,0,0) and smaller than the current passing through bit line BL in states S(1,0,0), S(0,1,0), and S(0,0,1). Accordingly, in selecting dummy cell DMCA, the potential at complementary bit line ZBL can be set at a level between those in state S(0,0,0) and states S(1,0,0), S(0,1,0) and S(0,0,1). In this state, current Id1 passing through dummy cell DMCA can be expressed as follows.
I1>Id1>Ih,
3×Ih<Id1<2×Ih+I1
Where Ih is a current passed through memory cell MC in the high-resistance state and I1 is a current passing through memory cell MC in the low-resistance state.
The case will be described below, in which dummy read word line DRWL2 is selected, dummy cell DMCB is selected, and dummy cell DMCB is connected to reference voltage node VREF4 through switch MSW2.
In the case where dummy cell DMCB is selected and reference voltage VREF4 is set at a negative voltage, the current that is larger than the current passing through one memory cell MC in the low-resistance state can be caused to flow through complementary bit line ZBL. Accordingly, in selecting dummy cell DMCB, the potential at complementary bit line ZBL can be set at a level between those in states S(1,1,0), S(1,0,1) and S(0,1,1) and state S(1,1,1). In this state, current Id2 passing through dummy cell DMCB can be expressed as follows.
I1<Id2,
3×I1>Id2>Ih+2×I1.
Sense amplifier SA differentially amplifies the currents of bit lines RBL and ZRBL to read the data stored in memory cells MCI, MCJ, and MCK. In sense amplifier SA, the binary determination of the bit line current is made with the current passing through dummy cell DMC being the reference value. Accordingly, the output of sense amplifier SA indicates one of two classifications into which the combination of data of three bits stored in memory cells MCI, MCJ, and MCK is classified on the basis of the reference voltage, so that the logic operation can be performed on the data stored in memory cells MCI, MCJ, and MCK by sense amplifier SA.
As shown in
In states S(1,0,0), S(0,1,0), S(0,0,1), S(1,1,0), S(1,0,1), and S(0,1,1), at least one of memory cells MTJI, MTJJ, and MTJK is in low-resistance state L (Rmin). Accordingly, in the case where the reference voltage VREF3 is selected, the current passing through bit line BL is larger than the current passing through complementary bit line ZBL, and the potential at bit line BL is lower than the potential at complementary bit line ZBL. Therefore, the output signal of the sense amplifier attains “0”. In the case where reference voltage VREF4 is selected, the current passing through bit line BL is smaller than the current passing through complementary bit line BL, and the potential at bit line BL is higher than the potential at complementary bit line ZBL. Therefore, the output signal of the sense amplifier attains “1”.
In a state S(1,1,1), memory cells MTJI, MTJJ, and MTJK are in low-resistance state L (Rmin), and the data “1” is stored in memory cells MTJI, MTJJ, and MTJK. In this state, even if any of reference voltages VREF3 and reference voltage VREF4 is selected, as shown in
As shown in
In the semiconductor signal processing device of the sixteenth embodiment, two dummy cells DMC are described to be provided in each memory cell column. However, the present invention is not limited to such arrangement. Alternatively, one dummy cell DMC may be provided in each memory cell column, and switch MSW connected to dummy cell DMC may selectively connect one of reference voltage nodes VREF1 to VREF4 to dummy cell DMC.
Thus, the operation similar to the LUT operation of the tenth to fifteenth embodiments can be performed using the MRAM cells. The entire configuration of the semiconductor signal processing device of the tenth to fifteenth embodiments can be used for the semiconductor signal processing device of the sixteenth embodiment by replacing unit operator cell UOE with memory cell MC.
When the processing for reading the inverted signal of output signal SOUT of sense amplifier SA is performed on the data string of entry i using the operation shown in
When the NAND operational processing shown in
When the NAND operational processing shown in
Accordingly, when the operations are selectively performed, the number of entries disposed in the memory cell sub-array can equivalently be increased, and the virtual entry space can be expanded as in the tenth embodiment. The operation to be performed can be specified by a control command that is supplied along with the address or a particular address bit.
The MRAM cell used in the sixteenth embodiment can be applied to the configurations of the first embodiment to ninth embodiments (MRAM memory cell is used instead of unit operator cell UOE).
[Seventeenth Embodiment]
The unit operator cell has the configuration similar to that of unit operator cell UOE shown in
The semiconductor signal processing device includes an ADC band 812, a data path 814, and a cell selection driving circuit 816. ADC zone 812 converts the data (current) read from a selected sub-array block into a digital signal. Data path 814 performs the data inputting and outputting. Cell selection driving circuit 816 drives the memory cells of sub-array blocks BK0 to BKs to the selected state, and cell selection driving circuit 816 controls the data writing and reading.
Each sub-array blocks BK0 to BKs is divided into a plurality of operation unit blocks. In each operation unit block, ADC band 812 includes an analog/digital converter (A/D converter: ADC) for converting an analog signal into a digital signal. ADC performs an addition of current information according to the storage data read from memory cells in an analog manner, and converts the added current value into a digital signal.
In reading data, data path 814 transfers the digital information produced by ADC band 812 to an outside of the device. In writing data, data path 814 produces internal write data such that each data bit of applied multi-bit numerical data is transferred to unit operator cells corresponding in number to a weight of each bit position.
Cell selection driving circuit 816 concurrently selects the unit operator cells of a plurality of columns in the selected sub-array block, and cell selection driving circuit 816 performs data writing and reading (write word line WWL and read word lines RWLA and RWLB are driven to the selected state). In the semiconductor signal processing device, control circuit 818 performs an internal operation control.
As shown in
As described in detail later, the information stored in the unit operator cells is read in the form of the current, so that the data can be read at high speed even under the low power supply voltage.
Cell sub-array 820 further includes a dummy cell area 821. In dummy cell area 821, dummy cell DMC is arranged corresponding to each unit operator cell column, and is connected to a complementary bit line ZBL on a corresponding column. Read word lines RWLA and RWLB and write word line WWL are arranged corresponding to each row of unit operator cells UOE. Although the read word line and the write word line are also arranged for dummy cell DMC, these read word line and the write word line are not shown in
Sub-array block BKi includes a sense amplifier band 822, a port connection circuit 823, and a read gate circuit 824. Sense amplifier band 822 reads the data stored in the selected memory cells. Port connection circuit 823 establishes the connection state between A- and B-read ports of the unit operator cell and sense amplifier band 822. Read gate circuit 824 transfers the data current read by sense amplifier band 822 to ADC band 812 shown in
In sense amplifier band 822, the sense amplifier circuit is provided corresponding to each pair of bit lines BL (RBLA and RBLB) and ZBL, and the sense amplifier circuit produces the internal read data by differentially amplifying the currents passing through read bit line RBLA or RGLB and the complementary read bit line ZBL. Although the sense amplifier circuit will be described in detail later, the sense amplifier circuit has the configuration similar to that of the sense amplifier circuit shown in
Port connection circuit 823 includes a connection switch that is provided corresponding to each set of read bit lines RBLA and RBLB, and connects one of A-port read bit line RBLA and B-port read bit line BLB to the corresponding sense amplifier circuit of sense amplifier band 822 in response to a port specification signal (not shown).
Read gate circuit 824 includes a read gate that is provided corresponding to each sense amplifier circuit in sense amplifier zone 822, and transfers the current information produced by sense amplifier band 822 to ADC band 812 shown in
In
Read bit lines RBLA1 and RBLB1 and global write data lines WGLB1 and WGLA1 are provided corresponding to unit operator cells UOE01, . . . , UOEk1. Global write data lines WGLA1 and WGLB1 are connected to write ports WPRTA and WPRTB of each of unit operator cells UOE01, . . . , and UOEk1, respectively. Read ports RPRTA and RPRTB of each of unit operator cells UOE01, . . . , and UOEk1 are connected to read bit lines RBLA1 and RBLB1, respectively.
Write word line WWL0 and read word lines RWLA0 and RWLB0 are provided corresponding to unit operator cells UOE00 and UOE01, and write word line WWLk and read word lines RWLAk and RWLBk are provided corresponding to unit operator cells UOEk0 and UOEk1.
Dummy cell DMC0 is arranged for unit operator cells UOE00 and UOEk0, and dummy cell DMC1 is arranged for unit operator cells UOE01, . . . , UOEk1. In
Reference voltage Vref supplied from reference voltage source Vref (power source and supply voltage are designated by the same reference symbol) supplies a current intermediate the currents which SOI transistors NQ1 and NQ2 included in unit operator cell UOE00 supply when in a high threshold voltage state and when in the low threshold voltage state.
In port connection circuit 823, similarly to the configuration shown in
Port connection switch PPSW1 is provided corresponding to read bit lines RBLA1 and RBLB1, and connects the read bit line of a specified port to a corresponding sense amplifier circuit SAK1 through sense read bit line RBL1 in response to port selection signal PRMX.
Port selection signal PRMX is a multi-bit selection signal and therefore, the connection path can be established for each group of a predetermined number of bit line pairs.
Port connection switches PRSW1 and PRSW2 have the configuration similar to that of the port connection switch shown in
Switching transistors (NT2 and NT3) are put into the non-conductive state when port selection signals /PRMXB and /PRMXA are activated (at the L level), respectively. That is, a specified read port RPRTA or RPRTB is connected to sense amplifier circuit SAK in response to port selection signals /PRMXA and /PRMXB corresponding to port selection signal PRMX, respectively. When read port RPRTA is specified, A-port read bit line RBLA is connected to sense read bit line RBL in response to port selection signal /PRMXA. When read port RPRTB is specified, port selection signal /PRMXA is inactivated, port selection signal /PRMXB is activated, and B-port read bit line RBLB is connected to sense read bit line RBL.
In read gate circuit 822, read gates CSG0 and CSG1 are provided corresponding to sense amplifier circuits SAK0 and SAK1, and read gates CSG0 and CSG1 supply the currents corresponding to the sense data supplied by sense amplifier circuits SAK0 and SAK1 to corresponding global read data lines RGL0 and RGL1 in response to read selection signal CSL. Global read data lines RGL (RGL0 and RGL1) are shared by sub-array blocks BK0 to BKs shown in
In
As shown in
Sense amplifier circuit SAK0 includes sense amplifier SA0 and a current source circuit 826<0>. Sense amplifier SA0 includes cross-coupled N-channel SOI transistors, cross-coupled P-channel SOI transistors, a sense activating P-channel SOI transistor, and a sense activating N-channel SOI transistor. The sense activating P-channel SOI transistor and the sense activating N-channel SOI transistor are selectively put into the conductive state in response to sense amplifier activation signals /SOP and SON. In the conductive state of the sense activating SOI transistors, sense power supply voltage VBL and the ground voltage are supplied to sense power supply nodes (power source nodes to which the cross-coupled SOI transistors are connected). Sense power supply voltage VBL may be the level of power supply voltage VCC or an intermediate voltage level. It is sufficient for sense power supply voltage VBL to be at a voltage level of a read word line in the selected state.
Similarly to sense amplifier SA shown in
Current source circuit 826<0> includes inverter buffers 827a and 827b, P-channel transistor PT1, and N-channel transistor NT1. Inverter buffers 827a and 827b invert the potentials at sense read bit lines RBL0 and ZRBL0, respectively. P-channel transistor PT1 is selectively put into the conductive state in response to the output signal of inverter buffer 827a. N-channel transistor NT1 is selectively put into the conductive state in response to the output signal of inverter buffer 827b. For example, transistors PT1 and NT1 are each formed by the SOI transistor having the same structure as the transistor constituting sense amplifier SA0.
A high-side power supply voltage of sense read bit lines RBL and ZRBL is the voltage VBL, and inverter buffers 827a and 827b are provided for converting the voltage VBL into the level of power supply voltage VCC to reliably put a charging transistor PT1 for supplying the current into non-conductive state and to reliably put discharging transistor NT1 into conductive state. Accordingly, inverter buffers 827a and 827b are formed by an inverter buffer having a level conversion function.
As described above with reference to
Inverter buffer 827b is used to equalize the sense nodes of sense amplifier SA0, that is, the loads on sense read bit lines RBL and ZRBL. Inverter buffer 827b may normally be maintained in the inactive state so as to be arranged only as a dummy for equalizing the load on the sense amplifier.
When the potential at sense read bit line ZRBL0 is at the H level, charging transistor PT1 for supplying the current is put into the conductive state in response to the output signal of inverter buffer 827a, to supply the current having a certain magnitude from the power supply node through internal output node 828a. When the potential at complementary sense read bit line RBL0 is at the L level, discharging transistor NT1 is put into the conductive state in response to the output signal of inverter buffer 827b to discharge internal output node 828b to the ground voltage level.
In read gate CSG0, internal output node 828b is shown being connected to the global read data line. However, the current from internal output node 828b is not used in an operation. In performing the operation, the complementary global read data line is fixed to the ground voltage and used as a shielding line to global read data line RGL. The complementary global read data line of the seventeenth embodiment is not used in an operation, the selection gate may be arranged only for global read data line RGL in read gate CSG.
In current source circuit 826<0>, when the potentials at sense read bit lines ZRBL0 and RBL are at the H level (voltage VBL level) and the L level (ground voltage level) respectively, transistors PT1 and NT1 enter the off-state in response to the output signals of inverter buffers 827a and 827b, and current source circuit 826<0> enters the output high-impedance state.
Although the sensing operation is described in detail later, when the current supplied from the dummy cell is larger than the current supplied from the unit operator cell, the potential at complementary sense read bit line ZRBL0 attains the H level, and current source circuit 826<0> stops the current supplying. When the current supplied from the dummy cell is smaller than the current supplied from the unit operator cell, the potential at complementary sense read bit line ZRBL0 attains the L level, and current source circuit 826<0> acts as the charge and discharge current supplying source.
Similarly to the configuration shown in
Read gate CSG0 has the configuration similar to that shown in
The transistors constituting sense amplifier SA0, bit line pre-charge/equalize circuit BLEQ0, and read gate CSG0 that are included in constitute sense amplifier band 822 may be formed by a general bulk MOS transistor formed at the surface of a semiconductor substrate, not the SOI transistor.
Similarly sense amplifier SA1, current source circuit 826<1>, bit line pre-charge/equalize circuit BLEQ1, and read gate CSG1 are provided corresponding to sense read bit lines ZRBL1 and RBL1. Sense amplifiers SA0 and SA1 are commonly and selectively activated in response to sense amplifier activation signals /SOP and SON. Bit line pre-charge/equalize circuits BLEQ0 and BLEQ1 are activated when bit line pre-charge instruction signal BLPE is activated. Read gates CSG0 and CSG1 are also put into the conductive state in response to read selection signal CSL.
As for the change in potential of bit lines RBL and ZRBL in reading the data stored in unit operator cell UOE, similarly to the first embodiment, the change in bit line potential shown in
For example, the voltage at source line SL is at the level of power supply voltage VCC, and is higher than reference voltage Vref supplied to dummy cell DMC. That is, reference voltage Vref (voltage source and the voltage at the voltage source are designated by the same reference symbol) is at a voltage level between the voltage (power supply voltage VCC level) supplied to source line SL and bit line pre-charge voltage VPC. In the case where the data “0” is stored in SOI transistor NQ1, SOI transistor NQ1 has the high threshold voltage and passes a smaller amount of current. On the other hand, in the case where the data “1” is stored in SOI transistor NQ1, SOI transistor NQ1 has the low threshold voltage and passes a larger amount of current.
Accordingly, in the cases where the data “1” is stored in SOI transistor NQ1, the amount of current supplied from unit operator cell UOE is larger than the amount of current supplied from dummy cell DMC, and the potential at sense read bit line RBL is higher than the potential at complementary sense read bit line ZRBL.
On the other hand, in the case where the data “0” is stored in SOI transistor NQ1, the amount of current supplied from dummy cell DMC to complementary sense read bit line ZRBL is larger than the amount of current supplied from unit operator cell UOE, and the potential at complementary bit line ZRBL is higher than the potential at bit line RBL.
In this state, sense amplifier activation signals /SOP and SON are set at the L level and the H level to activate sense amplifier SA. The read out data (potential or current amount) on sense read bit lines RBL and ZRBL are differentially amplified by sense amplifier SA.
Similarly to the sensing operation in the first embodiment, even if the voltage having the level of high-side power supply voltage VBC of sense amplifier SA is transmitted to one of sense read bit lines RBL and ZRBL, the PN junction at the body region of each of SOI transistors NQ1 and NQ2 and the dummy transistor is prevented from being forward-biased to cause the charges to flow into the body region, so that the sensing operation can correctly be performed without causing destruction of the storage data.
Current source circuit 826 receives the output signal of sense amplifier SA, and transistors PT1 and NT1 selectively enter the on-state according to the output signals of sense amplifier SA, that is, the potentials at sense read bit lines RBL and ZRBL. Alternatively, transistor NT1 may always be maintained in the non-conductive state and inverter buffer 827b may always be maintained in the inactive state.
Then, read gate CSG shown in
Similarly to the first embodiment, the data is read in the nondestructive manner and the restoring period in which the storage data is rewritten is not required. Accordingly, read word line RWLA may be driven to the non-selected state before operation of the sense amplifier, and the read cycle can be shortened by eliminating the restoring period.
In ADC band 812, current summing lines VMa to VMn are provided corresponding to global read data buses RGBa to RGBn, respectively. Each of current summing lines VMa to VMn is commonly connected to global read data lines RGL0 to RGLk of the corresponding global read data bus. The complementary global read data line is not used in the seventeenth embodiment.
Accordingly, the currents read onto global read data lines RGL0 to RGLk of each of global read data buses RGBa to RGBn are added by current summing lines VMa to VMn, and the voltage level of current summing line VM is changed according to the added current value.
In ADC band 812, M-bit ADCs (analog-digital converter) 835a to 835n are provided corresponding to global read data buses RGBa to RGBD. M-bit ADCs 835a to 835n convert the analog voltages corresponding to the current values added on current summing lines VMa to VMn into the M-bit digital signals.
In the configuration shown in
In the case where the addition/subtraction processing is performed during an operational processing, the need to produce the carry/borrow is eliminated, so that the operational processing can be performed at high speed.
Referring to
A tunable voltage generating circuit 845 generates a conversion reference voltage VREFADC used for the A/D conversion (analog-digital conversion) to reference power supply node 840. Each of resistive elements 841a and 841u has a resistance values R12, and each of resistive elements 841b to 841t has a resistance value R. The resistance value of each of resistive elements 841a and 841u is set smaller than the resistance value of each of other resistive elements 841b to 841t, thereby bringing the voltage value applied on current summing line VM corresponding to the maximum digital converted value close to a conversion reference voltage VREF_ADC as much as possible and bringing the minimum voltage value corresponding to the minimum digital conversed value close to the ground voltage level as much as possible.
Comparators 842a to 842u receive the potentials at the lower-potential-side nodes of corresponding resistive elements 841a to 841u at the respective positive inputs, and the voltage at current summing line VM at the respective negative inputs.
Each of gate circuits 843a to 843t receives the output signal of one of comparators 842a to 842t, which is located on the one-step upper side of the voltage steps produced by resistive elements 841a to 841u, and the output signal of corresponding one of comparators 842b to 842u. Each of gate circuits 843a to 843t produces an L-level signal when the output signal of the comparator located on the one-step upper side attains the H level while the output signal of the corresponding comparator attains the L level. For example, gate circuit 843a produces the L-level signal when the output signal of comparator 842a attains the H level while the output signal of comparator 842b attains the L level. Accordingly, gate circuits 843a to 843t detects a changing point of “0” to “1” in the output signal string of comparators 842a to 842u.
Encoder 844 produces M-bit digital data Q<M−1:0> corresponding to the detected changing point according to the output signal string of gate circuits 843a to 843t.
Reference voltages VVREF0 to VVREF14 are produced from higher-potential-side connection nodes of the respective resistive elements ZZ0 to ZZ14. Comparators 842a to 842u shown in
For example, it is assumed that the voltage at current summing line VM is at a level between reference voltages VVREF10 and VVREF11. As shown in
In ADC 835 shown in
Comparators 842a to 842u are activated in response to conversion activation signal ADCEN to start the comparing operation. A pre-charge transistor 847 that is put into the conductive state in response to a pre-charge instruction signal PRG pre-charges current summing line VM to the ground voltage level before the converting operation.
For example, a register file may be used for implementing encoder 844, to have the contents of the register corresponding to the bit “0” read out. In
Referring to
Global write drivers WDR drive the corresponding global write data lines WGLA. Global write driver WDR00 drives global write data line WGLA00 constituting global write data bus WGB0, global write drivers WDR10 and WDR11 drive global write data lines WGLA10 and WGLA11 constituting global write data bus WGB1, and global write drivers WDR20 to WDR23 drive global write data lines WGLA20 to WGLA23 constituting global write data bus WGB2. Global write drivers WDR30 to WDR37 drive global write data lines WGLA30 to WGLA37 constituting global write data bus WGB3.
Global write data line WGLA is shared by a plurality of cell sub-array blocks.
In writing data, the write data bits each are transferred through global write data lines corresponding in number to the weight of the bit location and written in the corresponding memory cells.
In reading the data, the data stored in unit operator cells are concurrently read, whereby the global read data line(s) corresponding to the bit position of the write data is/are driven in one operation unit block OUB, and sense current (Is) weighted according to the bit location is supplied. Accordingly, in operation unit block OUB, the data of different entries (entry is formed by the memory cells aligned in the row direction) are concurrently read an the total current of the data stored in the memory cells of the concurrently read entries flows through the global read data line, and the analog current addition value is produced on the current summing line. Therefore, the addition result, for example, can be obtained at high speed without waiting for the carry decision time.
After the input data DIN#0 to DIN#m are written in sub-array blocks BK0 to BKm, the data are read from sub-array blocks BK0 to BKm. That is, in cell sub-array 820 of sub-array blocks BK0 to BKm, A port is selected by the port connection circuit, the port-A read bit line is connected to the corresponding sense amplifier, and the data are read the data at the storage nodes SNA of the unit operator cells in which the data DIN#0 to DIN#m are stored. Sense amplifier circuit SAK included in sense amplifier band 822/read gate circuit 824 selectively supplies the current according to the current supplied to complementary read bit line ZRBL from dummy cell and to the current supplied to sense read bit line RBL, and the sense current corresponding to the read data from sense amplifier circuit SAK is supplied to corresponding global read data line RGL through read gate CSG of read gate circuit 824.
The timing of reading data of memory cell data and of activation of sense amplifier circuit SAK in sub-array blocks BK0 to BKm may sequentially be shifted or may be set to be concurrently performed.
Then, all read selection signals CSL<0> to CSL<m> for sub-array blocks BK0 to BKm are driven to the selected state. Therefore, all read gates CSG included in sense amplifier band 822/read gate circuit 824 are put into the conductive state in sub-array blocks BK0 to BKm, and corresponding sense amplifier circuit SAK selectively supplies the sense current to global read data lines RGL0 to RGL3, . . . .
That is, sense currents Is00 to Is03, . . . are read from sub-array block BK0 onto global read data lines RGL0 to RGL3, . . . , and sense read current Is10 to Is13 are read from sub-array block BK1 onto global read data lines RGL0 to RGL3. Similarly, sense currents Ism0 to Ism3 are selectively supplied from in sub-array block BKm onto global read data lines RGL0 to RGL3.
In one operation unit block OUBa, global read data line RGL is connected to a common current summing line VM0. Accordingly, the currents read on global read data lines RGL (RGL0 to RGL3, . . . ) are added in current summing line VM0. In the current addition, a weight corresponding to the data bit position is allotted to the number of selected memory cells. Before the reading operation, the discharge transistor (not shown, pre-charge transistor 847 shown in
ΣIsij·2k,
i=0 to m, j=0 to 15, k=0 to 3
Because the four-bit data addition is performed, the total of 15 global read data lines are used as global read data lines RGL. That is, the 15 global read data lines include one global read data line of least significant bit <0>, two global read data lines of first bit <1>, four global read data lines of second bit <2>, and eight global read data lines of the most significant bit <3>.
Then, the analog-digital conversion is performed with ADC 835 of ADC band 812, thereby obtaining the digital data in which the analog current value appearing on current summing line VM (VM0, VM1, . . . ) is expressed by M bits
In
The operation target data is not limited to the four bits, but data of any bit width may be used for addition.
The semiconductor signal processing device waits for an addition command (Step SP0). When the addition command is issued, the block address is initialized to set the sub-array block to be first written. Then, the input data is taken in, the write data is transferred through global write driver WDR of the data path shown in
A determination on whether the write data is the final write data is made when the data writing is completed (Step SP2). When the remaining write data exists, the block address is updated to write the next data as in Step SP1 (Step SP3). Then, the process returns to Step SP2.
When the writing of final data is completed in Step SP2, in all the target sub-array blocks in which data are written, port A is selected, and the data of the unit operator cells in which the data are written are read an the sense amplifier circuits are activated (Step SP4). The sense amplifier circuits may concurrently be activated in all the target sub-array blocks or be sequentially activated with activation timing being shifted. In order to correctly add sense currents Is, it is necessary that timing at which current source circuit 826 shown in
Upon the activation of the sense amplifier circuit, or before the activation of read selection signal CSL, the pre-charging of current summing line VM to the ground voltage level is completed, and the read gates of all the target sub-array blocks are driven to the on-state (Step SP5). In order to put the read gate of the target sub-array block into the on-state, read selection signals CSL (CSL<0> to CSL<m>) shown in
When the voltage level at current summing line VM is raised by the supplied currents, conversion activation signal ADCEN is activated at a predetermined timing, ADC is activated to perform the A/D conversion, and the conversion data is produced and supplied externally (Step SP6). The processes in Steps SP4 to SP6 are performed in one clock cycle.
When the number of data to be performed is predetermined in the addition processing, the write target blocks can concurrently be driven to the selected state in reading the data according to the predetermined number of the data (the read word line driving circuits are concurrently activated according to the number of input operation data).
Although the word line address (write word line and read word line address) is not particularly described, it is necessary to select the word lines at the same position in each sub-array block, and the write/read word line of the same row is selected in writing and reading the data.
Tunable voltage generating circuit 845 waits for a tuning instruction in a test mode (Step SP20). When the tuning instruction is supplied, block address BA is set at initial value “0”, and the input data is set at (1111). Here, it is assumed that eight-bit ADC is used as ADC. The data (1111) is written in the block specified by block address BA (Step SP22). A determination on whether block address BA reaches “16 (decimal notation)” is made when the first data write is completed for the cell array block (Step SP23). Because block address BA does not reach “16 (decimal notation)”, block address BA is incremented by one (Step SP24). The process returns to Step SP22, the data (1111) is written in the sub-array block specified by the next block address.
When block address BA reaches “16 (decimal notation)” in Step SP23, the write of the data (1111) is completed for the final sub-array block. Then the data are concurrently read from the sub-array blocks specified by block addresses BA of 0 to 16, and ADC performs the AD conversion to produce the conversion result (Step SP25). In this operation, the addition of 17 data of (1111) is performed, and a determination on whether ADC produces the data (11111111) (=255 (decimal notation)) is made (Step SP26).
When ADC does not produce the data (11111111) in decimal notation, the conversion output value indicates the value lower than 255, the level of conversion reference voltage VREF_ADC is higher than a predetermined value. Accordingly, the level of conversion reference voltage VREF_ADC is lowered (Step SP27). The data is read in the nondestructive manner, and the write data are stored in the unit operator cells. After the processing in Step SP27, the process returns to Step SP25, the processing in Steps SP26 and SP27 is performed. That is, the data (1111) is read from the sub-array blocks specified by block addresses BA of 0 to 16, the AD conversion is performed on the read out data (1111), and the data outputting and determination are performed.
On the other hand, when ADC produces the data (11111111) in Step SP26, because there is a possibility that conversion reference voltage VREF_ADC is decreased lower than the predetermined value, the tuning is performed again with the next data. That is, a certain block address BA is set at the initial value “1” (Step SP28). Then, data (0001) is written in the sub-array block specified by block address BA (Step SP29).
Then, a determination on whether block address BA reaches “15 (decimal notation)” is made (Step SP30). Because block address BA does not reach “15 (decimal notation)”, block address BA is incremented by one, and the process returns to Step SP29 to write the data (0001) (Step SP31). On the other hand, when block address BA reaches “15 (decimal notation)” in Step SP30, the data stored in the sub-array blocks specified by the block addresses BA in writing the data, that is, the sub-array blocks of block addresses BA of 1 to 15 are read out, the AD conversion is performed on the read out data, and the AD converted data is produced (Step SP32).
Then, a determination on whether the output data after the conversion is (00001111) is made (Step SP33). When the output data is not (00001111), the voltage level of the conversion reference voltage is excessively lowered, an the level of conversion reference voltage VREF_ADC is adjusted (voltage level is raised) (Step SP34). Then, the process returns to Step SP32, the data (0001) is read from the sub-array blocks specified by block addresses BA of 0 to 15, and the AD conversion and determination are performed.
When the output data after the conversion is (00001111) in Step SP33, the adjustment of conversion reference voltage VREF_ADC is completed. Alternatively, in Step SP33, the level of conversion reference voltage VREF_ADC is finely adjusted, and the data is read, and a margin may be adjusted to the AD conversion.
Alternatively, in the processing in Steps SP28 to SP33, initial block address is set at “0”, the final block address is set at “15 (decimal notation)”, and a determination on whether the conversion output value is (0001000) (=16 (decimal notation)) may be made.
The configuration of tunable voltage generating circuit 845 will be described below by way of example. In a resistance network circuit for converting the reference current into the voltage, the switching element is provided in parallel with each resistor, the voltage level is adjusted by adjusting the resistance value of the resistance network according to the on/off-state of the switching elements.
According to the semiconductor signal processing device of the seventeenth embodiment, the data stored in the memory cells (unit operator cells) are concurrently read from a plurality of sub-array blocks, the number of read data lines is set such that each read data line is weighted according to the associated data bit position, and the total operation processing is performed to the currents, so that the addition operation can be performed at high speed without producing the carry.
The addition operation is the current addition, so that the addition processing can be performed at high speed. Because the conversion reference voltage used in the ADC conversion is variable, the correct A/D conversion can be secured.
[Eighteenth Embodiment]
In the following description, the state in which SOI transistors NQ1 and NQ2 have the high threshold voltage is correlated with the state of storing data “0”, and the state in which SOI transistors NQ1 and NQ2 have the low threshold voltage is correlated with the state of storing data “1”.
During the pre-charge period, read bit line RBL and complementary read bit line ZRBL are pre-charged to the level of pre-charge voltage VPC by bit line pre-charge/equalize circuit BLEQ shown in
When the read cycle is started, read word lines RWLA and RWLB and dummy cell selection signal DCLB are driven to selected state. For example, the voltage at source line SL is set at the level of power supply voltage VCC, and is higher than reference voltage Vref supplied to dummy cell DMC. For example, reference voltage Vref is set at the level of half a power supply voltage VCC. In the case where the data “0” is stored in one of SOI transistors NQ1 and NQ2, the SOI transistor storing data “0” has the high threshold voltage and passes a smaller current amount. On the other hand, in the case where the data “1” is stored in SOI transistors NQ1 and NQ2, SOI transistors NQ1 and NQ2 have the low threshold voltage, and the larger current flows through SOI transistors NQ1 and NQ2.
Accordingly, in the case where the data “1” is stored in both SOI transistors NQ1 and NQ2 (state S(1,1)), the larger current flows from source line SL to sense read bit line RBL through read port RPRTB. In dummy cell DMC, the current passes through from reference voltage source Vref to complementary sense read bit line ZRBL through dummy transistors DTB0 and DTB1. Reference voltage Vref (voltage source and the supplied voltage are designated by the same reference symbol) has the voltage level between the voltage (level of power supply voltage VCC) supplied to located source line SL and bit line pre-charge voltage VPC. In this state, the amount of current supplied from unit operator cell UOE is larger than the amount of current supplied from dummy cell DMC, and the potential at sense read bit line RBL is higher than the potential at complementary sense read bit line ZRBL.
On the other hand, in the case where the data “0” is stored in one of SOI transistors NQ1 and NQ2 (states S(0,1), S(1,0), and S(0,0)), the amount of current supplied from dummy cell DMC to complementary sense read bit line ZRBL is larger than the amount of current supplied from unit operator cell UOE. The potential at sense read bit line RBL is lower than the potential at complementary sense read bit line ZRBL due to the difference in current amount.
In this state, sense amplifier activation signal (/SOP and SON) is made active to activate sense amplifier SA. Sense amplifier SA differentially amplifies the data (potential or current amount) read on sense read bit lines RBL and ZRBL. The sensing operation performed by sense amplifier SA is similar to that shown in
Current source circuit 826 supplies the current to internal output node 828a when sense amplifier SA produces the H-level output signal (potential at sense read bit line RBL), and current source circuit 826 enters the output high-impedance state when sense amplifier SA produces the L-level output signal.
Read gate CSG shown in
As shown in
The output signal of the sense amplifier SA indicates the AND operational result of the data stored in storage nodes SNA and SNB of SOI transistors NQ1 and NQ2. Current source circuit 826 enters the on-state to supply the current when sense amplifier SA produces the output signal of “1”, and current source circuit 826 enters the off-state to stop the current supplying when sense amplifier SA produces the output signal of “0”. Accordingly, the current is supplied to the corresponding global read data line according to the AND operational result of the data stored in storage nodes SNA and SNB of the unit operator cell.
Thus, the data are not read outside the device, but merely the data stored in the unit operator cell are internally read, whereby the logic operation can be performed on the storage data to obtain the operational result. In the seventeenth embodiment, the product-sum operation is performed to perform the multiplication in the fashion that is different from the fashion of the eighth embodiment.
A global write driver WDRA/B is provided corresponding to each global write data line pair WGLP, and the applied data bits are transferred to corresponding global write data buses WGB0 to WGB6. Global write driver WDRA/B includes a global write driver WDRA provided corresponding to A-port global write data line WGLA and a global write driver WDRB provided corresponding to B-port global write data line WGLB.
Global write driver WDRA/B provided for global write data bus WGBk transfers data bit at a k-th bit location of the input data. Here, k is an integer of 0 to 6. Accordingly, the write data having write data bits weighed according to the corresponding bit positions is produced, and the write data is transferred through the corresponding global write data lines.
A switch box 852 and register circuits 850a to 850d and 851a to 851d are provided corresponding to global write data buses WGB0 to WGB6. Register circuits 850a to 850d retain applied input data bits DINA<0> to DINA<3>, respectively. Register circuits 851a to 851d retain applied input data bits DINB<0> to DINB<3>, respectively.
Switch box 852 has input nodes EA0 to EA3 and EA4 to EA7 that are disposed for register circuits 850a to 850d, input node EB0 to EB3 and EB4 to EB7 that are disposed for register circuits 851a to 851d, a ground line 855 that is disposed on the input side, and output nodes FA0 to FA6 and FB0 to FB6 provided corresponding to global write data buses WG0 to WGB6. For the sake of simplification, in
In switch box 852, the data bit transfer paths are set for port A and port B by switch control signals SWCA and SWCB, respectively.
Switch box 852 switches the connection paths between output node F0 to F6 and input nodes E0 to E7 in response to data clock signal DCLK. Input data bits DINA<3:0> are transferred to the global write data bus while being sequentially shifted bit by bit in the upper bit direction by the switching operation of switch box 852, input data bits DINB<3:0> are sequentially selected bit by bit, and input data bits DINB<3:0> are sequentially selected bit by bit and the bit position of the selected bit of input data bits DINB<3:0> is shifted to be transferred.
As shown in
In
On the other hand, as shown in
When multiplicand data X<3:0> and multiplier data bit Y<0> are transferred through global write data buses WGB0 to WGB3, the write word line is activated in the starting sub-array block #0 of the write target, and the data are written in storage nodes SNA and SNB of the unit operator cells.
When the first write cycle is completed, for port. A, the connection path of switch box 852 is switched by switch control signal SWCA as shown in
On the other hand, for port B, the connection path of switch box 852 is switched by switch control signal SWCB as shown in
When the data X<3:0> and Y<1> are concurrently transferred through global write data buses WGB1 to WGB4, the write word line is driven to the selected state in sub-array block #1 of the next write target, and the transferred data are written in storage nodes SNA and SNB of the corresponding unit operator cells. Therefore, multiplicand data X<3:0> and multiplier data bit Y<1> are stored in sub-array block #1 after multiplicand data X<3:0> and multiplier data bit Y<1> are shifted by one bit toward the upper bit direction with respect to sub-array block #0.
For port A, as shown in
For B port, the connection path of switch box 852 is switched by switch control signal SWCB as shown in
When multiplicand data X<3:0> and multiplier data bit Y<2> are transferred through global write data buses WGB2 to WGB5, the write word line is driven to the selected state in sub-array block #2 of the next write target, and the transferred data are written in storage nodes SNA and SNB of the corresponding unit operator cells. Therefore, the data are written in the positions shifted by one bit toward the upper bit direction with respect to the write cycle shown in
As shown in
For port B, the data transfer path is switched by switch control signal SWCB in switch box 52 as shown in
Multiplicand data X<3:0> and multiplier data bit Y<3> are concurrently transferred through global write data buses WGB3 to WGB6. When the data are transferred, the write word line is driven to the selected state in sub-array block #3 of the next write target, and the transferred data are written in the unit operator cells.
Multiplicand data X and multiplier data Y are concurrently written. Accordingly, four-time write access is required to write all the data bits.
When the four-time write access is completed to end the data writing of the multiplication target, similarly to the seventeenth embodiment, the data are read from the memory sub-array blocks.
Referring to
In reading the data, similarly to the seventeenth embodiment, read selection signals CSL<0> to CSL<m> are concurrently driven to the connection (selected) state for sub-array blocks BK0 to BKm (m=3 in the case of the four-bit data) in which the multiplier data and multiplicand data are written. At this time, port B is selected in the port connection circuit. Sense amplifier circuit SAK supplies the current corresponding to the AND operational result of the data stored in corresponding unit operator cells UOE. Sense read currents Is0(0) to Is0(126) and Ism(0) to Ism(126) are concurrently supplied to 127 global read data lines RGL0 to RGL126 from memory sub-array blocks BK0 to BKm. Global read data lines RGL0 to RGL 126 are commonly connected to current summing line VM. ADC 835 converts the analog voltage corresponding to the total current on the current summing line VM into digital data.
In sub-array block #1, multiplicand data bits X<0> to X<3> and multiplier data bit Y<1> are stored in storage nodes SNA and SNB of the unit operator cells arranged for global write data buses WGB1 to WGB4. The data “0” is stored in storage nodes SNA and SNB of the unit operator cells arranged for global write data buses WGB0, WGB5, and WGB6.
In sub-array block #2, multiplicand data bits X<0> to X<3> are stored in storage nodes SNA of the unit operator cells arranged for global write data buses WGB2 to WGB5, and multiplier data bit Y<2> is stored in storage node SNB. The data “0” is stored in storage nodes SNA and SNB of the unit operator cells arranged for global write data buses WGB0, WGB1, and WGB6.
In sub-array block #3, the data “0” is stored in storage nodes SNA and SNB of the unit operator cells arranged for global write data buses WGB0 to WGB2. Multiplicand data bits X<0> to X<3> and multiplier data bit Y<3> are stored in storage nodes SNA and SNB of the unit operator cells arranged for global write data buses WGB3 to WGB6.
In each of sub-array blocks #0 to #3, the data are written in unit operator cells UOE corresponding in number to the bit widths of global write data buses WGB0 to WGB6. Sense amplifier circuit SAK transfers the current to global read data line RGL according to the AND operational result of the data stored in storage nodes SNA and SNB of the unit operator cells UOE. Sub-array blocks #0 to #3 supply the currents corresponding to partial products PP1 to PP4 shown in
Accordingly, analog multiplication results Xa·Ya, . . . , and Xk·Yk of multiplicand data Xa, Xb, . . . , and Xk and multiplier data Ya, Yb, . . . , and Yk are produced in operation unit blocks OUBa, OUBb, . . . , and OUBk, and M-bit ADCs 835a to 835k can concurrently perform the AD conversion to produce the M-bit digital data.
In operation unit blocks OUBa to OUBk, the unit operator cells of the same row are selected to perform the data write and read. Accordingly, in the multiplication, although the weighting of the transferred data bit is made to global write data line(s) and global read data line(s), it is only necessary to provide global write drivers of the number corresponding to the weight of each bit position. In the selected sub-array block, it is merely required to concurrently select the unit operator cells of one entry (formed by unit operator cells aligned in one row) to perform the data write and read, and it is not necessary to select the bit lines of the number corresponding to the position of an associated write/read data bit in each sub-array block.
(Modification)
In each of sub-array blocks BK#4 to BK7, multiplicand data X#2<3:0> is stored in storage nodes SNA of the unit operator cells with the weighting according to each bit position. Multiplier data bits Y#2<0> to Y#2<3> are stored in storage nodes SNA of the unit operator cells of sub-array blocks BK4 to BK7 with storage locations being weighted according to each bit position.
A set of operation data are stored by the procedure similar to that shown in
Referring to
Command decoder 860 takes in command CMD in synchronization with clock signal CLK, and command decoder 860 produces a signal for specifying operational processing contents specified by command CMD.
Data latch control circuit 862 produces data clock signal DCLK and data latch enable signal DEN when operational processing instruction (OPLOG) applied from command decoder 860 indicates multiplication processing. When the operation processing instruction received from command decoder 860 indicates the multiplication processing, switch control circuit 864 produces switch control signals SWCA and SWCB in a predetermined sequence in synchronization with clock signal CLK, and switch control circuit 864 switches the connection path of switch box 852 in each write cycle such that the write data transfer path is shifted by one bit toward the upper bit direction.
When the operational processing instruction received from command decoder 860 indicates a processing involving the data writing, write control circuit 866 activates write activation signal WREN and write word line enable signal WWLEN at predetermined timings. When the operational processing instruction received from command decoder 860 indicates the multiplication processing, write control circuit 866 produces a latch enable signal LATEN.
Control circuit 818 includes a read control circuit 868 that controls the reading operation, a word line address register 870 that produces the word line address in the multiplication processing, and a block address counter 872 that counts clock signal CLK to produce block address BRAD.
When the operational processing instruction supplied from command decoder 860 indicates a processing involving the data read, read control circuit 868 produces read activation (enable) signal REDEN, read word line enable signal RWLEN, sense amplifier enable (activation) signal SAEN, and AD conversion enable (activation) signal ADCEN at predetermined timings in a predetermined sequence. When the operational processing instruction supplied from command decoder 860 indicates the multiplication processing, a storage value of word line address register 870 is set at a predetermined value, and word line address register 870 retains word line address WLAD for specifying a word line (write word line and read word line) in the selected sub-array block in the multiplication processing.
When the operational processing instruction received from command decoder 860 indicates the multiplication processing, block address counter 872 counts clock signal CLK to produce the count value as block address BRAD for specifying a sub-array block. When the count value reaches a predetermined value, block address counter 872 produces a count-up signal CUP, and count-up signal CUP is applied to read control circuit 868 and write control circuit 866. In the case where the operational processing instruction indicates the multiplication processing, read control circuit 868 produces control signals SAEN, RWLEN, REDEN, and ADCEN to start the next read operation when block address counter 872 produces count-up signal CUP predetermined number of times. The number of count-up signals CUP corresponds to the number of sets of the operation target data. For example, in the case where the multiplication is performed on the set of multiplicand data X<3:0> and multiplier data Y<3:0>, a transition to the read operation is made when count-up signal CUP is asserted once.
Write control circuit 866 activates latch enable signal LATEN when block address counter 872 produces count-up signal CUP to write control circuit 866. The decoding result of the block address is latched into the local cell selection circuit provided corresponding to each sub-array block by the latch enable signal LATEN. Therefore, the sub-array blocks can concurrently be driven to the selected state during the multiplication processing and during the next reading operation after the write completion.
Write word line drive circuit 882 is enabled when the output signal of block decoder latch 880 is in the selected state, to drive write word line WWL of the corresponding row to the selected state according to write word line enable signal WWLEN and word line address WLAD.
Local cell selection circuit 875 includes a read word line drive circuit 884 that drives the read word line to the selected state, a sense amplifier control circuit 886 that controls the operation of the sense amplifier circuit, and a read activation circuit 888 that reads the output signal of the sense amplifier circuit. Read word line drive circuit 884 is enabled when the decode signal supplied from block decoder latch 880 is in the selected state, to drive read word lines RWLA and RWLB corresponding to the row specified by word line address signal WLAD to the selected ion state in response to read word line enable signal RWLEN.
Sense amplifier control circuit 886 is enabled when the output signal of block decoder latch 880 is in the selected state, to activate sense amplifier activation signal SE (SON and /SOP) in response to sense amplifier enable signal SAEN. Read activation circuit 888 is enabled when the decoded signal of block decoder latch 880 is in the selected state, to drives read selection signal CSL to the selected state at activation timing of read activation signal REDEN.
The portion where dummy cell selection signals DCLA and DCLB are produced to select the dummy cell is not shown. It is sufficient to activate dummy cell selection signals DCLA and DCLB at the same timing as read word lines RWLA and RWLB in response to read word line enable signal RWLEN.
With reference to the configuration of switch box 852, it is sufficient to provide the switching transistors so as to establish the connection paths shown in
Thus, according to the semiconductor signal processing device of the eighteenth embodiment, the data are stored in the unit operator cells with the bit storage positions being weighted in each sub-array block, and the current corresponding to AND operational result of the data stored in unit operator cells are transmitted to global read data lines using the sense amplifier circuits. Therefore, the multiplication of the multi-bit data and the addition processing of the plurality of multiplication results can be performed at high speed.
In the above description of the multiplication, the multiplication result of the four-bit data is obtained using the eight-bit ADC. The bit width of the data used is not limited to the four bits, but the data having another bit width may be used.
[Nineteenth Embodiment]
Similarly to the seventeenth embodiment, sense amplifier SA has the configuration similar to that shown in
Current source circuit 826 includes P-channel transistor PT10 that supplies the current from the power supply node in response to the output signal of inverter buffer 827a and discharging transistor NT10 that sinks the current in response to the output signal of inverter buffer 827b. Discharging transistor NT10, in the conductive state, discharges the current according to the voltage at low-side power supply node VNF that is not higher than the ground voltage.
Unlike the configuration of the seventeenth embodiment, read gate CSG of read gate circuit 824 includes two switching transistors NT11 and NT12 that are commonly connected to a corresponding global read data line RGL. Switching transistor NT11 is put into the conductive state in response to addition read selection signal CSLP, to connect charging transistor PT10 of current source circuit 826 to global read data line RGL in the conductive state. Switching transistor NT12 is selectively put into the conductive state in response to subtraction read selection signal CSLN, to connect discharge transistor NT10 to global read data line RGL during the conductive stte.
Accordingly, in current source circuit 826, the corresponding global read data line RGL can be charged and discharged by the configuration of the read gate.
When the data “1” is stored in storage node SNA of the corresponding unit operator cell, sense read bit lines RBL and ZRBL attain the H level and the L level respectively, inverter buffers 827a and 827b concurrently put transistors PT10 and NT10 into the conductive state, and global read data line RGL is charged or discharged in response to read selection signals CSLP and CSLN. When the data “0” is stored in storage node SNA of the corresponding unit operator cell, sense read bit lines RBL and ZRBL attain the H level and the L level respectively, both transistors PT10 and NT10 enter the off-state, and current source circuit 826 enters the output high-impedance state, Accordingly, when the data “0” is stored in storage node SNA, sense amplifier circuit has no influence on the current passing through global read data line RGL.
Charging transistor PT10 and discharging transistor NT10 act as a constant current source, and transistors PT10 and NT10 supply the constant current to global read data line RGL (the current sinking behavior is considered to supply a negative current). Accordingly, when the data “1” is stored in storage node SNA of the corresponding unit operator cell, by selectively activating read selection signals CSLP and CSLN in the read gate CSG, the constant current can be supplied to or pulled out from global read data line RGL, that is, the positive and negative currents can be supplied. Thus, the addition or subtraction can be performed. The current addition and current subtraction are set by read selection signals CSLP and CSLN.
Even if the addition and subtraction result has a negative value, a negative current value can be produced by the use of positive and negative reference voltages VREF_ADC and to −VREF_ADC as the conversion reference voltage. In such case, encoder 844 produces a signed multi-bit data with a sign indicating the positive or negative through the encoding operation.
Referring to
The four-bit input data DIN#1 to DIN#m are each a non-signed input data. Accordingly, the most significant bit of each of the four-bit input data DIN#1 to DIN#m does not indicate a sign.
In
In ADC band 812, ADCs (835) are provided corresponding to operation unit blocks OUBa and OUBb, respectively. ADC (835) performs the AD conversion on the voltage corresponding to the current supplied to corresponding current summing line VM with reference to the voltages produced through resistance-division of the conversion reference voltages VREF_ADC and −VREF_ADC. The A/D conversion behavior of ADC 835 is similar to that of the seventeenth embodiment except that the encoder supplies a signed output data.
Accordingly, from memory sub-array block BKj in which the data to be subtracted is stored, the sense amplifier circuit corresponding to the memory cell storing the data “1” subtracts the current from the global read data line. From memory sub-array block BKj in which the data to be added is stored, the current is supplied to the global read data line for the data “1”. The addition and subtraction shown in
In the case where the addition and subtraction are performed, as shown in
On the other hand, for sub-array block BK2, four-bit input data DIN#3 is written, and read selection signal CSLN is set at the selected state. In this stage, in sub-array block BK2, the current is extracted (pulled out) from the corresponding global read data line to perform the current subtraction in the case where the unit operator cell stores the data bit “1”.
In the case where the addition and subtraction are performed, for a plurality of sub-array blocks, the block for storing addition data and the block for storing subtraction data may be fixed in advance. The configuration in which the addition data storage block and the subtraction data storage block are flexibly allocated to sub-array blocks BK0 to BKm will be described below, by way of example.
During the activation of read activation signal REDEN, read activation circuit 890 drives one of read selection signals CSLP and CSLN to the selected state according to the flag latched by operation flag latch circuit 892.
In
In the case where the addition and subtraction are performed to the input data, in writing the data in a corresponding sub-array block, the flag (for example, sign bit) indicating the addition or subtraction is used as addition and subtraction instruction flag ASF, and operation instructing contents are concurrently stored in operation flag latch circuit 892. Therefore, read selection signal CSLP and CSLN can selectively be driven to the on-state (selected state) according to the addition and subtraction of the write data in sub-array blocks.
Thus, according to the semiconductor signal processing device of the nineteenth embodiment, when the data “1” is stored in storage node SNA of the unit operator cell, the current source and sink (positive and negative current supplying) are selectively performed to the global read data line, so that the addition and subtraction can concurrently be performed.
Because only the current source and sink of the global read data line are performed according to the addition and subtraction, it is not necessary to convert the subtraction data into two's complement data to perform the addition, and the addition and subtraction processing is simplified. The same effect as the seventeenth embodiment can be also achieved.
[Twentieth Embodiment]
Local write word lines WWL0 and WWL1 extending in the column direction are provided corresponding to unit operator cells UOEA and UOEB. Local write word lines WWL0 and WWL1 are arranged in parallel with the bit line, so that unit operator cells on one column can be selected by one local write word line WWL in one sub-array block.
Unit operator cell UOEA includes P-channel SOI transistors PQA1 and PQA2 and N-channel SOI transistors NQA1 and NQA2, and unit operator cell UOEB includes P-channel SOI transistors PQB1 and PQB2 and N-channel SOI transistors NQB1 and NQB2.
P-channel SOI transistors PQA1 and PQB1 are selectively put into the conductive state according to the potentials at write word lines WWL0 and WWL1, and P-channel SOI transistors PQA1 and PQB1 transmit write data DINA to body regions (storage node) SNA of N-channel SOI transistors NQA1 and NQB1, respectively. P-channel SOI transistors PQA2 and PQB2 are selectively put into the conductive state according to the potentials at write word lines WWL0 and WWL1, and P-channel SOI transistors PQA2 and PQB2 transmit write data DINB to body regions (storage node) SNB of N-channel SOI transistors NQA2 and NQB2, respectively.
Local write word lines WWL0 and WWL1 are arranged extending in the corresponding operator cell sub-array block. The hierarchical arrangement of the local write word line will be described later.
The sources of SOI transistors NQA1 and NQB1 are each connected to the source lines SL. In unit operator cells UOEA and UOEB, the connection manner between the SOI transistors of the read section is similar to that of the unit operator cell shown in
SOI transistors NQA1 and NQB1 are selectively put into the conductive state according to the storage data in response to the signal potential at read word line RWLA, and SOI transistors NQA2 and NQB2 are selectively put into the conductive state according to the storage data in response to the signal potential at read word line RWLB.
In the P-type transistor forming region, high-concentration P-type regions 1200a and 1200b are arranged in alignment in the Y-direction. An N-type region 1202a is arranged between P-type regions 1200a and 1200b. A P-type region 1204a is arranged adjacent to and in alignment with P-type region 1200b in the Y-direction.
In alignment with P-type regions 1200a, 1200b and 1204a in the Y-direction, P-type regions 1204b and high-concentration P-type regions 1200c and 1200d are arranged. An N-type region 1202b is arranged between P-type regions 1200c and 1200d.
Outside the P-type transistor forming region, an N-type region 1206a is arranged adjacent to P-type region 1200b, and high-concentration N-type regions 1206b and 1206c are arranged being aligned with N-type region 1206a in the Y-direction. P-type region 1204a is arranged between N-type regions 1206a and 1206b and continuously extending in the X-direction. P-type region 1204b is arranged, between N-type regions 1206b and 1206c, continuously extending in the X-direction.
In the P-type transistor forming region, high-concentration P-type regions 1200e and 1200f are arranged in alignment in the Y-direction. An N-type region 1202c is arranged between P-type region 1200e and 1200f. A P-type region 1204c is arranged adjacent to and in alignment with P-type region 1200f in the Y-direction.
A P-type region 1204d and high-concentration P-type regions 1200g and 1200h are arranged aligning with P-type regions 1200e, 1200f, and 1204e in the Y-direction. An N-type region 1202d is arranged between high-concentration P-type regions 1200g and 1200h.
Outside the P-type transistor forming region, an N-type region 1206d is arranged adjacent to P-type region 1200f, and high-concentration N-type regions 1206e and 1206f are arranged aligning with N-type region 1206d in the Y-direction. P-type region 1204c is arranged, between N-type regions 1206d and 1206e, continuously extending in the X-direction. P-type region 1204d is arranged between N-type regions 1206e and 1206f and continuously extending in the X-direction.
Gate electrode interconnection lines 1208a and 1208e are arranged continuously extending in the X-direction, and gate electrode interconnection lines 1208a and 1208e are arranged overlapping N-type regions 1202a and 1202c. Gate electrode interconnection lines 1208a and 1208e are arranged being separated from each other.
Due to such separated structure of gate electrode interconnection lines 1208a and 1208e, unit operator cells UOEA and UOEB are individually driven to the selected state by different write word lines in writing data.
A gate electrode interconnection line 1208b is arranged continuously extending in the X-direction, and gate electrode interconnection line 1208b is arranged overlapping N-type regions 1204a and 1204c. A gate electrode interconnection line 1208c is arranged continuously extending in the X-direction, and gate electrode interconnection line 1208c is arranged overlapping N-type regions 1204b and 1204d. Gate electrode interconnection lines 1208d and 1208f are continuously arranged overlapping N-type regions 1202b and 1202d. Gate electrodes 1208d and 1208f are arranged being separated from each other, and are electrically connected to the different write word lines.
First metal interconnection lines 1210a to 1210g continuously extending in the X-direction are arranged being separated from one another. First metal interconnection line 1210a is electrically connected to N-type region 1206f through contact/via VV11. First metal interconnection line 1210b is electrically connected to N-type region 1206e through contact/via VV10. First metal interconnection line 1210c is electrically connected to gate electrodes 1208f and 1208e through contacts/vias VV13 and VV12.
First metal interconnection line 1210e is electrically connected to gate electrodes 1208d and 1208a through contacts/vias VV7 and VV6. First metal interconnection line 1210f is electrically connected to N-type region 1206b through contact/via VV3. First metal interconnection line 1210g is electrically connected to N-type region 1206c through contact/via VV4.
First metal interconnection lines 1210a and 1210b constitute B-port and A-port bit lines respectively, and first metal interconnection line 1210c constitutes local write word line WWL0. First metal interconnection line 1210e constitutes local write word line WWL1, and first metal interconnection line 1210f constitutes A-port read bit line to transmit data DOUTA. First metal interconnection line 1210g constitutes B-port read bit line to transmit data DOUTB.
Second metal interconnection lines 1212b to 1212f continuously extending in the X-direction are arranged being separated from one another. Second metal interconnection line 1212b is electrically connected to P-type region 1200a through contact/via VV1 and the intermediate interconnect. Second metal interconnection line 1212c is electrically connected to N-type region 1206d through contact/via VV9 and the intermediate interconnect, and second metal interconnection line 1212c is electrically connected to N-type region 1206a through contact/via VV2. Second metal interconnection line 1212d is disposed in parallel with gate electrode interconnection line 1208b continuously extending in the X-direction, and second metal interconnection line 1212d is electrically connected to gate electrode interconnection line 1208b in a not shown portion.
Second metal interconnection line 1212e is arranged overlapping gate electrode interconnection line 1208c, and second metal interconnection line 1212e is electrically connected to gate electrode interconnection line 1208c in a not shown portion. Second metal interconnection line 1212f is electrically connected to P-type region 1200h through via/contact VV8 and the intermediate interconnect, and second metal interconnection line 1212f is electrically connected to P-type region 1200d through via/contact VV5.
Second metal interconnection lines 1212b and 1212f transmit input data DINA and DINB, respectively. Second metal interconnection line 1212c constitutes source line SL, and second metal interconnection line 1212d constitutes read word line RWLA together with lower-layer gate electrode interconnection line 1208b. Second metal interconnection line 1212e constitutes read word line RWLB together with lower-layer gate electrode interconnection 1208c.
In performing an operation, input data DINA and DINB are set to the same data. Therefore, the effect that the data reading from port B is equivalent to data reading from port A can be achieved.
Although not clearly shown in
In sense amplifier band 822, the sense amplifier circuit is provided corresponding to the unit operator cell column. Similarly to the previously-described embodiments, a port connection switch for selecting a port and a read gate are provided. The configuration of the sense amplifier circuit differs from that of the previously-described embodiments in that the current corresponding to the magnitude of currents supplied from a plurality of unit operator cells onto a corresponding read bit line is supplied to a corresponding global read data line (the configuration of the output portion is described later).
A write word line decoder 1220 is provided being shared by sub-array blocks BK0 to BK31. Write word line decoder 1220 includes write word line drivers 1222 that are provided corresponding to the respective global write data lines WWL<0>, and WWL<m>. Write word line drivers 1222 drives an addressed global write word lines WWL<0>, WWL<1>, . . . according to a write word line address.
A sub-decoder band 1225 is provided corresponding to each of sub-array blocks BK0 to BK31. In sub-decoder band 1225, a sub-decoder 1223 is provided corresponding to each of global write word lines WWL<0> to WWL<m>. Similarly to the fifteenth embodiment, sub-decoder 1223 drives a corresponding local write word line WWLi to the selected state in response to the signal on corresponding global write word line WWL<i> and block selection signal BSk supplied from row selection driving circuit 816, and sub-decoder 1223 drives unit operator cells on one column to the selected state.
In sub-array blocks BK0 to BK31, local write word line WWL is driven to the selected state in response to block selection signal BS. The write word line is formed into the hierarchical structure of the global and local word lines, which allows input data DINA and DINB to be written in the selected sub-array block. The data of the operation target are written in the same column of the plurality of sub-array blocks, and the operational result can be obtained by sensing the current passing through global read data line RGL.
ADC band 812 has the configuration similar to that of one of the seventeenth to nineteenth embodiments. In data path 814, the global write data line is not arranged, and the global write driver is not provided. The (m+1)-bit digital data from ADC band 812 is externally supplied through buffering, for example. Row selection driving circuit (cell selection driving circuit) 816 transfers write data DINA and DINB through data lines (second metal interconnection lines 1212b and 1212f shown in
In row selection driving circuit 816, row/data line selection driving circuits XXDR0 to XXDR31 are provided corresponding to each of sub-array blocks BK0 to BK31. The data DINA<m:0> and DINB<m:0> of the operation target are applied to row/data line selection driving circuits XXDR0 to DDXR31.
The data are transferred to a selected operator cell sub-array block in parallel. According to the write access cycle, a control circuit 1250 determines block selection signal BS to be driven to the selected state, to determine the sub-array block of the write target.
Each of row/data line selection driving circuits XXDR0 to XXDR31 includes a data line drive circuit 1234 and a word line drive circuit 1230. Data line drive circuit 1234 produces internal write data DINA and DINB according to corresponding bits DINA<i> and DINB<i> of applied input data DINA and DINB. Word line drive circuit 1230 drives read word lines RWLA and RWLB to the selected state in response to an address signal (not shown).
Word line drive circuit 1230 is arranged corresponding to each unit operator cell row of the corresponding operator cell sub-array block. In operator cell sub-array block BK0 to BK31, read word lines RWLA and RWLB can individually and concurrently be driven to the selected state.
In an operator cell sub-array block, the number of allocated read word lines is determined according to the bit position of the storage data. That is, one unit operator cell is allocated to the data of 0-th bit<0>, and two unit operator cells are allocated to the read word line for which first bit <1> is stored. The data of i-th bit <i> is stored in the unit operator cells of two to the power of i (i-ty power of 2). Accordingly, one sub-array block supplies the current having the magnitude corresponding to the value of the storage numerical data.
N-channel SOI transistor QN3 is provided between node ND11 and the ground node, in order to activate sense amplifier SA. Transistor QN3 connects internal node ND11 to the ground node during the activation of sense amplifier activation signal SE.
Sense amplifier SA further includes P-channel SOI transistors QP2 and QP3 and N-channel SOI transistors QN4 to QN6 in order to sense the current passing through complementary sense read bit line ZRBL. Transistor QN4 discharges dummy cell current Id supplied from complementary sense read bit line ZRBL during the sensing operation. Transistor QN5 constitutes a current-mirror stage with transistor QN4, to produce the mirror current of current Id passing through complementary sense read bit line ZRBL.
Transistor QP3 supplies the current to transistor QN5. Transistor QP2 constitutes the current-mirror stage with transistor QP3, to produce the mirror current of the current passed through transistor QP3. Transistor QN6 discharges the current supplied from transistor QP5 during the sensing operation. Current source circuit 826 includes P-channel SOI transistors QP10 and QP11 that are connected in series between the power supply node and internal output node 828 and N-channel SOI transistors QN11 and QN10 that are connected in series between internal output node 828 and the ground node. The source of transistor QP10 is connected to the power supply node, and the gate of transistor QP10 is connected to the gate of transistor QP2. The gate of transistor QP11 receives current supply activation signal /ENA. The source of transistor QN10 is connected to the ground node, and the gate of transistor QN10 is connected to the gate of transistor QN6. The gate of transistor QN11 receives current supply activation signal ENA.
Read gate CSG connects internal output node 828 to global read data line RGL. In
In the configuration of sense amplifier circuit SAK shown in
Before the sensing operation, read word line is driven to the selected state, and the unit operator cell and the dummy cell supply the currents to sense read bits line RBL and ZRBL. The dummy cell is set at the state of storing data “0”. Accordingly, the dummy cell supplies the reference current corresponding to the data “0” to complementary sense read bit line ZRBL.
Current Ic corresponding to the data stored in the unit operator cell is supplied to sense read bit line RBL. When the supply currents are stabilized, sense amplifier activation signal SE is activated to perform the sensing operation. During the sensing operation, the mirror current of the current passing through sense read bit line RBL is passed through transistor QP1 by the current-mirror behavior of transistors QN1 and QN2.
Similarly, the mirror current of current Id passing through complementary sense read bit line ZRBL is passed through transistor QP3 by the current-mirror behavior of transistors QN4 and QN5. Transistors QP3 and QP2 constitute the current-minor stage, and the mirror current of dummy cell current Id is passed through transistor QP2. Therefore, the mirror current of dummy cell current Id supplied from transistor QP2 flows through transistor QN6.
When the currents passing through sense read bit lines RBL and ZRBL are stabilized, current supply activation signals ENA and /ENA are activated, and current source circuit 826 starts the current supplying. During the activation, in current source circuit 826, transistor QP10 constitutes a current-minor stage with transistor QP1, to supply the mirror current of current Ic passing through sense read bit line RBL. On the other hand, transistor QN10 constitutes a current-mirror stage with transistor QN6, to supply the mirror current of current Id passing through complementary sense read bit line ZRBL.
When the read selection signal is activated at a predetermined timing, read gate CSG passes a current Ic·K−Id·K through global read data line RGL. Here, a coefficient K is a mirror ratio of the mirror currents supplied from transistors QP10 and QN10.
The data “0” is stored in the dummy cell, and the current on the basis of the data “0” passes through global read data line RGL, so that the current corresponding to the magnitude of the numerical data stored in the unit operator cell can be supplied to the global read data line. Accordingly, even if the currents are supplied from a plurality of unit operator cells to sense read bit line RBL, the current having the magnitude corresponding to the value of the numerical data can correctly be supplied.
Read word line drivers 1242 and 1244 are enabled to decode address signal AD when the corresponding enable or activation signals are activated, and read word line drivers 1242 and 1244 drive corresponding word lines WWLB, RWLA and RWLB to the selected state according to the decoding result. In this case, the block selection signal shown in
Data line drive circuit 1234 includes an A-port data line driver 1246 and a B-port data line driver 1248. A-port data line driver 1246 receives data bit DINA<i>, write enable (activation) signal WEN, and address signal AD to produce internal write data bit DINA. B-port data line driver 248 receives data bit DINB<i>, write enable (activation) signal WEN, and address signal AD to produce internal write data bit DINB.
During the activation of the write word line driver shown in
In data line drive circuit 1234, the same configurations are provided in a duplicated manner according to bit position <i> of the allocated data bit. Accordingly, the same configurations of two to the power of i (=2^i) are provided for bit <i>, so that the same data bits can be arranged for unit operator cells of the number corresponding to the bit position.
For word line drive circuit 1230, during the data read, read word lines of the number corresponding to the number of data bits of the operation target are concurrently driven to the selected state. For example, in a four-bit data operation, 15 read word lines are concurrently driven to the selected state. The selection manner of read word lines RWLA and RWLB depends on the operation target to be performed. For example, when in one sub-array block, multiplication of input data DINA and DINB is performed and the multiplication result is added, B port is selected in the sub-array block of the operation target. A port is selected when the addition of input data DINA is performed.
Unit operator cells of the number corresponding to the bit positions of read word lines RWL are activated by row/data line selection driving circuits XXDRa and XXDRb that are disposed for sub-blocks BKa and BKb. Row/data line selection driving circuits XXDRa and XXDRb have the configuration shown in
When the global write data line is activated in writing the data, local write word line WWL is driven to the selected state in the sub-array block specified by the block selection signal. Data line driving circuit 234 is activated, and the data is written in the unit operator cell that is located at an intersection portion of data driving line DIN and local write word line WWL.
In reading the data, the read word lines for which the operation target data is stored, that is, 15 read word lines RWL in the case of the four-bit data are concurrently driven to the selected state using read word line drive circuit 230 included in corresponding row/data line selection driving circuit XXDR (XXDRa and XXDRb). The selection manner of read word lines RWLA and RWLB depends on the operation to be performed.
In this case, the dummy cell is selected. Dummy cell DMC is set at the state of storing data “0”. In the selection manner of the dummy cell, the reference current corresponding to the data “0” may be supplied to the sense read bit line, or similarly to the read word line, 15 dummy word lines DRWL may be concurrently driven to the selected state. 15 dummy cells DMC are connected to complementary sense read bit line ZRBL to supply the dummy cell currents corresponding to the data “0”, and the current corresponding to the data stored in 15 unit operator cells is supplied to sense read bit line RBL.
In sense amplifier band 22, the total current of current I1 passing through the unit operator cell storing data “1” and of the low threshold voltage state and current Ih (<I1) passing through the unit operator cell storing data “0” and of the high threshold voltage state is supplied to sense amplifier circuit SAK. For simultaneously selected unit operator cells UOE, it is assumed that the number, a, of unit operator cells UOE output the data “1” and the number, b, of unit operator cells UOE output the data “0”. In such case, the current passing through sense read bit line RBL attains a·I1+b·Ih. On the other hand, the current passing through complementary sense read bit line ZRBL becomes (a+b)·Ih even if the number of selected dummy cells DMC is equal to the number of unit operator cells.
In current source circuit 26 of sense amplifier circuit SAK, the mirror current of the current corresponding to the difference between the current passing through sense read bit line RBL and the current passing through complementary sense read bit line ZRBL, current K·b·(I1−Ih), is supplied to the corresponding global read data line. For example, data A<3:0> is (0001), and the data A is read from unit operator cells UOE. In case where the number of selected dummy cells is equal to the number of selected unit operator cells, current K. (I1−Ih) is supplied to the corresponding global read data line. On the other hand, in the case where data A<3:0> is (1010), the current of 10·K·(I1−Ih) is supplied to the corresponding global read data line.
In such case, because the supplying current of dummy cells DMC is subtracted as the reference current, it is not particularly necessary that the number of concurrently selected dummy cells be equal to the number of concurrently selected unit operator cells.
Accordingly, the current corresponding to the magnitude of an analog converted value of the data stored in sub-array block BKi passes through global read data line RGL. That is, in a plurality of cell sub-arrays 820, the read word lines and the dummy word lines can be driven to the selected state to supply the current corresponding to the addition value of the data stored in sub-array blocks BKi, BKa, to the corresponding ADC.
In sub-array block BK, in the case where port B is selected while the data A and B are stored as input data DINA and DINB in unit operator cells UOE, the analog current corresponding to the multiplication result of the data A and B is supplied to the corresponding global read data line.
The data writing is performed as follows. The sub-array block in which an operation target data is written is specified by block selection signal BS#. Write word line decoder (220) drives global write word line WWL<0> of the first column to the selected state. In the specified sub-array block, local write word line WWL is driven to the selected state, and data DINA and DINB are written (only data DINA may be written).
When the first-time data write is completed, the next sub-array block is specified by the block selection signal, the next data in the set of operation target data are written while the same global write word line is set at the selected state. When all the data in one set of operation target data are written, the next global write word line is driven to the selected state in order to write the data in the next set of operation target data, and the block selection signal is returned to the initial value to write the data in the next set of operation target data. Then, the similar procedure is repeated to write the data in all the sets of operation target data.
In sub-array blocks BK0 to BKi, the set of operation target data is stored at the position corresponding to the same global read data line. In each of operation unit blocks OUBa and OUBb, the output of one sense amplifier circuit SAK is selected in each sub-array block and transferred to one global read data line RGL (RGLa and RGLb). Current summing lines VMa and VMb are provided in each of operation unit blocks OUBa and OUBb. Accordingly, in each of operation units OUBa and OUBb, the addition of the data stored in selected sub-array blocks is performed, and the corresponding ADC included in ADC band 812 performs the A/D conversion of the addition result.
In performing an operation, read selection signals CSL#<0> to CSL#<L> are sequentially selected, the sets of operation target data corresponding to different write word lines are selected to sequentially produce the operational result, and then, A/D converted data is produced. In such case, when the pipeline type ADC is used in ADC band 812, the operational result can be produced in the pipeline manner after the digital conversion. In the pipeline type ADC, one-stage unit conversion circuit is arranged per one bit, and the unit conversion circuits are cascaded.
In the configuration shown in
For example, the following configuration can be used for the configuration of the control circuit. Write word line address is sequentially updated and applied to the write decoder, and the block selection signal is produced so as to concurrently specify 16 sub-array blocks in the case where the number of p write target data, for example 16 four-bit data are transferred through the 64-bit data bus. In reading the data, read word lines of the number corresponding to the number of data bits are concurrently driven to the selected state such that the unit operator cells in which the data are already written are concurrently selected. Read selection signal CSL is sequentially updated for each read cycle. The sub-array block of the read target can be identified by setting the flag at the sub-array block in which the data are already written, and the data indicating the number of sub-array blocks concurrently driven to the selected state is stored in a register circuit, and the sub-array block can be driven to the selected state according to the value stored in the register circuit.
(Modification)
In the configuration of sense amplifier SA shown in
A flag register 1255 is provided for current source circuit 826. Addition and subtraction instruction flag ASF is stored in flag register 1255, and the conduction and non-conduction of MOS transistors QP11 and QN11 are controlled in response to current addition instruction signal /POEN and current subtraction instruction signal SUEN. In the case where the bit “0” is stored in flag register 1255, the addition is instructed, current addition instruction signal /POEN is activated (set at the L level) at a predetermined timing, thereby putting the transistor QP11 into the conductive state. At this time, current subtraction instruction signal SUEN is maintained in the inactive state of the L level, and transistor QN11 is held at the off-state. Accordingly, transistors QP1 and QP10 constitute the current-mirror circuit, and current K·Ic, that is, k times sense read bit line current Ic is supplied to global read data line RGL through read gate CSG.
On the other hand, in the case where the bit “1” is stored in flag register 1255, the subtraction is instructed, current addition instruction signal /POEN is set at the inactive state of the H level, and current subtraction instruction signal SUEN is activated (set at the H level). Therefore, transistor PQ11 maintains the non-conduction state and transistor NQ11 turns into the conduction state. Transistor QN10 and transistor QN6 constitute the current-mirror circuit to pass the current that is k times current Ic passing through sense read bit line RBL. Accordingly, the current corresponding to current Ic passing through read bit line RBL is extracted from global read line RGL. That is, the negative current is supplied. In such case, the subtraction is performed on data stored in the corresponding unit operator cells.
In
Using the sense amplifier circuit shown in
As for flag ASF stored in flag register 1255, when the input data is applied, the input data is transferred with a sign bit being attached at the highest-order bit location, and the highest-order bit is transferred to and latched in the flag register of the corresponding sub-array block, as addition and subtraction instruction flag ASF. Operation flag latch circuit 892 shown in
Thus, according to the semiconductor signal processing device of the twentieth embodiment, in the same column of one sub-array block, the bits of the operation target data are stored in unit operator cells of the number according to the bit position and read onto the sense read bit lines corresponding to the storage data, and sense amplifier circuit supplies the current corresponding to the sense read bit line current to the global read data line (negative current is supplied in the subtraction). Accordingly, the analog current corresponding to the storage data can correctly be read onto the global read data line to perform the current addition with the dummy cell current being the reference current. Therefore, similarly to the seventeenth embodiment, the addition and subtraction can be performed at high speed without producing the carry/borrow even under the low power supply voltage.
[Twenty-First Embodiment]
The configuration of the memory sub-array of sub-array blocks BK0 to BKs is similar to that of the twentieth embodiment shown in
The unit operator cell has the configuration shown in
Because the local write word lines are arranged in sub-array blocks BK0 to BKs, write word line decoder 1220 is commonly provided for the sub-array blocks of memory cell array 810 in order to drive the global write data lines.
The configuration of the twentieth embodiment shown in
In the configuration shown in
That is, the read gate is kept conductive for a time period corresponding to the weight of the bit position, to supply the current from the current source circuit included in the sense amplifier circuit. Thus, the current weighted according to a bit position is transmitted to a corresponding read global data line.
In sub-array block BKb to which bit <1> is allocated, data line drive circuits 1234 included in corresponding row/data line selection driving circuit XXDRb transmit least significant bits A#0<1> to A#m<1> of data A#0 to A#m and least significant bits B#0<1> to B#m<1> of data B#0 to B#m through data driving lines DIN0 to DINm to unit operator cells UOE connected to read word lines RWL0 to RWLm. Similarly, the data bits of the allocated bit positions of the operation target data are transferred to and stored in other sub-array blocks.
In sub-array blocks BKa and BKb, local write word lines WWL are arranged as in the twentieth embodiment, and the local write word line WW1 is driven to the selected state. Therefore, similarly to the twentieth embodiment, sub-decoder band 1225 is arranged adjacent to sense amplifier band 822 in each sub-array block.
In response to a block selection signal (not shown), local write word lines are driven to the selected state according to the bit width of the operation target data, and the operation target data bits are stored.
The write sequence of the operation target data is similar to that of the twentieth embodiment, and the global write word lines are sequentially driven to the selected state to write the data.
The set of operation target data are arranged in the same column of memory array 810, and another set of operation target data are disposed in different column. The block selection signal and global write word line are sequentially updated to write the operation data until the writing of necessary operation data is completed.
In reading the data, read word line drive circuits 1230 concurrently drives read word lines RWL (RWLA and RWLB) connected to the unit operator cells in which the data is already written to the selected state. The current corresponding to the value of the data bit stored in unit operator cell UOE passes through corresponding sense read bit line RBL. Sense amplifier circuit SAK produces the current of the magnitude corresponding to the current passing through sense read bit line RBL with the current supplied from dummy cell DMC being used as the reference current, and sense amplifier circuit SAK transmits the produced current to the corresponding global read bit line.
In
Bit position <0> is allocated to sub-array block BK0, and bit position <1> is allocated to sub-array block BK1. Bit position <k> is allocated to sub-block BKs. Similarly to the twentieth embodiment, the data are written in units of rows. That is, one local write word line is driven to the selected state, and data line drive circuits 1234 write the data in the sub-array block specified by the block selection signal.
In reading the data, read selection signals CSL#0<0> to CSL#s<0> are set at the on-state for unit operation blocks OUBa, OUBb, . . . . In this state, for sub-array block BK0, read selection signal CSL#0<0> is set at the on-state for the time t0. For sub-array block BK1, read selection signal CSL#1<0> is set at the on-state for the time 2·t0. For sub-array block BKs, read selection signal CSL#s<0> is set at the on-state for the time (2k)·t0. Accordingly, sense amplifier circuit SAK supplies the current to corresponding global read data line RGL for the time corresponding to the bit position allocated to each respective sub-array block.
In
The time during which read selection signal CSL# is kept in the selected state for the read section shown in
In
The sub-array blocks to which the same bit positions are allocated, that is, the number of sub-array blocks used can appropriately be determined according to the number of operation target data and operation contents.
Thus, according to the semiconductor signal processing device of the twenty-first embodiment, the operation data bit positions are previously allocated to memory sub-blocks, and the time during which the current supplied from the sense amplifier circuit passes through the global read data line is set according to the weight of each bit position. Thus, the addition can be performed at high speed. In each sub-array block, only one write word line and one read word line are driven to the selected state in writing and reading the data, respectively, so that the consumed current can be reduced.
In the above description, four-bit data is shown as the operation target data by way of example. However, any bit width of the operation target data may be used depending on the application.
In the above description, the SOI transistor is used as the unit operator cell. Alternatively, the present invention can be applied to the cell structure, such as an MRAM cell, in which the amount of current passing through the unit operator cell varies according to the storage data and therefore the current passing through the bit line changes.
For example, in the case where the MRAM cell is used, the sense amplifier shown in
The processing system in which the operation processing is performed at high speed with the low power consumption can be implemented by applying the semiconductor signal processing device of the present invention to the circuitry that performs the operational processing o various signals.
The first to fifteenth embodiments and the tenth to twenty-first embodiments can appropriately be combined.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being interpreted by the terms of the appended claims.
Arimoto, Kazutami, Shimano, Hiroki
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