A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.
|
43. An accumulated charge control (ACC) nmosfet (ACC nmosfet), comprising:
a. an nmosfet having a floating body, a gate, a source, a drain and a gate oxide layer between the gate and the body, and
b. an accumulated charge sink (acs) coupled to the body of the nmosfet;
wherein the nmosfet is selectively biased to operate in an accumulated charge regime, and for at least part of a time when so biased:
(1) but for the acs, accumulated charge accumulates within the body in a region proximate to the gate oxide; and
(2) an acs bias voltage (Vacs) is applied to the acs to remove or otherwise control the accumulated charge, wherein the Vacs is sufficiently negative with respect to ground, the source, and the drain and Vth to cause removal of or otherwise control the accumulated charge.
1. An accumulated charge control (ACC) nmosfet (ACC nmosfet), comprising:
a) an nmosfet having a floating body, a gate, a source, a drain and a gate oxide layer between the gate and the body, wherein the nmosfet is selectively biased to operate in an accumulated charge regime, and wherein, but for an accumulated charge control structure, accumulated charge accumulates within the body in a region proximate to the gate oxide when the nmosfet is biased to operate in the accumulated charge regime; and
b) an accumulated charge control structure comprising an accumulated charge sink (acs) coupled to the body of the nmosfet, wherein when the nmosfet is operated in the accumulated charge regime, an acs bias voltage (Vacs) is applied to the acs to remove or otherwise control the accumulated charge;
wherein the Vacs is sufficiently negative with respect to ground, the source, and the drain to cause removal or control of the accumulated charge.
20. An accumulated charge control nmosfet (ACC nmosfet), comprising:
a) an nmosfet including a floating body, a gate, a drain, a source, and a gate oxide layer between the gate and the body, wherein the nmosfet has a threshold voltage (Vth); and
b) an accumulated charge sink (acs) electrically coupled to the body of the nmosfet, wherein the nmosfet operates in an accumulated charge regime when the nmosfet is biased by means of a gate control voltage (Vg) to operate in an OFF-state (non-conducting state), and wherein, but for the acs, charge accumulates within the body in a region proximate the gate oxide, and wherein the nmosfet has no source-to-drain DC voltage applied thereto; and wherein an acs bias voltage (Vacs) is applied to the acs and thereby substantially prevents accumulated charge from accumulating in the body, and wherein Vacs is sufficiently negative with respect to ground, the source, the drain, and Vth to substantially prevent accumulated charge from accumulating in the body; and
c) a silicon-on-insulator substrate having at least a silicon layer and an insulating layer, wherein the nmosfet and acs are fabricated in the silicon layer to form the ACC nmosfet and wherein the nmosfet body is situated between the source, the drain, the gate oxide, and the insulating layer.
2. The ACC nmosfet of
3. The ACC nmosfet of
4. The ACC nmosfet of
5. The ACC nmosfet of
7. The ACC nmosfet of
8. The ACC nmosfet of
10. The ACC nmosfet of
11. The ACC nmosfet of
12. The ACC nmosfet of
13. The ACC nmosfet of
14. The ACC nmosfet of
15. The ACC nmosfet of
16. The ACC nmosfet of
17. The ACC nmosfet of
18. The ACC nmosfet of
19. The ACC nmosfet of
21. The ACC nmosfet of
22. The ACC nmosfet of
23. The ACC nmosfet of
25. The ACC nmosfet of
26. The ACC nmosfet of
27. The ACC nmosfet of
28. The ACC nmosfet of
29. The ACC nmosfet of
30. The ACC nmosfet of
31. The ACC nmosfet of
32. The ACC nmosfet of
33. The ACC nmosfet of
34. The ACC nmosfet of
35. The ACC nmosfet of
36. The ACC nmosfet of
37. The ACC nmosfet of
38. The ACC nmosfet of
41. The ACC nmosfet of
|
This application is a continuation application of co-pending U.S. application Ser. No. 13/028,144, “Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge”, filed Feb. 15, 2011, which is a divisional application of U.S. application Ser. No. 11/520,912, “Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge”, filed Sep. 14, 2006, issuing Feb. 15, 2011 as U.S. Pat. No. 7,890,891, which is a Continuation-in-Part (CIP) of commonly assigned U.S. patent application Ser. No. 11/484,370, filed Jul. 10, 2006, entitled “Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink”, now U.S. Pat. No. 7,910,993, issuing on Mar. 22, 2011 , which claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/698,523, filed Jul. 11, 2005, entitled “Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink”; and application Ser. No. 11/520,912, also claims the benefit under 35 U.S.C. §119 (e) of U.S. Provisional Application No. 60/718,260, filed Sep. 15, 2005, entitled “Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated CHARGE”; and the contents of application Ser. Nos. 11/484,370, 11/520,912, 13/028,144; and provisional application Nos. 60/698,523 and 60/718,260, are all incorporated by reference herein in their entirety.
1. Field
The present invention relates to metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates. In one embodiment, an SOI (or SOS) MOSFET is adapted to control accumulated charge and thereby improve linearity of circuit elements. In another embodiment, according to the present CIP, an SOI (or SOS) MOSFET is adapted to control accumulated charge and thereby improve gate oxide reliability.
2. Description of Related Art
Although the disclosed method and apparatus for use in improving the linearity of MOSFETs are described herein as applicable for use in SOI MOSFETs, it will be appreciated by those skilled in the electronic device design arts that the present teachings are equally applicable for use in SOS MOSFETs. The present teachings also apply to other semiconductor-on-insulator systems, wherein the silicon is replaced by another semiconductor such as silicon-germanium (SiGe). It will also be appreciated by those skilled in the electronic design arts that the present disclosed method and apparatus also apply to virtually any insulating gate technology, and to integrated circuits having a floating body. As those skilled in the art will appreciate, technologies are constantly being developed for achieving “floating body” implementations. For example, the inventors are aware of circuits implemented in bulk silicon wherein circuit implementations are used to “float” the body of the device. The disclosure contemplates embodiments of the disclosed method and apparatus implemented in any of the developing floating body implementations. Therefore, references to and exemplary descriptions of SOI MOSFETs herein are not to be construed as limiting the applicability of the present teachings to SOI MOSFETs only. Rather, as described below in more detail, the disclosed method and apparatus find utility in MOSFETs implemented in a plurality of device technologies, including SOS.
As is well known, a MOSFET employs a gate-modulated conductive channel of n-type or p-type conductivity, and is accordingly referred to as an “NMOSFET” or “PMOSFET”, respectively.
A source terminal 102 is operatively coupled to the source 112 so that a source bias voltage “Vs” may be applied to the source 112. A drain terminal 106 is operatively coupled to the drain 116 so that a drain bias voltage “Vd” may be applied to the drain 116. A gate terminal 104 is operatively coupled to the gate 108 so that a gate bias voltage “Vg” may be applied to the gate 108.
As is well known, when a voltage is applied between the gate and source terminals of a MOSFET, a generated electric field penetrates through the gate oxide to the transistor body. For an enhancement mode device, a positive gate bias creates a channel in the channel region of the MOSFET body through which current passes between the source and drain. For a depletion mode device, a channel is present for a zero gate bias. Varying the voltage applied to the gate modulates the conductivity of the channel and thereby controls the current flow between the source and drain.
For an enhancement mode MOSFET, for example, the gate bias creates a so-called “inversion channel” in a channel region of the body 114 under the gate oxide 110. The inversion channel comprises carriers having the same polarity (e.g., “P” polarity (i.e., hole carriers), or “N” polarity (i.e., electron carriers) carriers) as the polarity of the source and drain carriers, and it thereby provides a conduit (i.e., channel) through which current passes between the source and the drain. For example, as shown in the SOI NMOSFET 100 of
Depletion mode MOSFETs operate similarly to enhancement mode MOSFETs, however, depletion mode MOSFETs are doped so that a conducting channel exists even without a voltage being applied to the gate. When a voltage of appropriate polarity is applied to the gate the channel is depleted. This, in turn, reduces the current flow through the depletion mode device. In essence, the depletion mode device is analogous to a “normally closed” switch, while the enhancement mode device is analogous to a “normally open” switch. Both enhancement and depletion mode MOSFETs have a gate voltage threshold, Vth, at which the MOSFET changes from an off-state (non-conducting) to an on-state (conducting).
No matter what mode of operation an SOI MOSFET employs (i.e., whether enhancement or depletion mode), when the MOSFET is operated in an off-state (i.e., the gate voltage does not exceed Vth), and when a sufficient nonzero gate bias voltage is applied with respect to the source and drain, an “accumulated charge” may occur under the gate. The “accumulated charge”, as defined in more detail below and used throughout the present application, is similar to the “accumulation charge” described in the prior art literature in reference to MOS capacitors. However, the prior art references describe “accumulation charge” as referring only to bias-induced charge existing under a MOS capacitor oxide, wherein the accumulation charge is of the same polarity as the majority carriers of the semiconductor material under the capacitor oxide. In contrast, and as described below in more detail, “accumulated charge” is used herein to refer to gate-bias induced carriers that may accumulate in the body of an off-state MOSFET, even if the majority carriers in the body do not have the same polarity as the accumulated charge. This situation may occur, for example, in an off-state depletion mode NMOSFET, wherein the accumulated charge may comprise holes (i.e., having P polarity) even though the body doping is N− rather than P−.
For example, as shown in
As is well known, electron-hole pair carriers may be generated in MOSFET bodies as a result of several mechanisms (e.g., thermal, optical, and band-to-band tunneling electron-hole pair generation processes). When electron-hole pair carriers are generated within an NMOSFET body, for example, and when the NMOSFET is biased in an off-state condition, electrons may be separated from their hole counterparts and pulled into both the source and drain. Over a period of time, assuming the NMOSFET continues to be biased in the off-state, the holes (resulting from the separated electron-hole pairs) may accumulate under the gate oxide (i.e., forming an “accumulated charge”) underneath and proximate the gate oxide. A similar process (with the behavior of electrons and holes reversed) occurs in similarly biased PMOSFET devices. This phenomenon is now described with reference to the SOI NMOSFET 100 of
When the SOI NMOSFET 100 is operated with gate, source and drain bias voltages that deplete the channel carriers in the body 114 (i.e., the NMOSFET 100 is in the off-state), holes may accumulate underneath and proximate the gate oxide 110. For example, if the source bias voltage Vs and the drain bias voltage Vd are both zero (e.g., connected to a ground contact, not shown), and the gate bias voltage Vg comprises a sufficiently negative voltage with respect to ground and with respect to Vth, holes present in the body 114 become attracted to the channel region proximate the gate oxide 110. Over a period of time, unless removed or otherwise controlled, the holes accumulate underneath the gate oxide 110 and result in the accumulated charge 120 shown in
Accumulated Charge Regime Defined
The accumulated charge is opposite in polarity to the polarity of carriers in the channel. Because, as described above, the polarity of carriers in the channel is identical to the polarity of carriers in the source and drain, the polarity of the accumulated charge 120 is also opposite to the polarity of carriers in the source and drain. For example, under the operating conditions described above, holes (having “P” polarity) accumulate in off-state NMOSFETs, and electrons (having “N” polarity) accumulate in off-state PMOSFETs. Therefore, a MOSFET device is defined herein as operating within the “accumulated charge regime” when the MOSFET is biased to operate in an off-state, and when carriers having opposite polarity to the channel carriers are present in the channel region. Stated in other terms, a MOSFET is defined as operating within the accumulated charge regime when the MOSFET is biased to operate in an off-state, and when carriers are present in the channel region having a polarity that is opposite the polarity of the source and drain carriers.
For example, and referring again to
In another example, wherein the SOI NMOSFET 100 comprises a depletion mode device, Vth is negative by definition. According to this example, the body 114 comprises an N− region (as contrasted with the P− region shown in
In other examples, Vs and Vd may comprise nonzero bias voltages. In some embodiments, Vg must be sufficiently negative to both Vs and Vd (in order for Vg to be sufficiently negative to Vth, for example) in order to bias the NMOSFET in the off-state. Those skilled in the MOSFET device design arts shall recognize that a wide variety of bias voltages may be used to practice the present teachings. As described below in more detail, the present disclosed method and apparatus contemplates use in any SOI MOSFET device biased to operate in the accumulated charge regime.
SOI and SOS MOSFETs are often used in applications in which operation within the accumulated charge regime adversely affects MOSFET performance. As described below in more detail, unless the accumulated charge is removed or otherwise controlled, it detrimentally affects performance of SOI MOSFETs under certain operating conditions. One exemplary application, described below in more detail with reference to the circuits shown in
Therefore, it is desirable to provide techniques for adapting and improving SOI (and SOS) MOSFETs, and circuits implemented with the improved SOI MOSFETs, in order to remove or otherwise control the accumulated charge, and thereby significantly improve SOI MOSFET performance. It is desirable to provide methods and apparatus for use in improving the linearity characteristics in SOI MOSFETs. The improved MOSFETs should have improved linearity, harmonic distortion, intermodulation distortion, and BVDSS characteristics as compared with prior art MOSFETs, and thereby improve the performance of circuits implemented with the improved MOSFETs. The present teachings provide such novel methods and apparatus.
Gate Oxide Reliability and the Accumulated Charge Regime
The gate oxide is a critical component of a MOSFET. In many applications, including RF switch implementation, it is desirable to make the gate oxide as thin as possible. In RF circuit applications, thinner gate oxide results in higher on-currents and lower insertion losses for RF signals. However, if the gate oxide is too thin, the oxide will break down when a gate voltage is applied. When an electric field is applied to a gate oxide, there is typically a significant time interval before the gate oxide fails. The time required for a gate oxide to fail is a function of the applied electric field and temperature. This phenomenon is known as Time Dependent Dielectric Breakdown (TDDB). As a rough rule of thumb, at room temperature the electric field in a gate oxide should not exceed approximately 5 MV/cm for a desired lifetime or time-to-breakdown of ten years.
TDDB in gate oxides has been investigated extensively. One exemplary reference is an article entitled “A Unified Gate Oxide Reliability Model,” C. Hu and Q. Lu, 37th International Reliability Physics Symposium, San Diego, Calif. 1999. This paper discusses two major mechanisms for TDDB which occur under different stress conditions related to the strength of the applied electric field.
Another exemplary reference is a technical paper entitled “Low Electric Field Breakdown of Thin SiO2 Films Under Static and Dynamic Stress,” J. S. Suehle and P. Chaparala, IEEE Transactions on Electron Devices, Vol. 44, No. 5, May 1997. This reference reports an increase in gate oxide lifetime under bipolar pulsed stress (positive and negative voltage pulses) relative to unipolar (DC) stress. This effect occurs only at very large fields, and is attributed to relaxation of hole trapping occurring in the gate oxide. This phenomenon is unrelated to the improvements in gate oxide reliability that can be obtained by controlling accumulated charge in SOI MOSFETs, as described in more detail herein.
Still yet another reference relating to TDDB is a technical paper entitled “Reliability Issues for Silicon-on-insulator,” R. Bolam, et al., Electron Devices Meeting 2000, IEDM Technical Digest, December 2000. The authors report that there is no significant difference for TDDB failure in bulk Si devices and SOI devices fabricated in accordance with current art. The paper by C. Hu and Q. Lu, the reference by Suehle and Chaparala, and the reference by R. Bolam, cited above (referred to herein as the “TDDB references”), are hereby fully incorporated by reference herein, as though set forth in full for their teachings on the reliability of SiO2 when used as a gate dielectric.
The TDDB references cited above indicate that TDDB lifetime, at a given temperature, is dependent on the electric field in the gate oxide. When charge carriers are present beneath the gate oxide (e.g., when the MOSFET is in an on-state), the electric field in the oxide is approximately equal to the gate-to-source voltage divided by the gate oxide thickness. However, in accordance with teachings presented herein, persons skilled in the arts of electronic devices will appreciate that this is not necessarily the case for an SOI MOSFET operated in an off-state in the accumulated charge regime. In this case, the electric field that stresses the gate oxide is also affected by the presence of an accumulated charge under the gate. In particular, the inventors have discovered that removing or otherwise controlling the accumulated charge can significantly reduce the electric field that stresses the gate oxide and thereby improve the gate oxide reliability. Therefore, it is desirable to provide techniques for adapting and operating SOI MOSFET devices and circuits in order to control the accumulated charge and thereby significantly improve gate oxide reliability. The present teachings provide such novel techniques for adapting and operating SOI MOSFET devices.
Apparatuses and methods are provided to control accumulated charge in SOI MOSFETs, thereby improving nonlinear responses and harmonic and intermodulaton distortion effects in the operation of the SOI MOSFETs.
In one embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink (ACS), operatively coupled to the body of the SOI MOSFET, receives accumulated charge generated in the body, thereby reducing the nonlinearity of the net source-drain capacitance of the SOI MOSFET.
In one embodiment, the ACS comprises a high impedance connection to the MOSFET body, with an exemplary impedance greater than 106 ohm.
Embodiments Relating to Methods and Apparatuses for Improving Gate Oxide Reliability in Accordance with the Present CIP
Circuits with SOI MOSFETs are adapted to control accumulated charge in the SOI MOSFETs, thereby improving gate oxide reliability of the SOI MOSFETs.
In one embodiment, a circuit comprises an SOI MOSFET, operating in the accumulated charge regime, and means for accumulated charge control (ACC), operatively coupled to the SOI MOSFET. The SOI MOSFET is adapted to have a maximum electric field Etb in the gate oxide of the SOI MOSFET, where Etb corresponds to a desired lifetime or average time-to-breakdown for the gate oxide. The SOI MOSFET is adapted responsive to a first determination of the maximum electric field Eox1 in the gate oxide with an uncontrolled accumulated charge proximate to the gate oxide, and further responsive to second determination of the maximum electric field Eox2 in the gate oxide with a controlled accumulated charge proximate to the gate oxide. Determinations of Etb, Eox1, and Eox2 may be performed using well known techniques such as TDDB measurements and simulations of the SOI MOSFET operation.
According to another embodiment, a method for improving gate oxide reliability of an SOI MOSFET, operating in the accumulated charge regime, begins at a STEP (a). At the STEP (a), a first maximum electric field Eox1 in the gate oxide of the SOI MOSFET is determined with an uncontrolled accumulated charge proximate to the gate oxide. Proceeding to a STEP (b), a second maximum electric field Eox2 in the gate oxide of the SOI MOSFET is determined with a controlled accumulated charge proximate to the gate oxide. At a STEP (c), the SOI MOSFET is implemented in a circuit, wherein the SOI MOSFET is adapted to have a maximum electric field Etb in the gate oxide. The maximum electric field Etb corresponds to a desired lifetime or time-to-breakdown for the gate oxide. The SOI MOSFET is adapted responsive to the determinations of the STEPS (a) and (b). At a final STEP (d), the circuit is operated using a means for ACC operatively coupled to the SOI MOSFET.
In another embodiment, the SOI MOSFET is adapted by implementing a second thickness Tox2 of the gate oxide, wherein Tox2 is less than a first thickness Tox1 of the gate oxide. The first thickness Tox1 corresponds to the SOI MOSFET having the maximum electric field Eox1 in the gate oxide less than or equal to Etb when the SOI MOSFET is operated without the means for ACC operatively coupled to the SOI MOSFET. Implementation of the means for ACC enables the use of the lesser second thickness Tox2, without allowing the maximum electric field Eox2 in the gate oxide to exceed Etb.
According to another embodiment, the SOI MOSFET is adapted to enable a specified performance for the SOI MOSFET using the second thickness Tox2 and a second body width W2 of the SOI MOSFET (the terms “gate width,” “body width” and “transistor width” are used equivalently and interchangeably herein), wherein the second body width W2 is less than a first body width W1 of the SOI MOSFET. The first body width W1 corresponds to the SOI MOSFET being adapted to enable the specified performance using the first thickness Tox1. Using the lesser second gate oxide thickness Tox2 provides improvements in the performance of the SOI MOSFET, such as reduced insertion loss, improved on-state conductance, and improved transconductance. This allows the body width of the SOI MOSFET to be reduced while maintaining the specified performance. Advantages of reduced body width include smaller die size for lower manufacturing cost and reduced parasitic capacitance, and better performance such as improved linearity.
In a further embodiment, the SOI MOSFET is adapted by implementing a second limiting gate bias voltage Vg2 applied to a gate of the SOI MOSFET. Vg2 has an absolute value greater than the absolute value of a first limiting gate bias voltage Vg1 applied to the gate of the SOI MOSFET. Vg1 corresponds to the SOI MOSFET having the maximum electric field Eox1 in the gate oxide less than or equal to Etb when the SOI MOSFET is operated without the means for ACC operatively coupled to the SOI MOSFET. Implementation of the means for ACC enables the magnitude of the off-state limiting gate bias Vg2 to be increased over Vg1 without having the maximum electric field Eox2 in the gate oxide exceed Etb. More generally, using ACC allows the use of thinner gate oxide, larger gate bias magnitude, or a selected combination thereof.
In another embodiment, the means for ACC may comprise an Accumulated Charge Sink (ACS), having a resistance greater than 106 ohm, operatively coupled to a body region of the SOI MOSFET to receive and remove the accumulated charge.
In another exemplary embodiment, the means for ACC may comprise an ACS, having a resistance not greater than 106 ohm, operatively coupled to a body region of the SOI MOSFET to receive and remove the accumulated charge.
In yet another exemplary embodiment, the means for ACC may comprise a control circuit operatively coupled to a gate of the SOI MOSFET. The control circuit is adapted to apply a voltage pulse to the gate to switch the SOI MOSFET from the off-state to an on-state for a selected interval, thereby dissipating the accumulated charge proximate to the gate oxide.
In yet another exemplary embodiment, the means for ACC may comprise a resistor electrically connected to a gate of the SOI MOSFET sufficient to prevent attenuation of an induced RF voltage on the gate, and wherein an RF signal voltage is applied to a drain of the SOI MOSFET that generates the induced RF voltage, thereby reducing the accumulated charge.
According to other exemplary embodiments, the SOI MOSFET may be an NMOSFET or a PMOSFET. The SOI MOSFET may be fabricated using silicon-on-sapphire, or other SOI technologies, such as Separation by Implantation of Oxygen (SIMOX)), silicon bonded to insulator, etc. The exemplary circuit including the SOI MOSFET may be an RF switching circuit, an RF mixer, a power amplifier, a level shifting circuit, a negative voltage generator, an oscillator, a DC-DC converter or other circuit using SOI MOSFETs.
Like reference numbers and designations in the various drawings indicate like elements.
As noted above, those skilled in the electronic device design arts shall appreciate that the teachings herein apply equally to NMOSFETs and PMOSFETs. For simplicity, the embodiments and examples presented herein for illustrative purposes include only NMOSFETs, unless otherwise noted. By making well known changes to dopants, charge carriers, polarity of bias voltages, etc., persons skilled in the arts of electronic devices will easily understand how these embodiments and examples may be adapted for use with PMOSFETs.
Non-Linearity and Harmonic Distortion Effects of Accumulated Charge in an SOI NMOSFET
As described in the background section above, no matter what mode of operation the MOSFET employs (i.e., enhancement mode or depletion mode), under some circumstances, when a MOSFET is operated in an off-state with a nonzero gate bias voltage applied with respect to the source and drain, an accumulated charge may occur under the gate. According to the present teachings, as described above when the MOSFET is in an off-state, and when carriers are present in the channel region having a polarity that is opposite the polarity of the source and drain carriers, the MOSFET is said to be operating in the accumulated charge regime.
According to the present teachings, the inventors have observed that, when used in certain circuit implementations, MOSFETs operating in the accumulated charge regime exhibit undesirable non-linear characteristics that adversely impact circuit performance. For example, as described below in more detail with reference to
As shown in
A capacitor 206 represents the capacitance between the gate 108 and the body 114. A capacitor 202 represents the capacitance between the source 112 and the gate 108, and another capacitor 204 represents the capacitance between the drain 116 and the gate 108. A substrate capacitance due to the electrical coupling between the source 112 and the drain 116 (through the insulating substrate 118 shown in
As described above, when the NMOSFET 100 is in the off-state, and when the accumulated charge 120 (
However, when the NMOSFET 100 operates within the accumulated charge regime, and the accumulated charge 120 is therefore present in the body 114, mobile holes comprising the accumulated charge produce p-type conductivity between the source-body junction 218 and the drain-body junction 220. In effect, the accumulated charge 120 produces an impedance between the source-body junction 218 and the drain-body junction 220 that is significantly less than the impedance between the junctions in the absence of the accumulated charge. If a Vds voltage is applied between the drain 116 and the source 112, the mobile holes redistribute according to the electrical potentials that result within the body 114. DC and low-frequency current flow through the SOI NMOSFET 100 is prevented by the diode properties of the source-body junction 218 and the drain-body junction 220, as represented by the junction diodes 208 and 210, respectively. That is, because the junction diodes 208 and 210 are anti-series (i.e., “back-to-back”) in this case, no DC or low-frequency currents flow through the SOI NMOSFET 100. However, high-frequency currents may flow through the SOI NMOSFET 100 via the capacitances of the source-body junction 218 and the drain-body junction 220, as represented by the junction capacitors 214 and 216, respectively.
The junction capacitors 214 and 216 are voltage dependent because they are associated with junctions between n-type and p-type regions. This voltage dependence results from the voltage dependence of the width of the depletion region of the junction between the n-type and p-type regions. As a bias voltage is applied to the NMOSFET, the width of the depletion region of the junction between the n-type and p-type regions is varied. Because the capacitance of the junction depends on the width of the junction depletion region, the capacitance also varies as a function of the bias applied across the junction (i.e., the capacitance is also voltage dependent).
Further, the capacitors 202 and 204 may also have a voltage dependence caused by the presence of the accumulated charge 120. Although the complex reasons for this voltage dependence are not described in detail herein, persons skilled in the arts of electronic devices shall understand that electric field regions (e.g., electric field regions 122 and 124 described above with reference to
The voltage dependencies of the junction capacitors 214 and 216, the gate-to-source and gate-to-drain capacitors 202, 204, respectively, and the direct capacitance (not shown), cause nonlinear behavior in off-state capacitance Coff of the MOSFET when AC voltages are applied to the NMOSFET 100, thereby producing undesirable generation of harmonic distortions and intermodulation distortion (IMD). The relative contributions of these effects are complex, and depend on fabrication processes, biases, signal amplitudes, and other variables. However, those skilled in the electronic device design arts shall understand from the teachings herein that reducing, removing, or otherwise controlling the accumulated charge provides an overall improvement in the nonlinear behavior of Coff. In addition, because the body impedance 212 is significantly decreased in the presence of the accumulated charge 120, the magnitude of Coff may be increased when the FET operates in the accumulated charge regime. Reducing, removing, or otherwise controlling the accumulated charge also mitigates this effect.
The inventors have observed that the nonlinear behavior of the MOSFET off-state capacitance Coff adversely affects the performance of certain circuits implemented with the prior art SOI MOSFETs. For example, when an RF switch is implemented using the prior art SOI MOSFETs, such as the prior art SOI NMOSFET 100 of
For example, the well known GSM cellular communication system standard imposes stringent linearity, harmonic and intermodulation suppression, and power consumption requirements on front-end components used to implement GSM cell phones. One exemplary GSM standard requires that all harmonics of a fundamental signal be suppressed to below −30 dBm at frequencies up to 12.75 GHz. If harmonics are not suppressed below these levels, reliable cell phone operation can be significantly adversely impacted (e.g., increased dropped calls or other communication problems may result due to harmonic and intermodulation distortion of the transmit and receive signals). Because the RF switching function is generally implemented in the cell phone front-end components, improvements in the RF switch linearity, harmonic and intermodulation suppression, and power consumption performance characteristics is highly desirable. A description of how the non-linear behavior of the off-state capacitance Coff of the prior art MOSFETs adversely affects these RF switch characteristics is now described with reference to
Harmonic Distortion Effects on RF Switch Circuits Implemented Using Prior Art SOI MOSFETs
The MOSFET 254 acts as a pass or switching transistor and is configured, when enabled, to selectively couple an RF input signal (applied to its drain, for example) to an RF antenna 258 via a transmission path 256. The shunting MOSFETs, 260a-260e, when enabled, act to alternatively shunt the RF input signal to ground. As is well known, the switching MOSFET 254 is selectively controlled by a first switch control signal (not shown) coupled to its gate, and the shunting MOSFETs, 260a-260e are similarly controlled by a second switch control signal (not shown) coupled to their gates. The switching MOSFET 254 is thereby enabled when the shunting MOSFETs 260a-260e are disabled, and vice versa. As shown in the exemplary embodiment of the RF switch 250 of
When the switch 250 is configured in this state, the RF signal 252 propagates through the switching MOSFET 254, through the transmission path 256, and to the antenna 258. As described above with reference to
More specifically, when the accumulated charge is present in the channel regions of the off-state SOI MOSFETs 260a-260e it responds to variations in the RF signals applied to their respective drains. As the time varying RF signal propagates along the transmission path 256, the RF signal applies time varying source-to-drain bias voltages to the SOI MOSFETs 260a-260e. The time varying source-to-drain bias voltages creates movement of the accumulated charge within the channel regions of the SOI MOSFETs 260-260e. The movement of the accumulated charge within the channel regions of the SOI MOSFETs causes variations in the drain-to-source off-state capacitance of the SOI MOSFETs 260a-260e. More specifically, the movement of the accumulated charge within the channel regions causes a voltage dependence of the drain-to-source off-state capacitance as described above with reference to
As noted above, harmonic distortion and IMD of the RF signal is a major disadvantage of the prior art RF switch circuits implemented using the prior art SOI MOSFET devices. For many applications, harmonics and IMD of the RF signal must be suppressed to levels that heretofore have been difficult or impossible to achieve using prior art SOI MOSFET devices. In GSM devices, for example, at a maximum operating power of +35 dBm, prior art switches typically have only a 6 dB margin to the GSM third order harmonics suppression requirement of less than −30 dBm. Very low even order harmonic distortion is also desirable in GSM systems as the second order harmonic of the GSM transmit band also resides in the DCS receive band. Suppression of odd order (e.g., third order) harmonics of the RF signal, however, is desirable and improvements in that regard are needed.
In addition, as is well known, presence of an accumulated charge in the bodies of floating body (e.g., SOI) MOSFETs can also adversely affect the drain-to-source breakdown voltage (BVDSS) performance characteristics of the floating body MOSFETs. As is well known, floating-body FETs demonstrate drain-to-source breakdown voltage problems, also known as BVDSS, wherein the drain-to-source “punch-through” voltage is reduced by a parasitic bipolar action. The parasitic bipolar action is caused when holes are generated in the channel and the holes have nowhere to dissipate (i.e., because the body is floating, the holes have no means for escaping the body). As a consequence, the potential of the MOSFET body is increased, which effectively reduces the threshold voltage. In turn, this condition causes the MOSFET device to experience increased leakage, thereby generating more holes in the body, and thereby exacerbating the BVDSS problem (as a result of this positive feedback condition).
The present disclosed method and apparatus for improving linearity of SOI (and SOS) MOSFET devices overcomes the above-described disadvantages of the prior art. Once the accumulated charge is recognized as a major source of harmonic distortion, IMD and compression/saturation in off-state SOI MOSFET devices, and in circuits (such as RF circuits) implemented with these devices, it becomes clear that reduction, removal, and/or control of the accumulated charge improves the harmonic suppression characteristics of these devices. In addition, reduction, removal, and/or control of the accumulated charge also improves the BVDSS performance characteristics by preventing the parasitic bipolar action from occurring. Improvements in BVDSS lead to consequent improvements in device linearity. Several exemplary structures and techniques for controlling the accumulated charge in SOI MOSFETs are described in detail in the next section.
Method and Apparatus for Improving the Linearity of MOSFETs Using Accumulated Charge Sinks (ACS)—Overview
As described below in more detail, the present disclosure describes methods and apparatuses for improving semiconductor device linearity (e.g., reducing adverse harmonic distortion and IMD effects) in SOI MOSFETs. In one exemplary embodiment, the method and apparatus improves the linearity and controls the harmonic distortion and IMD effects of the MOSFET devices by reducing the accumulated charge in the bodies of the MOSFET devices. In one embodiment, the present method and apparatus reduces or otherwise controls the accumulated charge in the MOSFET bodies using an accumulated charge sink (ACS) that is operatively coupled to the MOSFET body. In one embodiment, the present method and apparatus entirely removes all of the accumulated charge from the bodies of the MOSFET devices. In one described embodiment, the MOSFET is biased to operate in an accumulated charge regime, and the ACS is used to entirely remove, reduce, or otherwise control, the accumulated charge and thereby reduce harmonic distortions and IMD that would otherwise result. Linearity is also improved in some embodiments by removing or otherwise controlling the accumulated charge thereby improving the floating body MOSFET BVDSS characteristics.
As noted in the background section above, persons skilled in the electronic device design and manufacture arts shall appreciate that the teachings herein apply equally to MOSFETs fabricated on Silicon-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates. As noted above, the present method and apparatus may also be applied to silicon-germanium (SiGe) SOI MOSFETs. For simplicity, the embodiments and examples presented herein for illustrative purposes include only NMOSFETs, unless otherwise noted. By making well known changes to dopants, charge carriers, polarity of bias voltages, etc., persons skilled in the electronic device design arts will easily understand how these embodiments and examples may be adapted for use with PMOSFETs.
As noted above, the present disclosure is particularly applicable to FETs and associated applications benefiting from a fully depleted channel when the FET is operated in the off-state, wherein an accumulated charge may result. The disclosed method and apparatus for use in improving the linearity of MOSFETs also finds applicability for use with partially depleted channels. As known to those skilled in the art, the doping and dimensions of the body vary widely. In an exemplary embodiment, the body comprises silicon having a thickness of approximately 100 angstroms to approximately 2,000 angstroms. In a further exemplary embodiment, dopant concentration within the FET bodies ranges from no more than that associated with intrinsic silicon to approximately 1×1018 active dopant atoms per cm3, resulting in fully-depleted transistor operation. In a further exemplary embodiment, dopant concentration within the FET bodies ranges from 1×1018 to 1×1019 active dopant atoms per cm3 and/or the silicon comprising the body ranges from a thickness of 2000 angstroms to many micrometers, resulting in partially-depleted transistor operation. As will be appreciated by those skilled in the electronic design and manufacturing arts, the present disclosed method and apparatus for use in improving linearity of MOSFETs can be used in MOSFETs implemented in wide variety of dopant concentrations and body dimensions. The present disclosed method and apparatus therefore is not limited for use in MOSFETs implemented using the exemplary dopant concentrations and body dimensions as set forth above.
According to one aspect of the present disclosure, accumulated charge within a FET body is reduced using control methodologies and associated circuitry. In one embodiment all of the accumulated charge is removed from the FET body. In other embodiments, the accumulated charge is reduced or otherwise controlled. In one embodiment, holes are removed from the FET body, whereas in another embodiment, electrons are removed from the FET body, as described below in more detail. By removing holes (or electrons) from the FET body using the novel and nonobvious teachings of the present disclosure, voltage induced variations in the parasitic capacitances of the off-state FETs are reduced or eliminated, thereby reducing or eliminating nonlinear behavior of the off-state FETs. In addition, as described above with reference to
Accumulated charge control not only facilitates a beneficial overall reduction in the FET off-state capacitance Coff (as described above with reference to
Reductions in harmonics and intermodulation distortion are generally beneficial in any semiconductor system, either bulk semiconductor or semiconductor-on-insulator (SOI) systems. SOI systems include any semiconductor architecture employing semiconductor-containing regions positioned above an underlying insulating substrate. While any suitable insulating substrate can be used in a SOI system, exemplary insulating substrates include silicon dioxide (e.g., a buried oxide layer supported by a silicon substrate, such as that known as Separation by Implantation of Oxygen (SIMOX)), bonded wafer (thick oxide), glass, and sapphire. As noted above, in addition to the commonly used silicon-based systems, some embodiments of the present disclosure may be implemented using silicon-germanium (SiGe), wherein the SiGe is used equivalently in place of Si.
A wide variety of ACS implementations and structures can be used to practice the present disclosed method and apparatus. In accordance with one embodiment of the present method and apparatus, an ACS is used to remove or otherwise control accumulated charge (referenced as 120 in
The ACC MOSFET is shown schematically embodied as a four-terminal device in
The operation of various exemplary RF switch circuits implemented using the ACC MOSFETs of the present disclosure is described below with reference to the circuit schematics of
Controlling Accumulated Charge Using an Accumulated Charge Sink (ACS)
Those skilled in the arts of electronic devices shall understand that the region 310 may be used to facilitate electrical coupling to the ACS 308 because in some embodiments it may be difficult to make a direct contact to a lightly doped region. In addition, in some embodiments the ACS 308 and the region 310 may be coextensive. In another embodiment, the region 310 comprises an N+ region. In this embodiment, the region 310 functions as a diode connection to the ACS 308, which prevents positive current flow into the ACS 308 (and also prevents positive current flow into the body 312) under particular bias conditions, as described below in more detail.
As is well known to those skilled in the electronic device design arts, in other embodiments, the ACC NMOSFET 300 of
Prior Art Body Contacts Distinguished from the Disclosed ACS
According to the present disclosure, the ACS 308 used to implement ACC SOI MOSFETs includes novel features in structure, function, operation and design that distinguish it from the so-called “body contacts” (also sometimes referred to as “body ties”, usually when the “body contact” is directly connected to the source) that are well known in the prior art.
Exemplary references relating to body contacts used in prior art SOI MOSFETs include the following: (1) F. Hameau and O. Rozeau, Radio-Frequency Circuits Integration Using CMOS SOI 0.25 μm Technology,” 2002 RF IC Design Workshop Europe, 19-22 Mar. 2002, Grenoble, France; (2) J. R. Cricci et al., “Silicon on Sapphire MOS Transistor,” U.S. Pat. No. 4,053,916, Oct. 11, 1977; (3) O. Rozeau et al., “SOI Technologies Overview for Low-Power Low-Voltage Radio-Frequency Applications,” Analog Integrated Circuits and Signal Processing, 25, pp. 93-114, Boston, Mass., Kluwer Academic Publishers, November 2000; (4) C. Tinella et al., “A High-Performance CMOS-SOI Antenna Switch for the 2.5-5-GHz Band, “IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, July, 2003; (5) H. Lee et al., “Analysis of body bias effect with PD-SOI for analog and RF applications,” Solid State Electron., Vol. 46, pp. 1169-1176, 2002; (6) J.-H. Lee, et al., “Effect of Body Structure on Analog Performance of SOI NMOSFETs,” Proceedings, 1998 IEEE International SOI Conference, 5-8 Oct. 1998, pp. 61-62; (7) C. F. Edwards, et al., The Effect of Body Contact Series Resistance on SOI CMOS Amplifier Stages,” IEEE Transactions on Electron Devices, Vol. 44, No. 12, December 1997 pp. 2290-2294; (8) S. Maeda, et al., Substrate-bias Effect and Source-drain Breakdown Characteristics in Body-tied Short-channel SOI MOSFET's,” IF Transactions on Electron Devices, Vol. 46, No. 1, January 1999 pp. 151-158; (9) F. Assaderaghi, et al., “Dynamic Threshold-voltage MOSFET (DTMOS) for Ultra-low Voltage VLSI,” IEEE Transactions on Electron Devices, Vol. 44, No. 3, March 1997, pp. 414-422; (10) G. O. Workman and J. G. Fossum, “A Comparative Analysis of the Dynamic Behavior of BTG/SOI MOSFETs and Circuits with Distributed Body Resistance,” IEEE Transactions on Electron Devices, Vol. 45, No. 10, October 1998 pp. 2138-2145; and (11) T.-S. Chao, et al., “High-voltage and High-temperature Applications of DTMOS with Reverse Schottky Barrier on Substrate Contacts,” IEEE Electron Device Letters, Vol. 25, No. 2, February 2004, pp. 86-88.
As described herein, applications such as RF switch circuits, may use SOI MOSFETs operated with off-state bias voltages, for which accumulated charge may result. The SOI MOSFETs are defined herein as operating within the accumulated charge regime when the MOSFETs are biased in the off-state, and when carriers having opposite polarity to the channel carriers are present in the channel regions of the MOSFETs. In some embodiments, the SOI MOSFETs may operate within the accumulated charge regime when the MOSFETs are partially depleted yet still biased to operate in the off-state. Significant benefits in improving nonlinear effects on source-drain capacitance can be realized by removing or otherwise controlling the accumulated charge according to the present teachings. In contrast to the disclosed techniques, none of the cited prior art teach or suggest ACS methods and apparatuses that are uniquely useful for removing or controlling accumulated charge. Nor are they informed regarding problems caused by the accumulated charge such as nonlinear effects on the off-state source-drain capacitance Coff. Consequently, the prior art body contacts described in the references cited above differ greatly (in structure, function, operation and design) from the ACSs described with reference to
In one example, the ACS 308 operates effectively to remove or otherwise control the accumulated charge from the SOI NMOSFET 300 using a high impedance connection to and throughout the body 312. High impedance ACSs may be used because the accumulated charge 120 is primarily generated by phenomena (e.g., thermal generation) that take a relatively long period of time to produce significant accumulated charge. For example, a typical time period for producing non-negligible accumulated charge when the NMOSFET operates in the accumulated charge regime is approximately a few milliseconds or greater. Such relatively slow generation of accumulated charge corresponds to very low currents, typically less than 100 nA/mm of transistor width. Such low currents can be effectively conveyed even using very high impedance connections to the body. According to one example, the ACS 308 is implemented with a connection having a resistance of greater than 106 ohms. Consequently, the ACS 308 is capable of effectively removing or otherwise controlling the accumulated charge 120 even when implemented with a relatively high impedance connection, relative to the low impedance prior art body contacts.
In stark contrast, the prior art teachings of body contacts described in the references cited above require low impedance (high efficiency) access to the body regions of SOI MOSFETs for proper operation (see, e.g., references (3), (6), and (7) above). A principal reason for this requirement is that the prior art body contacts are primarily directed to reducing the adverse effects on SOI MOSFET functions caused by much faster and more effective electron-hole pair generation processes than occur when the FET is operated in the accumulated charge regime. For example, in some prior art MOSFETs not operated in the accumulated charge regime, electron-hole pair carriers are generated as a result of impact ionization. Impact ionization produces electron-hole pairs at a much faster rate than occurs when the FET is operated in the accumulated charge regime.
The relative rates for electron-hole pair generation by impact ionization versus the pair generation processes causing accumulated charge can be estimated from the roll-off frequencies for the two phenomena. For example, reference (3) cited above indicates roll-off frequencies for impact ionization effects in the range of 105 Hz. In contrast, a roll-off frequency for the accumulated charge effects has been observed to be in the range of 103 Hz or less, as indicated by recovery times for odd harmonics. These observations indicate that the ACS 308 can effectively control accumulated charge using an impedance that is at least 100 times larger than required of prior art body contacts used in controlling impact ionization charge, for example. Further, because impact ionization primarily occurs when the SOI MOSFET operates in an on-state, the effects of impact ionization can be amplified by on-state transistor operation. Low impedance body contacts to and throughout a body region is even more critical in these environments in order to control the effects of impact ionization under the on-state conditions.
In stark contrast, the ACS 308 of the present teachings removes or otherwise controls the accumulated charge only when the ACC SOI MOSFET operates in the accumulated charge regime. By definition, the FET is in the off-state in this regime, so there is no requirement to remove impact ionization as amplified by an on-state FET. Therefore, a high impedance ACS 308 is perfectly adequate for removing the accumulated charge under these operating conditions. The prior art requirements for low impedance body connections results in numerous problems of implementation that are overcome by the present teachings, as described below in more detail.
In addition, the ACS 308 may be implemented with much lower source-to-drain parasitic capacitance as compared to the body contacts of the prior art. The above-described low impedance connection to the SOI MOSFET body required of the prior art body contacts necessitates proximity of the contacts to the entire body. This may require a plurality body contact “fingers” that contact the body at different locations along the body. The low impedance connection to the body also necessitates proximity of the prior art body contacts to the source and drain. Because of parasitic capacitances produced by such body contacts, the cited prior art references teach away from the use of such structures for many high frequency applications such as RF. In stark contrast, the ACS 308 of the present disclosure may be positioned away from the source 304, the body 312, and the drain 306, as shown in
Further, because impact ionization hole currents are much larger (in the range of 5,000 nA per mm body width) than for accumulated charge generation (less than approximately 100 nA per mm body width), the prior art does not teach how to effectively implement very large body widths (i.e., much greater than approximately 10 μm). In contrast, the ACS 308 of the present disclosed device may be implemented in SOI MOSFETs having relatively large body widths. This provides improvements in on-state conductance and transconductance, insertion loss and fabrication costs, particularly for RF switch devices. According to the prior art teachings cited above, larger body widths adversely affect the efficient operation of body contacts because their impedances are necessarily thereby increased. Although the cited prior art suggests that a plurality of fingers may be used to contact the body at different locations, the plurality of fingers adversely affects parasitic source-to-drain capacitances, as described above.
For these reasons, and for the reasons described below in more detail, the present disclosure provides novel MOSFET devices, circuits and methods that overcome the limitations according to the prior art teachings as cited above.
As described above with reference to
In most embodiments, as described above with reference to
In accordance with the disclosed method and apparatus, when the ACC NMOSFET 300′ is biased to operate in the accumulated charge regime (i.e., when the ACC NMOSFET 300′ is in the off-state, and there is an accumulated charge 120 of P polarity (i.e., holes) present in the channel region of the body 312), the accumulated charge is removed or otherwise controlled via the ACS terminal 308′. When accumulated charge 120 is present in the body 312, the charge 312 can be removed or otherwise controlled by applying a bias voltage (Vb (for “body”) or VACS (ACS bias voltage)) to the ACS terminal 308′. In general, the ACS bias voltage VACS applied to the ACS terminal 308′ may be selected to be equal to or more negative than the lesser of the source bias voltage Vs and drain bias voltage Vd. More specifically, in some embodiments, the ACS terminal 308′ can be coupled to various accumulated charge sinking mechanisms that remove (or “sink”) the accumulated charge when the FET operates in the accumulated charge regime. Several exemplary accumulated charge sinking mechanisms and circuit configurations are described below with reference to
Similar to the prior art NMOSFET 100 described above with reference to
However, those skilled in the electronics design arts shall appreciate that a myriad of bias voltages can be applied to the four device terminals while still employing the techniques of the present disclosed method and apparatus. As long as the ACC SOI NMOSFET 300′ is biased to operate in the accumulated charge regime, the accumulated charge can be removed or otherwise controlled by applying a bias voltage VACS to the ACS terminal 308′, and thereby remove the accumulated charge from the body 312.
For example, in one embodiment wherein the ACC NMOSFET 300′ comprises a depletion mode device, Vth is negative by definition. In this embodiment if both the Vs and Vd bias voltages comprise zero volts (i.e., both terminals tied to circuit ground node), and a gate bias Vg applied to the gate terminal 302′ is sufficiently negative to Vth (for example, Vg is more negative than approximately −1 V relative to Vth), holes may accumulate under the gate oxide 110 thereby becoming the accumulated charge 120. In this example, in order to remove the accumulated holes (i.e., the accumulated charge 120) from the FET body 312, the voltage VACS applied to the ACS 308 may be selected to be equal to or more negative than the lesser of Vs and Vd.
In other examples, the source and drain bias voltages, Vs and Vd, respectively, may comprise voltage other than zero volts. According to these embodiments, the gate bias voltage Vg must be sufficiently negative to both Vs and Vd (in order for Vg to be sufficiently negative to Vth, for example) in order to bias the NMOSFET in the off-state. As described above, if the NMOSFET is biased in the off-state for a sufficiently long time period (approximately 1-2 ms, for example) an accumulated charge will accumulate under the gate oxide. In these embodiments, as noted above, in order to remove the accumulated charge 120 from the body 312, the ACS bias voltage VACS applied to the ACS terminal 308′ may be selected to be equal to or more negative than the lesser of Vs and Vd.
It should be noted that, in contrast to the examples described above, the prior art body contacts are implemented largely for purposes of mitigating the adverse effects caused by impact ionization. Consequently, the prior art body contacts are typically tied to the source of the MOSFET. In order to effectively control, reduce, or entirely remove the accumulated charge in an NMOSFET, VACS should, in the exemplary embodiments, be equal to or more negative than the lesser of Vs and Vd. Those skilled in the electronic device design arts shall appreciate that different Vs, Vd, Vg and VACS bias voltages may be used when the ACC MOSFET comprises a PMOSFET device. Because the prior art body contacts are typically tied to the source, this implementation cannot be effected using the prior art body contact approach.
View line A-A′ slices through the following component regions of the ACC NMOSFET 300′″: the P+ region 310, the ACS 308 (shown in
Although the present teachings encompass such embodiments described above, those skilled in the electronic device design and manufacturing arts shall recognize that such low-resistance connections are not required. Therefore, the disadvantages associated with the embodiment shown in
Owing to the presence of the P+ overlap region 310′ over the gate oxide 110, over the body 312, and proximate an edge 340 of the poly-silicon gate 302, an increased threshold voltage is created in one region of the NMOSFET 300′″. More specifically, due to the P+ doping (in the overlap region 310′) proximate the edge 340 of the gate 302 over the channel region of the body 312, a higher magnitude threshold voltage is created in that portion of the MOSFET 300′″. The effects of the increased threshold voltage are now described in more detail with reference to
The threshold voltage increase can be reduced by reducing the size of the region 307. Eliminating the region 307 will eliminate the threshold voltage increase. Because the threshold voltage increase can increase harmonic and intermodulation distortion of the “on” MOSFET, eliminating this effect improves device performance.
In one exemplary embodiment, as shown, for example in the embodiments of the ACC NMOSFET 300 described above with reference to
In another exemplary embodiment, as described below with reference to
Moreover, as described above with reference to
It shall be understood by those skilled in the electronic device design arts that although the illustrated embodiment shows the ACSs 308 and 308″ extending approximately the entire width of the ACC NMOSFET 300′″″, the ACSs 308 and 308″ may also comprise much narrower (or wider) regions, and still function perfectly well to remove or otherwise control the accumulated charge. Also, in some embodiments, it is not necessary that the impedance of the ACS 308 matches the impedance of the ACS 308″. It will further be understood by the skilled person that the ACSs 308 and 308″ may comprise different sizes and configurations (i.e., rectangular, square, or any other convenient shape), and may also be positioned at various distances away from the body 312 (i.e., not necessarily the same distance away from the body 312). As described above with reference to
Four-Terminal ACC MOSFET Devices—Simple Circuit Configurations
The SOI NMOSFET 300 of
The ACC SOI NMOSFET 300 of
Advantageously, the accumulated charge can be removed via the ACS terminal 408 by connecting the ACS terminal 408 to the gate terminal 402 as shown. This configuration ensures that when the FET 300 is in the off-state, it is held in the correct bias region to effectively remove or otherwise control the accumulated charge. As shown in
In other exemplary embodiments, as described above with reference to
In another exemplary embodiment, as described above, the ACC NMOSFET 300 comprises a depletion mode device. In this embodiment, the threshold voltage, Vth is, by definition, less than zero. For Vs and Vd both at zero volts, when a gate bias Vg sufficiently negative to Vth is applied to the gate terminal 402 (for example, Vg more negative than approximately −1 V relative to Vth), holes may accumulate under the gate oxide and thereby comprise an accumulated charge. For this example, the voltage VACS may also be selected to be equal to Vg by connecting the ACS terminal 408 to the gate terminal 402, thereby conveying the accumulated charge from the ACC NMOSFET as described above.
In some embodiments of the improved ACC SOI NMOSFET 300, such as that described above with reference to
Another exemplary simplified circuit using the improved ACC SOI NMOSFET 300 is shown in
As with the device shown in
When the SOI NMOSFET 300 is biased in an on condition, the diode 410 is reverse-biased, thereby preventing the flow of positive current into the source and drain regions. The reverse-biased configuration reduces power consumption and improves linearity of the device. The circuit shown in
With the exception of the diode 410 used to prevent the flow of positive current into the ACS terminal 408, exemplary operation of the simplified circuit shown in
In yet another embodiment, the ACS terminal 408 may be coupled to a control circuit 412 as illustrated in the simplified circuit of
It may be desirable to provide a negative ACS bias voltage VACS to the ACS terminal 408 when the SOI NMOSFET 300 is biased into an accumulated charge regime. In this exemplary embodiment, the control circuit 412 may prevent positive current flow into the ACS terminal 408 by selectively maintaining an ACS bias voltage VACS that is consistently negative with respect to both the source and drain bias voltages. In particular, the control circuit 412 may be used to apply an ACS bias voltage that is equal to or more negative than the lesser of Vs and Vd. By application of such an ACS bias voltage, the accumulated charge is thereby removed or otherwise controlled.
In the exemplary embodiment of the simplified circuit shown in
In other embodiments, Vs and Vd may comprise bias voltages that are other than zero. According to these examples, Vg must be sufficiently negative to both Vs and Vd in order for Vg to be sufficiently negative to Vth, in order to bias the NMOSFET 300 in the off-state. This allows the accumulation of accumulated charge under the gate oxide. For this example, the ACS bias voltage VACS may be selected to be equal to or more negative than the lesser of Vs and Vd by connecting the ACS terminal 408 to the control circuit 412 to provide selected ACS bias voltages, thereby conveying the accumulated charge from the ACC NMOSFET 300.
In other embodiments, if the ACC NMOSFET 300 of
As described above, in one embodiment, instead of having the control circuit 412 provide a bias to the ACS terminal 408 as shown in
In another embodiment, the circuit shown in
In one exemplary circuit, as shown in
In some embodiments, such as for example in an RF switch circuit, the gate terminal 402 and the ACS terminal 408 follow Vds at half the value (Vds/2) of Vds. At high Vds excursions, Vgs may approach the threshold voltage Vth, resulting in increased Ids leakage current. In some cases, such a leakage current exits the ACS terminal 408 and can overwhelm associated circuitry (e.g., a negative voltage generator). Hence, the circuit shown in
In yet another exemplary embodiment, the simplified circuit shown in
As shown in the simplified circuit of
In some circuit embodiments, body nodes of a multi-finger FET implementation may be connected to one another (using, for example, metal or silicon), overlapping the source fingers. On another side of the FET implementation, gate nodes may be are connected to one another (using, for example, metal or silicon) overlapping the drain fingers. As a result of this FET implementation, additional capacitance may result between the source and body (S-B), and further additional capacitance may result between the drain and gate (D-G). These additional capacitances may degrade the symmetry of the intrinsic device. Under AC excitation, this results in the gate terminal following the drain terminal more closely, and the body terminal following the source terminal more closely, which effectively creates an AC signal across the diode 410, which can excite nonlinearities of the diode 410 as described above. Using the exemplary embodiment shown in
Improved Coff Performance Characteristics of ACC MOSFETs Made in Accordance with the Present Disclosed Method and Apparatus
As described above with reference to
Exemplary Improved Performance RF Switch Implementations Using ACC SOI MOSFETs in Accordance with the Present Teachings
Referring again to
Referring again to
The first and second control signals, C1 and C1x, respectively, are generated so that the SOI NMOSFET 506 operates in an on-state when the SOI NMOSFET 508 operates in an off-state, and vice versa. These control signals provide the gate bias voltages Vg to the gate terminals of the NMOSFETs 506 and 508. When either of the NMOSFETs 506 or 508 is biased to select the transistor off-state, the respective Vg must comprise a sufficiently large negative voltage so that the respective NMOSFET does not enter, or approach, an on-state due to the time varying applied voltages of the RF input signal RFin. The maximum power of the RF input signal RFin is thereby limited by the maximum magnitude of the gate bias voltage Vg (or, more generally, the gate-to-source operating voltage, Vgs) that the SOI NMOSFETs 506 and 508 can reliably sustain. For RF switching circuits such as those exemplified herein, Vgs(max)=Vg+Vds(max)/2, where Vds=Vd−Vs, and Vds(max) comprises the maximum Vds due to the high-power input signal voltage levels associated with the RF input signal RFin.
Exemplary bias voltages for the SOI NMOSFETs 506 and 508 may include the following: with Vth approximately zero volts, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of −2.5 V. For these bias voltages, the SOI NMOSFETs may eventually operate in an accumulated charge regime when placed into their off-states. In particular, and as described above with reference to
Exemplary bias voltages for the NMOSFET 526 and the ACC NMOSFET 528 may include: with Vth approximately zero, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of −2.5 V. For these bias voltages, the SOI NMOSFETs may operate in an accumulated charge regime when placed into the off-state. However, when the NMOSFET 526 is in the on-state and the ACC NMOSFET 528 is in the off-state, the output signal RFout at the output terminal 505 will not be distorted by nonlinear behavior of the off-state capacitance Coff of the improved ACC NMOSFET 528 due to the accumulated charge. When the ACC NMOSFET 528 operates in the accumulated charge regime, the accumulated charge is removed via the ACS terminal 508′. More specifically, because the gate terminal 502′ of the ACC NMOSFET 528 is connected to the ACS terminal 508′, the accumulated charge is removed or otherwise controlled as described above in reference to the simplified circuit of
Exemplary bias voltages for the NMOSFET 526 and the ACC NMOSFET 528 may include the following: with Vth approximately zero volts, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of −2.5 V. For these bias voltages, the SOI NMOSFETs 526, 528 may operate in an accumulated charge regime when placed into an off-state. However, when the NMOSFET 526 is in the on-state and the ACC NMOSFET 528 is in the off-state, the output signal RFout will not be distorted by nonlinear behavior of the off-state capacitance Coff of the ACC NMOSFET 528 due to the accumulated charge. Because the gate terminal 502′ of the ACC NMOSFET 528 is connected to the ACS terminal 508′ via a diode 509, the accumulated charge is entirely removed, reduced or otherwise controlled, as described above with reference to
Exemplary bias voltages for the NMOSFET 526 and the ACC NMOSFET 528 may include the following: with Vth approximately zero volts, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of −2.5 V. For these bias voltages, the SOI NMOSFETs 526, 528 may operate in an accumulated charge regime when placed into the off-state. However, when the NMOSFET 526 is in the on-state and the ACC NMOSFET 528 is in the off-state, the output signal RFout produced at the output terminal 505 will not be distorted by the nonlinear behavior of the off-state capacitance Coff of the ACC NMOSFET 528 due to the accumulated charge. When the NMOSFET 528 operates in the accumulated charge regime, the accumulated charge is removed via the ACS terminal 508′. More specifically, because the ACS terminal 508′ of the ACC NMOSFET 528 is electrically coupled to the control circuit 520 via the control line 517 (i.e., controlled by the control signal “C2” as shown), the accumulated charge can be eliminated, reduced or otherwise controlled by applying selected bias voltages to the ACS terminal 508′ as described above with reference to
In the circuits described above with respect to
Exemplary RF Switch Implementation Using Stacked Transistors
In the exemplary embodiments of RF switch circuits described above, the switch circuits are implemented using a single SOI NMOSFET (e.g., the single SOI NMOSFET 506 of
One example of how stacked NMOSFETs may be implemented in accordance with the teachings of the present disclosure is illustrated in
Three stacked ACC SOI NMOSFETs are shown in each ACC NMOSFET stack in the exemplary stacked RF switch circuit 600 of
Other stacked RF switch circuits, adapted for accumulated charge control, analogous to the circuits described above with reference to
Exemplary Method of Operation
At the STEP 704, the ACC SOI MOSFET is controlled, at least part of the time, so that it operates in an accumulated charge regime. In most embodiments, as described above, the ACC MOSFET is operated in the accumulated charge regime by applying bias voltages that place the FET in an off-state condition. In one exemplary embodiment, the ACC SOI MOSFET comprises an ACC SOI NMOSFET that is configured as part of a shunting circuit of an RF switch. According to this exemplary embodiment, the SOI NMOSFET may be operated in an accumulated charge regime after the shunting circuit is placed into an off-state by applying a negative bias voltage to the gate terminal of the ACC NMOSFET.
The method then proceeds to a STEP 706, whereat the accumulated charge that has accumulated in the channel region of the ACC MOSFET is removed or otherwise controlled via the ACS terminal. In this embodiment, the accumulated charge is conveyed to another circuit terminal and is thereby reduced or otherwise controlled. One such exemplary circuit terminal that can be used to convey the accumulated charge from the MOSFET body comprises a gate terminal of the ACC MOSFET (see, e.g., the description above with reference to
Exemplary RF Switch Implementations Using Stacked Transistors Having Source to Drain Resistors
As shall be appreciated by skilled persons from the present teachings, removal of the accumulated charge via the ACS terminal causes current to flow from the body of the ACC SOI MOSFET. For example, when a hole current flows from the body of an ACC SOI MOSFET via the ACS, an equal electron current flows to the FET source and/or drain. For some circuits (e.g., the RF switch circuit of
Exemplary operating voltages for the NMOSFETs 602-606 of
Even currents smaller than the exemplary currents may produce adverse affects on the operation of the RF switching circuit 800 by reducing Vgs and/or Vgd of the ACC SOI MOSFETs 620-624 in the off-state, thereby reducing the power handling capability and reliability of the circuit by increasing leakage (e.g., when either Vgs or Vgd approaches Vth), by increasing hot-carrier damage caused by excess leakage, etc. Linearity of the MOSFETs is also degraded by reducing Vgs and/or Vgd when either value approaches Vth.
Exemplary values for the Rds resistors 802 to 806 may be selected in some embodiments by selecting a value approximately equal to the resistance of the gate resistors 632-636 divided by the number of ACC SOI NMOSFETs in the stack (in the exemplary embodiment, there are three ACC FETs in the stack). More generally, the value of the Rds resistors may be equal to the gate resistor value divided by the number of ACC SOI NMOSFETs in the stack. In one example, a stack of eight ACC SOI NMOSFETs may have gate resistors of 80 kohm and Rds resistors of 10 kohm.
In some embodiments, the Rds resistors may be selected so that they do not adversely affect switch performance characteristics, such as, for example, the insertion loss of the switch 800 due to the off-state ACC SOI NMOSFETs. For example, for a net shunt resistance greater than 10 kohm, the insertion loss is increased by less than 0.02 dB.
In other embodiments, the Rds resistors may be implemented in circuits comprising a single ACC SOI MOSFET (as contrasted with the stacked shunting configuration exemplified in
A first control signal C1 is provided to control the operating states of the ACC SOI NMOSFETs 526 and 528′ (i.e., C1 selectively operates the FETs in the on-state or the off-state). Similarly, a second control signal C1x is provided to control the operating states of the ACC SOI NMOSFETs 528 and 526′. As is well known, and as described for example in the above incorporated commonly assigned U.S. Pat. No. 6,804,502, the control signals C1 and C1x are generated so that the ACC SOI NMOSFETs 526 and 528′ are in an on-state when the ACC SOI NMOSFETs 528 and 526′ are in an off-state, and vice versa. This configuration allows the RF switch circuit 900 to selectively convey either the signal RF1 or RF2 to the RF common output node 903.
A first ACS control signal C2 is configured to control the operation of the ACS terminals of the SOI NMOSFETs 526 and 528′. A second ACS control signal C2x is configured to control the ACS terminals of the ACC SOI NMOSFETs 528 and 526′. The first and second ACS control signals, C2 and C2x, respectively, are selected so that the ACSs of the associated and respective NMOSFETs are appropriately biased in order to eliminate, reduce, or otherwise control their accumulated charge when the ACC SOI NMOSFETs operate in an accumulated charge regime.
As shown in the RF switch circuit 900 of
Additional Exemplary Benefits Afforded by the ACC MOSFETs of the Present Disclosure
As described above, presence of the accumulated charge in the bodies of the SOI MOSFETs can adversely affect the drain-to-source breakdown voltage (BVDSS) performance characteristics of the floating body MOSFETs. This also has the undesirable affect of worsening the linearity of off-state MOSFETs when used in certain circuits such as RF switching circuits. For example, consider the shunting SOI NMOSFET 528 shown in
When sufficiently large signals are input that cause the NMOSFET 528 to enter a BVDSS regime, some of the RF current is clipped, or redirected through the NMOSFET 528 to ground, resulting in a loss of signal power. This current “clipping” causes compression behavior that can be shown, for instance, in a RF switch “Pout vs. Pin” plot. This is frequently characterized by P1 dB, wherein the insertion loss is increased by 1.0 dB over the small-signal insertion loss. This is an obvious indication of nonlinearity of the switch. In accordance with the present disclosed method and apparatus, removing, reducing or otherwise controlling the accumulated charge increases the BVDSS point. Increases to the BVDSS point of the NMOSFET 528 commensurately increases the large-signal power handling of the switch. As an example, for a switch, doubling the BVDSS voltage of the ACC NMOSFET increases the P1 dB point by 6 dB. This is a significant accomplishment as compared with the prior art RF switch designs.
In addition, as described above in more detail, presence of the accumulated charge in SOI MOSFET body adversely impacts the magnitude of Coff and also takes time to form when the FET is switched from an on-state to an off-state. In terms of switch performance, the nonlinearity of Coff adversely impacts the overall switch linearity performance (as described above), and the magnitude of Coff adversely affects the small-signal performance parameters such as insertion loss, insertion phase (or delay), and isolation. By reducing the magnitude of Coff using the present disclosed method and apparatus, the switch (implemented with ACC MOSFETs) has reduced insertion loss due to lowered parasitic capacitance, reduced insertion phase (or delay), again due to lowered parasitic capacitance, and increased isolation due to less capacitive feedthrough.
The ACC MOSFET also improves the drift characteristic of SOI MOSFETs as pertains to the drift of the small-signal parameters over a period of time. As the SOI MOSFET takes some time to accumulate the accumulated charge when the switch is off, the Coff capacitance is initially fairly small. However, over a period of time while operated in the accumulated charge regime, the off-state capacitance Coff increases toward a final value. The time it takes for the NMOSFET to reach a full accumulated charge state depends on the electron-hole pair (EHP) generation mechanism. Typically, this time period is on the order of approximately hundreds of milliseconds for thermal EHP generation at room temperature, for example. During this charge-up time period, the insertion loss and insertion phase increase. Also, during this time period, the isolation decreases. As is well known, these are undesirable phenomena in standard SOI MOSFET devices. These problems are alleviated or otherwise mitigated using the ACC NMOSFETs and related circuits described above.
In addition to the above-described benefits afforded by the disclosed ACC MOSFET method and apparatus, the disclosed techniques also allow the implementation of SOI MOSFETs having improved temperature performance, improved sensitivity to Vdd variations, and improved sensitivity to process variations. Other improvements to the prior art SOI MOSFETs afforded by the present disclosed method and apparatus will be understood and appreciated by those skilled in the electronic device design and manufacturing arts.
Exemplary Fabrication Methods
In one embodiment of the present disclosure, the exemplary RF switches described above may be implemented using a fully insulating substrate silicon-on-insulator (SOI) technology. Also, as noted above, in addition to the commonly used silicon-based systems, some embodiments of the present disclosure may be implemented using silicon-germanium (SiGe), wherein the SiGe is used equivalently in place of silicon.
In some exemplary embodiments, the MOSFET transistors of the present disclosure may be implemented using “Ultra-Thin-Silicon (UTSi)” (also referred to herein as “ultrathin silicon-on-sapphire”) technology. In accordance with UTSi manufacturing methods, the transistors used to implement the inventive methods disclosed herein are formed in an extremely thin layer of silicon in an insulating sapphire wafer. The fully insulating sapphire substrate enhances the performance characteristics of the inventive RF circuits by reducing the deleterious substrate coupling effects associated with non-insulating and partially insulating substrates. For example, insertion loss improvements may be realized by lowering the transistor on-state resistances and by reducing parasitic substrate conductance and capacitance. In addition, switch isolation is improved using the fully insulating substrates provided by UTSi technology. Owing to the fully insulating nature of silicon-on-sapphire technology, the parasitic capacitance between the nodes of the RF switches is greatly reduced as compared with bulk CMOS and other traditional integrated circuit manufacturing technologies.
Examples of and methods for making silicon-on-sapphire devices that can be implemented in the MOSFETs and circuits described herein, are described in U.S. Pat. No. 5,416,043 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,492,857 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,572,040 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,596,205 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,600,169 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,663,570 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,861,336 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,863,823 (“Self-aligned edge control in silicon on insulator”); U.S. Pat. No. 5,883,396 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”); U.S. Pat. No. 5,895,957 (“Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer”); U.S. Pat. No. 5,920,233 (“Phase locked loop including a sampling circuit for reducing spurious side bands”); U.S. Pat. No. 5,930,638 (“Method of making a low parasitic resistor on ultrathin silicon on insulator”); U.S. Pat. No. 5,973,363 (“CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator”); U.S. Pat. No. 5,973,382 (“Capacitor on ultrathin semiconductor on insulator”); and U.S. Pat. No. 6,057,555 (“High-frequency wireless communication system on a single ultrathin silicon on sapphire chip”). All of these referenced patents are incorporated herein in their entirety for their teachings on ultrathin silicon-on-sapphire integrated circuit design and fabrication.
Similarly to other bulk and SOI CMOS processes, an SOS enhancement mode NMOSFET, suitable for some embodiments of the present disclosure, may, in some embodiments, be fabricated with a p-type implant into the channel region with n-type source and drain regions, and may have a threshold voltage of approximately +500 mV. The threshold voltage is directly related to the p-type doping level, with higher doping resulting in higher thresholds. Similarly, the SOS enhancement mode PMOSFET may, in some exemplary embodiments, be implemented with a n-type channel region and p-type source and drain regions. Again, the doping level defines the threshold voltage with higher doping resulting in a more negative threshold.
In some exemplary embodiments, an SOS depletion-mode NMOSFET, suitable for some embodiments of the present disclosure, may be fabricated by applying the p-type channel-implant mask to the n-type transistor, resulting in a structure that has n-type channel, source, and drain regions and a negative threshold voltage of approximately −500 mV. Similarly, in some exemplary embodiments, a suitable depletion-mode PMOSFET may be implemented by applying the n-type channel-implant mask to the p-type transistor, resulting in a structure that has p-type channel, source, and drain regions and a positive threshold voltage of approximately +500 mV.
A reference relating to the fabrication of enhancement-mode and depletion-mode transistors in SOS is “CMOS/SOS/LSI Switching Regulator Control Device,” Orndorff, R. and Butcher, D., Solid-State Circuits Conference, Digest of Technical Papers, 1978 IEEE International, Volume XXI, pp. 234-235, February 1978. The “Orndorff” reference is hereby incorporated in its entirety herein for its techniques on the fabrication of enhancement-mode and depletion-mode SOS transistors.
Embodiments of Methods and Apparatuses for Improving Gate Oxide Reliability in Accordance with the Present CIP
The present CIP describes methods and devices for improving gate oxide reliability of SOI MOSFETs using ACC techniques to control accumulated charge and the adverse effects thereof. Persons skilled in the arts of electronic devices will appreciate that the teachings herein apply equally to NMOSFETs and PMOSFETs. For simplicity, the embodiments and examples presented herein for illustrative purposes include only NMOSFETs, unless otherwise noted. By making well known changes to dopants, charge carriers, polarity of bias voltages, etc., persons skilled in the arts of electronic devices will easily understand how these embodiments and examples may be adapted for use with PMOSFETs.
Impact of Accumulated Charge on Gate Oxide Reliability
Referring to
Reduction or otherwise control of the accumulated charge therefore enables use of larger bias voltages for a given thickness of the gate oxide 110. Alternatively, reduction or control of the accumulated charge enables use of reduced gate oxide 110 thickness for given bias voltages. A combination of larger bias voltages and reduced gate oxide 110 thickness is also enabled by control of the accumulated charge. Larger bias voltages allow larger input voltages in the transition off-state, thereby improving power handling capability. Reduced gate oxide thickness provides improved insertion loss, thereby allowing either improvements in power handling capability, or an option of using smaller SOI NMOSFETs to control a given power level.
Although many of the examples herein relate to RF switches, persons skilled in the arts of electronic circuits will understand that the present teachings may also be applied to RF mixers, power amplifiers, level shifting circuits, negative voltage generators, oscillators, DC-DC converters and other circuits that employ SOI MOSFETs. In particular, persons skilled in the arts of RF circuits will readily understand how the present teachings may be implemented for RF power amplifiers such as described in the following U.S. patent applications: “STACKED TRANSISTOR METHOD AND APPARATUS,” application Ser. No. 10/875,405, filed Jun. 23, 2004, and “INTEGRATED RF FRONT END,” application Ser. No. 11/158,597 (CIP of application Ser. No. 10/875,405, filed Jun. 23, 2004), filed Jun. 22, 2005, pending (Docket. No. PER-006-CIP). These cited applications are commonly owned by the assignee of the present application, and are hereby fully incorporated by reference herein, as though set forth in full for teachings on using SOI MOSFETs for RF power amplifiers.
Accumulated Charge Control Using Bias Voltage Pulses
In one embodiment, applying bias voltage pulses comprises an ACC technique that may be used to control the accumulated charge 120. Referring again to
Accumulated Charge Control Using RF Signal Voltage
In one embodiment, an applied RF signal voltage comprises an ACC technique. According to this embodiment, an NMOSFET is operated with a large series resistor electrically connected to the gate in series with the gate bias source (as described below in reference to
RF Switch Circuits Adapted for Improved Oxide Reliability Using Bias Voltage Pulses
Referring again to
Referring again to
The first and second control signals, C1 and C1x, respectively, are generated so that the SOI NMOSFET 506 operates in an on-state when the SOI NMOSFET 508 operates in an off-state, and vice versa. These control signals provide the gate bias voltages Vg to the gate terminals of the NMOSFETs 506 and 508. When either of the NMOSFETs 506 or 508 is biased to select the transistor off-state, the respective Vg must comprise a sufficiently large negative voltage so that the respective NMOSFET does not enter, or approach, an on-state due to the time varying applied voltages of the RF input signal RFin. The maximum power of the RF input signal RFin is thereby limited by the maximum magnitude of the gate bias voltage Vg (or, more generally, the gate-to-source operating voltage, Vgs) that the SOI NMOSFETs 506 and 508 can reliably sustain. For RF switching circuits such as those exemplified herein, Vgs(max)=Vg+Vds(max)/2, where Vds=Vd−Vs, and Vds(max) comprises the maximum Vds due to the high-power input signal voltage levels associated with the RF input signal RFin.
The power that can be accommodated by the SOI NMOSFETs 506, 508 is limited by insertion loss. Insertion loss can be improved by reducing gate oxide thicknesses. Therefore, as described above, the power handling performance of the SOI NMOSFETs 506, 508 can be improved using the ACC techniques of the present disclosure which allow implementation of SOI MOSFETs having thinner gate oxides. Persons skilled in the electronic device and circuit design arts shall appreciate that an appropriate combination of higher bias voltages and reduced gate oxide thicknesses can be used to improve circuit performance.
Exemplary bias voltages for the SOI NMOSFETs 506 and 508 may include the following: with Vth approximately zero volts, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of −2.5 V. For these bias voltages, the SOI NMOSFETs may eventually operate in an accumulated charge regime when placed into their off-states. As described above in reference to
Accumulated charge control may be implemented by pulsing bias voltages applied to the gates of the SOI NMOSFETs 506, 508. In reference to
The gate bias voltage pulses are provided at any suitable magnitude, interval, and duration in order to reduce accumulated charge to the desired level. It is to be understood that each of these variables is dependent on the others and can be altered according to the application and preference of IC designer. For example, an individual IC may be capable of generating different pulses at different time periods and depending on any of a number of predetermined factors. By different, it is meant that the pulses may be of different magnitudes, intervals, durations, or a combination thereof. While a number of external factors can influence the nature of applied pulses according to the disclosure, recognize that one factor relevant thereto is the operating temperature of the SOI NMOSFET. At higher operating temperatures, accumulated charge builds up more rapidly. Thus, more frequent pulsing may be desirable under such conditions.
In one embodiment, a gate bias voltage pulse is applied to an off-state FET to force the FET toward an on-state. Although this gate bias voltage pulse need not exceed the threshold voltage (Vth) of the FET, exceeding Vth is an exemplary embodiment of the present disclosure. The magnitude of the gate bias voltage pulse may be fixed or variable. For simplicity, a pulse of a fixed magnitude, to exceed Vth by a selected value (e.g., the pulse voltage may have a maximum value of Vth+0.5 V) may be used in an exemplary embodiment.
The magnitude of the pulsed gate voltage impacts the pulse duration needed to achieve the desired effects and vice versa. In one embodiment, the FET is pulsed for a duration of approximately 5 μs or less. This meets the GSM standard switching time requirements and further provides for preferred switching times of from 1 μs to 5 μs.
At the end of a gate bias voltage pulse, the FET is maintained in an off-state by the control signal. The time period for which the FET is maintained in the off-state varies depending on the application and on the pulsed gate bias voltage applied during the last pulse. In order to control the electric field stress in the gate oxide, it is desirable to apply the gate bias pulses at a sufficient frequency to prevent a build-up of accumulated charge proximate to the gate oxide. For example, if it is known that the accumulated charge build-up time is on the order of 100 mS or more, a repetition interval for the gate bias voltage pulses may be selected to be on the order of 10 mS or less.
RF Switch Circuits Adapted for Improved Oxide Reliability Using RF Signal Voltage
In another embodiment, an RF signal voltage may be used as an ACC technique. When the SOI NMOSFETs 506 and 508 are in the off-state with the exemplary applied gate bias of −2.5 V, the gate voltage will vary around the −2.5 V bias level in response to an applied AC drain signal because the resistors 510 and 514 (these resistors may have exemplary values of 10 kohm) allow the gate voltages to track the AC drain signal at one-half amplitude as described above. If a 2 V amplitude high-frequency signal (i.e., a 4 V peak-to-peak RF signal) is applied to the drain of one of the SOI NMOSFETs 506 or 508 in the off-state as Vd, the gate voltage will be moved from the quiescent level of −2.5 V to −1.5 V at a maximum and to −3.5 V at a minimum. When the gate voltage moves to −1.5 V, the accumulated charge moves toward the level that would be present in equilibrium at −1.5 V, through diffusion to the source and drain, where the accumulated holes recombine with the large concentrations of electrons. Alternatively, the accumulated charge may recombine by other processes with other electron sources. When the gate voltage moves more negative, the accumulated charge will increase, but the time spent at the more negative voltage is too short for the accumulated charge to increase significantly before the voltage moves less negative again. I.e., the recombination process at the less negative voltage will occur more rapidly than at more negative voltages, while the generation process is largely independent of voltage. Consequently, under the dynamic conditions of the present example, the net effect of the AC voltage swing in the gate voltage is to reduce the effective level of accumulated charge relative to what it would be absent the AC signal. After many cycles of RF swing, a steady-state accumulated charge level will be present that is significantly less than would be present at the DC gate bias voltage of −2.5 V. According to the present example the effective accumulated charge may be approximately at the level that would be present for an effective gate bias of −1.5 V.
Circuits Adapted for Improved Oxide Reliability Using ACC MOSFETs
In one embodiment, circuits having ACC SOI MOSFETs may be adapted for improved oxide reliability in accordance with the present CIP. The use of ACC SOI MOSFETs to control accumulated charge in RF switch circuits is described above in reference to
Methods for Using ACC Techniques to Improve Gate Oxide Reliability
At a STEP 1004, the reliability of the gate oxides of the SOI NMOSFETs is determined with and without ACC. In one embodiment, the gate oxide reliability is determined by performing time dependent dielectric breakdown (TDDB) measurements on test SOI NMOSFETs corresponding to the SOI NMOSFETs included in the first circuit. The TDDB measurements provide information relating to the lifetime of the SOI NMOSFETs due to gate oxide breakdown. The results of the TDDB measurements indicate a maximum electric field, “Etb”, in the oxide that can be sustained and yet still achieve a desired lifetime (i.e., an average “time-to-breakdown” or “tb”) for the SOI NMOSFETs. With a given value for Etb, minimum gate oxide thicknesses and maximum bias voltages required to achieve the desired lifetime can be determined, as described below. The results of the TDDB measurements may also indicate a maximum gate-to-source bias voltage Vgs, that can be sustained and yet still achieve a desired lifetime for the SOI NMOSFETs. TDDB measurements are well known to persons skilled in the electronic device arts. Examples of TDDB measurement techniques are described in the above-incorporated paper by C. Hu and Q. Lu, the reference by Suehle and Chaparala, and reference by R. Bolam.
Reliability of the gate oxides is further determined with and without ACC by performing TDDB measurements of the SOI NMOSFETs operating with selected bias voltages. The measurement results provide information relating to the improved TDDB present in the gate oxides for selected bias conditions and gate oxide thicknesses. In one example of a TDDB measurement of an SOI NMOSFET, using a first gate bias Vg1=−10 V, Vs=0 V, Vd=0 V, and a gate oxide thickness Tox1 of 8.2 nm, an average time to failure of 500 seconds was determined without ACC. With ACC, the same average time to failure of 500 seconds required Vg2 of −14V. Thus, according to this example, using ACC enables using a second Vg2 that is increased by a factor of approximately 40% over Vg1, while maintaining an equivalent TDDB lifetime. Alternatively, using ACC enables using a second Tox2 that is equal to Tox1 multiplied by a factor of approximately 1/1.4, without an adverse effect on TDDB lifetime.
Referring again to the method 1000 of
At a STEP 1008, the second circuit is operated using the present ACC techniques, as described above. In one embodiment, the second circuit may comprise an RF switch operated at higher RF power levels than the first circuit.
Referring to the method 1001 of
At a STEP 1016, a circuit including the SOI NMOSFET is implemented responsive to the improvement factor F1. In one embodiment of the disclosed method, the circuit is implemented by selecting a maximum gate-to-source operating voltage Vgs for the off-state and Tox in accordance with the following equation:
Vgs(max)/Tox=F1·Etb; (1)
wherein Etb comprises the maximum oxide electric field for which a given TDDB lifetime of the SOI NMOSFET can be obtained (e.g., ˜5 MV/cm for a lifetime of 10 years is a “rule of thumb” value). More generally, the SOI NMOSFET bias voltages, maximum signal voltages, and gate oxide thicknesses can be selectively improved using the ACC techniques of the present teachings. These improvements over the prior art SOI NMOSFET devices are provided according to the improvement factor F1, as shall be readily appreciated by persons skilled in the electronic device design arts. Finally, at a STEP 1018, the circuit is operated using ACC techniques as described above.
At a STEP 1024, a limiting gate bias voltage Vg2 is determined using TDDB measurements for the SOI NMOSFET having an oxide thickness Tox, operated in the off-state with ACC. For example, for Vd=Vs=0, the limiting gate bias voltage Vg2 represents the most negative gate bias that can be sustained to obtain a desired operating lifetime with ACC. An improvement factor F2 is defined according to the following expression: F2=Vg1/Vg2.
At a STEP 1026, a circuit including the SOI NMOSFET is implemented responsive to the improvement factor, F2. In one embodiment of the inventive method, the circuit is implemented by selecting a maximum gate-to-source operating voltage Vgs for the off-state and Tox according to the following equation:
Vgs(max)/Tox=F2·Etb (2)
More generally, the SOI NMOSFET bias voltages, maximum signal voltages, and gate oxide thicknesses can be selectively improved over the prior art according to the improvement factor F2, as shall be readily appreciated by persons skilled in the electronic device arts. Referring again to
A number of embodiments of the present inventive concept have been described. Nevertheless, it will be understood that various modifications may be made without departing from the scope of the inventive teachings. For example, it should be understood that the functions described as being part of one module may in general be performed equivalently in another module.
Accordingly, it is to be understood that the concepts described herein are not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.
Imthurn, George P., Burgener, Mark L., Stuber, Michael A., Dribinsky, Alexander, Kim, Tae Youn, Kelly, Dylan J., Brindle, Christopher N., Welstand, Robert B., Kemerling, Clint L.
Patent | Priority | Assignee | Title |
10236872, | Mar 28 2018 | pSemi Corporation | AC coupling modules for bias ladders |
10505530, | Mar 28 2018 | pSemi Corporation | Positive logic switch with selectable DC blocking circuit |
10797691, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
10797694, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
10804892, | Jul 11 2005 | pSemi Corporation | Circuit and method for controlling charge injection in radio frequency switches |
10812068, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
10818796, | Jul 11 2005 | pSemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
10862473, | Mar 28 2018 | pSemi Corporation | Positive logic switch with selectable DC blocking circuit |
10886911, | Mar 28 2018 | pSemi Corporation | Stacked FET switch bias ladders |
10901023, | Aug 09 2018 | NXP B.V.; NXP B V | Apparatuses and methods involving adjustable circuit-stress test conditions for stressing regional circuits |
11011633, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
11018662, | Mar 28 2018 | pSemi Corporation | AC coupling modules for bias ladders |
11201245, | Jul 11 2005 | pSemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
11362652, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
11418183, | Mar 28 2018 | pSemi Corporation | AC coupling modules for bias ladders |
11476849, | Jan 06 2020 | pSemi Corporation | High power positive logic switch |
11695407, | Jul 11 2005 | pSemi Corporation | Circuit and method for controlling charge injection in radio frequency switches |
11870431, | Mar 28 2018 | pSemi Corporation | AC coupling modules for bias ladders |
11901459, | Jul 11 2005 | pSemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
9780775, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
9780778, | Oct 08 2002 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
9786781, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
9831857, | Mar 11 2015 | pSemi Corporation | Power splitter with programmable output phase shift |
9887695, | Jul 11 2005 | pSemi Corporation | Circuit and method for controlling charge injection in radio frequency switches |
RE48944, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETS using an accumulated charge sink |
RE48965, | Jul 11 2005 | pSemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
Patent | Priority | Assignee | Title |
3646361, | |||
3699359, | |||
3975671, | Feb 24 1975 | Intel Corporation | Capacitive voltage converter employing CMOS switches |
3988727, | Jun 24 1974 | EMERSON ELECTRIC CO A CORP OF MISSOURI | Timed switching circuit |
4053916, | Sep 04 1975 | Westinghouse Electric Corporation | Silicon on sapphire MOS transistor |
4139826, | Dec 27 1977 | RCA Corporation | Crystal overtone oscillator using cascade connected transistors |
4145719, | Sep 28 1977 | GTE International Incorporated | Multi-channel video switch using dual-gate MOS-FETS |
4244000, | Nov 28 1978 | Nippon Telegraph & Telephone Corporation | PNPN Semiconductor switches |
4256977, | Dec 26 1978 | Honeywell Inc. | Alternating polarity power supply control apparatus |
4316101, | Nov 30 1978 | Telefunken Electronic GmbH | Circuit for switching and transmitting alternating voltages |
4317055, | May 24 1978 | Hitachi, Ltd. | High-voltage circuit for insulated gate field-effect transistor |
4367421, | Apr 21 1980 | RELIANCE ELECTRIC COMPANY, A CORP OF DE | Biasing methods and circuits for series connected transistor switches |
4390798, | Nov 22 1979 | Fujitsu Limited | Bias-voltage generator |
4638184, | Sep 22 1983 | Oki Electric Industry Co., Ltd. | CMOS bias voltage generating circuit |
4736169, | Sep 29 1986 | Hughes Electronics Corporation | Voltage controlled oscillator with frequency sensitivity control |
4739191, | Apr 27 1981 | SIGNETICS CORPORATION, 811 EAST ARQUES AVENUE, SUNNYVALE, CA 94086 A CORP OF | Depletion-mode FET for the regulation of the on-chip generated substrate bias voltage |
4746960, | Jul 27 1987 | General Motors Corporation | Vertical depletion-mode j-MOSFET |
4810911, | Nov 14 1986 | NEC Electronics Corporation | FET switch circuit having small insertion loss and exhibiting stable operation |
4825145, | Jan 14 1987 | Hitachi, Ltd. | Constant current circuit |
4849651, | Feb 24 1988 | Raytheon Company | Two-state, bilateral, single-pole, double-throw, half-bridge power-switching apparatus and power supply means for such electronic power switching apparatus |
4890077, | Mar 28 1989 | TELEDYNE WIRELESS, INC | FET monolithic microwave integrated circuit variable attenuator |
4891609, | Dec 22 1987 | U S PHILIPS CORPORATION, A CORP OF DE | Ring oscillator |
4929855, | Dec 09 1988 | GRUMMAN AEROSPACE CORPORATION, 1111 STEWART AVENUE, BETHPAGE, LONG ISLAND, NY 11714-3580 | High frequency switching device |
4939485, | Dec 09 1988 | Litton Systems, Inc | Microwave field effect switch |
4984040, | Jun 15 1989 | Xerox Corporation | High voltage thin film transistor with second gate |
4985647, | Jun 21 1988 | NEC Electronics Corporation | CMOS transfer switch free from malfunction on noise signal |
4999585, | Nov 06 1989 | Burr-Brown Corporation | Circuit technique for cancelling non-linear capacitor-induced harmonic distortion |
5012123, | Mar 29 1989 | Hittite Microwave, Inc.; HITTITE MICROWAVE, INC , 21 CABOT ROAD, WOBURN, MASSACHUSETTS 01801, A MASSACHUSETTS CORP | High-power rf switching system |
5023494, | Oct 20 1989 | RAYTHEON COMPANY, A CORP OF DE | High isolation passive switch |
5061907, | Jan 17 1991 | National Semiconductor Corporation | High frequency CMOS VCO with gain constant and duty cycle compensation |
5061911, | Apr 03 1990 | Apple Inc | Single fault/tolerant MMIC switches |
5081706, | Jul 30 1987 | Texas Instruments Incorporated | Broadband merged switch |
5107152, | Sep 08 1989 | AMP Incorporated; AMP INVESTMENTS, INC ; WHITAKER CORPORATION, THE | Control component for a three-electrode device |
5124762, | Dec 31 1990 | HONEYWELL INC , A CORP OF DE | GaAs heterostructure metal-insulator-semiconductor integrated circuit technology |
5125007, | Nov 25 1988 | Mitsubishi Denki Kabushiki Kaisha | Thin-film SOI-MOSFET with a body region |
5146178, | Nov 16 1990 | NTT Mobile Communications Network Inc | Impedance-matched, class F high-frequency amplifier |
5182529, | Mar 06 1992 | Micron Technology, Inc. | Zero crossing-current ring oscillator for substrate charge pump |
5208557, | Feb 18 1992 | Texas Instruments Incorporated | Multiple frequency ring oscillator |
5272457, | Mar 10 1992 | Harris Corporation | High isolation integrated switch circuit |
5274343, | Aug 06 1991 | Raytheon Company | Plural switch circuits having RF propagation networks and RF terminations |
5285367, | Feb 07 1992 | Power Integrations, Inc.; Power Integrations, Inc | Linear load circuit to control switching power supplies under minimum load conditions |
5306954, | Jun 04 1992 | Exar Corporation | Charge pump with symmetrical +V and -V outputs |
5313083, | Dec 16 1988 | Raytheon Company | R.F. switching circuits |
5317181, | Sep 10 1992 | UTMC MICROELECTRONIC SYSTEMS INC | Alternative body contact for fully-depleted silicon-on-insulator transistors |
5319604, | May 08 1990 | Texas Instruments Incorporated | Circuitry and method for selectively switching negative voltages in CMOS integrated circuits |
5345422, | Jul 31 1990 | Texas Instruments Incorporated | Power up detection circuit |
5350957, | May 17 1991 | Texas Instrument Incorporated | Electronic switch controlled by plural inputs |
5375257, | Dec 06 1993 | Raytheon Company | Microwave switch |
5416043, | Jul 12 1993 | Peregrine Semiconductor Corporation | Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer |
5422590, | Jan 05 1993 | Texas Instruments Incorporated | High voltage negative charge pump with low voltage CMOS transistors |
5442327, | Jun 21 1994 | GENERAL DYNAMICS C4 SYSTEMS, INC | MMIC tunable biphase modulator |
5446418, | Nov 06 1992 | Mitsubishi Denki Kabushiki Kaisha | Ring oscillator and constant voltage generation circuit |
5448207, | Sep 30 1993 | Sony Corporation | Attenuator circuit apparatus |
5477184, | Apr 15 1992 | Sanyo Electric Co., Ltd. | Fet switching circuit for switching between a high power transmitting signal and a lower power receiving signal |
5488243, | Dec 04 1992 | NIPPONDENSO CO , LTD | SOI MOSFET with floating gate |
5492857, | Mar 25 1994 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
5493249, | Dec 06 1993 | Round Rock Research, LLC | System powered with inter-coupled charge pumps |
5548239, | May 21 1993 | Sony Corporation | Radio receiver-transmitter apparatus and signal changeover switch |
5553295, | Mar 23 1994 | Intel Corporation | Method and apparatus for regulating the output voltage of negative charge pumps |
5554892, | Apr 28 1993 | NEC Corproation | Signal processing circuit for switch capable of reducing insertion loss |
5572040, | Jul 12 1993 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
5576647, | Jun 22 1995 | CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD | Charge pump for phase lock loop |
5596205, | Mar 25 1994 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
5597739, | Jan 19 1994 | Sony Corporation | MOS transistor and method for making the same |
5600169, | Jul 12 1993 | Peregrine Semiconductor Corporation | Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer |
5629655, | Oct 27 1992 | Unwired Planet, LLC | Integrated distributed RC low-pass filters |
5663570, | Jul 12 1993 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
5670907, | Mar 14 1995 | Lattice Semiconductor Corporation | VBB reference for pumped substrates |
5681761, | Dec 28 1995 | AMPLEON NETHERLANDS B V | Microwave power SOI-MOSFET with high conductivity metal gate |
5694308, | Jul 03 1995 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method and apparatus for regulated low voltage charge pump |
5699018, | Dec 08 1995 | Mitsubishi Denki Kabushiki Kaisha | Negative voltage generator |
5717356, | Jan 23 1995 | Sony Corporation | Low insertion loss switch |
5729039, | Nov 10 1994 | International Business Machines Corporation | SOI transistor having a self-aligned body contact |
5731607, | Apr 24 1995 | Sony Corporation | Semiconductor integrated circuit device |
5734291, | Mar 11 1996 | Microchip Technology Incorporated | Power saving technique for battery powered devices |
5748053, | Sep 28 1995 | Kabushiki Kaisha Toshiba | Switching circuit |
5760652, | Jun 06 1996 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuit device |
5774792, | Aug 29 1994 | Renesas Electronics Corporation | Low distortion switch |
5777530, | Jan 31 1996 | Matsushita Electric Industrial Co., Ltd. | Switch attenuator |
5784687, | Aug 30 1994 | Matsushita Electric Industrial Co., Ltd. | Transmitting-receiving circuit for radiocommunication apparatus, semiconductor integrated circuit device including the circuit, and radiocommunication apparatus including the same |
5793246, | Nov 08 1995 | ALTERA CORPORATION, A DELEWARE CORPORATION | High voltage pump scheme incorporating an overlapping clock |
5801577, | Dec 26 1995 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | High voltage generator |
5807772, | Jun 09 1992 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming semiconductor device with bottom gate connected to source or drain |
5808505, | May 25 1993 | NEC Electronics Corporation | Substrate biasing circuit having controllable ring oscillator |
5812939, | Aug 10 1995 | Sony Semiconductor Solutions Corporation | Switch semiconductor integrated circuit and communication terminal device |
5818099, | Oct 03 1996 | International Business Machines Corporation | MOS high frequency switch circuit using a variable well bias |
5818278, | Sep 06 1996 | Mitsubishi Denki Kabushiki Kaisha | Level shift circuit |
5818283, | Jul 13 1995 | JAPAN RADIO CO , LTD | High power FET switch |
5818289, | Jul 18 1996 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit |
5818766, | Mar 05 1997 | Integrated Silicon Solution Inc.; INTEGRATED SILICON SOLUTION, INC | Drain voltage pump circuit for nonvolatile memory device |
5821800, | Feb 11 1997 | Cypress Semiconductor Corporation | High-voltage CMOS level shifter |
5825227, | Jan 23 1995 | Sony Corporation | Switching circuit at high frequency with low insertion loss |
5861336, | Jul 12 1993 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
5863823, | Jul 12 1993 | PEREGRINE SEMICONDUCTOR CORP | Self-aligned edge control in silicon on insulator |
5864328, | Sep 01 1995 | Sharp Kabushiki Kaisha | Driving method for a liquid crystal display apparatus |
5874836, | Sep 06 1996 | International Business Machines Corporation | High reliability I/O stacked fets |
5874849, | Jul 19 1996 | Texas Instruments Incorporated | Low voltage, high current pump for flash memory |
5878331, | Jan 22 1996 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuit |
5880620, | Apr 22 1997 | XILINX, Inc. | Pass gate circuit with body bias control |
5883396, | Jul 12 1993 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
5883541, | Mar 05 1997 | Renesas Electronics Corporation | High frequency switching circuit |
5892400, | Dec 12 1996 | Skyworks Solutions, Inc | Amplifier using a single polarity power supply and including depletion mode FET and negative voltage generator |
5895957, | Jul 12 1993 | Peregrine Semiconductor Corporation | Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer |
5903178, | Dec 16 1994 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | Semiconductor integrated circuit |
5912560, | Feb 25 1997 | STMicroelectronics, Inc | Charge pump circuit for voltage boosting in integrated semiconductor circuits |
5917362, | Jan 29 1996 | Sony Semiconductor Solutions Corporation | Switching circuit |
5920093, | Apr 07 1997 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | SOI FET having gate sub-regions conforming to t-shape |
5920233, | Nov 18 1996 | Peregrine Semiconductor Corporation | Phase locked loop including a sampling circuit for reducing spurious side bands |
5926466, | May 16 1995 | Matsushita Electric Industrial Co., Ltd. | Time division multiple access FDD wireless unit and time division multiple access FDD/TDD dual mode wireless unit |
5930638, | Jul 12 1993 | PEREGRINE SEMICONDUCTOR CORP | Method of making a low parasitic resistor on ultrathin silicon on insulator |
5945867, | Feb 24 1997 | Sanyo Electric Co., Ltd. | Switch circuit device |
5953557, | Nov 28 1997 | FUJI XEROX CO , LTD | Image forming apparatus with controlled toner charging voltage |
5959335, | Sep 23 1998 | GLOBALFOUNDRIES Inc | Device design for enhanced avalanche SOI CMOS |
5969560, | Jan 23 1995 | Sony Corporation | Switching circuit at high frequency with low insertion loss |
5973363, | Jul 12 1993 | PEREGRINE SEMICONDUCTOR CORP | CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator |
5973364, | Sep 19 1997 | TOSHIBA MEMORY CORPORATION | MIS semiconductor device having body-contact region |
5973382, | Jul 12 1993 | Peregrine Semiconductor Corporation | Capacitor on ultrathin semiconductor on insulator |
5973636, | Mar 12 1996 | Fujitsu Limited; Fujitsu Ten Limited | Radar apparatus with a simplified construction |
5986518, | Jun 30 1998 | TORSAL TECHNOLOGY GROUP LTD LLC | Distributed MMIC active quadrature hybrid and method for providing in-phase and quadrature-phase signals |
5990580, | Mar 05 1998 | The Whitaker Corporation | Single pole double throw switch |
6020781, | Dec 27 1996 | SOCIONEXT INC | Step-up circuit using two frequencies |
6057555, | Jul 12 1993 | Peregrine Semiconductor Corporation | High-frequency wireless communication system on a single ultrathin silicon on sapphire chip |
6057723, | Jan 13 1997 | Kabushiki Kaisha Toshiba | Phase shifter |
6064275, | Apr 22 1996 | Renesas Electronics Corporation | Internal voltage generation circuit having ring oscillator whose frequency changes inversely with power supply voltage |
6064872, | Mar 12 1991 | WJ COMMUNICATIONS, INC | Totem pole mixer having grounded serially connected stacked FET pair |
6066993, | Jan 16 1998 | Mitsubishi Denki Kabushiki Kaisha | Duplexer circuit apparatus provided with amplifier and impedance matching inductor |
6081165, | Jul 25 1997 | Texas Instruments Incorporated | Ring oscillator |
6081443, | Mar 04 1996 | Renesas Electronics Corporation | Semiconductor memory device |
6081694, | Oct 21 1997 | Matsushita Electric Industrial Co., Ltd.; MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | Mobile telephone transmitter with internal auxiliary matching circuit |
6094088, | Feb 26 1997 | NEC Corporation | Radio frequency switch circuit having resistors connected to back gates of transistors |
6114923, | Sep 01 1997 | NEC COMPOUND SEMICONDUCTOR DEVICES, LTD | Switching circuit and semiconductor device |
6118343, | May 10 1999 | Cobham Defense Electronic Systems Corporation | Power Amplifier incorporating single drain switch and single negative voltage generator |
6122185, | Jul 22 1997 | ABLIC INC | Electronic apparatus |
6130570, | Sep 18 1997 | SAMSUNG ELECTRONICS CO , LTD | MESFET circuit utilizing only positive power supplies |
6133752, | Sep 25 1997 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit having tri-state logic gate circuit |
6160292, | Apr 23 1997 | GLOBALFOUNDRIES Inc | Circuit and methods to improve the operation of SOI devices |
6169444, | Jul 15 1999 | Maxim Integrated Products, Inc. | Pulse frequency operation of regulated charge pumps |
6173235, | Apr 11 1996 | Mitsubishi Denki Kabushiki Kaisha | Method of estimating lifetime of floating SOI-MOSFET |
6177826, | Dec 01 1997 | Mitsubishi Denki Kabushiki Kaisha | Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate |
6188247, | Jan 29 1999 | International Business Machines Corporation | Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements |
6188590, | Dec 18 1996 | Macronix International Co., Ltd. | Regulator system for charge pump circuits |
6195307, | Feb 26 1997 | TOSHIBA MEMORY CORPORATION | Booster circuit and semiconductor memory device having the same |
6215360, | Feb 23 1998 | Google Technology Holdings LLC | Semiconductor chip for RF transceiver and power output circuit therefor |
6218890, | Jul 14 1998 | SANYO ELECTRIC CO , LTD | Switching circuit device and semiconductor device |
6249027, | Jun 08 1998 | Oracle America, Inc | Partially depleted SOI device having a dedicated single body bias means |
6249446, | Aug 23 2000 | INTERSIL AMERICAS LLC | Cascadable, high efficiency charge pump circuit and related methods |
6288458, | Sep 30 1999 | Honeywell International Inc | Power stealing solid state switch |
6297687, | Aug 11 1998 | OKI SEMICONDUCTOR CO , LTD | Drive control circuit of charged pump circuit |
6300796, | Feb 19 1999 | IXYS Intl Limited | High voltage PMOS level shifter |
6308047, | Feb 03 1999 | Mitsubishi Denki Kabushiki Kaisha | Radio-frequency integrated circuit for a radio-frequency wireless transmitter-receiver with reduced influence by radio-frequency power leakage |
6310508, | Aug 24 2000 | Agilent Technologies, Inc. | High frequency switch |
6316983, | Jul 26 2000 | YRP Advanced Mobile Communication Systems Research Laboratories Co., Ltd. | Predistortion circuit |
6337594, | Jun 17 1998 | Hynix Semiconductor, Inc. | Charge pump circuit |
6355957, | Jan 05 2000 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having body potential fixing portion and closed-loop gate structure |
6356536, | Sep 30 1998 | Ericsson Inc.; Ericsson, Inc | Protective and decoupling shunt switch at LNA input for TDMA/TDD transceivers |
6365488, | Mar 05 1998 | Industrial Technology Research Institute | Method of manufacturing SOI wafer with buried layer |
6380793, | Oct 28 1999 | Pixtech S.A. | Very high voltage switch |
6380796, | Nov 05 1999 | Hitachi, Ltd. | Semiconductor power converting apparatus |
6392440, | Jun 04 1998 | Siemens Aktiengesellschaft | 5V compliant transmission gate and the drive logic using 3.3V technology |
6400211, | Sep 19 2000 | Rohm Co., Ltd. | DC/DC converter |
6407614, | Dec 07 2000 | New Japan Radio Co., Ltd. | Semiconductor integrated switching circuit |
6411156, | Jun 20 1997 | Intel Corporation | Employing transistor body bias in controlling chip parameters |
6414353, | Aug 07 1998 | TESSERA ADVANCED TECHNOLOGIES, INC | TFT with partially depleted body |
6414863, | Aug 30 2001 | Texas Instruments Incorporated | Frequency control circuit for unregulated inductorless DC/DC converters |
6429632, | Feb 11 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Efficient CMOS DC-DC converters based on switched capacitor power supplies with inductive current limiters |
6429723, | Nov 18 1999 | Texas Instruments Incorporated | Integrated circuit with charge pump and method |
6452232, | Dec 03 1998 | Sharp Kabushiki Kaisha | Semiconductor device having SOI structure and manufacturing method thereof |
6461902, | Jul 18 2000 | Institute of Microelectronics | RF LDMOS on partial SOI substrate |
6486511, | Aug 30 2001 | Northrop Grumman Systems Corporation | Solid state RF switch with high cutoff frequency |
6486729, | May 24 2000 | TOSHIBA MEMORY CORPORATION | Potential detector and semiconductor integrated circuit |
6498058, | Sep 30 1998 | GLOBALFOUNDRIES Inc | SOI pass-gate disturb solution |
6504212, | Feb 03 2000 | International Business Machines Corporation | Method and apparatus for enhanced SOI passgate operations |
6504213, | Jul 27 1999 | Seiko Epson Corporation | SOI-structure field-effect transistor and method of manufacturing the same |
6512269, | Sep 07 2000 | GLOBALFOUNDRIES U S INC | High-voltage high-speed SOI MOSFET |
6537861, | Aug 29 1998 | International Business Machines Corporation | SOI transistor with body contact and method of forming same |
6559689, | Oct 02 2000 | Allegro MicroSystems, LLC | Circuit providing a control voltage to a switch and including a capacitor |
6563366, | Oct 30 1997 | Sony Corporation | High-frequency Circuit |
6573533, | Jul 16 1999 | 138 EAST LCD ADVANCEMENTS LIMITED | Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment |
6617933, | Sep 29 2000 | Mitsubishi Denki Kabushiki Kaisha | VCO circuit with wide output frequency range and PLL circuit with the VCO circuit |
6631505, | Nov 29 2000 | Renesas Electronics Corporation | Simulation circuit for MOS transistor, simulation testing method, netlist of simulation circuit and storage medium storing same |
6632724, | May 12 1997 | Silicon Genesis Corporation | Controlled cleaving process |
6642578, | Jul 22 2002 | Skyworks Solutions, Inc | Linearity radio frequency switch with low control voltage |
6653697, | Mar 27 2001 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | High frequency switch circuit and communications terminal using the same |
6670655, | Apr 18 2001 | GLOBALFOUNDRIES U S INC | SOI CMOS device with body to gate connection |
6677641, | Oct 17 2001 | Semiconductor Components Industries, LLC | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability |
6684065, | Dec 20 1999 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Variable gain amplifier for low voltage applications |
6693326, | Apr 04 2000 | Sharp Kabushiki Kaisha | Semiconductor device of SOI structure |
6693498, | Feb 22 2000 | Murata Manufacturing Co. Ltd | SPDT switch and communication unit using the same |
6698082, | Aug 28 2001 | Texas Instruments Incorporated | Micro-electromechanical switch fabricated by simultaneous formation of a resistor and bottom electrode |
6698498, | Apr 08 1999 | Nucor Corporation | Casting strip |
6704550, | Sep 14 1999 | Sony Semiconductor Solutions Corporation | Antenna switching circuit and communication system using the same |
6711397, | Nov 20 2000 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Structures and methods for direct conversion from radio frequency modulated signals to baseband signals |
6714065, | Oct 26 2001 | Renesas Electronics Corporation | Semiconductor device including power supply circuit conducting charge pumping operation |
6717458, | Dec 03 2001 | National Semiconductor Corporation | Method and apparatus for a DC-DC charge pump voltage converter-regulator circuit |
6730953, | Sep 13 2002 | Macom Technology Solutions Holdings, Inc | Apparatus, methods and articles of manufacture for a low control voltage switch |
6769110, | Dec 26 1997 | Renesas Electronics Corporation | Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit |
6774701, | Feb 19 2003 | OL SECURITY LIMITED LIABILITY COMPANY | Method and apparatus for electronic switching with low insertion loss and high isolation |
6781805, | Sep 22 1999 | Kabushiki Kaisha Toshiba | Stacked MOSFET protection circuit |
6788130, | Sep 25 2002 | Texas Instruments Incorporated | Efficient charge pump capable of high voltage operation |
6790747, | May 12 1997 | Silicon Genesis Corporation | Method and device for controlled cleaving process |
6801076, | Apr 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | High output high efficiency low voltage charge pump |
6803680, | Sep 13 2002 | Macom Technology Solutions Holdings, Inc | Apparatus, methods, and articles of manufacture for a switch having sharpened control voltage |
6804502, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
6816016, | Aug 10 2000 | Apple Inc | High-efficiency modulating RF amplifier |
6819938, | Jun 26 2001 | Qualcomm Incorporated | System and method for power control calibration and a wireless communication device |
6830963, | Oct 09 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Fully depleted silicon-on-insulator CMOS logic |
6836172, | May 30 2002 | Renesas Electronics Corporation | Semiconductor switch apparatus including isolated MOS transistors |
6871059, | Jun 16 1999 | Skyworks Solutions, Inc | Passive balun FET mixer |
6879502, | Jun 13 2002 | ABLIC INC | Power source inverter circuit |
6882210, | Apr 19 2001 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Semiconductor switching device |
6891234, | Jan 07 2004 | Acorn Semi, LLC | Transistor with workfunction-induced charge layer |
6898778, | Jul 13 2000 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and method of manufacturing the same |
6903596, | Mar 17 2003 | RENESAS ELECTRONICS AMERICA INC | Method and system for impedance matched switching |
6908832, | Aug 29 1997 | Silicon Genesis Corporation | In situ plasma wafer bonding method |
6917258, | Oct 24 2002 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | High frequency switch |
6947720, | Oct 17 2000 | Qorvo US, Inc | Low noise mixer circuit with improved gain |
6969668, | Apr 21 1999 | Silicon Genesis Corporation | Treatment method of film quality for the manufacture of substrates |
6975271, | Feb 26 2003 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | Antenna switch module, all-in-one communication module, communication apparatus and method for manufacturing antenna switch module |
6978122, | May 25 2001 | Kabushiki Kaisha Toshiba | High-frequency switching device incorporating an inverter circuit |
6978437, | Oct 10 2000 | CELERICS TECHNOLOGIES CORPORATION | Photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufacture with same |
7023260, | Jun 30 2003 | INNOVATIVE MEMORY SYSTEMS, INC | Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor |
7042245, | Oct 25 2002 | Renesas Electronics Corporation; NEC Electronics Corporation | Low power consumption MIS semiconductor device |
7045873, | Dec 08 2003 | GLOBALFOUNDRIES U S INC | Dynamic threshold voltage MOSFET on SOI |
7056808, | Aug 10 1999 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
7057472, | Aug 10 2001 | MURATA MANUFACTURING CO , LTD | Bypass filter, multi-band antenna switch circuit, and layered module composite part and communication device using them |
7058922, | Jul 13 2000 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit and method of manufacturing the same |
7082293, | Oct 21 1999 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Adaptive radio transceiver with CMOS offset PLL |
7092677, | Sep 05 2002 | Analog Devices, Inc | 2V SPDT switch for high power RF wireless applications |
7109532, | Dec 23 2003 | T-RAM ASSIGNMENT FOR THE BENEFIT OF CREDITORS , LLC | High Ion/Ioff SOI MOSFET using body voltage control |
7123898, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
7129545, | Feb 24 2005 | GLOBALFOUNDRIES Inc | Charge modulation network for multiple power domains for silicon-on-insulator technology |
7132873, | Jan 08 2003 | EMOSYN AMERICA, INC | Method and apparatus for avoiding gated diode breakdown in transistor circuits |
7138846, | Dec 20 2001 | Matsushita Electric Industrial Co., Ltd. | Field effect transistor switch circuit |
7161197, | May 31 2004 | COLLABO INNOVATIONS, INC | RF switching circuit for use in mobile communication systems |
7173471, | Jun 13 2003 | COLLABO INNOVATIONS, INC | High frequency switching circuit and semiconductor device |
7199635, | Jun 12 2003 | COLLABO INNOVATIONS, INC | High-frequency switching device and semiconductor |
7212788, | Aug 13 2002 | The Connectivity Patent Trust | Method and apparatus for signal power loss reduction in RF communication systems |
7266014, | Aug 01 2005 | Macronix International Co., Ltd | Method of operating non-volatile memory device |
7269392, | Aug 27 2003 | MURATA MANUFACTURING CO , LTD | Electric component for communication device and semiconductor device for switching transmission and reception |
7307490, | Oct 09 2003 | Mitsubishi Denki Kabushiki Kaisha; Sharp Kabushiki Kaisha | High frequency switch device |
7345342, | May 20 2003 | Semiconductor Components Industries, LLC | Power semiconductor devices and methods of manufacture |
7345521, | May 17 2002 | NEC Corporation | High frequency switch circuit |
7355455, | Oct 25 2002 | Renesas Electronics Corporation; NEC Electronics Corporation | Low power consumption MIS semiconductor device |
7391282, | Nov 17 2004 | COLLABO INNOVATIONS, INC | Radio-frequency switch circuit and semiconductor device |
7404157, | Dec 25 2002 | NEC Corporation | Evaluation device and circuit design method used for the same |
7432552, | Jun 11 2005 | Seoul National University Industry Foundation; Samsung Electronics Co., Ltd. | Body biasing structure of SOI |
7460852, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
7515882, | Dec 17 2002 | Macom Technology Solutions Holdings, Inc | Apparatus, methods and articles of manufacture for a multi-band switch |
7546089, | Dec 23 2004 | TriQuint Semiconductor, Inc | Switchable directional coupler for use with RF devices |
7561853, | Jan 16 2004 | Eudyna Devices Inc. | Radio frequency switch |
7616482, | Feb 24 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Multi-state memory cell with asymmetric charge trapping |
7659152, | Aug 29 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Localized biasing for silicon on insulator structures |
7710189, | May 27 2005 | Renesas Electronics Corporation | Semiconductor device for RF switching |
7733156, | Sep 04 2003 | Infineon Technologies AG | Transistor arrangement, integrated circuit and method for operating field effect transistors |
7733157, | Dec 15 2003 | Infineon Technologies AG | Noise-reducing transistor arrangement |
7741869, | Oct 25 2002 | Renesas Electronics Corporation; NEC Electronics Corporation | Low power consumption MIS semiconductor device |
7796969, | Oct 10 2001 | pSemi Corporation | Symmetrically and asymmetrically stacked transistor group RF switch |
7860499, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
7890891, | Jul 11 2005 | pSemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
7910993, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink |
7928759, | Oct 25 2002 | Renesas Electronics Corporation | Low power consumption MIS semiconductor device |
7982265, | May 20 2003 | Semiconductor Components Industries, LLC | Trenched shield gate power semiconductor devices and methods of manufacture |
8081928, | Feb 03 2005 | pSemi Corporation | Canceling harmonics in semiconductor RF switches |
8129787, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
8405147, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
8527949, | Nov 19 2001 | MUFG UNION BANK, N A | Graphical user interface for dynamically reconfiguring a programmable device |
8583111, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
8669804, | Feb 28 2008 | pSemi Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
8742502, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
8954902, | Jul 11 2005 | pSemi Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
9087899, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction |
9130564, | Jul 11 2005 | pSemi Corporation | Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink |
9225378, | Oct 10 2001 | pSemi Corporation | Switch circuit and method of switching radio frequency signals |
9397656, | Jul 11 2005 | pSemi Corporation | Circuit and method for controlling charge injection in radio frequency switches |
20010015461, | |||
20010031518, | |||
20010040479, | |||
20010045602, | |||
20020029971, | |||
20020115244, | |||
20020126767, | |||
20020195623, | |||
20030002452, | |||
20030141543, | |||
20030181167, | |||
20030201494, | |||
20030205760, | |||
20030227056, | |||
20040021137, | |||
20040061130, | |||
20040080364, | |||
20040129975, | |||
20040204013, | |||
20040227565, | |||
20040242182, | |||
20050077564, | |||
20050079829, | |||
20050121699, | |||
20050127442, | |||
20050167751, | |||
20050212595, | |||
20050264341, | |||
20060009164, | |||
20060022526, | |||
20060160520, | |||
20060194558, | |||
20060194567, | |||
20060267093, | |||
20070018247, | |||
20070023833, | |||
20070045697, | |||
20070279120, | |||
20080034335, | |||
20080073719, | |||
20080076371, | |||
20080191788, | |||
20080303080, | |||
20090007036, | |||
20090029511, | |||
20110163779, | |||
20110227637, | |||
20120169398, | |||
20120267719, | |||
20130293280, | |||
20140167834, | |||
20140179374, | |||
20150015321, | |||
20150022256, | |||
20160064561, | |||
20160226478, | |||
CN12556521, | |||
CN1256521, | |||
DE112011103554, | |||
DE19832565, | |||
EP622901, | |||
EP851561, | |||
EP1006584, | |||
EP2387094, | |||
EP3113280, | |||
EP385641, | |||
EP625831, | |||
EP782267, | |||
EP913939, | |||
H1435, | |||
JP10079467, | |||
JP10242477, | |||
JP10242826, | |||
JP10242829, | |||
JP10335901, | |||
JP10344247, | |||
JP1093471, | |||
JP11026776, | |||
JP11112316, | |||
JP11136111, | |||
JP11163642, | |||
JP11163704, | |||
JP11205188, | |||
JP11274804, | |||
JP1254014, | |||
JP2000031167, | |||
JP2000183353, | |||
JP2000188501, | |||
JP2000208614, | |||
JP2000223713, | |||
JP2000243973, | |||
JP2000277703, | |||
JP2000294786, | |||
JP2000311986, | |||
JP2001007332, | |||
JP2001089448, | |||
JP2001119281, | |||
JP2001156182, | |||
JP2001157487, | |||
JP2001274265, | |||
JP2002156602, | |||
JP2002164441, | |||
JP2003060451, | |||
JP2003101407, | |||
JP2003143004, | |||
JP2003167615, | |||
JP2003189248, | |||
JP2003332583, | |||
JP2003347553, | |||
JP2004147175, | |||
JP2004166470, | |||
JP2004199950, | |||
JP2004288978, | |||
JP2004515937, | |||
JP2005251931, | |||
JP2161769, | |||
JP4183008, | |||
JP434980, | |||
JP5215850, | |||
JP5299995, | |||
JP5575348, | |||
JP5678106, | |||
JP6006219, | |||
JP6112795, | |||
JP6314985, | |||
JP6334506, | |||
JP7046109, | |||
JP7070245, | |||
JP7106937, | |||
JP8023270, | |||
JP8070245, | |||
JP8148949, | |||
JP8251012, | |||
JP8307305, | |||
JP8330930, | |||
JP9008621, | |||
JP9008627, | |||
JP9041275, | |||
JP9055682, | |||
JP9092785, | |||
JP9148587, | |||
JP9163721, | |||
JP9181641, | |||
JP9186501, | |||
JP9200021, | |||
JP9200074, | |||
JP9238059, | |||
JP9243738, | |||
JP9270659, | |||
JP9284114, | |||
JP9284170, | |||
JP9298493, | |||
JP9326642, | |||
KR1994027615, | |||
RE31749, | Sep 03 1975 | Hitachi, Ltd. | Class B FET amplifier circuit |
RE37124, | Apr 30 1993 | STMicroelectronics, Inc | Ring oscillator using current mirror inverter stages |
WO2006038190, | |||
WO227920, | |||
WO2007008934, | |||
WO2007033045, | |||
WO2007035610, | |||
WO2009108391, | |||
WO2012054642, | |||
WO8601037, | |||
WO9523460, | |||
WO9806174, | |||
WO9935695, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Sep 29 2006 | KIM, TAE YOUN | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Sep 29 2006 | BURGENER, MARK L | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Sep 29 2006 | IMTHURN, GEORGE P | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Sep 29 2006 | KEMERLING, CLINT L | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Sep 29 2006 | KELLY, DYLAN J | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Sep 29 2006 | BRINDLE, CHRISTOPHER N | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Sep 29 2006 | STUBER, MICHAEL A | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Oct 05 2006 | DRIBINSKY, ALEXANDER | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Oct 13 2006 | WELSTAND, ROBERT B | Peregrine Semiconductor Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 031961 | /0725 | |
Jul 22 2013 | Peregrine Semiconductor Corporation | (assignment on the face of the patent) | / | |||
Dec 27 2017 | Peregrine Semiconductor Corporation | pSemi Corporation | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 045749 | /0391 |
Date | Maintenance Fee Events |
Aug 06 2020 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Date | Maintenance Schedule |
Mar 28 2020 | 4 years fee payment window open |
Sep 28 2020 | 6 months grace period start (w surcharge) |
Mar 28 2021 | patent expiry (for year 4) |
Mar 28 2023 | 2 years to revive unintentionally abandoned end. (for year 4) |
Mar 28 2024 | 8 years fee payment window open |
Sep 28 2024 | 6 months grace period start (w surcharge) |
Mar 28 2025 | patent expiry (for year 8) |
Mar 28 2027 | 2 years to revive unintentionally abandoned end. (for year 8) |
Mar 28 2028 | 12 years fee payment window open |
Sep 28 2028 | 6 months grace period start (w surcharge) |
Mar 28 2029 | patent expiry (for year 12) |
Mar 28 2031 | 2 years to revive unintentionally abandoned end. (for year 12) |