A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.
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51. An rf switch, comprising:
a first rf port;
a second rf port;
a first switch transistor grouping coupled to the first rf port and to the second rf port and comprising a first plurality of switch nmosfets arranged in a stacked configuration;
a first shunt transistor grouping coupled to the first rf port and to ground and comprising a first plurality of shunt nmosfets arranged in a stacked configuration,
wherein at least one of the first plurality of shunt nmosfets comprises a first gate, a first source, a first drain, a first body, and a first accumulated charge sink (acs) coupled to the first body,
wherein a first acs bias voltage is applied to the first acs,
wherein the first acs is in electrical communication with the first body and is configured so that when the at least one shunt nmosfet of the first plurality of shunt nmosfets is operated in an off-state (non-conducting state), the first acs bias voltage is substantially negative with respect to ground to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt nmosfet; and
wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.
71. An rf switch, comprising:
a first rf port;
a second rf port;
a first switch transistor grouping coupled to the first rf port and to the second rf port and comprising a first plurality of switch nmosfets arranged in a stacked configuration;
a first shunt transistor grouping coupled to the first rf port and to ground and comprising a first plurality of shunt nmosfets arranged in a stacked configuration,
wherein at least one of the first plurality of shunt nmosfets comprises a first gate, a first source, a first drain, a first body, and a first accumulated charge sink (acs) coupled to the first body,
wherein a first acs bias voltage is applied to the first acs,
wherein the first acs is in electrical communication with the first body and is configured so that when the at least one shunt nmosfet of the first plurality of shunt nmosfets is operated in an off-state (non-conducting state), the first acs bias voltage is substantially more negative than the lesser of a first source bias voltage applied to the first source and a first drain bias voltage applied to the first drain to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt nmosfet; and
wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.
88. An rf switch, comprising:
a first rf port;
a second rf port;
a first switch transistor grouping coupled to the first rf port and to the second rf port and comprising a first plurality of switch nmosfets arranged in a stacked configuration;
a first shunt transistor grouping coupled to the first rf port and to ground and comprising a first plurality of shunt nmosfets arranged in a stacked configuration,
wherein at least one of the first plurality of shunt nmosfets comprises a first gate, a first source, a first drain, a first body, a first accumulated charge sink (acs) coupled to the first body, wherein the first acs is positioned proximate a first distal end of the first body and is in electrical communication with the first body, and a second accumulated charge sink (acs) coupled to the first body, wherein the second acs is positioned proximate a second distal end of the first body and is in electrical communication with the first body,
wherein a first acs bias voltage is applied to the first acs and second acs,
wherein, when the at least one shunt nmosfet of the first plurality of shunt nmosfets is configured to operate in an off-state (non-conducting state), the first acs bias voltage is substantially negative with respect to ground to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt nmosfet; and
wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.
1. An rf switch, comprising:
a first rf port;
a second rf port;
a first switch transistor grouping coupled with the first and second rf ports, and controlled by a first switch control signal, the first switch transistor grouping comprising a first plurality of switch nmosfets arranged in a stacked configuration;
a shunt transistor grouping coupled with the first rf port and with ground, and controlled by a shunt control signal, the shunt transistor grouping comprising a plurality of shunt nmosfets arranged in a stacked configuration, wherein at least one of the plurality of shunt nmosfets comprises a first body and a first accumulated charge sink (acs) coupled with the first body and configured so that when the at least one shunt nmosfet is disabled, a first negative bias voltage that is substantially negative with respect to ground applied to the first acs substantially prevents accumulated charge from accumulating in the first body of the at least one shunt nmosfet; and
a silicon-on-insulator substrate, wherein the first switch transistor grouping and the shunt transistor grouping are fabricated in a silicon layer of the silicon-on-insulator substrate so that when the first switch transistor grouping is enabled by the first switch control signal and the shunt transistor grouping is disabled by the shunt control signal, a signal on the first rf port is passed through to the second rf port, and when the first switch transistor grouping is disabled by the first switch control signal and the shunt transistor grouping is enabled by the shunt control signal, the signal on the first rf port is grounded.
97. An rf switch, comprising:
a first rf port;
a second rf port;
a first switch transistor grouping coupled to the first rf port and to the second rf port and comprising a first plurality of switch nmosfets arranged in a stacked configuration;
a first shunt transistor grouping coupled to the first rf port and to ground and comprising a first plurality of shunt nmosfets arranged in a stacked configuration,
wherein at least one of the first plurality of shunt nmosfets comprises a first gate, a first source, a first drain, a first body, a first accumulated charge sink (acs) coupled to the first body, wherein the first acs is positioned proximate a first distal end of the first body and is in electrical communication with the first body, and a second accumulated charge sink (acs) coupled to the first body, wherein the second acs is positioned proximate a second distal end of the first body and is in electrical communication with the first body,
wherein a first acs bias voltage is applied to the first acs and second acs,
wherein, when the at least one shunt nmosfet of the first plurality of shunt nmosfets is configured to operate in an off-state (non-conducting state), the first acs bias voltage is substantially more negative than the lesser of a first source bias voltage applied to the first source and a first drain bias voltage applied to the first drain to substantially prevent accumulated charge from accumulating in the first body of the at least one shunt nmosfet; and
wherein the first switch transistor grouping and the first shunt transistor grouping are fabricated on a silicon-on-insulator substrate.
47. A circuit routing rf signals, comprising:
a first rf port;
a second rf port;
a third rf port;
a plurality of stacked shunt nmosfets coupled with the first rf port and ground, and controlled by a shunt control signal, wherein at least one of the plurality of stacked shunt nmosfets comprises a first body and a first accumulated charge sink (acs) coupled with the first body and configured so that when the at least one shunt nmosfet is disabled, a first negative bias voltage that is substantially negative with respect to ground applied to the first acs substantially prevents accumulated charge from accumulating in the first body of the at least one shunt nmosfet;
a first plurality of first stacked switch nmosfets coupled with the first and second rf ports, and controlled by a first switch control signal, wherein at least one of the first plurality of first switch nmosfets has a second body and a second accumulated charge sink (acs) coupled with the second body and configured so that when the at least one first switch nmosfet is disabled, a second negative bias voltage that is substantially negative with respect to ground applied to the second acs substantially prevents accumulated charge from accumulating in the second body of the at least one first switch nmosfet;
a second plurality of second stacked switch nmosfets coupled with the second and third rf ports, wherein at least one of the second plurality of second switch nmosfets has a third body and a third accumulated charge sink (acs) coupled to the third body and configured so that when the at least one second switch nmosfet is disabled, a third negative bias voltage that is substantially negative with respect to ground applied to the third acs substantially prevents accumulated charge from accumulating in the third body; and
a silicon-on-insulator substrate, wherein the shunt, first switch and second switch nmosfets are fabricated in a silicon layer of the silicon-on-insulator substrate.
2. The rf switch of
3. The rf switch of
4. The rf switch of
5. The rf switch of
6. The rf switch of
7. The rf switch of
8. The rf switch of
9. The rf switch of
10. The rf switch of
11. The rf switch of
12. The rf switch of
13. The rf switch of
a third rf port; and
a second switch transistor grouping coupled with the second and third rf ports wherein the second switch transistor grouping comprises a second plurality of switch nmosfets arranged in a stacked configuration, wherein at least one of the second plurality of switch nmosfets has a third body and a third accumulated charge sink (acs) coupled to the third body and configured so that when the at least one switch nmosfet of the second plurality of switch nmosfets is disabled, a third negative bias voltage that is substantially negative with respect to ground applied to the third acs substantially prevents accumulated charge from accumulating in the third body.
14. The rf switch of
15. The rf switch of
16. The rf switch of
17. The rf switch of
18. The rf switch of
19. The rf switch of
20. The rf switch of
21. The rf switch of
22. The rf switch of
23. The rf switch of
24. The rf switch of
25. The rf switch of
26. The rf switch of
27. The rf switch of
28. The rf switch of
29. The rf switch of
30. The rf switch of
31. The rf switch according to
32. The rf switch according to
35. The rf switch of
36. The rf switch of
37. The rf switch of
38. The rf switch of
39. The rf switch of
40. The rf switch of
41. The rf switch of
42. The rf switch of
43. The rf switch of
44. The rf switch of
45. The rf switch of
46. The rf switch of
48. The circuit of
49. The circuit of
50. The circuit of
52. The rf switch of
53. The rf switch of
54. The rf switch of
55. The rf switch of
57. The rf switch of
58. The rf switch of
59. The rf switch of
a third rf port;
a second switch transistor grouping coupled to the third rf port and to the second rf port and comprising a second plurality of switch nmosfets arranged in a stacked configuration,
wherein at least one of the second plurality of switch nmosfets comprises a second gate, a second source, a second drain, a second body, and a second accumulated charge sink (acs) coupled to the second body,
wherein a second acs bias voltage is applied to the second acs,
wherein the second acs is in electrical communication with the second body and is configured so that when the at least one switch nmosfet of the second plurality of switch nmosfets is operated in an off-state (non-conducting state), the second acs bias voltage is substantially negative with respect to ground to substantially prevent accumulated charge from accumulating in the second body of the at least one switch nmosfet of the second plurality of switch nmosfets; and
wherein the second switch transistor grouping is fabricated on the silicon-on-insulator substrate.
60. The rf switch of
61. The rf switch of
62. The rf switch of
63. The rf switch of
64. The rf switch of
65. The rf switch of
66. The rf switch of
67. The rf switch of
68. The rf switch of
69. The rf switch of
70. The rf switch of
72. The rf switch of
73. The rf switch of
75. The rf switch of
76. The rf switch of
77. The rf switch of
a third rf port;
a second switch transistor grouping coupled to the third rf port and to the second rf port and comprising a second plurality of switch nmosfets arranged in a stacked configuration,
wherein at least one of the second plurality of switch nmosfets comprises a second gate, a second source, a second drain, a second body, and a second accumulated charge sink (acs) coupled to the second body,
wherein a second acs bias voltage is applied to the second acs,
wherein the second acs is in electrical communication with the second body and is configured so that when the at least one switch nmosfet of the second plurality of switch nmosfets is operated in an off-state (non-conducting state), the second acs bias voltage is substantially more negative than the lesser of a second source bias voltage applied to the second source and a second drain bias voltage applied to the second drain to substantially prevent accumulated charge from accumulating in the second body of the at least one switch nmosfet of the second plurality of switch nmosfets; and
wherein the second switch transistor grouping is fabricated on the silicon-on-insulator substrate.
78. The rf switch of
79. The rf switch of
80. The rf switch of
81. The rf switch of
82. The rf switch of
83. The rf switch of
84. The rf switch of
85. The rf switch of
86. The rf switch of
87. The rf switch of
89. The rf switch of
90. The rf switch of
a first electrical contact region positioned proximate to and in electrical communication with the first acs, wherein the first electrical contact region facilitates electrical coupling to the first acs; and
a second electrical contact region positioned proximate to and in electrical communication with the second acs, wherein the second electrical contact region facilitates electrical coupling to the second acs.
91. The rf switch of
92. The rf switch of
93. The rf switch of
94. The rf switch of
95. The rf switch of
96. The rf switch of
98. The rf switch of
99. The rf switch of
a first electrical contact region positioned proximate to and in electrical communication with the first acs, wherein the first electrical contact region facilitates electrical coupling to the first acs; and
a second electrical contact region positioned proximate to and in electrical communication with the second acs, wherein the second electrical contact region facilitates electrical coupling to the second acs.
100. The rf switch of
101. The rf switch of
102. The rf switch of
103. The rf switch of
104. The rf switch of
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This application
wherein Etb comprises the maximum oxide electric field for which a given TDDB lifetime of the SOI NMOSFET can be obtained (e.g., ˜5 MV/cm for a lifetime of 10 years is a “rule of thumb” value). More generally, the SOI NMOSFET bias voltages, maximum signal voltages, and gate oxide thicknesses can be selectively improved using the ACC techniques of the present teachings. These improvements over the prior art SOI NMOSFET devices are provided according to the improvement factor F1, as shall be readily appreciated by persons skilled in the electronic device design arts. Finally, at a STEP 1018, the circuit is operated using ACC techniques as described above.
At a STEP 1024, a limiting gate bias voltage Vg2 is determined using TDDB measurements for the SOI NMOSFET having an oxide thickness Tox, operated in the off-state with ACC. For example, for Vd=Vs=0, the limiting gate bias voltage Vg2 represents the most negative gate bias that can be sustained to obtain a desired operating lifetime with ACC. An improvement factor F2 is defined according to the following expression: F2=Vg1/Vg2.
At a STEP 1026, a circuit including the SOI NMOSFET is implemented responsive to the improvement factor, F2. In one embodiment of the inventive method, the circuit is implemented by selecting a maximum gate-to-source operating voltage Vgs for the off-state and Tox according to the following equation:
Vgs(max)/Tox=F2·Etb (2)
More generally, the SOI NMOSFET bias voltages, maximum signal voltages, and gate oxide thicknesses can be selectively improved over the prior art according to the improvement factor F2, as shall be readily appreciated by persons skilled in the electronic device arts. Referring again to
A number of embodiments of the present inventive concept have been described. Nevertheless, it will be understood that various modifications may be made without departing from the scope of the inventive teachings. For example, it should be understood that the functions described as being part of one module may in general be performed equivalently in another module.
Accordingly, it is to be understood that the concepts described herein are not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.
Imthurn, George P., Burgener, Mark L., Stuber, Michael A., Dribinsky, Alexander, Kim, Tae Youn, Kelly, Dylan J., Brindle, Christopher N., Welstand, Robert B., Kemerling, Clint L.
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