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The ornamental design for an integrated circuit device, as shown. |
FIG. 1 is a bottom plan view of an integrated circuit device showing our new design;
FIG. 2 is a top plan view thereof;
FIG. 3 is a left side elevational view thereof;
FIG. 4 is a front elevational view thereof;
FIG. 5 is a right side elevational view thereof;
FIG. 6 is a rear elevational view thereof;
FIG. 7 is a perspective view thereof; and
FIG. 8 is a sectional view taken along line A--A of FIG. 2.
Sugimoto, Masahiro, Wakabayashi, Tetsushi, Akasaki, Hidehiko
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 05 1982 | SUGIMOTO, MASAHIRO | FUJITSU LIMITED, A CORP OF JAPAN | ASSIGNMENT OF ASSIGNORS INTEREST | 004034 | /0904 | |
Jul 05 1982 | AKASAKI, HIDEHIKO | FUJITSU LIMITED, A CORP OF JAPAN | ASSIGNMENT OF ASSIGNORS INTEREST | 004034 | /0904 | |
Jul 05 1982 | WAKABAYASHI, TETSUSHI | FUJITSU LIMITED, A CORP OF JAPAN | ASSIGNMENT OF ASSIGNORS INTEREST | 004034 | /0904 | |
Jul 12 1982 | Fujitsu Limited | (assignment on the face of the patent) | / |
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