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The ornamental design for an integrated circuits substrate, as shown and described.
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FIG. 1 is a front, top and right side perspective view of an integrated circuits substrate, showing my new design;
FIG. 2 is a front elevational view thereof, the rear elevational view is omitted as that is symmetrical to the front elevational view thereof;
FIG. 3 is a top plan view thereof;
FIG. 4 is a bottom plan view thereof;
FIG. 5 is a right side elevational view thereof;
FIG. 6 is a left side elevational view thereof; and,
FIG. 7 is an enlarged cross-sectional view thereof, taken along line 7--7 of FIG. 2, with the internal system omitted.
The broken lines in all views are shown for illustrative purposes only and form no part of the claimed design.
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