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The ornamental design for a semiconductor module, as shown.
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FIG. 1 is a front view of a semiconductor module showing our new design;
FIG. 2 is a rear view thereof;
FIG. 3 is a top plan view thereof;
FIG. 4 is a bottom plan view thereof;
FIG. 5 is a left side view thereof; and,
FIG. 6 is a right side view thereof.
The broken lines shown in the drawings are for illustrative purposes only and form no part of the claimed design.
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 25 2005 | HIGASHIBATA, KAZUAKI | MURATA MANUFACTURING CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 017022 | /0419 | |
Sep 22 2005 | Murata Manufacturing Co., Ltd. | (assignment on the face of the patent) | / |
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