Electrically erasable programmable read-only memory with NAND cell structure

Abstract

An erasable programmable read-only memory with nand cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into nand cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain nand cell block is selected, memory cells in the nand cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected nand cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

Description

5u it 12conductive nonconductive, thus electrically disconnecting each cell block Bi from corresponding bit line Bi BLi. A positive boosted potential (e.g. 18 volts) is applied to word lines WL1 through WL4. In this case well potential Vwell and potential Vbit of all the bit lines including bit lines BL1 and BL2 are set to ground potential (0 volts). By such a voltage application scheme, in all the memory cells M including memory cells M1 through M4, electrons are tunneled from between their floating gates 50 back to and P-well layer 40 in accordance with the same manner as the above erase mechanism. Consequently, all the memory cells M are erased simultaneously.

In the data write mode, a voltage of 5 volts is applied to control gate line SG1 so that first selection transistor Qs1 is rendered nonconductive conductive, thereby electrically disconnecting connecting cell block B1 from to bit line BL1. A positive boosted voltage (e.g. 20 volts) is applied to control gate line SG2 so that second selection transistor Qs2 is rendered nonconductive, thus electrically disconnecting cell block B1 at the source of memory cell transistor M4 from N-well layer 102 source potential Vs. At this time well potential Vwell is also set to the positive boosted voltage (20 volts). Vwell is also set to the positive boosted voltage (20 volts).

As in the previous case, cell M4 is subjected to data writing first. At this time ground potential (-0 volts) is applied only to word line WL4, whereas a positive intermediate voltage (10 volts) is applied to the remaining word lines WL1 through WL3. Potential Vbitl of selected bit line BL1 is set to a positive boosted voltage (20 volts) and potential Vbit2 of nonselected bit line BL2 is set to a positive intermediate voltage (10 volts). Consequently, a strong electric field is generated in selected cell M4 in accordance with the same manner as described above so that electrons are tunneled from the floating gate back to N-well layer 102 and thus the threshold of cell M4 shifts in the negative direction, causing logic "1" data to be written into M4. Similarly, the selective data writing will be performed on cells M in the order of M3, M2, M1.

In the data read mode, for example, when cell M4 is selected, gate voltages Vsg1 and Vsg2 of first and second selection transistors Qs1 and Qs2, control gate voltages Vcg1 to Vcg3 of nonselected cells M1 to M3, and voltage Vbitl of selected bit line BL1 are set to ground potential (0 volts). At this time selected bit line BL2 and well potential Vwell are set to 5 volts. Control gate voltage Vcg4 of selected cell M4 is set to 5 volts by applying 5 volts to word line WL4. Consequently, the readout voltage corresponding to the stored data in selected cell M4 is transferred to bit line BL1 via nonselected cell transistors M1 to M3 which has been rendered conductive and then subjected to the logic level discrimination in the same manner as described above.

The EEPROM may be modified such that the NAND cell structure with memory cells M consisting of N channel MOSFETs as shown in FIG. 5 is formed in P-type chip substrate 150 as shown in FIG. 10. In this case, an N-well layer 152 is additionally formed in P-substrate 150 so as to surround P-well layer 40 in which first and second selection transistors Qs1 and Qs2 and N type diffusion layers 66, 68, 70, 72, 76, 78 serving as the sources and drains of memory cells M1 to M4 of NAND cell block B1 are formed. P-well layer 40 and N-well layer 152 are connected together to a terminal 154 so that they are at the same potential. The simultaneous erase, write and read operations of this modifications are performed by the use of the same voltage application scheme as that in the previous modification of FIG. 8.

The plan configuration of NAND cell block B1 of the EEPROM according to still another modification has a "three-gate structure" as shown in FIG. 11. More specifically, an erase gate layer 200 is insulatingly provided between floating gates 50 and control gates 54 of series-arrayed memory cell transistors M1 to M4 of NAND cell block B1 so as to run perpendicular to those gates. Floating gates 50 overlap erase gate 200 as shown. Erase gate layer 200 is formed of a polysilicon layer which runs parallel to aluminum wiring layer 46. The polysilicon layer is ranged in thickness from 100 to 400 nm. The cell sectional structure taken along aluminum wiring layer 46 is exactly the same as that in the embodiment of FIG. 5.

The sectional structure taken along erase gate layer 200 is shown in FIG. 12 wherein like reference symbols are used to denote like portions in FIG. 5. As shown in FIG. 12, erase gate layer 200 is also insulatingly sandwiched between double-layered gates 58 and 60 (62 and 64) of each of first and second selection transistors Qs1 and Qs2 provided at the opposite ends of the series array of cell transistors M1 to M4. In each memory cell transistor, floating gate 50 and control gate 52 are capacitively coupled to each other through erase gate 200. An equivalent circuit of NAND cell block B1 having the "three-gate" structure is shown in FIG. 13 wherein erase gate 200 of NAND cell block B1 and the erase gate of another NAND cell block B2 adjacent to B1 are connected together to gate control voltage Veg.

In the simultaneous erase mode, voltage Veg on erase gate 200 is set a boosted potential (20 volts) as shown in FIG. 14. Well potential Vwell and substrate potential Vsub are constantly maintained at ground potential (0 volts) during all the operation modes including the simultaneous erase mode. Gate voltages Vsg1 and Vsg2 of first and second selection transistors Qs1 and Qs2 are set to a voltage which may be ranged from 0 to 5 volts (e.g. 0 volts). Voltage Vbit on all bit lines BL and voltages Vcgl to Vcg4 on word lines WL1 to WL4 are set to ground potential (0 volts). Consequently, in NAND cell block B1, electrons accumulated at floating gates of memory cells M1 to M4 are simultaneously discharged to erase gate 200 due to tunnel effect so that all the memory cells M are erased simultaneously. The selective writing and reading is performed in the same way as in the embodiment having P-well layer 40.

With such an arrangement, since floating gate 50 and control gate 54 of each of memory cells M are partly capacitively coupled to each other, no high gate voltage is needed for erasing data. Hence, this will enable the reduction of the power dissipation in the EEPROM and the simplification of the peripheral circuit arrangement. Further, since, in each cell, a region through which tunnel current flows to erase data is relatively narrow, when the EEPROM is repeatedly subjected to the simultaneous erase, the degradation of the quality of polycrystalline silicon gate insulating layer 52 (see FIG. 4) of NAND cell block B1 can be minimized. Thus the operational reliability of the EEPROM can be improved. This type of NAND cell structure may be directly formed on a chip substrate without the use of P-well layer 40, if desired.

Claims

1. A non-volatile dynamic semiconductor memory device comprising:

(a) a semiconductive substrate having a major surface;

(b) a semiconductive well region formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device;

(c) parallel bit lines provided above said substrate;

(d) rewritable memory cells connected to said bit lines, said memory cells comprising nand cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer, a control gate and semiconductive layers formed in said well region to function as sources and drains, and said well region functioning as a surface breakdown prevention layer; and

(e) control means for writing data into memory cells of a selected nand cell block sequentially during a data write mode subsequent to the a data erase mode, said control means applying, when a certain memory cell of said selected nand cell block is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well region.

2. The device according to claim 1, wherein said substrate has a first conductivity type, said well region has a second conductivity type, and said semiconductive layers have the first conductivity type.

3. The device according to claim 1, wherein said substrate and said well region have a first conductivity type and said semiconductive layers have a second conductivity type; and wherein said device further comprises an additional well region of the second conductivity type formed in said substrate so as to surround said well region.

4. The device according to claim 3, wherein said well regions are connected to a common well potential.

5. The device according to claim 1, wherein said selected nand cell block comprises:

a first selection transistor provided at one end of said selected nand cell block and selectively rendered conductive for electrically connecting said selected nand cell block to a corresponding bit line associated therewith; and

a second selection transistor provided at the other end of said selected nand cell block and selectively rendered conductive for electrically connecting said selected nand cell block to said well area a source potential, said second selection transistor being rendered nonconductive during the data write mode so as to prevent leakage flow of current between in said corresponding bit line and said substrate.

6. The device according to claim 1, wherein each of said nand cell blocks comprises:

an erase gate layer provided insulatingly over said substrate so as to extend substantially parallel to said series array of memory cell transistors and sandwiched insulatingly by said charge accumulation layer and said control gate of each of said memory cell transistors, said erase gate layer overlapping said charge accumulation layer, and said charge accumulation layer and said control gate being capacitively coupled to each other by said erase gate layer.

7. An erasable programmable read-only memory device comprising:

(a) a semiconductive substrate having a semiconductive well layer formed in its major surface;

(b) parallel bit lines provided over said substrate;

(c) parallel word lines intersecting said bit lines insulatingly;

(d) double-gate field effect transistors provided at intersections of said bit lines and said word lines for functioning as memory cells, said transistors including a cell array which has a series-circuit of cell transistors constituting a nand cell block, each of said cell transistors having semiconductor layers serving as a source and a drain thereof, an electrically floating gate layer serving as a charge accumulation layer and a control gate layer connected to a corresponding word line, said semiconductor layers being formed in said well layer;

(e) a field effect transistor provided at one end of said nand cell block and selectively rendered conductive for serving as a first selection transistor;

(f) a field effect transistor provided at the other end of said nand cell block and selectively rendered conductive for serving as a second selection transistor; and

(g) driving means for, when said nand cell block is selected during a data write mode of said device, (1) rendering said first selection transistor conductive to electrically connect said nand cell block to a corresponding bit line associated therewith to which write data is applied, (2) rendering said second selection transistor nonconductive to electrically disconnect said nand cell block from said well layer, and (3) writing data into memory cells of said nand cell block sequentially, said driving means changing a potential of said well layer to have a level different from that of a potential of said well layer in a simultaneous erase mode prior to the data write mode of said device.

8. The device according to claim 7, wherein said driving means writes data into memory cells of said nand cell block in a predetermined sequence in which a cell transistor adjacent to said second selection transistor is subjected to writing first and a cell transistor adjacent to said first selection transistor is subjected to writing last.

9. The device according to claim 8, wherein said driving means applies, when a certain memory cell of said nand cell block is subjected to writing, to said control gate of said certain memory cell a first voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well layer and to the remaining memory cells of said nand cell block a second voltage lower than the first voltage.

10. The device according to claim 9, wherein said substrate has a first conductivity type, said well layer has a second conductivity type, and said semiconductive layers have the first conductivity type.

11. The device according to claim 10, wherein said driving means applies to said well layer one of a "H" level potential and a "L" level potential during the simultaneous erase mode and the other of the "H" level potential and the "L" level potential during the data write mode.

12. The device according to claim 9, wherein said substrate and said well layer have a first conductivity type and said semiconductive layers have a second conductivity type; and wherein said device further comprises an additional well layer of the second conductivity type formed in said substrate so as to surround said well layer.

13. The device according to claim 12, wherein said driving means applies to said well layers a "L" "H" level potential during the simultaneous erase mode and a "H" "L" level potential during the data write mode.

14. The device according to claim 1, wherein said control means erases data stored in all said memory cells simultaneously during a data erase mode of said memory device.

15. A non-volatile dynamic semiconductor memory device comprising:

a semiconductor substrate having a major surface;

a semiconductor well region formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device;

parallel bit lines provided above said substrate;

rewritable memory cells connected to said bit lines, said memory cells comprising nand cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer, a control gate and semiconductor layers formed in said well region to function as sources and drains, and said well region functioning as a surface breakdown prevention layer;

control means for erasing data stored in all said memory cells simultaneously during a data erase mode of said memory device and writing data into memory cells of a selected nand cell block sequentially during a data write mode subsequent to the data erase mode, said control means applying, when a certain memory cell of said selected nand cell block is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well region;

a first selection transistor provided at one end of said selected nand cell block and selectively rendered conductive for electrically connecting said selected nand cell block to a corresponding bit line associated therewith; and

a second selection transistor provided at the other end of said selected nand cell block and selectively rendered conductive for electrically connecting said selected nand cell block to said well area a source potential, said second selection transistor being rendered nonconductive during the data write mode so as to prevent leakage of current between flow of current in said corresponding bit line and said substrate.

16. A nonvolatile semiconductor memory device comprising:

(a) a semiconductor substrate having a major surface;

(b) a semiconductor well region formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device;

(c) parallel bit lines provided above said substrate;

(d) rewritable memory cells connected to said bit lines, said memory cells comprising nand cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer, a control gate and semiconductor layers formed in said well region to function as sources and drains;

(e) at least first selection transistors included in said nand cell blocks, each of said first selection transistors provided at one end of said series array of memory cell transistors, and said first selection transistors being formed in said well region in which said nand cell blocks are formed; and

(f) control means for writing data into memory cells of a selected nand cell block sequentially during a data write mode subsequent to a data erase mode, said control means applying, when a certain memory cell of said selected nand cell block is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well region. 17. The device according to claim 16, wherein said substrate has a first conductivity type, said well region has a second conductivity type, and said semiconductor layers have the first conductivity type. 18. The device according to claim 16, wherein said substrate and said well region have a first conductivity type and said semiconductor layers have a second conductivity type; and wherein said device further comprises an additional well region of the second conductivity type formed in said substrate so as to surround said well region. 19. The device according to claim 18, wherein said well regions are connected to a common well potential. 20. The device according to claim 16, wherein said selected nand cell block further comprises:

second selection transistors included in said nand cell blocks, each of said second selection transistors provided at the other end of said series array of memory cell transistors, and said second selection transistors being formed in said well region in which said nand cell blocks are formed. 21. The device according to claim 16, wherein each of said nand cell blocks comprises:

an erase gate layer provided insulatingly over said substrate so as to extend substantially parallel to said series array of memory cell transistors and sandwiched insulatingly by said charge accumulation layer and said control gate of each of said memory cell transistors, said erase gate layer overlapping said charge accumulation layer, and said charge accumulation layer and said control gate being capacitively coupled to each other by said erase gate layer. 22. The device according to claim 20, wherein:

said first selection transistors are selectively rendered conductive for electrically connecting said series array of memory cell transistors to a corresponding bit line associated therewith; and

said second selection transistors are selectively rendered conductive for electrically connecting said series array of memory cell transistors to a source potential and are rendered nonconductive during the data write mode so as to prevent flow of current in said corresponding bit line.