memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer arrays and methods of operation are described.
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0. 15. A method of forming a memory device, comprising:
forming a first plurality of gates;
forming a first semiconductor body;
forming a first plurality of multi-layered hole-tunneling dielectrics and a first plurality of charge storage regions between the first plurality of gates and the first semiconductor body;
forming a second plurality of gates;
forming a second semiconductor body; and
forming a second plurality of multi-layered hole-tunneling dielectrics and a second plurality of charge storage regions between the second plurality of gates and the second semiconductor body, wherein a semiconductor region between one of the second gates and another one of the second gates is junction-free and the first plurality of charge storage regions are over the second plurality of charge storage regions.
0. 13. A memory device, comprising:
a first gate and a second gate;
a first semiconductor body including a first channel surface and a second semiconductor body including a second channel surface;
a first tunnel structure and a first charge storage region located between the first gate and the first channel surface;
the first tunnel structure including a first portion and second portion, a middle portion located between the first and second portion, the first portion having a valence band energy, the middle portion having a valence band energy greater than that of the first portion, the second portion having a valence band energy less than that of the middle portion; and
a second tunnel structure and a second charge storage region located between the second gate and the second channel surface, wherein the first charge storage region is over the second charge storage region.
12. A method for forming a semiconductor structure, comprising:
forming a plurality of first semiconductor body regions bodies;
forming a plurality of first word lines, each of the plurality of first word lines overlying crossing over a channel region in each of the first semiconductor body regions bodies;
forming a first tunneling barrier, a first charge storage layer, and a first dielectric layer between each of the first word lines and a corresponding channel region in each of the first semiconductor body regions bodies, wherein regions in the first semiconductor body regions bodies between one of the first word lines and another one of the first word lines are junction-free;
forming an inter-dielectric layer over the first word lines;
forming a plurality of second semiconductor body regions bodies overlying the inter-dielectric layer;
forming a plurality of second word lines over crossing over channel regions in each of the second semiconductor body regions bodies; and
forming a second tunneling barrier, a second charge storage layer and a second dielectric layer between the second word lines and a corresponding channel region in each of the second semiconductor body region bodies.
1. A method for forming a semiconductor structure, comprising:
forming a plurality of first parallel semiconductor body regions bodies with a first dopant type over a substrate;
forming a plurality of first parallel word lines between a first select line and a second select line, the first word lines, the first select line and the second select line being over and intersecting the first semiconductor body regions bodies in an array of cross points;
forming a first tunneling barrier, a first charge storage layer and a first dielectric layer between the first semiconductor body regions bodies and the first word lines;
forming first dielectric spacers on a sidewall of the first select line and a sidewall of the second select line;
forming first source/drain (S/D) junctions with a second dopant type adjacent to the first select line and the second select line;
forming a second dielectric layer over the first word lines;
forming a plurality of second parallel semiconductor body regions bodies with the first dopant type over the second dielectric layer;
forming a plurality of second parallel word lines between a third select line and a fourth select line, the second parallel word lines, the third select line and the fourth select line being over and substantially perpendicular to the second semiconductor body regions bodies;
forming a second tunneling barrier, a second charge storage layer and a third dielectric layer between the second semiconductor body regions bodies and the second word lines;
forming second dielectric spacers on a sidewall of the third select line and a sidewall of the fourth select line; and
forming second source/drain (S/D) regions junctions with the second dopant type adjacent to the third select line and the fourth select line;
wherein the regions in the first semiconductor body regions bodies between two neighboring first word lines and the regions in the second semiconductorbody regions bodies between two neighboring second word lines are junction-free.
2. The method of
3. The method of
4. The method of
5. The method of
forming a patterned mask layer overlying at least portions of the first and second select lines and the first word lines; and
implanting dopants of the second dopant type into the first semiconductor body regions bodies by using the patterned mask layer as an implantation mask.
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
11. The method of
0. 14. The memory device of claim 13, wherein the first and second gates include a material having a work function greater than that of N+ polysilicon.
0. 16. The method of forming a memory device of claim 15, wherein a semiconductor region between one of the first gates and another one of the first gates is junction-free.
0. 17. The method of forming a memory device of claim 16, wherein the first and second plurality of gates include a material having a work function greater than that of N+ polysilicon.
0. 18. The method of forming a memory device of claim 16, wherein both the first and the second plurality of multi-layered hole-tunneling dielectrics include a first portion and second portion, a middle portion located between the first and second portion, the first portion having a valence band energy, the middle portion having a valence band energy greater than that of the first portion, the second portion having a valence band energy less than that of the middle portion.
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This application is a reissue application of U.S. Pat. No. 8,937,340, issued from U.S. application Ser. No. 13/899,629, filed 22 May 2013, which is a divisional of U.S. application Ser. No. 12/056,489, filed Mar. 27, 2008 (now U.S. Pat. No. 8,482,052). The U.S. application Ser. No. 12/056,489 is a continuation-in-part of U.S. patent application Ser. No. 11/831,594, filed Jul. 31, 2007 (now U.S. Pat. No. 7,426,140); which is a continuation of U.S. patent application Ser. No. 11/324,581, filed Jan. 3, 2006 (now U.S. Pat. No. 7,315,474), which is based upon, and claims priority under 35 U.S.C. §119(e) of provisional U.S. Patent Application No. 60/640,229, filed on Jan. 3, 2005; provisional U.S. Patent Application No. 60/647,012, filed on Jan. 27, 2005; provisional U.S. Patent Application No. 60/689,231, filed on Jun. 10, 2005; and provisional U.S. patent application No. 60/689,314, filed on Jun. 10, 2005; the entire contents of each of which are incorporated herein by reference. The U.S. application Ser. No. 12/056,489 is a continuation-in-part of U.S. patent application Ser. No. 11/425,959, filed on Jun. 22, 2006 (now U.S. Pat. No. 7,709,334), which claims priority to provisional U.S. Patent Application No. 60/748,807, filed on Dec. 9, 2005, the entire contents of each of which are incorporated herein by reference. The U.S. application Ser. No. 12/056,489 is a continuation-in-part of U.S. patent application Ser. No. 11/549,520, filed on Oct. 13, 2006 (now U.S. Pat. No. 7,473,589), which claims priority to provisional U.S. Patent Application No. 60/748,911, filed on Dec. 9, 2005, the entire contents of each of which are incorporated herein by reference. The U.S. application Ser. No. 12/056,489 claims the benefit of provisional U.S. Patent Application No. 60/980,788, filed on Oct. 18, 2007 and provisional U.S. Patent Application No. 61/018,589, filed on Jan. 2, 2008, the entire contents of each of which are incorporated herein by reference.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
Generally, non-volatile memory devices may have various designs. One example of an NVM cell design is the so-called SONOS (silicon-oxide-nitride-oxide-silicon) device, which may use a thin tunnel oxide layer, to allow hole direct tunneling erase operations. Although such designs may have good erase speed, the data retention is usually poor, in part because direct tunneling may occur even at a low electrical field strengths that may exist during a retention state of a memory device.
Another NVM design is NROM (nitrided read-only memory), which uses a thicker tunnel oxide layer to prevent charge loss during retention states. However, a thick tunnel oxide layer may impact channel erase speed. As a result, band-to-band tunneling hot-hole (BTBTHH) erase methods can be used to inject hole traps to compensate the electrons. However, the BTBTHH erase methods may cause some reliability issues. For example, the characteristics of NROM devices employing BTBTHH erase methods may degrade after numerous P/E (program/erase) cycles.
In addition, techniques have been explored to stack layers of memory arrays on a single integrated circuit in order to address the need for high-density non-volatile memory.
Thus, a need in the art exists for non-volatile memory cell designs and arrays which can be operated (programmed/erased/read) numerous times with improved data retention performance and increased operation speeds, and in addition are suitable for implementation in thin film structures and in stacked arrays.
The present invention relates to junction-free, thin-film memory cells formed on silicon on insulator substrates and similar insulating structures, and to stacked junction free memory cells. An integrated circuit memory device is described comprising a semiconductor body formed on an insulating layer, such as on a silicon on insulator substrate; a plurality of gates arranged in series on the semiconductor body, the plurality of gates including a first gate in the series and a last gate in the series, with insulating members isolating gates in the series from adjacent gates in the series; and a charge storage structure on the semiconductor body. The charge storage structure includes dielectric charge trapping locations beneath more than one of the plurality of gates in the series, the charge storage structure including a tunnel dielectric structure disposed above the semiconductor body, a charge storage layer disposed above the tunnel dielectric structure, and an insulating layer disposed above the charge storage layer. The semiconductor body includes a continuous, junction-free, multiple-gate channel region beneath the plurality of gates in the series. The multiple-gate channel region may have one of n-type and p-type conductivity.
One embodiment of the present invention includes memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a hole tunneling barrier height at an interface with the semiconductor body, and a hole tunneling barrier height spaced away from the interface that is less than the hole tunneling barrier height at an interface. A tunnel dielectric layer having this characteristic comprises a multi-layer structure including a layer in contact with the semiconductor body and at least one layer having a hole-tunneling-barrier height less than that of the layer in contact with the semiconductor body. A charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer.
Another embodiment of the present invention includes memory cells in contrast to the junction-free embodiments, comprising a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a multi-layer tunnel dielectric structure disposed above the channel region, the multi-layer tunnel dielectric structure comprising at least one layer having a hole-tunneling-barrier height less than that of the layer in contact with the semiconductor body; a charge storage layer disposed above the multi-layer tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer.
In certain preferred embodiments, the layer providing a smaller hole-tunneling-barrier height may contain materials such as silicon nitride (Si3N4) or hafnium oxide (HfO2). In certain preferred embodiments of the present invention memory cells include a tunnel dielectric structure having multiple layers, such as a stacked dielectric tri-layer structure of silicon oxide, silicon nitride, and silicon oxide (ONO). Such tunnel dielectric structures provide a SONONOS (silicon-oxide-nitride-oxide-nitride-oxide-silicon) or a super-lattice SONONOS design.
In certain preferred embodiments of the present invention the tunnel dielectric structure can comprise at least two dielectric layers each having a thickness of up to about 4 nm. Additionally, in certain preferred embodiments of the present invention, the gate electrode comprises a material having a work function value greater than that of N+ polysilicon.
In certain preferred embodiments, the tunnel dielectric structure can include a layer comprising a material having a small hole tunneling barrier height, wherein the material is present in the layer at a concentration gradient such that the concentration of the material is at a maximum at a depth point within the layer.
The present invention also includes non-volatile memory devices which comprise a plurality of memory cells (i.e., an array) in accordance with one or more of the embodiments described herein. As used herein, a “plurality” refers to two or more. Memory devices in accordance with the present invention exhibit significantly improved operational properties including increased erase speeds, improved charge retention and larger windows of operation.
The present invention also includes methods of operating non-volatile memory cells and arrays. Methods of operation in accordance with the present invention include resetting the memory devices by applying a self-converging method to tighten Vt distribution of the memory devices; programming at least one of the memory devices by channel +FN injection; and reading at least one of the memory devices by applying a voltage between an erased state level and a programmed state level of at least one of the memory devices. As used herein, the term “tighten” refers to the narrowing of the threshold voltage distribution among the many memory cells of an array. In general, threshold voltage distribution is “tightened” where the threshold voltages of several cells are within a narrow range of one another such that operation of the array is improved over conventional designs. For example, in some preferred embodiments, such as in a NAND array comprising memory cells in accordance with one or more embodiments of the present invention, a “tightened” threshold voltage distribution indicates that the threshold voltages of the various memory cells are within a 0.5V range of one another. In other array architectures employing memory cells in accordance with the present invention, the “tightened” threshold voltage distribution may have a range of about 1.0V from the upper limit to the lower limit.
One embodiment of a method of operation in accordance with the present invention includes operating an array in accordance with the present invention by applying self-converging reset/erase voltages to the substrate and the gate electrode in each memory cell to be reset/erased; programming at least one of the plurality of memory cells; and reading at least one of the plurality of memory cells by applying a voltage between an erased state level and a programmed state level of at least one of the memory devices.
The present invention also includes methods of forming a memory cell, comprising: providing a semiconductor substrate having a source region and a drain region formed therein below a surface of the substrate and separated by a channel region; forming a tunnel dielectric structure above the channel region, wherein forming the tunnel dielectric structure comprises forming at least two dielectric layers, wherein one of the at least two dielectric layers has a smaller hole tunneling barrier height than the other of the at least two dielectric layers; forming a charge storage layer above the tunnel dielectric structure; forming an insulating layer above the charge storage layer; and forming a gate electrode above the insulating layer.
According to an exemplary embodiment of junction-free technology, a semiconductor structure includes a plurality of first parallel semiconductor semiconductor body regions over a silicon-on-insulator substrate, the plurality of first semiconductor body regions being characterized by a first concentration of a first dopant type. A first select line and a second select line overlie and are substantially perpendicular to the first semiconductor body regions. A plurality of first parallel word lines are between the first select line and the second select line, each of the plurality of first word lines overlying a channel region in each of the first semiconductor body regions and being substantially perpendicular to the first semiconductor body regions. A first tunneling barrier, a first charge storage layer, and a first dielectric layer are between each of the first word lines and a corresponding channel region in each of the first semiconductor body regions. At least one first region is in each of the first semiconductor body regions. The at least one first region is adjacent to the first select line or the second select line. The at least one first region is characterized by a second dopant type. One or more second regions are in each of the first semiconductor body regions, each of the one or more second regions being between two neighboring channel regions, the one or more second regions being characterized by a second concentration of the first dopant type, wherein the one or more second regions are junction-free.
According to an exemplary embodiment of this SOI technology, the semiconductor structure further comprises a plurality of trench structures adjacent to and in parallel with the first semiconductor body regions, each of the trench structures separating two adjacent first semiconductor body regions.
According to an exemplary embodiment of this SOI technology, the first tunneling barrier includes a first oxide layer, a nitride layer and a second oxide layer.
According to an exemplary embodiment of this SOI technology, the first tunneling barrier, the first charge storage layer, and the first dielectric layer is an ONONO structure.
According to an exemplary embodiment of this SOI technology, the SOI substrate comprises an oxide layer over the substrate and under the first semiconductor body regions.
According to an exemplary embodiment of this SOI technology, the first region extends under at least one of the first select line and the second select line.
According to an exemplary embodiment of this SOI technology, the semiconductor structure is stacked providing multiple layers of junction-free, memory cells, such that it further comprises: a second dielectric layer over the first word lines. A plurality of second parallel semiconductor body regions with a third concentration of the first dopant type overlie the second dielectric layer. A plurality of second parallel word lines are between a third select line and a fourth select line, the second word lines, the third select line and the fourth select line being over and substantially perpendicular to the second semiconductor body regions. A second tunneling barrier, a second charge storage layer and a second dielectric layer are between the second word lines and the second semiconductor body regions. The second semiconductor body regions include at least one third region adjacent to the third select line and the fourth select line and fourth regions between two neighboring second word lines. The fourth regions are characterized with a fourth concentration of the first dopant type. A dimension of the first region is larger than that of the third region.
It is to be noted that in stacked, junction-free embodiments, the bottom layer can be implemented on a SOI substrate, or directly on a semiconductor bulk region, without an overlying layer of insulation.
According to another exemplary embodiment of this technology disclosed herein, a method for forming a semiconductor structure comprises forming a plurality of first parallel semiconductor body regions having a first conductivity type over a substrate. A first select line, a second select line and a plurality of first parallel word lines are formed over and substantially perpendicular to the first semiconductor body regions, the word lines configured between the first select line and the second select line. A first tunneling barrier, a first charge storage layer and a first dielectric layer are formed between the first semiconductor body regions and the word lines. First dielectric spacers are formed on a sidewall of the first select line and a sidewall of the second select line, while forming first dielectric materials between two neighboring word lines. First source/drain (S/D) regions having a second conductivity type are formed adjacent to the first select line and the second select line by using the first dielectric spacers as an implantation mask. A region is formed between two neighboring word lines. The region between neighboring word lines has a second concentration of the first type, wherein the region between two neighboring word lines is substantially junction-free.
According to an exemplary embodiment of this application, a method for operating a semiconductor structure is provided. The semiconductor structure comprises: a plurality of parallel semiconductor body regions over a substrate; a plurality of parallel word lines between a first select line and a second select line, the word lines including a selected word line and a plurality of unselected word lines, the word lines, the first select line and the second select line being over and substantially perpendicular to the semiconductor body regions; and a tunneling barrier, a charge storage layer and a dielectric layer between the word lines and the semiconductor body regions, wherein the semiconductor body regions include at least one first region adjacent to the first select line and the second select line and second regions between two neighboring word lines, wherein the first region has a dopant concentration higher than that of the second regions and wherein at least one of the second regions is junction-free. The method comprises applying a first voltage to the first select line and the second select line; applying a second voltage to the word lines, the first voltage being higher than the second voltage; and applying a third voltage to the semiconductor body regions to reset the semiconductor structure, the third voltage being higher than the second voltage.
As used herein, the phrase “small hole tunneling barrier height” refers generally to values which are less than the approximate hole tunneling barrier height at a silicon dioxide/silicon interface. In particular, a small hole tunneling barrier height is preferably less than about 4.5 eV. More preferably, a small hole tunneling barrier height is less than or equal to about 1.9 eV.
A junction-free TFT NAND device for multiple stackable 3D Flash memory is proposed. The TFT NAND has no diffusion junction (such as N+-doped junction) in the memory array. Diffusion junctions are only fabricated outside the array select transistors BLT and SLT.
An inversion layer will be induced by the wordline fringing field when the space between each wordline is small (for example, a 75 nm node). The junction-free TFT NAND structure avoids the junction punch through after repeating thermal budget. Short-channel effect can be suppressed. Thus this technique enables multiple short stacks of TFT NAND structure, achieving very high density.
3D Flash memory has attracted a lot of attention recently. 3D multiple stacks of memory enables much higher density than the conventional single-layer memory devices.
Traditional doped junction (such as n+ doped junction) has a large lateral diffusion after thermal process. The lateral diffusion is serious for very short channel device. The short-channel effect becomes more serious for a 3D Flash with multiple stacks of TFT NAND devices. The bottom layers have much larger thermal budgets so that lateral diffusion of the junction causes a severe punch through, which seriously degrades the short channel effect performance.
The junction-free NAND described herein enables multiple stacks and junction only diffuses at the array boundary, which offers a large process window to avoid punch-through.
Unlike conventional devices where the junction is formed before the spacers, a method for manufacturing the junction-free TFT NAND includes forming the junction after the spacers between the wordlines are formed. The spacer between each wordline is completely filled without a gap due to the small pitch of the TFT NAND array. Therefore, the junction IMP is blocked by the spacers inside the memory array, and junctions are instead formed outside the array.
In an alternative method one additional mask is introduced which overlays the wordlines and the BLT and SLT, and the junction IMP is carried out.
Simulation results show that an inversion layer can be induced underlying the spacers due to the fringing field from the high electric field on the wordlines, such that there is no need to fabricate n+-doped regions.
The devices described herein also include p-channel TFT NAND, where n-well and P+ junction are used.
The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
In the drawings:
Reference will now be made in detail to the invention and the presently preferred embodiments thereof, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the non-graph drawings are in greatly simplified form and are not to precise scale. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as top, bottom, left, right, up, down, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms used in conjunction with the following description of the drawings should not be construed to limit the scope of the invention in any manner not explicitly set forth in the appended claims. Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of entire integrated circuits. The present invention may be practiced in conjunction with various integrated circuit fabrication techniques that are known in the art or to be developed.
Memory cells in accordance with the present invention can overcome some of the reliability issues in SONOS and NROM devices. For example, memory cell structures in accordance with the present invention may allow fast FN channel erase methods, while at the same time, maintaining good charge retention characteristics. Various embodiments of the memory cells according to the present invention can also alleviate reliance on the BTBTHH erase method, thereby avoiding device degradation after numerous P/E cycles.
One example may employ an ultra-thin tunnel dielectric or ultra-thin oxide layer in conjunction with the small hole tunneling barrier height layer in embodiments where the tunnel dielectric structure is a multilayer structure. This may provide better stress immunity. Non-volatile memory cells according to the present invention also show little degradation after numerous P/E cycles.
Memory cells according to the present invention may employ either an n-channel or a p-channel design, such as shown in
Thus, for example, as depicted in
Charge storage materials such as a silicon nitride layer, HfO2, and Al2O3 may be used as the small hole tunneling barrier height layer in a tunnel dielectric structure. In certain preferred embodiments of the present invention, an efficient charge storage material, such as a silicon nitride can be used as a charge storage layer in the memory device. A blocking oxide that prevents charge loss may serve as an insulating layer, such as a third silicon oxide layer O3. The memory cells according to the present invention also include a gate or gate electrode, such as a polysilicon gate, above the insulating layer. The tunnel dielectric structure, charge storage layer, insulating layer and gate can be formed above the substrate above at least a portion of a channel region, which is defined by and is disposed between a source region and a drain region.
Memory cells according to various embodiments of the present invention comprise a tunnel dielectric structure which can provide fast FN erase speeds of around 10 msec under a negative gate voltage (Vg), such as a Vg of about −10 to about −20 V. On the other hand, the charge retention can still be maintained, and, in some examples, may be better than many conventional SONOS devices. Memory cells according to the present invention can also avoid the use of band-to-band hot hole erase operations, which, are commonly used in NROM devices. Avoidance of such band-to-band hot hole erase operations may greatly eliminate hot-hole introduced damages and such avoidance is therefore desirable.
Referring to
An experiment with measured and simulated hole tunneling currents, as shown in
Memory cell designs in accordance with the present invention may be applied to various memory types, including but not limited to, NOR and/or NAND-type flash memories.
As noted above, a tunnel dielectric layer may include two or more layers, including one layer that may provide a small hole-tunneling-barrier height. In one example, the layer providing a small hole-tunneling-barrier height may contain silicon nitride. The layer may be sandwiched between two silicon oxide layers, thereby forming an O/N/O tunnel dielectric if silicon nitride is used as the intermediate layer. In some preferred embodiments, the bottom layer can have a thickness from about 2 nm or less. The middle and top layers in the tunnel dielectric structure can have a thickness of about 1 nm to 3 nm. In one exemplary device, a tri-layer structure may have a bottom layer, such as a silicon oxide layer, of about 10 Å to 20 Å, an intermediate layer, such as a silicon nitride layer, of about 10 Å to 30 Å, and a top layer, such as another silicon oxide layer, of about 10 Å to 30 Å. In one particular example, an O/N/O tri-layer structure having a 15 Å bottom silicon oxide layer, a 20 Å intermediate silicon nitride layer, and an 18 Å top silicon oxide layer may be used. In one particular example, an O/N/O tri-layer structure having a 13 Å bottom silicon oxide layer, a 25 Å intermediate silicon nitride layer, and an 25 Å top silicon oxide layer may be used.
In one example, a thin O/N/O tri-layer structure shows negligible charge trapping. Theoretical band diagram and tunneling current analysis, such as described with reference to
In certain preferred embodiments, the tunnel dielectric structure includes at least a middle layer and two adjacent layers on opposing sides of the middle layer, wherein each of the middle layer and two adjacent layers comprises a first material and a second material, wherein the second material has a valence band energy level greater than the valence band energy level of the first material and the second material has a conduction band energy level less than the conduction band energy level of the first material; and wherein the concentration of the second material is higher in the middle layer than in the two adjacent layers and the concentration of the first material is higher in the two adjacent layers than in the middle layer. Preferably, in a tunnel dielectric structure in accordance with this embodiment of the present invention, the first material comprises oxygen and/or an oxygen-containing compound and the second material comprises nitrogen and/or a nitrogen-containing compound. For example, the first material can comprise an oxide, such as silicon oxide, and the second material can comprise a nitride, such as Si3N4 or SixOyNz.
Tunnel dielectrics in accordance with this aspect of the invention may be comprised of three or more layers, all of which can contain similar elements (such as Si, N and O), so long as the concentration of the material having the smallest hole tunneling barrier height is higher within the middle layer than in the two adjacent layers.
In certain tunnel dielectric structures according to the preceding embodiment of the present invention, the second material can be present in the middle layer in a gradient concentration such that the concentration of the second material in the middle layer increases from one adjacent layer/middle layer interface to a maximum concentration at a depth point within the middle layer, and decreases from the maximum concentration depth point to a lower concentration at the other adjacent layer/middle layer interface. The increase and decrease in concentration is preferably gradual.
In still other embodiments of the present invention, the tunnel dielectric structure includes at least a middle layer and two adjacent layers on opposing sides of the middle layer, wherein the two adjacent layers comprise a first material and the middle layer comprises a second material, wherein the second material has a valence band energy level greater than the valence band energy level of the first material and the second material has a conduction band energy level less than the conduction band energy level of the first material; and wherein the second material is present in the middle layer in a gradient concentration such that the concentration of the second material in the middle layer increases from one adjacent layer/middle layer interface to a maximum concentration at a depth point within the middle layer, and decreases from the maximum concentration depth point to a lower concentration at the other adjacent layer/middle layer interface. The increase and decrease in concentration is preferably gradual. Preferably, in a tunnel dielectric structure in accordance with this embodiment of the present invention, the first material comprises oxygen and/or an oxygen-containing compound and the second material comprises nitrogen and/or a nitrogen-containing compound. For example, the first material can comprise an oxide, such as silicon oxide, and the second material can comprise a nitride, such as Si3N4 or SixOyNz.
For example, in embodiments of the present invention where the tunnel dielectric layer comprises a tri-layer ONO structure, the bottom oxide and top oxide layers can comprise silicon dioxide and the middle nitride layer can be comprised of, for example, silicon oxynitride and silicon nitride wherein the concentration of silicon nitride (i.e., the material having the smaller hole tunneling barrier height of the two) is not constant within the layer, but rather reaches a maximum at some depth point within the layer between the two interfaces with the sandwiching oxide layers.
The precise point within the middle layer where the material with the smallest hole tunneling barrier height reaches its maximum concentration is not critical, so long as it is present in a gradient and reaches its maximum concentration in the tunnel dielectric layer at some point within the middle layer.
The gradient concentration of the material having the smallest hole tunneling barrier height can be advantageous in improving various properties of non-volatile memory devices, particularly those having a SONONOS, or SONONOS-like structure. For example, retention state charge loss can be diminished, hole tunneling under high electric fields can be improved and, to the extent it may occur, charge-trapping in the tunnel dielectric can be avoided.
The band diagram of a tunnel dielectric layer can be advantageously modified in accordance with this aspect of the present invention such that the valence band energy level and the conduction band energy level of the middle layer do not have a constant value, but rather vary across the thickness of the layer with the concentration of the material having the smallest hole tunneling barrier height. Referring to
Multi-layer tunnel dielectric structures in accordance with such embodiments of the present invention, can be prepared in a variety of ways. For example, a first silicon dioxide or silicon oxynitride layer can be formed using any number of conventional oxidation approaches including, but not limited to thermal oxidation, radical (ISSG) oxidation, and plasma oxidation/nitridation, as well as chemical vapor deposition processes. A middle layer with a gradient concentration of SiN can then be formed, for example, via chemical vapor deposition processes, or alternatively, by plasma nitridation of excess oxide or oxynitride formed on top of the first layer. A third layer, the upper oxide layer, can then be formed, for example, by oxidation or chemical vapor deposition.
A charge storage layer can then be formed over the tunnel dielectric structure. In one example, a charge storage layer of about 5 nm to 10 nm may be formed over the tunnel dielectric structure. In one particular example, a silicon nitride layer of about 7 nm or thicker may be used. The insulating layer above the charge storage layer may be about 5 nm to 12 nm. For example, a silicon oxide layer of about 9 nm or thicker may be used. And the silicon oxide layer may be formed by a thermal process converting at least a portion of a nitride layer to form the silicon oxide layer. Any method, known or to be developed, for forming layers of suitable materials described herein can be used to deposit or form tunnel dielectric layers, charge-storage layers and/or insulating layers. Suitable methods include, for example, thermal growth methods and chemical vapor deposition methods.
In one example, a thermal conversion process may provide a high density or concentration of interfacial traps that can enhance the trapping efficiency of a memory device. For example, thermal conversion of nitride can be carried out at 1000, while the gate flow ratio is H2:O2=1000:4000 sccm.
In addition, because silicon nitride generally has very low (about 1.9 eV) hole barrier, it may become transparent to hole tunneling under high field. Meanwhile, the total thickness of a tunnel dielectric, such as an ONO structure, may prevent direct tunneling of electrons under a low electric field. In one example, this asymmetrical behavior may provide a memory device offering not only fast hole-tunneling erase, but also reduction or elimination of charge leakage during retention.
An exemplary device may be fabricated by 0.12 μm NROM/NBit technologies. Table 1 shows the device structure and parameters in one example. The proposed tunnel dielectric with an ultra-thin O/N/O may alter the hole tunneling current. A thicker (7 nm) N2 layer may serve as a charge-trapping layer and an O3 (9 nm) layer may serve as the blocking layer in one example. Both N2 and O3 may be fabricated using NROM/NBit technologies.
TABLE 1
Layer
Approximate Thickness (Angstroms)
Bottom Oxide (O1)
15
Inter Nitride (N1)
20
Inter Oxide (O2)
18
Trapping Nitride (N2)
70
Blocking Oxide (O3)
90
Gate: N+-polysilicon
Channel length: 0.22 μm
Channel width: 0.16 μm
In certain embodiments of the present invention, a gate can comprise a material having a work function greater than that of N+ polysilicon. In certain preferred embodiments of the present invention, such a high work function gate material can comprise a metal such as, for example, platinum, iridium, tungsten, and other noble metals. Preferably, the gate material in such embodiments has a work function greater than or equal to about 4.5 eV. In particularly preferred embodiments, the gate material comprises a high work function metal such as, for example, platinum or iridium. Additionally, preferred high work function materials include, but are not limited to P+ polysilicon, and metal nitrides such as, for example, titanium nitride and tantalum nitride. In particularly preferred embodiments of the present invention, the gate material comprises platinum.
An exemplary device in accordance with an embodiment of the present invention having a high work function gate material may also be fabricated by 0.12 μm NROM/NBit technologies. Table 2 shows the device structure and parameters in one example. The proposed tunnel dielectric with an ultra-thin O/N/O may alter the hole tunneling current. A thicker (7 nm) N2 layer may serve as a charge-trapping layer and an O3 (9 nm) layer may serve as the blocking layer in one example. Both N2 and O3 may be fabricated using NROM/NBit technologies.
TABLE 2
Layer
Approximate Thickness (Angstroms)
Bottom Oxide
15
Inter Nitride
20
Inter Oxide
18
Trapping Nitride (N2)
70
Blocking Oxide
90
Gate: Platinum
Channel length: 0.22 μm
Channel width: 0.16 μm
Memory cells in accordance with high work function gate material embodiments of the present invention exhibit erase properties which are even more improved over other embodiments. High work function gate materials suppress gate electron injection into the trapping layer. In certain embodiments of the present invention wherein the memory cells comprise an N+ polysilicon gate, hole tunneling into the charge-trapping layer during erase occurs simultaneously with gate electron injection. This self-converging erase effect results in higher threshold voltage levels in the erased state, which can be undesirable in NAND applications. Memory cells in accordance with high work function gate material embodiments of the present invention can be used in various type of memory applications including, for example, NOR- and NAND-type memories. However, the memory cells according to high work function gate material embodiments of the present invention are particularly suitable for use in NAND applications where elevated threshold voltages in the erased/reset state can be undesirable. Memory cells in accordance with high work function gate material embodiments of the present invention can be erased via hole tunneling methods and preferably via −FN erasing operations.
An exemplary device having an ONO tunneling dielectric and an N+ polysilicon gate may be programmed by conventional SONOS or NROM method and erased by channel FN hole tunneling.
In accordance with certain embodiments of memory cells of the present invention having high work function gate materials, wherein the high work function gate suppresses gate electron injection, the threshold voltage of the device in an erased or reset state can be much lower, and even negative, depending upon erase time. The threshold voltage values of a memory device in accordance with one embodiment of the present invention wherein the gate is comprised of platinum and the tunnel dielectric layer comprises a 15/20/18 angstrom ONO structure are shown in
Moreover, retention properties of memory devices in accordance with high work function gate material embodiments the present invention are improved. The retention properties of a memory device having a platinum gate are shown in
Memory cells in accordance with various embodiments of the present invention may be operated with at least two separate schemes. For example, CHE programming with reverse read (mode 1) may be used to perform a 2-bits/cell operation. Additionally, low-power +FN programming (mode 2) may also be used for a 2-bits/cell operation. Both modes can use the same hole tunneling erase method. Mode 1 may preferably be used for a virtual ground array architecture for NOR-type flash memories. Mode 2 may preferably be used for NAND-type flash memories.
As an example,
The charge retention of an exemplary SONONOS device in accordance with one embodiment of the present invention is shown in
Accordingly, the SONONOS design identified in the above examples may provide a fast hole tunneling erase with excellent endurance properties. As noted above, the design may be implemented in both NOR and NAND-type nitride-storage flash memories. Additionally, a memory array in accordance with the present invention may include multiple memory devices with similar or different configurations.
In various embodiments of arrays according to the present invention, memory cells according to the present invention may be used in place of conventional NROM or SONOS devices in a virtual ground array architecture. The reliability problems and erase degradations may be solved or mitigated by using FN hole tunneling instead of hot-hole injection. Without limiting the scope of the invention to the specific structures described below, various operation methods in accordance with memory arrays of the present invention are described below for exemplary NOR virtual ground array architectures.
CHE or CHISEL (channel initiated secondary electron) programming and reverse read may be used for 2-bit/cell memory array. And the erase method may be a uniform channel FN hole tunneling erase. In one example, the array architecture may be a virtual ground array or a JTOX array. With reference to
In addition,
Alternatively, referring to
However, the convergent Vt is also higher. This is because gate injection is more active under higher gate voltages. To reduce gate injection, P+-polysilicon gate or other metal gate with a high work function may be used alternatively as the gate material to reduce the gate-injected electrons during the erase.
As noted above, memory cell structures in accordance with the present invention are suitable for both NOR- and NAND-type flash memories. The following will describe additional examples of memory array designs and their operation methods. Without limiting the scope of the invention to the specific structures described below, various operation methods in accordance with memory arrays of the present invention are described below for exemplary NAND architectures.
As noted above, n-channel SONONOS memory devices having an ONO tunneling dielectric may be used in a memory device.
In addition to the single-block gate structure design, a split-gate array, such as a NAND array using SONONOS devices positioned between two transistor gates which are located next to the source/drain regions, may also be used. In some examples, a split-gate design may scale down device dimension to F=30 nm or below. Furthermore, the devices may be designed to obtain good reliability, to reduce or eliminate the inter-floating-gate coupling effect, or to achieve both. As discussed above, an SONONOS memory device may provide excellent self-converging, or high speed erase, which may help sector-erase operations and Vt distribution control. Furthermore, a tightened erased state distribution may facilitate multi-level applications (MLC).
By using certain designs for a memory array structure, the effective channel length (Leff) may be enlarged to reduce or eliminate short-channel effects. Some examples may be designed to use no diffusion junctions, thereby avoiding the challenges in providing shallow junctions or using pocket implantations during the manufacturing processes of memory devices.
Referring again to
In some examples, the gate voltages applied to BLTs and SLTs may be less than 10 V, which may cause less gate disturb. In cases where the gate dielectric layer of BLTs and SLTs may be charged or trapped with charges, additional −Vg erase can be applied to the gates of BLT or SLT to discharge their gate dielectric layers.
Referring again to
In examples of manufacturing a memory array, such as the arrays noted above, the processes may involve using only two primary masks or lithography processes, such as one for the polysilicon (word line) and another for STI (bit lines). In contrast, the manufacturing of NAND-type floating gate devices may require at least two-poly processing and another inter-poly ONO processing. Accordingly, the structure and manufacturing processes of the proposed devices may be simpler than those of NAND-type floating gate memories.
Referring to
In examples where STI is used of isolating separate memory devices, the trench depth of STI regions may be larger than the depletion width in p-well, especially when the junction bias used is raised higher. For example, the junction bias may be as high as about 7V for program inhibited bit line(s) (unselected bit line(s) during programming). In one example, the depth of STI regions may be in the range of about 200 to 400 nm.
After a memory array is manufactured, a reset operation may be performed to tighten the Vt distribution first before other operations of the memory array.
Generally, traditionally floating-gate devices are not capable of providing self-converging erase. In contrast, SONONOS devices may be operated with converging Reset/Erase methods. In some examples, this operation may become essential because the initial Vt distribution is often in a wide range due to certain process issues, such as process non-uniformity or plasma charging effects. The exemplary self-converging “Reset” may help to tighten, or narrow the range of, the initial Vt distribution of memory devices.
In one example of programming operations, the selected WL may be applied with a high voltage, such as a voltage of about +16 V to +20 V, to induce channel +FN injection. Other PASS gates (other unselected WL's) may be turned on to induce the inversion layer in a NAND string. +FN programming may be a low-power method in some examples. In one example, parallel programming methods such as page programming with 4K Bytes cells in parallel can burst the programming throughput to more than 10 MB/sec, while the total current consumption can be controlled within 1 mA. In some examples, to avoid program disturb in other BLs, a high voltage, such as a voltage of about 7 V may be applied to other BLs so that the inversion layer potential is raised higher to suppress the voltage drop in the unselected BLs (such as cell B in
In examples of read operations, the selected WL may be raised to a voltage that is between an erased state level (EV) and a programmed state level (PV). Other WLs may serve as the “PASS gates” so that their gate voltages may be raised a voltage higher than PV. In some examples, erase operations may be similar to the reset operation noted above, which may allow self-convergence to the same or similar reset Vt.
In particular, for cell A, which is the cell selected for programming, the voltage drop is about +18 V, which causes +FN injection. And the Vt may be raised to PV. For cell B, the voltage drop is +11 V, causing much less +FN injection, as FN injection is sensitive to Vg. For cell C, only +10 V is applied, causing no or negligible +FN injection. In some examples, a programming operation is not limited to the technique illustrated. In other words, other adequate program inhibit techniques may be applied.
In some examples, the pass gate voltage for other WLs should be higher than the high-Vt state or the programmed state Vt, but not too high to trigger gate disturb. In one example, the PASS voltage is in the range of about 7 to 10 V. The applied voltage at the BL may be about 1 V. Although a larger read voltage may induce more current, the read disturb may become more apparent in some examples. In some examples, the sensing amplifier can be either placed on a source line (source sensing) or on a bit line (drain sensing).
Some examples of NAND strings may have 8, 16, or 32 memory devices per string. A larger NAND string may save more overhead and increase array efficiency. However, in some examples, the read current may be smaller and disturb may become more apparent. Therefore, adequate numbers of NAND string should be chosen based on various design, manufacture, and operation factors.
In some examples, a split-gate design, such as a split-gate SONONOS-NAND design, may be used to achieve a more aggressive down-scaling of a memory array.
Referring again to
In one example, the space Ls between neighboring memory devices along the same bit line may be in the range of about 15 nm to about 30 nm. As noted above, the effective channel length may be enlarged to 2F−Ls in this example. In one example, if F is about 30 nm and Ls is about 15 nm, Leff is about 45 nm. For the operation of those exemplary memory devices, the gate voltage may be reduced to below 15 V. In addition, the inter-polysilicon voltage drop between word lines may be designed to be no larger than 7V to avoid breakdown of the spacers in the Ls spaces. In one example, this may be achieved by having an electric field of less than 5 MV/cm between neighboring word lines.
The Leff with diffusion junctions for conventional NAND floating-gate devices is about half of the their gate length. In contrast, if F is about 50 nm and Leff is about 30 nm, Leff is about 80 nm for the proposed design (the split-gate NAND) in one example. The longer Leff can provide better device characteristics by reducing or eliminating the impact of short-channel effects.
As illustrated above, a split-gate NAND design may further shrink the space (Ls) between neighboring memory cells of the same bit line. In contrast, traditional NAND-type floating-gate devices may not provide a small spacing, because inter-floating-gate coupling effect may lose the memory window The inter-floating gate coupling is the interference between adjacent memory cells when the coupling capacitance between adjacent floating gate is high (the space between the floating gates is small so that the coupling capacitance between the adjacent floating gates becomes very high such that read disturb happens). As noted above, the design may eliminate the need to fabricate certain diffusion junctions, and the inversion layer can be directly connected if all the word lines are turned on. Therefore, the design may simplify the manufacturing process of memory devices.
A multi-layer SONOS device is described using and ultra-thin ONO tunneling dielectric. With an n+ polysilicon gate, a self-convergent positive erase threshold voltage of for example about +3 V is achieved suitable for a NOR architecture, in which channel hot electron programming can be applied for storing two-bits per cell, read using the standard reverse read method, and erased with hole tunneling erase apply electric field assisted FN tunneling with a gate voltage of for example −15 volts. With a p+ polysilicon (or other high work function material) gate, a depletion mode device can be obtained having an erase threshold voltage less than zero, with a very large memory window with a program threshold voltage over about 6 volts can be achieved, suitable for NAND architecture using electric field assisted FN electron tunneling for program and electric field assisted FN hole tunneling for erase operations, with a gate voltage during erasing of for example −18 Volts.
For NAND applications, a depletion mode device (VT<0) for the erased state is desired. By using a P+-poly gate, the gate injection is reduced and the device can be erased into depletion mode as shown in
As illustrated, some examples noted above, including the structural design, array design, and operation of memory devices, may provide desirable array dimension, good reliability, good performance, or the combination of any of them. Some examples noted may be applicable for down-scaling the dimensions of non-volatile flash memories, such as NAND flash memories and flash memory for data applications. Some examples may provide SONONOS devices with uniform and high speed channel hole-tunneling erase. Some examples also may provide good endurance of memory devices and reduce certain no hard-to-erase or over-erase issues. Also, good device characteristics, such as small degradations after P/E cycles and good charge retention, may be provided. Device uniformity within a memory array may be provided without having erratic bits or cells. Furthermore, some examples may provide good short-channel device characteristics via a split-gate NAND design, which may offer a better sense margin during the operations of the memory devices.
The substrate 401 may be a silicon substrate, a III-V compound substrate, a silicon/germanium (SiGe) substrate, an epi-substrate, a silicon-on-insulator (SOI) substrate, a display substrate such as a liquid crystal display (LCD), a plasma display, an electro luminescence (EL) lamp display, or a light emitting diode (LED) substrate, for example. For silicon on insulator SOI embodiments, the substrate 401 includes at least one insulating dielectric layer such as dielectric layer 405 (shown in
Referring again to the embodiment shown in
In the illustrated embodiment, the portion of the memory array 400 includes a plurality of parallel isolation trench structures 430 adjacent to the semiconductor body regions 410, and between two neighboring semiconductor body regions 410.
Referring again to
The top oxide process has the largest thermal budget. Two top oxide (O3) formation processes are representative, including an LPCVD oxide (HTO) with rapid thermal annealing, and an in-situ steam generation (ISSG) oxidation to convert a portion of the trapping nitride (N2) into oxide. Lower thermal budget processes are preferred to reduce dopant diffusion from the select gate junctions. However, the ISSG process may result in better endurance characteristics, as we reported in Lai, et al. “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory”, International Electron Devices Meeting, IEDM, December, 2006, which article is incorporated by reference as if fully set forth herein. Planarization is then carried out by, for example, HDP oxide deposition and Chemical Mechanical Polishing. After forming the bottom-layer TFT devices, the processes are repeated to form a second and subsequent layers of TFT devices. Contact etching for the multiple layers can be performed independently to avoid over etching.
Referring again to
Each of the select lines 420a, 420b includes a gate insulator 331 and a conductive layer 336. The gate insulator 331 may be an oxide layer, a nitride layer, an oxynitride layer, high-k dielectric layer, other dielectric material layer or various combinations thereof. The conductive layer 336 may be, for example, a polysilicon layer, an amorphous silicon layer, a metal-containing layer, a tungsten silicide layer, a copper layer, an aluminum layer or other conductive material layer. The conductive layer 335 may be formed by, for example, a CVD process, a physical vapor deposition (PVD) process, an electroplating process and/or an electroless plating process.
Each of the word lines 420c may include the tunneling barrier 310, the charge storage layer 320, the dielectric layer 330 and the conductive layer 335. In some embodiments, the tunneling barrier 310, the charge storage layer 320, the dielectric layer 330 and the conductive layer 335 may be sequentially formed over the semiconductor body region 410.
The tunneling barrier 310 may allow charges, i.e., holes or electrons, tunneling from the semiconductor body regions 410 to the charge storage layer 320 during an erase operation and/or a reset operation. The tunneling barrier 310 may be an oxide layer, a nitride layer, an oxynitride layer, other dielectric layer, or various combinations thereof. In some embodiments, the tunneling barrier 310 may include a first oxide layer (not labeled), a nitride layer (not labeled) and a second oxide layer (not labeled) which are referred to as an ONO structure. In some embodiments, the first oxide layer may be an ultra-thin oxide which may have a thickness of about 2 nm or less. In another embodiment, the first oxide layer may have a thickness of about 1.5 nm or less. In other embodiments, the first oxide layer may have a thickness between about 0.5 nm and about 2 nm. The ultra-thin oxide layer may be formed, for example, by an in-situ steam generation (ISSG) process. The process for forming the nitride layer may use, for example, DCS and NH3 as precursors with a processing temperature at about 680. In some embodiments, the nitride layer may have a thickness of about 3 nm or less. In other embodiments, the nitride layer may have a thickness between about 1 nm and about 2 nm. The second oxide layer may be formed by, for example, a LPCVD process. In some embodiments, the second oxide layer may have a thickness of about 3.5 nm or less. In another embodiment, the second oxide layer may have a thickness of about 2.5 nm or less. In other embodiments, the second oxide layer may have a thickness between about 2.0 nm and about 3.5 nm.
The charge storage layer 320 may store charges such as electrons or holes therein. The charge storage layer 320 may be, for example, a nitride layer, an oxynitride layer, a polysilicon layer or other material layer that may desirably store charges. In some embodiments for forming a nitride charge storage layer, the process may use, for example, dichlorosilane DCS and NH3 as precursors with a processing temperature at about 680. In other embodiments for forming an oxynitride charge storage layer, the process may use, for example, DCS, NH3 and N2O as precursors. In some embodiments, the charge storage layer 320 may have a thickness of about 5 nm or more, for example, about 7 nm.
The dielectric layer 330 may isolate the conductive layer 335 from the charge storage layer 330. The dielectric layer 330 may be, for example, an oxide layer, a nitride layer, an oxynitride layer, an aluminum oxide layer, other dielectric materials or various combinations thereof. In some embodiments, the process for forming the dielectric layer 330 may convert a portion of the charge storage layer 320 such as a nitride layer so as to form the dielectric layer 330. The process may be a wet conversion process using O2 and H2O gas in furnace at a temperature between about 950 and about 1,000 For example, a nitride layer having a thickness of about 13 nm may be converted into the dielectric layer 330 having a thickness of about 9 nm and the remaining nitride layer, i.e., the charge storage layer 320, having a thickness of about 7 nm. The wet conversion process is applied for a small initial part of the layer, followed by deposition of the balance of the layer by lower thermal budget processes for deposition of silicon dioxide, such as a high temperature oxide HTO process or an in situ steam generation ISSG process. In still other embodiments, the dielectric layer 330 is formed over the charge storage layer 320 without a wet conversion process. Various thicknesses of the tunneling barrier 310, the charge storage layer 320 and the dielectric layer 330 may be used to form a desired structure.
The conductive layer 335 may be, for example, a polysilicon layer, an amorphous silicon layer, a metal-containing layer, a tungsten silicide layer, a copper layer, an aluminum layer or other conductive material layer, and combinations of layers of materials. The conductive layer 335 may be formed by, for example, a CVD process, a physical vapor deposition (PVD) process, an electroplating process and/or an electroless plating process. In some embodiments, the conductive layers 335 and 336 can be formed by the same process. In some embodiments, the structure including the tunneling barrier 310, the charge storage layer 320 and the dielectric layer 330 may be referred to as a bandgap engineered SONOS (BE-SONOS) structure.
Referring again to
Referring to
Referring again to
Referring again to
It is noted that the exemplary structure of
Reset
In some embodiments, a reset operation may be performed to tighten the Vt distribution first before other operations of the memory array. For example, voltages are applied to and turn on the select lines 420a and 420b. Prior to other operations, a voltage of about −7 V may be applied to the word lines 420c-420e and a voltage of about +8 V may be applied to the semiconductor body region 410 as shown in
Programming
In some embodiments for programming cells of the memory array, a high voltage, e.g. between about +16 V and about +20 V, may be applied to word line 420c to induced channel +FN injection. In some embodiments, the high voltage is about +18 V. A voltage, such as about +10 V, may be applied to other pass gates, i.e., unselected word lines 420d and 420e to induce inversion layers in the NAND string. Semiconductor body region 410 is substantially grounded. Charges, such as electrons, can be injected into the charge storage layer of word line 420c. In some embodiments, the +FN programming may be a low-power programming. In some embodiments, parallel programming methods, such as page programming method with 4 K Bytes cells may desirably increase the programming throughput to more than 10 MB/sec. The total current consumption can be about 1 mA or less. In some embodiments, a voltage, such as about 7 V, may be applied to other bit lines to avoid program disturb. The voltage applied to the bit lines may raise the potential of the inversion layer to suppress the voltage drop in the unselected bit lines.
Erasing
In some embodiments, the erasing operation may be similar to the reset operation. A voltage of about −7 V may be applied to the word lines 420c and a voltage of about +8 V may be applied to the semiconductor body region 410 as shown in
Read
In some embodiments for reading the memory array, the selected word line may be raised to a voltage, such as about +5 V that is between an erased state level (EV) and a programmed state level (PV) of a memory cell. Other unselected word lines may serve as the “PASS gates” so that their gate voltages may be raised a voltage higher than PV. In some embodiments, the voltage applied to the pass gates is about +9 V. In some embodiments, a voltage of about +1 V is applied to the semiconductor body region 410.
The structures and methods for forming the structures described above in conjunction with
Following are descriptions of exemplary junction-free BE-SONOS devices. In some embodiments, the device has a poly pitch of about 0.15 um. After patterning the hard mask of poly, an oxide liner can be formed to fill-in the poly space, e.g., about 70 nm or more, followed by the poly etching to define the final poly space. It is found that the device may be free from abnormal poly short or line-end breaking. The narrow space (S) between the sidewalls of the oxide liner can be accurately controlled by the liner oxide thickness.
The conventional junction implantation can be performed after the poly etching. In embodiments of junction-free devices, shallow junction can be saved and spacers can be kept. Oxide spacer can be fill-in the narrow space between word lines. A tilt-angle implantation can be carried out to form the junction outside and adjacent to the array. Due to the thick poly gate blocking the implantation, the array center is not subjected to the tilt-angle implantation and is junction-free. It is noted that this process is desirably compatible with conventional NAND process. No additional mask is required.
Following are the descriptions of electrical characteristics of junction-free devices. The devices are configured with a 16-WL NAND array. The ONONO structure, e.g., O1/N1/O2/N2/O3, has dimensions of about are 13/20/25/60/60 Å, respectively. Å
For the p-channel NAND, the program/erase voltage polarity should be opposite to that of the n-channel NAND.
The foregoing disclosure of the preferred embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.
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