Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion

Abstract

A method An apparatus and system for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H_snyc) (H_sync) that controls a line scan rate, and a vertical synchronizing signal (V_snyc) (V_sync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W.

Description

Mhz MHz clocks per twenty lines, and number of lines per frame. An exemplary look-up table showing a few common non-interlaced 60 Hz video modes is as follows:

TABLE 1
	Number of
	50 MHz
	Clocks/20			Pixel Clocks/
Ysync (Hz)	lines	Lines/Frame	Resolution	Line (n)
60 Hz	31778	525	640 × 480	800
60 Hz	24400	628	800 × 600	1056
60 Hz	20677	806	1024 × 768	1344
60 Hz	15631	1066	1280 × 1024	1696

Thus, for exemplary values of 31778 50 MHz clocks in twenty lines, and 525 lines per frame, the look-up table determines a resolution of 640×480 with a number n of pixel clocks per line of 800. The expected width (in pixels) of the active video region 11 (see FIG. 1d) is initially set at the horizontal component of the resolution (e.g. 640).

It is to be understood that such number n is an initial guess, and that a range of initial n values will work, due to the iterative corrective nature of the present invention. Accordingly, n may be determined in other ways, such as by multiplying the horizontal resolution by a constant slightly larger than 1.0. It is also to be understood that the preferred look-up table will cover modes from 640×480 to 1600×1200 resolution, and from 60 Hz to 100 Hz frame refresh rates. Moreover, other ways of determining the resolution are possible, such as by using the number of lines per frame to determine the vertical and horizontal resolution.

Digitization of the analog video data signals occurs based on the n pixel clocks per line. Referring to the PLL 20, the VCO 50 generates the pixel clock signal, and the microcontroller 16 sets the counter 22 to generate a feedback pulse (i.e. line advance signal) once every n pixel clocks. Once n is selected, the PLL automatically adjusts to produce a line advance signal frequency corresponding to H_sync, and a pixel clock signal having a frequency of n times the line advance frequency.

The PLL works by the phase comparator 46 receiving the H_sync, signal from the delay device 18 through conductor 44, and receiving the feedback pulse signal through the feedback loop 52. The phase comparator 46 compares the frequencies of the H_sync and the feedback pulse signal, generating an output voltage that is a measure of their phase difference. If the feedback pulse frequency does not equal the H_sync frequency, the phase difference signal causes the VCO pixel clock frequency to deviate so that the feedback pulse frequency of the counter 22 deviates toward the H_sync frequency.

The feedback pulse signal (line advance signal) of the counter 22 is directed to the ASIC 26 through a conductor 53, and the pixel clock signal of the VCO 50 is directed to the ASIC 26 and the A/D converter 24 through conductor 54. The line advance signal and V_sync are conditioned to be one clock pulse in duration, through the use of a pulse edge detection circuit or the like.

The A/D converter 24 samples (reads) the instantaneous voltage value of the analog video data signal at the leading edge of each of the pixel clocks, thereby generating a series of sampled data signal values. The A/D converter then quantizes the sampled values by matching each value to one of a series of preselected voltage amplitude levels, which have corresponding numerical values. These numerical values are then represented digitally and coded to establish 8-bit data for each of the colors red, green and blue. The three eight-bit color data signals are input through the three respective color data signal channels 56a, 56b, 56c to the edge detection circuit 26. At the LCD, the coded color data signal set pixels at blank (black) or specific activated (non-black) status corresponding to the sampled voltage level.

The actual width W of the active video region 11 (FIG. 1d) is then determined by the image edge detection circuit shown in FIG. 4. The actual width W is measured in number of pixel clocks equal to: ((the right-most active pixel in a frame)−(the left most-active pixel in a frame)+1). Thus, W is a measure of the total number of pixels across the active video region of a frame of video data. The pixel clock positions referred to in the following are the sampling positions of pixel clocks along the lines of analog video data in a frame.

The PIXCOMP compares the threshold value with the value of each pixel of the pixel data signal, and generates a binary “yes” if the pixel value is greater than the threshold value. The pixel value calculator 97 determines the value of each pixel by grouping the twenty-four total bits of each pixel together in eight groups of individual red, green and blue bits. Each of these groups of three bits is passed through the “OR” gate 99a, and the results of all of the eight “ored” groups and the digital RGB data signals are multiplexed in the 4:1 multiplexer 99b to establish a value for each pixel. It is contemplated that the pixel value may be set in various other ways, including setting a separate value for one or each of the RGB digital data signals.

The pixel value is compared against a selected threshold value at the PIXCOMP. If the sum is greater than the threshold value, a binary “yes” signal is delivered to the LGATE and RGATE, designating the pixel as active. If the pixel value sum is less than the threshold value, the PIXCOMP generates a binary “no”, indicating the pixel as inactive.

The LCOMP compares the instantaneous pixel position generated by the HPC with a pixel position stored in the LEFT REG. At the beginning of each frame, the LEFT REG is preferably initialed at the far right pixel position of the video region (i.e., the right edge of the inactive margin region 13 in FIG. 1d). The LCOMP outputs a binary “yes” to the LGATE when the instantaneous HPC pixel position is less than the pixel position stored in the LEFT REG. When the PIXCOMP is simultaneously outputting a “yes”, the LGATE signals the LEFT REG through the LLOAD input 120 to replace the stored LEFT REG pixel position with the instantaneous HPC pixel position.

Similarly, the RCOMP compares the instantaneous pixel position generated by the HPC with a pixel position stored in the RIGHT REG. At the beginning of each frame, the RIGHT REG is preferably initialed at the far left pixel position of a video region (i.e., the left edge of the inactive margin region 13 in FIG. 1d). Referring again to FIG. 4, the RCOMP outputs a binary “yes” to the RGATE when the instantaneous HPC pixel position is greater than the pixel position stored in the RIGHT REG. When the PIXCOMP is simultaneously outputting a “yes”, the RGATE signals the RIGHT REG through the RLOAD input to update the stored RIGHT REG pixel position with the instantaneous HPC pixel position.

At the end of each frame, V_sync signals the LEFT STATUS and RIGHT STATUS to update the respective stored left edge and right edge pixel positions. The stored left and right pixel positions are then read by the microcontroller, and the actual width W (in pixels) of the active video region 11 of the frame 9 (FIG. 1d) is calculated by subtracting the left edge pixel position stored in LEFT STATUS from the right edge pixel position stored in RIGHT STATUS.

Once the actual width W is determined, the microcontroller compares it with the expected width E. If E=W, then the clock phase and the number n of clocks per line is correct. In other words, at E=W, each discreet discrete data region (plateau) of the analog video data signal is aligned with and sampled by a pixel clock, resulting in error-free digitization of the analog video data signal. In this case, n and the pixel clock phase are left unchanged for the scanning of the next frame.

If W>E+1 or W<E, then the number n of clocks per line is incorrectly set, resulting in tracking error. To correct such tracking error, a the number n of pixel clocks is adjusted to a new number n′=n·(E/W). The original n is replaced by the adjusted n′, and the next frame is scanned as set forth above. Such adjustment of n is iteratively repeated every frame until W=E or W=E+1. Put another way, if the actual width W is larger than the expected width E, the number of pixel clocks n per line is decreased, (i.e. the period of each pixel clock is increased, and the frequency of the pixel clock signal is decreased), so that the width of the E pixel clocks is effectively spread out to precisely register with the active pixel data region. Conversely, if the actual width W is smaller than the expected width E, the number of pixel clocks n per line is increased, so that the width of the E pixel clocks is effectively contracted to register precisely with the active pixel data region of the analog video data signal.

Once the tracking error is corrected, any phase error is corrected. As discussed above, if W=E, the number of pixel clocks n per line is correctly configured, and no phase error exists. However, if W=E+1, phase error is present, resulting in noise in the video display. Referring to FIG. 1, phase error occurs because of the “jitter” zones present in the leading and trailing edges of clock pulses. Even if the pixel clock signal frequency is equal to the analog video data signal frequency, phase error noise will occur if the jitter zone on the leading edge of the pixel clock waveform overlaps with a transition zone on either side of plateau regions of the analog video data waveform.

To correct the phase error when W=E+1, microcontroller signals the programmable delay to adjust the pixel clock signal phase by a selected iterative amount for each of a series of subsequent frames. The pixel clock phase iteration proceeds until the frame phase error condition passes from W=E+1 through a subseries of frames without phase error (i.e. W=E), and back to a frame with a phase error condition of W=E+1. The resulting series of W values is stored in the microcontroller. The stored series of W values are then examined to identify the subseries of consecutive frames in which W=E. A phase corrected frame in the center of the subseries is then selected, and the programmable delay is signaled to set the pixel clock phase at the phase of the phase corrected frame. Thus, the phase is set so that the pixel clock leading edges are located in the middle of the analog video signal pixel components, in order to consistently avoid sampling in transition regions.

The digital video signals output from the video capture circuit 14 are manipulated by the WRAM 132 and LCD control module 134 to appropriately control the LCD 28. For instance, the WRAM and LCD control module may “flip” the digital video signals as appropriate for different multimedia display system 10 applications, such as front lighting and back lighting of a display screen. The WRAM and LCD control module may also serve to manipulate interlaced video modes into noninterlaced form appropriate for controlling the LCD.

It is also noteworthy that the method and apparatus of the present invention can be used to properly horizontally position the active video region 11 (FIG. 1d) on the LCD. In this application, the value of LEFT STATUS may be used to determine when video data begins to be stored by the WRAM 132. Thus, no data is stored for the blanked margins on either side of the active video region, eliminating the possible possibility that spuriously activated analog pixel components in the blanked margin region will be transferred to the LCD.

EXAMPLE

An exemplary image edge detection method will now be described in conjunction with the exemplary screen image shown in FIG. 6. The determination of the actual image width W for a single frame will be described, with the assumption that that the original image has a resolution of 640×480. Referring to the look-up table, the number of lines/frame is 525, and n is 800. In this example, the pixel position will be designated by Cartesian coordinates corresponding to the horizontal line position and vertical line of the pixel.

The exemplary screen image 140 is a diamond-shape 142 above a horizontal menu bar 144. A margin of blanked pixels 146 (bounded by a dashed line) extends along the sides and the top and bottom of the active image region 148. The diamond has an upper point at horizontal pixel position 400, 20. The diamond widens to a pair of side points on the same horizontal pixel line at respective pixel positions 200, 300 and 600, 300. The diamond has a lower point at horizontal pixel position 400, 475. The menu bar immediately below the diamond has upper left and right edges at horizontal pixel positions 80, 475 and 720, 475 respectively.

Prior to imaging, the LEFT REG is initialized at 800 and the RIGHT REG is initialized at 0. The frame scan begins with blanked pixel data that is advanced line by line down through the blanked upper margin of the total data region. Since none of the blanked pixel values P are above the threshold value T. the LEFT REG and RIGHT REG are not updated.

The first active pixel is sampled at the diamond upper point at 400, 20. At this point the HPC<LEFT REG and the HPC>RIGHT REG, so that both LEFT REG and RIGHT REG update to 400. The LEFT REG updates toward the left and the RIGHT REG updates toward the right as the frame scan moves downward through upper diagonal section 150 of the diamond. The LEFT REG and RIGHT REG are respectively updated to 200 and 300 at the diamond side comers, and then are not further updated as the frame scan moves through narrowing lower diagonal section 152 of the diamond.

As the frame scan moves onto the menu bar area, active pixel data begins at HPC=80. Since HPC=80<LEFT REG=200, the LEFT REG updates to 80. As the scan moves past HPC=600 toward the right edge of the menu bar, the RIGHT REG updates rightward until RIGHT REG=720 at the right edge of the menu bar. The LEFT REG and RIGHT REG do not further update as the frame scan moves down through the menu bar and the lower blanked area.

At the end of the frame, V_sync signals the LEFT STATUS and RIGHT STATUS to update the left and right edge positions respectively to 80 and 720. The microcontroller then calculates W=RIGHT STATUS−LEFT STATUS=640. Thus, in this example W=E=640, and no tracking or phase error correction is required. Of course, if W>E+1 or W<E, an adjusted number n′ of pixel clocks would be calculated as described above. If W=E+1, then pixel clock phase correction as described above would be initiated.

Although the present invention has been described in connection with a preferred embodiment thereof, it is to be understood that such preferred embodiment is exemplary only. It will be appreciated by those skilled in the art that additions, deletions, modifications and substitutions may be made to the described preferred embodiment without departing from the spirit and scope of the invention. For instance, the present invention is applicable to any digital display device that converts analog video signals into digital video signals for controlling a digital display object. Such a digital display object, in addition to various types of LCD, may be a light valve of diffraction grating, micro-mirror, or other type. The analog video source may also be a VCR, a computer workstation, or other device. Moreover, the edge detection circuit can also be utilized to detect the upper and lower vertical edges of an image. Accordingly, the present invention should be interpreted broadly in reference to the appended claims.

Claims

1. A method for recovering a correct phase and frequency clock for an analog video signal that is converted for display on a digital display object having pixels arranged in lines and columns, the analog video signal including an analog video data signal that is operable for raster scanning in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by timing signals that control a line scan rate and a frame refresh rate, to produce consecutive frames of video information, comprising the steps of:

converting an analog video signal to a digital video signal;

estimating an expected width of an image producible by the analog video signal;

determining an actual width of a image producible by the digital video signal;

iteratively adjusting the digital video signal until the actual width equals the expected width.

2. The method of claim 1, including the steps of:

generating a pixel clock signal that samples the analog video signal in order to convert the analog video signal to the digital video signal; and

iteratively adjusting at least one of frequency and phase of the pixel clock signal in order to iteratively adjust the digital video signal.

3. The method of claim 2, including the step of:

adjusting the frequency of the pixel clock signal before adjusting the phase of the pixel clock signal.

4. The method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is operable for raster scanning in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by timing signals that control a horizontal line scan rate and a frame refresh rate, to produce consecutive frames of video information, comprising the steps of:

generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal;

digitizing the analog video data signal based on the pixel clock sampling;

estimating an expected width E, measured in number of pixel clocks, of an expected video image producible by the analog video signal;

calculating an actual width W, measured in number of pixel clocks, of an actual video image producible by the analog video signal;

comparing the actual width W with the expected width E, and when E is unequal to W;

automatically adjusting at least one of a frequency component and a phase component of the pixel clock signal until E equals W.

5. The method of claim 4, including the steps of:

automatically determining whether a phase difference exists between the pixel clock signal and the analog video data signal; and

automatically shifting the pixel clock phase to substantially eliminate the phase difference.

6. The method of claim 4, wherein the actual width W is equal to an actual number of pixel clocks from an actual left-most active pixel clock in a frame that reads a left-most actual active portion of the analog video data signal in the frame, to an actual right-most pixel clock in the frame that reads a right-most actual active portion of the analog video data signal in the frame.

7. The method of claim 6, wherein the expected width E is equal to an expected number of pixel clocks from an expected left-most pixel clock in the frame that reads an expected left-most active portion of the analog video data signal in the frame, to an expected right-most pixel clock in the frame that reads an expected right-most active value of the analog video data signal in the frame.

8. The method of claim 7, wherein the frequency component of the pixel clock signal is adjusted whenever one of W>E+1 and W<E holds true in the frame.

9. The method of claim 7, wherein the frequency component of the pixel clock signal is decreased whenever E<W−1.

10. The method of claim 7, wherein the frequency component of the pixel clock signal is increased whenever E>W.

11. The method of claim 4, wherein the frequency component of the pixel clock signal is adjusted by adjusting a number n of pixel clocks across each line in a frame of the analog video data signal.

12. The method of claim 11, wherein the number n of pixel clocks and the expected width E are determined by reference to a look-up table.

13. The method of claim 4, wherein the frequency component of the pixel clock signal is adjusted before the phase component of the pixel clock signal is adjusted.

14. The method of claim 4, wherein the phase of the pixel clock signal is adjusted by the steps:

adjusting the pixel clock signal phase by a selected iterative amount for each of a series of subsequent frames until a frame phase error condition passes from W=E+1 through a subseries of frames where W=E, and back to a frame with a phase error condition of W=E+1;

storing the W values from the series of subsequent frames;

examining the W values to identify the subseries of consecutive frames in which W=E;

selecting a phase corrected frame in a center portion of the subseries of frames; and

setting the pixel clock phase at the phase of the phase corrected frame.

15. A method for recovering a correct phase and frequency clock for an analog video signal that is converted for display on a digital display object having pixels arranged in lines and columns, the analog video signal including an analog video data signal that is operable for raster scanning in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by timing signals that control a line scan rate and a frame refresh rate, to produce consecutive frames of video information, comprising the steps of:

generating a pixel clock signal that reads instantaneous values of the analog video data signal;

setting a total number n of pixel clocks that read the analog video data signal along each horizontal line;

determining an expected number E of pixel clocks from an expected left-most pixel clock in a frame that reads a left-most value of the analog video data signal that is greater than a selected threshold value, to an expected right-most pixel clock in the frame that reads a right-most value of the analog video data signal that is greater than the selected threshold value, the expected number E indicating an expected width of active analog video data;

determining an actual number W of pixel clocks from an actual left-most active pixel clock in the frame that reads a left-most actual value of the analog video data signal that is greater than the selected threshold value, to an actual right-most pixel clock in the frame that reads a right-most actual value of the analog video data signal that is greater than the selected threshold value, the actual member W indicating an actual width of active analog video data; and

comparing the actual number W with the expected number E.

16. The method of claim 15, including the steps of:

when one of W>E+1 and W<E, calculating an adjusted total number n′ of pixel clocks that read instantaneous analog video data signal values across each line of analog video signal=n·(E/W);

substituting n′ for n for a next frame; and

redetermining the actual number W of pixel clocks for the next frame.

17. The method of claim 15, including the steps of:

when W=E+1, adjusting pixel clock signal phase for a next frame; and

redetermining the actual number W of pixel clocks for the next frame.

18. The method of claim 15, including the steps of:

when W=E+1, adjusting pixel clock signal phase by a selected iterative amount for each of a series of subsequent frames;

determining the actual number W of pixel clocks for each of the series of subsequent frames; and

storing the actual number W of pixel clocks for each of the series of subsequent frames;

identifying a subseries of consecutive frames in which W=E;

selecting a corrected frame from the subseries of consecutive frames, the corrected frame being from a middle portion of the subseries of consecutive frames;

identifying a corrected pixel clock signal phase of the corrected frame; and

setting the pixel clock signal phase to the corrected pixel clock signal phase.

19. The method of claim 15, including the step of correlating the expected width of the video image to an expected number E of pixel clocks.

20. The method of claim 15, including the step of correlating the actual width of the video image to an actual number W of activated pixels.

21. An apparatus comprising:

a clock circuit to generate a pixel clock signal for converting an analog video signal into a digital video signal;

an edge detection circuit adapted to receive the digital video signal and to determine an actual width of an image produced by the digital video signal; and

a controller coupled to the clock circuit and the edge detection circuit to estimate an expected width of an image producible by the analog video signal and to facilitate the iterative adjustment of the pixel clock signal until the actual width equals the expected width.

22. The apparatus of claim 21, wherein the controller is adapted to receive a first timing signal associated with the analog video signal and to estimate the expected width of the image producible by the analog video signal based, at least in part, on the first timing signal.

23. The apparatus of claim 22, wherein the controller is adapted to receive a second timing signal associated with the analog video signal and to estimate the expected width of the image producible by the analog video signal based, at least in part, on the first and second timing signals.

24. The apparatus of claim 23, wherein the first and second timing signals correspond to a line scan rate and a frame refresh rate, respectively.

25. The apparatus of claim 21, wherein the edge detection circuit is coupled to the clock circuit to receive the pixel clock signal, said edge detection circuit to determine the actual width of the image produced by the digital video signal based at least in part on the pixel clock signal and the digital video signal.

26. The apparatus of claim 21, wherein the clock circuit comprises:

a phase lock loop to generate the pixel clock signal based at least in part upon a horizontal synchronizing signal and a feedback signal; and

a programmable counter coupled to the phase lock loop to cooperatively generate a line advance signal and the feedback signal based at least in part upon a value n determined by the controller based upon the expected width of the image.

27. The apparatus of claim 26, wherein the clock circuit generates a line advance signal frequency corresponding to the horizontal synchronizing signal, and a pixel clock signal frequency corresponding to n times the line advance signal frequency.

28. The apparatus of claim 21, wherein the pixel clock signal comprises a frequency component and a phase component, and the controller is adapted to facilitate the iterative adjustment of the pixel clock signal by adjusting at least one component selected from a group consisting of the frequency component and the phase component.

29. The apparatus of claim 28, wherein the frequency component is adjusted prior to adjustment of the phase component.

30. The apparatus of claim 28, wherein the clock circuit further comprises:

programmable delay logic to facilitate the adjustment of the phase component.

31. The apparatus of claim 21, wherein the controller comprises a processor.

32. The apparatus of claim 21, further comprising:

an analog-to-digital converter, to receive the analog video signal and the pixel clock signal, and to convert the analog video signal to the digital video signal based at least in part on the pixel clock signal.

33. The apparatus of claim 21, wherein the edge detection circuit comprises:

a pixel clock calculator adapted to receive the digital video signal and to determine a pixel value for each pixel clock pulse based, at least in part, on the digital video signal; and

comparison logic to compare the pixel values with a threshold value to determine whether a pixel clock pulse is active or inactive.

34. The apparatus of claim 33, wherein the edge detection circuit is adapted to determine the actual width based on the number of pixel clock pulses from a left-most active pixel clock pulse to a right-most active pixel clock pulse in a frame.

35. The apparatus of claim 21, wherein the edge detection circuit comprises an application specific integrated circuit.

36. A system comprising:

an image capture circuit having

a clock circuit to generate a pixel clock signal for converting an analog video signal into a digital video signal; and

an edge detection circuit adapted to receive the digital video signal and to determine an actual width of an image produced by the digital video signal;

a controller, coupled to the image capture circuit, to estimate the expected width of an image producible by the analog video signal and to facilitate the iterative adjustment of the pixel clock signal until the actual width equals the expected width; and

a light valve controller, coupled to the image capture circuit, to receive the digital video signal and to transmit control signals to a light valve based at least in part on the digital video signal.

37. The system of claim 36, wherein the image capture circuit further comprises:

an analog-to-digital converter adapted to receive the analog video signal from a multimedia source and the pixel clock signal from the clock circuit, and to transmit the digital video signal to the edge detection circuit and the light valve controller.

38. The system of claim 36, further comprising:

a light source, to output light;

the light valve adapted to receive light from the light source and the control signals from the light valve controller, and to modulate the light based on the control signals; and

projection optics, coupled to receive the modulated light from the light valve and to project the image.

39. The system of claim 38, wherein the light valve comprises a liquid crystal display.

40. The system of claim 38, wherein the light valve comprises a digital micromirror device.

41. The system of claim 36, wherein the controller is adapted to receive a first timing signal associated with a line scan rate and a second timing signal associated with a frame refresh rate, and to estimate the expected width of the image based at least in part on the first and second timing signals.

42. The system of claim 36, wherein the clock circuit comprises

a phase lock loop to generate the pixel clock signal based at least in part upon a horizontal synchronizing signal and a feedback signal; and

a programmable counter coupled to the phase lock loop to cooperatively generate a line advance signal and the feedback signal based at least in part upon a value n determined by the controller based upon the expected width of the image.

43. The system of claim 42, wherein the clock circuit generates a line advance signal frequency corresponding to the horizontal synchronizing signal, and a pixel clock signal frequency corresponding to n times the line advance signal frequency.

44. The system of claim 36, wherein the pixel clock signal comprises a frequency component and a phase component, and the controller is adapted to facilitate the iterative adjustment of the pixel clock signal by adjusting at least one component selected from a group consisting of the frequency component and the phase component.