An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A system includes a CMOS active pixel image sensor having an array for photoreceptors to convert an image into an analog signal. The CMOS image sensor converts the analog signal into a digital signal using a pipelined analog to digital converter.
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0. 15. A camera having a lens to receive and focus light, the camera further comprising:
an array of photoreceptors of a CMOS active pixel sensor to convert the focused light into a plurality of staggered in time analog signals;
an analog to digital (A/D) converter comprising a plurality of A/D converter cells; and
a controller to assign a respective analog signal of the plurality of staggered in time analog signals to a respective A/D converter cell of the plurality of A/D converter cells at staggered times that are offset from each other, wherein at least one of the plurality of A/D converter cells is configured to convert its respective analog signal to a respective digital signal during a time period that is staggered from at least one other of the plurality of A/D converter cells.
0. 1. An analog-to-digital (A/D) converter, comprising:
an input, for receiving a series of analog signals;
an output, for outputting a series of digital signals respectively corresponding to said series of analog signals;
a plurality of A/D cells, each of said A/D cells for converting one of said series of analog signals to a corresponding one of said series of digital signals; and
a control circuit, coupled to said input, said output, and said plurality of A/D cells;
wherein said control circuit operates said input, said output, and said plurality of A/D cells so that each successive A/D cell is assigned, at a different time, to convert a different one of each successive analog signal from said series of analog signals to a corresponding digital signal in said series of digital signals.
0. 2. The analog-to-digital converter of
0. 3. The analog-to-digital converter of
0. 4. The analog-to-digital converter of
0. 5. The analog-to-digital converter of
0. 6. The analog-to-digital converter of
0. 7. The analog-to-digital converter of
0. 8. The analog-to-digital converter of
0. 9. The analog-to-digital converter of
0. 10. A method for converting a series of analog signals to a corresponding series of digital signals, comprising:
receiving over a period of time, a series of analog signals;
assigning each analog signal from said series of analog signals as they are received to an available A/D cell for analog-to-digital conversion to a corresponding digital signal; and
outputting a different digital signal corresponding to a respective analog signal from said series of analog signals as each A/D cell finishes its analog-to-digital conversion;
wherein at least two A/D cells are performing respective analog-to-digital conversions while another A/D cell outputs one of said digital signals.
0. 11. The method of
calibrating each A/D cell so that an analog-to-digital conversion performed on a same analog signal by any A/D cell results in a same digital signal.
0. 12. The method of
0. 13. The method of
0. 14. The method of
0. 16. The camera of claim 15, wherein the respective digital signal comprises at least a respective first bit.
0. 17. The camera of claim 16, wherein the respective digital signal comprises ten bits.
0. 18. The camera of claim 15, wherein each of the plurality of A/D converter cells is a successive approximation A/D converter cell.
0. 19. The camera of claim 18, wherein the staggered times are offset by one clock cycle.
0. 20. The camera of claim 15, wherein the staggered times are offset by one clock cycle.
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analog data to be sent to the A/D converter array 130. The analog data is sent via an INPUT such that each A/D converter receives data at a different, staggered time. Digital signals corresponding to the input analog signals are outputted via an OUTPUT. A control circuit 135 is coupled to the INPUT, the A/D converter, and the OUTPUT.
This system may adaptively assign the channels to A/D converters in a different way than conventional. Conventional methods of removing fixed patterned noise, therefore, might not be as effective. Therefore, it becomes important that these A/D converters have consistent characteristics. In this embodiment, calibration may be used to compensate for offsets between the comparators of the system.
Successive approximation A/D converters as used herein may have built-in calibration shown as elements 320. Any type of internal calibration system may be used.
The inventors also realize that comparator kickback noise may become a problem within this system. That comparator itself may produce noise which may affect the signal being processed. In this embodiment, a single preamplifier, here shown as a follower 330, is introduced between the signal and the comparator.
This system also requires generation of multiple timing and control signals to maintain the synchronization. Each successive approximation A/D converter requires about 20 control signals. The timing is offset for each of the twelve different A/D converters. Therefore, digital logic is used to replicate control signals after a delay.
In one embodiment, shown in
Each cycle of the A/D converter may require finer timing than can be offered by a usual clock. Hence, the clock input 410 may be a divided higher speed clock.
Two D type flip-flops are required to delay each signal. Any signal which is only half a clock cycle in length may require falling edge flip-flops, in addition to the rising edge flip-flops, and may also require additional logic.
Although only a few embodiments have been disclosed in detail above, other modifications are possible. For example, different logic techniques may be used herein. In addition, while the above describes specific numbers of bits, the same techniques are applicable to other numbers of elements. For example, this system may be used with as few as three elements, with the three successive approximation devices staggered to receive one out of every three inputs.
The above has described matched unit cell capacitors, but it should also be understood that other capacitors could be used. Conventional capacitors which are not matched in this way can be used. In addition, the capacitors can be scaled relative to one another by some amount, e.g. in powers of two.
All such modifications are intended to be used within the following claims.
Fossum, Eric R., Barna, Sandor L.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4366469, | Sep 22 1980 | ILC Data Device Corporation | Companding analog to digital converter |
5382975, | Aug 30 1991 | Fuji Xerox Co., Ltd. | Image reading apparatus |
5471515, | Jan 28 1994 | California Institute of Technology | Active pixel sensor with intra-pixel charge transfer |
5801657, | Feb 05 1997 | Stanford University | Serial analog-to-digital converter using successive comparisons |
5880691, | Nov 07 1996 | California Institute of Technology | Capacitively coupled successive approximation ultra low power analog-to-digital converter |
5886659, | Aug 21 1997 | California Institute of Technology | On-focal-plane analog-to-digital conversion for current-mode imaging devices |
5920274, | Aug 05 1997 | IBM Corporation | Image sensor employing non-uniform A/D conversion |
6124819, | Aug 05 1996 | California Institute of Technology | Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier |
6377303, | Nov 26 1997 | Intel Corporation | Strobe compatible digital image sensor with low device count per pixel analog-to-digital conversion |
6456326, | Jan 28 1994 | California Institute of Technology | Single chip camera device having double sampling operation |
6518907, | Nov 27 2000 | Round Rock Research, LLC | System with high-speed A/D converter using multiple successive approximation cells |
6646583, | Oct 25 2000 | Round Rock Research, LLC | High speed digital to analog converter using multiple staggered successive approximation cells |
6734817, | Dec 26 2001 | SOCIONEXT INC | A/D converter, method of A/D conversion, and signal processing device |
6771202, | Apr 24 2002 | Denso Corporation | Analog-to-digital conversion method and device |
6816196, | Jun 18 2001 | RE SECURED NETWORKS LLC | CMOS imager with quantized correlated double sampling |
7283080, | Jun 30 2005 | Aptina Imaging Corporation | High density row RAM for column parallel CMOS image sensors |
7313380, | Dec 27 2002 | Kabushiki Kaisha Toshiba | Variable resolution A/D converter |
20040041927, | |||
20070223626, | |||
20080218621, | |||
RE41730, | Oct 25 2000 | Round Rock Research, LLC | Method for operating a CMOS imager having a pipelined analog to digital converter |
RE42117, | Oct 25 2000 | Round Rock Research, LLC | Apparatus for operating a CMOS imager having a pipelined analog to digital converter |
RE42918, | Jan 28 1994 | California Institute of Technology | Single substrate camera device with CMOS image sensor |
RE42974, | Jan 28 1994 | California Institute of Technology | CMOS active pixel sensor type imaging system on a chip |
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