CMOS active pixel sensor type imaging system on a chip

Abstract

A single chip camera which includes an intergrated integrated image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the intergrated integrated structure reduces the noise that is picked up during imaging.

Description

This a divisional of U.S. application Ser. No. 09/120,856, filed Jul. 21 1998 FIG. 5 shows
where n is number of columns, I is the load transistor bias, V is the supply voltage, and d is the duty cycle. Using n=512, I=μA, V=5V and d=10%, a value for Ps of 2.5 mW is obtained.

A load current of 1 mA or more is needed to drive the horizontal bus lines at the video scan rate. The power dissipated is typically 5 mW.

Quantum efficiency measured in this CMOS APS array is similar to that for interline CCDs. A typical response curve is shown in FIG. 2. The inventors noticed from this that the quantum efficiency reflects significant responsivity in the “dead” part of the pixel; the part containing the readout circuitry rather than the photogate collector. The responsiveness was measured by intra-pixel laser spot scanning.

The inventors postulate the following reason. The transistor gate and channel absorb photons with short absorption lengths (i.e. blue/green). However, longer wavelength photons penetrate through these regions. The subsequently-generated carriers diffuse laterally and are subsequently collected by the photogate.

Thus, despite a fill factor of 25%-30%, the CMOS APS achieves quantum efficiencies that peak between 30%-35% in the red and near infrared. Microlenses are preferably added to refract photoelectrons from the dead part to a live part and hence improve quantum efficiency.

An important feature of the system described herein is the integration of on-chip timing and control circuits within the same substrate that houses the pixel array and the signal chain electronics. A block diagram of the chip architecture is shown in FIG. 3.

The analog outputs VS_out (signal) and VR_out (reset) are as described above. The digital outputs include FRAME and READ. Most of the inputs to the chip are asynchronous digital signals, as described herein.

The chip includes a pixel array 300, which is driven by on-chip electronics. Timing and control circuit 302 drives row electronics 310, and column electronics 320.

The control circuits can command read-out of any area of interest within the array. Row decoder 312 controls row drivers 314 which can select a certain row for readout. A specific row is selected by entry of a row value 316 which is output from timing and control 302. Row value 316 is stored in latch 318 which drives counter 319. Counter 319 can allow selection of subsequent rows that follow the current row. Similarly, columns can be selected and accessed by latches 322, counter 324, decoder 326 and column signal conditioning 328.

Each of the decoder counters can be preset to start and stop at any value that has been loaded into the chip via the 8-bit data bus 330. Therefore, as described above, selection of a row commands pixels in that row to be transferred to the appropriate row decoding elements, e.g., capacitors. Preferably there is one capacitor associated with each column. This provides for the sequential readout of rows using the column. The capacitors are preferably included within the column signal conditioner 328. Column decoders 326 also allow selection of only a certain column to be read. There are two parts of each column selection: where to start reading, and where to stop reading. Preferably the operation is carried out using counters and registers. A binary up-counter within the decoder 326 is preset to the start value. A preset number of rows is used by loading the 2's compliment. The up counter then counts up until an overflow.

An alternate loading command is provided using the DEFAULT LOAD input line 332. Activation of this line forces all counters to a readout window of 128×128.

A programmable integration time is set by adjusting the delay between the end of one frame and the beginning of the next. This parameter is set by loading a 32-bit latch via the input data bus 330. A 32-bit counter operates from one-fourth the clock input frequency and is preset at each frame from the latch. The counter can hence provide vary large integration delays. The input clock can be any frequency up to about 10 MHZ. The pixel readout rate is tied to one-fourth the clock rate. Thus, frame rate is determined by the clock frequency, the window settings, and the delay integration time. The integration time is therefore equal to the delay time and the readout time for a 2.5 MHZ clock. The maximum delay time is 2³²/2.5 MHz, or around 28 minutes. These values therefore easily allow obtaining a 30 Hz frame.

The timing and control circuit controls the phase generation to generate the sequences for accessing the rows. The sequences must occur in a specified order. However, different sequences are used for different modes of operation. The system is selectable between the photodiode mode of operation and the photogate mode of operation. The timing diagrams for the two gates are respectively shown in FIGS. 4a and 4b. FIG. 4a shows an operation to operate in the photogate mode and FIG. 4b shows operating in the photodiode mode. These different timing diagrams show that different column operations are possible. Conceptually this is done as follows. Column fixed pattern noise is based on differences in source follower thresholds between the different transistors. For example, if the base bias on a transistor is V1, the output is V1 plus the threshold.

The column signal conditioning circuitry contains a double-delta sampling fixed pattern noise (“FPN”) suppression stage that reduces FPN to below 0.2% sat with a random distribution. Since the APS is formed of a logic family that is compatible with CMOS, e.g., NMOS, the circuitry can be formed of CMOS. This allows power dissipation in the timing and control digital circuitry to be minimized and to scale with clock rate.

An active pixel sensor includes both a photodetector and the readout amplifier integrated within the same substrate as the light collecting device, e.g., the photodiode. The readout amplifier is preferably within and/or associated with a pixel.

A first embodiment of the present invention is a 128×128 CMOS photodiode type active pixel sensor that includes on chip timing, control and signal train electronics. A more detailed drawing of the chip is shown in
Where α is the gain of the pixel source follower 508, β is the gain of the column source follower 526, and V_pdr is the voltage on the photodiode after reset, V_tpix is the threshold voltage of the pixel source follower and channel transistor, and V_tcolr is the threshold voltage of the column source follower p-channel transistor.

Using similar reasoning, the output voltage of the signal branch of the column circuit is
Vcol_S≅β{α[V_pds−V_tpix]−V_tcols}
where V_pds is the voltage on the photodiode with the signal charge present and V_tcols is the threshold voltage of the column source-follower p-channel transistor.

The inventors have found experimentally that the peak-to-peak variation V_tcolr−V_tcols is typically between 10 and 20 millivolts. This, however, is a source of column to column fixed pattern noise. The inventors herein suggest a double delta sampling technique to eliminate this column to column noise. The present approach represents an improved version of the previously-described double delta sampling circuitry. The operation proceeds as follows. A column is first selected. After a settling time equivalent to half of the column selection period, a special double delta sampling technique is performed to remove the column fixed pattern noise. Therefore, the varying thresholds on the different transistors cause varying outputs. According to this aspect, the threshold outputs of these transistors are equalized using a capacitor to equalize the charge. The capacitor is applied with the charge before and after the voltage change. Therefore, the output of the capacitor represents the difference between before and after, and the fixed pattern noise component drops out of the equation.

This system uses a DDS switch 520 and first and second column select switches 522, 524 to short across the respective capacitors. All three switches are turned on to short across the two sample and hold capacitors 510. This clamp operation is shown in line 8 of FIG. 6.

Prior to the DDS operation, the reset and signal column components, Vcol_R and Vcol_S include their signal values plus a source follower voltage threshold component from the appropriate source follower. The object of the special following circuit of the present invention is to remove that source follower threshold component. The operation proceeds as follows. Prior to the beginning of some operation, the capacitors are precharged through clamp transistors to a clamp voltage V_cl. This is maintained by turning on clamp transistors 550 and 552 to connect the appropriate capacitors to the voltage V_cl. The clamp operation is shown on line 8 of FIG. 6. Immediately after the clamp is released, the DDS transistors 520, 522 and 524 are turned on. This has the effect of shorting across the capacitors 510 and 512. When the transistors are shorted, the voltage that is applied to the output drivers 554, 556 includes only the voltage threshold component. The differential amplification of the voltage render the output voltage free of the voltage threshold component. Mathematically, prior to clamp being deactivated, the output signals are:
VR_OUT≅γ(V_cl−V_tr)
and
VS_OUT≅γ(V_cl−V_ts)
where γ is the gain of the third stage source-follower, V_cl is the clamp voltage, and V_tr and V_ts are the threshold voltages of the third stage source-follower n-channel transistors, reset and signal branch respectively. Deactivation of the clamp circuit and simultaneous activation of the DDS switch causes several changes. The voltages in the two column branch sampling circuits equalize becoming:
V_c3=V_cr=α[V_pdr−V_tpix+V_pds−V_tpix]/2
This in turn causes a change in Vcol_S and Vcol_R to:
Vcol_R′≅β{α[V_pdr−V_tpix+V_pds−V_tpix]/2−V_tcolr}
and
Vcol_S′≅β{α[V_pdr−V_tpix+V_pds−V_tpix]/2−V_tcols}
Consequently, the voltage outputs change to:
VR_OUT≅γ(V_cl−Vcol_R′−Vcol_R−V_tr)
and
VS_OUT≅γ(V_cl−Vcol_S′−Vcol_S−V_ts)
We note
Vcol_S′−Vcol_S=β{α[V_pds−V_pdr]/2}
and
Vcol_R′−Vcol_R=β{α[V_pdr−V_pds]/2}
When the outputs are differentially amplified off-chip, the common clamp voltage Vcl is removed, leaving only the difference between signal and reset. The net differential output voltage is given by:
VR_OUT−VS_OUT=αβγ(V_pdr−V_pds=V_const)

FIG. 7 shows the layout-of the pixel for 128×128 array size device. This system formed a 19.2 micron pixel size using 1.2 μm n-well CMOS. The maximum clock rate is 10 MHZ, the maximum pixel rate is 2.5 MHZ and maximum integration delay is 1.6×10⁹ clock periods.

A second embodiment uses similar design techniques to produce a 256×256 array size. This embodiment also uses a pixel with a photogate imaging element along with four transistors to perform the functions of readout, selection, and reset. Readout is preferably achieved using a column parallel architecture which is multiplexed one row at a time and then one column at a time through an on-chip amplifier/buffer. An important part of this embodiment, like the first embodiment, is the use of a chip common logic elements to control row and address decoders and delay counters.

This embodiment allows use in three modes of operation: Photogate mode, photodiode mode and differencing mode. The photogate mode is the standard mode for this chip. The photodiode mode alters the readout timing to be similar to that for photodiode operation. The differencing mode alters the readout timing in such a way that the value of each pixel output is the difference between the current frame and the previous frame. The chip inputs that are required are a single +5 V power supply, start command, and parallel data load commands for defining integration time and windowing parameters. The output has two differential analog channels.

The second embodiment uses the block diagram of the chip architecture shown in FIG. 8. The analog outputs of VS_OUT (signal) and VR_OUT (reset), and digital outputs of FRAME and READ. The inputs to the chip are asynchronous digital signals. The chip includes addressing circuitry allowing readout of any area of interest within the 256×256 array. The decoder includes counters that are preset to start and stop at any value that has been loaded into the chip via the 8-bit data bus. An alternate loading command is provided using the DEFAULT input line. Activation of this line forces all counters to a readout window of 256×256.

A programmable integration time is set by adjusting the delay between the end of one frame and the beginning of the next. This parameter is set by loading a 32-bit latch via the input data bus. A 32-bit counter operates from one-fourth the clock input frequency and is preset at each frame from the latch. This counter allows forming very large integration delays. The input clock can be any frequency up to about 10 MHZ. The pixel readout rate is tied to one fourth the clock rate. Thus, frame rate is determined by the clock frequency, the window settings, and the delay integration time. A 30 HZ frame rate can be achieved without difficulty.

The chip is idle when the RUN command is deactivated. This is the recommended time for setting the operating parameters. However, these parameters can be set at any time because of the asynchronous nature of operation. When RUN is activated, the chip begins continuous readout of frames based on the parameters loaded in the control registers. When RUN is deactivated, the frame in progress runs to completion and then stops.

The 256×256 CMOS APS uses a system having a similar block diagram to those described previously. The pixel unit cell has a photogate (PG), a source-follower input transistor, a row selection transistor and a reset transistor. A load transistor VLN and two output branches to store the reset and signal levels are located at the bottom of each column of pixels. Each branch has a sample and hold capacitor (CS or CR) with a sampling switch (SHS or SHR) and a source-follower with a column-selection switch (COL). The reset and signal levels are read out differentially, allowing correlated double sampling to suppress 1/f noise and fixed pattern noise (not kTC noise) from the pixel.

A double delta sampling (DDS) circuit shorts the sampled signals during the readout cycle reducing column fixed pattern noise. These readout circuits are common to an entire column of pixels. The load transistors of the second set of source followers (VLP) and the subsequent clamp circuits and output source followers are common to the entire array. After a row has been selected, each pixel is reset (RESET) and the reset value is sampled (SHR) onto the holding capacitor CR. Next, the charge under each photogate in the row is transferred to the floating diffusion (FD). This is followed by sampling this level (SHS) onto holding capacitor CS. These signals are then placed on the output data bus by the column select circuitry. In the Photodiode mode this process, is reversed; first the charge under the photogate is read out and then the reset level is sampled. This non-correlated double sampling mode would be primarily used with a photodiode, i.e., non active pixel sensor, pixel.

In the differencing mode, the capacitors CS and CR are used to store the signal from the previous frame and the current frame. This is achieved by altering the timing in the following way: Rather than starting with a reset operation, the signal on the floating diffusion is read out to one of the sample and hold capacitors. This represents the previous pixel value. The reset is then performed followed by a normal read operation. This value is then stored on the other sample and hold capacitor. The difference between these two signals is now the frame to frame difference.

A simplified expression for the output of the reset branch of the column circuit is given by:
Vcol_R≅β{α[Vr−V_tpix]−V_tcolr}
where α is the gain of the pixel source-follower; β is the gain of the column source-follower, Vr is the voltage on the floating diffusion after reset, V_tpix is the threshold voltage of the pixel source-follower n-channel transistor, and V_tcolr is the threshold voltage of the column source-follower p-channel transistor. Similarly, the output voltage of the signal branch of the column circuit is given by:
Vcol_S≅β{α[V_s−V_tpix]−V_tcols}
where V_S is the voltage on the floating diffusion wish the signal charge present and V_tcols is the threshold voltage of the column source-follower p-channel transistor. Experimentally, the peak to peak variation in V_tcolr−V_tcols is typically 10-20 mV. It is desirable to remove this source of column-to-column fixed pattern noise FPN. JPL has previously developed a double delta sampling (DDS) technique to eliminate the column-to-column FPN. This approach represented an improved version of the DDS circuitry.

Sequential readout of each column is as follows. First a column is selected. After a settling time equivalent to one-half the column selection period, the DDS is performed to remove column fixed pattern noise. In this operation, a DDS switch and two column selection switches on either side are used to short the two sample and hold capacitors CS and CR. Prior to the DDS operation the reset and signal outputs (Vcol_R and VCOL_S) contain their respective signal values plus a source follower voltage threshold component. The DDS switch is activated immediately after CLAMP is turned off. The result is a difference voltage coupled to the output drivers (VR_OUT and VS_OUT) that is free of the voltage threshold component.

This chip uses a similar pixel cell to that shown in FIG. 5 FIG. 5A. FIG. 9 shows the layout of the pixel cell. PG and RESET are routed horizontally in polysilicon while the pixel output is routed vertically in metal1. Metal2 was routed within the pixel for row selection. Metal2 was also used as a light shield and covers most of the active area outside of the pixel array. The designed fill factor of the pixel is approximately 21%.

According to another feature, a logo can be formed on the acquired image by using a light blocking metal light shield. The light shield is formed to cover certain pixels in the shape of the logo to be applied. This blocks out those underlying pixels in the array, thereby forming a logo in the shape of the blocked pixels.

The output saturation level of the sensor is 800 mv when operated from a 5 V supply. Saturation is determined by the difference between the reset level on the floating diffusion node (e.g. 3 V) and the minimum voltage allowed on the pixel source follower gate (e.g. threshold voltage of approx. 0.8 volts). This corresponds to a full well of approximately 75,000 electrons. This can be increased by operating at a larger supply voltage, gaining about 47,000 per supply volt.

Dark current was measured at less than 500 pA/cm².

Conversion gain (μV/e−) was obtained per pixel by plotting the variance in pixel output as a function of mean signal for flat field exposure. The fixed pattern noise arising from dispersion in conversion gain was under 1%—similar to the value found in CCDs and consistent with the well-controlled gain of a source-follower buffer.

The quantum efficiency of the detector was measured using a CVI ¼ m monochromator and a tungsten/halogen light source, calibrated using a photodiode traceable to NIST standards.

Claims

1. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise, wherein said signal controlling device includes a column-parallel read out device, which reads out a row of said photoreceptors at substantially the same time.

2. A camera device as in claim 1, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

3. A camera device as in claim 2, wherein said readout amplifier is preferably within and/or associated with one element of the array.

4. A camera device as in claim 2, wherein said photoreceptors are photodiodes.

5. A camera device as in claim 2 wherein said photoreceptors are photogates.

6. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;

a circuit, integrated on said substrate, which reduces a fixed pattern noise; and

a mode selector device, selecting a mode of operation of said chip, wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes.

7. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise,

wherein said timing circuit controls readout from said chip in a correlated double sampling mode.

8. A camera device as in claim 6, further comprising a differencing mode which alters readout timing in such a way that the value of each pixel output represents a difference between a current frame and a previous frame.

9. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise including at least one charge storage device, sampling a level indicative of reset.

10. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors; and

a circuit, integrated on said substrate, which reduces a fixed pattern noise, including at least two charge storage devices, one controlled by said timing circuit to first sample a level indicative of reset, and another controlled by said timing circuit to second sample a level indicative of a charged device.

11. A camera device as in claim 10, further comprising a shorting element that shorts together said two charge storage devices prior to sampling said reset level.

12. A camera device as in claim 10, wherein said timing circuit allows changing an integration time for said array of photoreceptors by changing a time between said first sample and said second sample.

13. A camera device as in claim 10, wherein said timing circuit times an operation of said fixed pattern noise reduction circuit to occur during a time of the video signal which is not being displayed.

14. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in rows and columns;

a charge storage element, associated with each said column;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;

said control portion including logic elements to control a double delta sampling, integrated on the chip, which shorts sampled signals during the readout cycle, thereby reducing column fixed pattern noise.

15. A camera device as in claim 14, wherein said signal controlling device includes a column-parallel read out device, which reads out a row of said photoreceptors at substantially the same time.

16. A camera device as in claim 14, wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout.

17. A camera device as in claim 14, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

18. A camera device as in claim 17, wherein said readout amplifier is preferably within and/or associated with one element of the array.

19. A camera device as in claim 17, wherein said photoreceptors are photodiodes.

20. A camera device as in claim 17, wherein said photoreceptors are photogates.

21. A camera device as in claim 14, further comprising a mode selector device, selecting a mode of operation of said chip.

22. A camera device as in claim 21, wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes.

23. A camera device as in claim 14, wherein said timing circuit allows changing an integration time for said array of photoreceptors.

24. A single chip camera device, comprising:

a substrate, having integrated thereon an image acquisition portion and control portion, both of which are formed using a logic family that is compatible with CMOS;

said image acquisition portion integrated in said substrate including an array of photoreceptors in rows and columns;

first and second charge storage elements, associated with each said column;

said control portion integrated in said substrate including a signal controlling device,

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, controlling said photoreceptors to output their signals such that said first charge storage element receives the signal indicative of reset and said second charge storage element receives a signal indicative of a charged state;

said control portion including a shorting element, formed on said substrate which shorts between said first and second charge storage elements to reduce noise produced thereby.

25. A device as in claim 24, wherein said photoreceptors are controlled to read out an entire column of information at one time, wherein there are one of said first and second charge storage elements on said substrate for each element of said column, and wherein there is one of said shorting elements on said substrate for each of said columns.

26. A camera device as in claim 24, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

27. A camera device as in claim 26, wherein said readout amplifier is preferably within and/or associated with one element of the array.

28. A camera device as in claim 26, wherein said photoreceptors are photodiodes.

29. A camera device as in claim 26, wherein said photoreceptors are photogates.

30. A camera device as in claim 24, wherein said timing circuit allows changing an integration time for said array of photoreceptors with changing timings of said first and second charge storage elements.

31. A method of controlling a single chip camera, comprising:

integrating, on a single substrate, an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS, said image acquisition portion integrated in said substrate including an array of photoreceptors with output nodes, and a signal controlling device, controlling said photoreceptors and a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and also integrating at least two charge storage elements on said substrate;

first, shorting together specified nodes of said two charge storage elements;

after said first shorting, sampling voltages on said charge storage elements, said voltages being related to one another.

32. A method as in claim 31, further comprising:

sampling a reset value as a first sample;

allowing said photoreceptors to accumulate charge, after resetting said output nodes;

sampling said output nodes after accumulating said charge, producing output signals indicative of a difference between said reset value and said sampled value after accumulating said charge.

33. A single chip camera device, comprising: a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS; said image acquisition portion integrated in said substrate including an array of photoreceptors and a noise reduction circuit;

said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals;

said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors to output a plurality of outputs at a time and controlling an operation of said noise reduction circuit to occur during a time when signals are not being read from said array of photodetectors.

34. A device as in claim 33, wherein said control portion controls the timing to output a column of said array at any one time.

35. A device as in claim 33, wherein said noise reduction circuit includes a correlated double sampling circuit.