Semiconductor device

Abstract

The semiconductor device according to the present invention includes: a semiconductor layer made of sic; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION

Thus, the gate insulating film 9 is formed so that the thickness of the portion (the insulating film bottom portion 11) located on the bottom surface 8 is smaller than that of the portions (the insulating film side portions 10) located on the side surfaces 7.

Then, a doped polysilicon material is deposited on the epitaxial layer 3 by CVD, as shown in FIG. 2J. The deposited polysilicon material is etched back until the etched-back surface is flush with the surface 31 of the epitaxial layer 3. Thus, portions of the polysilicon layer located outside the gate trench 6 are removed, and the gate electrode 12 is formed by the polysilicon material remaining in the gate trench 6.

Then, the interlayer dielectric film 15 made of SiO₂ is laminated on the epitaxial layer 3 by CVD, as shown in FIG. 2K. Then, the interlayer dielectric film 15 and the gate insulating film 9 are so patterned that the contact hole 16 exposing the source regions 13 and the body contact regions 14 is formed in the interlayer dielectric film 15 and the gate insulating film 9.

Then, a polysilicon material 38 is laminated by CVD to fill up the contact hole 16, as shown in FIG. 2L.

Then, an N- or P-type impurity is implanted into the deposited polysilicon material, as shown in FIG. 2M. While the implantation conditions vary with the type of the impurity, acceleration energy is 10 to 100 keV, for example. Thus, the polysilicon layer 18 doped with the impurity in a high concentration is formed.

Then, titanium and titanium nitride are deposited in this order on the surface of the polysilicon layer 18 by a method such as sputtering or vapor deposition to form the intermediate layer 19, as shown in FIG. 2N. Then, aluminum is deposited on the surface of the intermediate layer 19 by a method such as sputtering or vapor deposition, to form the metal layer 20. Then, the metal layer 20, the intermediate layer 19 and the polysilicon layer 18 are worked into a prescribed pattern, to form the source wire 17. Then, the gate wire 27 connected to the gate electrode 12 is formed. Thereafter the drain wire 23 having the polysilicon layer 24, the intermediate layer 25 and the metal layer 26 is formed on the rear surface 22 of the SiC substrate 2 by a method similar to that for the source wire 17.

The semiconductor device 1 shown in FIG. 1 is obtained through the aforementioned steps.

In the semiconductor device 1, as hereinabove described, the source wire 17 in contact with the source regions 13 and the body contact regions 14 has the polysilicon layer 18 in the portion in contact with the source regions 13 and the body contact regions 14, and has the metal layer 20 on the polysilicon layer 18.

Polysilicon can form excellent ohmic contact with a region (an impurity region) of SiC doped with an impurity. Therefore, ohmic contact can be formed between the polysilicon layer 18 and the source regions 13 as well as the body contact regions 14 by depositing the polysilicon material 38 by CVD as hereinabove described and bringing the polysilicon layer 18 into contact with the source regions 13 and the body contact regions 14.

Therefore, silicification indispensable for a structure having a metal layer directly brought into contact with an impurity region can be omitted. Thus, formation of a carbon layer can be prevented on the surface of the polysilicon layer 18 and in the vicinity of the interface between the polysilicon layer 18 and the source regions 13 and the body contact regions 14.

Consequently, layer peeling can be suppressed between the polysilicon layer 18 and the metal layer 20 as well as between the polysilicon layer 18 and the source regions 13 and the body contact regions 14. Thus, connection reliability of the source wire 17 can be improved.

The source wire 17 is in contact with the source regions 13 and the body contact regions 14 through the contact hole 16 of the interlayer dielectric film 15. In the source wire 17, the polysilicon layer 18 made of the polysilicon material excellent in coverage is formed with the thickness filling up the contact hole 16. Therefore, coverage of the source wire 17 can be improved. Consequently, the connection reliability of the source wire 17 can be further improved. Further, planarity of the metal layer 20 formed on the polysilicon layer 18 can be improved. Consequently, bondability can be improved when the metal wire is bonded to the metal layer 20.

The polysilicon layer 18 is a high-concentration doped layer doped with the impurity in the high concentration of 10¹⁹ to 10²¹ cm⁻³, whereby the resistance of the source wire 17 can be reduced.

Further, the intermediate layer 19 having the multilayer structure of the titanium layer and the titanium nitride layer is interposed between the polysilicon layer 18 and the metal layer 20. A material containing titanium has excellent adhesiveness with respect to both of a polysilicon material and a metal material. Therefore, the adhesiveness between the polysilicon layer 18 and the metal layer 20 can be improved. Consequently, the connection reliability of the source wire 17 can be further improved.

Functions and effects attained by the drain wire 23 having the polysilicon layer 24, the intermediate layer 25 and the metal layer 26 are similar to those attained by the source wire 17, and hence redundant description is omitted.

FIGS. 3(a) and 3(b) are schematic plan views of a semiconductor device according to a second embodiment of the present invention, with FIG. 3(a) showing the overall semiconductor device and FIG. 3(b) showing an inner portion thereof in an enlarged manner.

A semiconductor device 41 according to the second embodiment of the present invention is a trench gate power VDMOSFET (an individual device) employing SiC, in the form of a chip square in plan view, for example. The chip-like semiconductor device 41 has a length of about several mm in the right-and-left (vertical) direction in the plane of FIG. 3(a).

The semiconductor device 41 has an SiC substrate 42 and a large number of unit cells 44 formed on the SiC substrate 42 and partitioned by a gate trench 43 latticed in plan view. In other words, the unit cells 44 in the form of rectangular parallelepipeds arranged in window portions of the latticed gate trench 43 respectively are aligned on the SiC substrate 42 in the form of a matrix. Each unit cell 44 has a length of not more than 10 μm in the right-and-left (vertical) direction in the plane of FIG. 3(b), for example, and a source trench 45, square in plan view, dug down from the surface side toward the side of the SiC substrate 42 is formed at the center thereof.

A source pad 46 is formed on the surface of the semiconductor device 41. The source pad 46 is generally in the form of a square having outwardly bent four corners in plan view, and formed to generally cover the overall region of the surface of the semiconductor device 41. A removed region 47 is formed in the source pad 46 by partially removing the same in a generally square manner in plan view, on a position slightly leftward in the right-and-left direction in the plane of FIG. 3(a).

A gate pad 48 is arranged on the removed region 47. An interval is provided between the gate pad 48 and the source pad 46, which are insulated from each other.

FIG. 4 is a schematic sectional view of the semiconductor device 41 according to the second embodiment of the preset invention, taken along a line IV-IV in FIG. 3(b).

The sectional structure of the semiconductor device 41 is described with reference to FIG. 4. The semiconductor device 4 includes the SiC substrate 42 of an N⁺-type (having a concentration of 10¹⁸ to 10²¹ cm⁻³, for example). The SiC substrate 42 has a surface 49 (an upper surface) formed by an Si surface and a rear surface 50 (a lower surface) formed by a C surface.

An N⁻-type epitaxial layer 51 made of SiC having a lower concentration (10¹⁵ to 10¹⁷ cm⁻³, for example) than the SiC substrate 42 is laminated on the SiC substrate 42. The epitaxial layer 51 as a semiconductor layer is formed on the SiC substrate 42 by the so-called epitaxy. The epitaxial layer 51 formed on the surface 49, i.e., the Si surface, is grown on a major growth surface formed by an Si surface. Therefore, a surface 52 of the epitaxial layer 51 formed by the growth is an Si surface, similarly to the surface 49 of the SiC substrate 42.

On the side of the epitaxial layer 51 closer to the surface 52 (the Si surface), a P-type body region 53 is provided in the form of a well over a wide range, with a concentration of 10¹⁶ to 10¹⁹ cm⁻³, for example. A region of the epitaxial layer 51 closer to the SiC substrate 42 (the C surface) than the body region 53 forms an N⁻-type drain region 54 (a drift region) maintaining the state after the epitaxy.

In the body region 53, an N⁺-type source region 55 (having a concentration of 10¹⁸ to 10²¹ cm⁻³, for example) is formed generally on the overall region of the side closer to the surface 52, while a P⁺-type body contact region 56 (having a concentration of 10¹⁸ to 10²¹ cm⁻³, for example) is formed on a side (the lower side) closer to the SiC substrate 42 than the source region 55. A large number of such body contact regions 56 are provided in the form of a matrix.

Source trenches 45 are formed in the same number as the body contact regions 56 so that each source trench 45 passes through each body contact region 56, and the latticed gate trench 43 is formed to surround each body contact region 56 provided with the source trench 45. Thus, the large number of unit cells 44 functioning as field-effect transistors respectively are formed on the epitaxial layer 51. In other words, the body contact region 56 is formed to surround the corresponding source trench 45 and the body region 53 is formed to surround the body contact region 56 in each unit cell 44. A side of the body region 53 opposite to the side closer to the body contact region 56 is exposed on the side surfaces of the gate trench 43. In the unit cell 44, the depth direction of the gate trench 43 corresponds to a gate length direction, and the peripheral direction of each unit cell 44 orthogonal to the gate length direction corresponds to a gate width direction.

Both of the source trench 45 and the gate trench 43 pass through the body region 53 from the surface 52 of the epitaxial layer 51 to reach the drain region 54, and the depths thereof are identical to each other in the second embodiment. The distance D₁ between side surfaces 59 and 57 of the source trench 45 and the gate trench 43 is 0.5 to 3 μm, for example. When the distance D₁ is in this range, increase in resistance (on-resistance) can be suppressed when each unit cell 44 is turned on, and an electric field applied to the bottom portion of the gate trench 43 can be relaxed.

The gate trench 43 is U-shaped in section, such that both end corner portions 61 of the bottom portion thereof in a direction (a direction opposed to the adjacent unit cell 44) orthogonal to the gate width are bent toward the side of the drain region 54 and the side surfaces 57 opposed to each other and a bottom surface 58 are continuous through bent surfaces. The source trench 45 is also U-shaped in section similarly to the gate trench 43, such that the side surfaces 59 opposed to each other and a bottom surface 60 are continuous through bent surfaces. When the unit cell 44 is turned off, therefore, the electric field applied to both end corner portions 61 of the bottom portion of the gate trench 43 can be dispersed to portions other than both end corner portions 61, whereby a portion of the gate insulating film 63 located on the bottom surface 58 can be prevented from dielectric breakdown.

A gate insulating film 63 is formed on the inner surfaces of the gate trench 43, to cover the overall regions thereof. The gate insulating film 63 consists of an oxide film containing nitrogen, such as a silicon oxynitride film formed by thermal oxidation with gas containing nitride and oxygen, for example. The nitrogen content (the nitrogen concentration) in the gate insulating film 63 is 0.1 to 10%, for example.

A gate electrode 66 is embedded in the gate trench 43 by filling up the inner side of the gate insulating film 63 with a polysilicon material doped with an N-type impurity in a high concentration.

An interlayer dielectric film 67 made of SiO₂ is laminated on the epitaxial layer 51. A contact hole 68 exposing the surfaces of the source trench 45 and the source region 55 of each unit cell 44 is formed in the interlayer dielectric film 67 and the gate insulating film 63.

A source wire 69 is formed on the interlayer dielectric film 67. The source wire 69 collectively enters the source trench 45 of every unit cell 44 through each contact hole 68, and is in contact with the drain region 54, the body contact region 56 and the source region 55 successively from the bottom side of the source trench 45 in each unit cell 44. In other words, the source wire 69 is common to all unit cells 44. An interlayer dielectric film (not shown) is formed on the source wire 69, which in turn is electrically connected to the source pad 46 (see FIG. 3(a)) through the interlayer dielectric film (not shown). On the other hand, the gate pad 48 (see FIG. 3(a)) is electrically connected to the gate electrode 66 through a gate wire (not shown) drawn onto the interlayer dielectric film (not shown).

The source wire 69 has a polysilicon layer 70, an intermediate layer 71 and a metal layer 72 successively from the side in contact with the epitaxial layer 51.

The polysilicon layer 70 is a doped layer made of doped polysilicon doped with an impurity, such as a high-concentration doped layer doped with the impurity in a high concentration of 10¹⁹ to 10²¹ cm⁻³, for example. The impurity for forming the polysilicon layer 70 as the doped layer (including the high-concentration doped layer) can be prepared from an N-type impurity such as N (nitrogen), P (phosphorus) or As (arsenic)or a P-type impurity such as Al (aluminum) or B (boron). The thickness of the polysilicon layer 70 is 5000 to 10000 Å, for example.

According to the second embodiment, the polysilicon layer 70 is formed to cover the overall region of the surface of the unit cell 44 exposed in the contact hole 68, and in contact with the drain region 54, the body contact region 56 and the source region 55 in the source trench 45.

The layer of the source wire 69 in contact with the drain region 54, the body contact region 56 and the source region 55 is made of polysilicon, whereby the source wire 69 can be brought into ohmic contact with both of the body contact region 56 and the source region 55, which are high-concentration impurity regions. On the other hand, a heterojunction having a smaller junction barrier than the diffusion potential of a body diode 73 (a PN diode formed by junction between the body region 53 and the drain region 54) intrinsic in the semiconductor device 41 can be formed with respect to the low-concentration drain region 54.

When a current flows to the body diode 73 intrinsic in the semiconductor device 41, positive holes (holes) moving from the body region 53 to the drain region 54 recombine with electrons in the drain region 54, and a defect of an SiC crystal in the epitaxial layer 51 may spread in the plane due to the resulting recombination energy. The resistance of the crystal defect is so high that the crystal defect may hinder an ordinary transistor operation to increase on-resistance when spreading toward the side of the gate trench 43.

When the heterojunction is formed due to the contact between the polysilicon layer 70 and the drain region 54 as in the second embodiment, on the other hand, a current can be fed to the side of the heterojunction in preference to the side of the body diode 73, even if a reverse voltage is applied between the source and the drain and the current can flow to the aforementioned body diode 73. Consequently, the crystal defect of SiC can be prevented from spreading, and increase in the on-resistance can be suppressed.

The intermediate layer 71, laminated on the polysilicon layer 70, is formed by a single layer containing Ti (titanium) or a plurality of layers including the layer. The layer containing Ti can be prepared from Ti, TiN (titanium nitride) or the like. The thickness of the intermediate layer 71 is 200 to 500 nm, for example.

The metal layer 72, laminated on the intermediate layer 71, is made of Al (aluminum), Au (gold), Ag (silver), Cu (copper) or Mo (molybdenum), an alloy thereof, or a metal material containing the same, for example. The metal layer 72 forms the outermost layer of the source wire 69. The thickness of the metal layer 72 is 1 to 5 μm, for example.

More specifically, the polysilicon layer 70, the intermediate layer 71 and the metal layer 72 may be combined in a multilayer structure (Poly-Si/Ti/TiN/Al) obtained by successively laminating Poly-Si (the polysilicon layer 70), Ti (the intermediate layer 71), TiN (the intermediate layer 71) and Al (the metal layer 72).

A drain electrode 74 is formed on the rear surface 50 of the SiC substrate 42, to cover the overall region thereof. The drain electrode 74 is common to all unit cells 44. The drain electrode 74 has a multilayer structure (Ti/Al) obtained by laminating Ti and Al successively from the side of the SiC substrate 42, for example.

A prescribed voltage (a voltage of not less than a gate threshold voltage) is applied to the gate pad 48 while a prescribed potential difference is caused between the source pad 46 (the source wire 69) and the drain electrode 74 (between a source and a drain), whereby a channel is formed in the vicinity of the interface between the body region 53 and the gate insulating film 63 due to an electric field from the gate electrode 66. Thus, a current flows between the source wire 69 and the drain wire 74, and the VDMOSFET is turned on.

FIGS. 5A to 5Q are schematic sectional views for illustrating a method of manufacturing the semiconductor device 41 shown in FIG. 4 in step order.

First, an SiC crystal is grown on the surface 49 (the Si surface) of the SiC substrate 42 by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping the same with an impurity, as shown in FIG. 5A. Thus, the N⁻-type epitaxial layer 51 is formed on the SiC substrate 42.

Then, a P-type impurity is implanted into the epitaxial layer 51 from the surface 52 thereof, as shown in FIG. 5B. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 200 to 3000 keV, for example.

Then, a mask 75 made of SiO₂ is formed on the epitaxial layer 51 by CVD, as shown in FIG. 5C. Then, the mask 75 is etched through a photoresist film (not shown) into a pattern having an opening 76 in a region for forming the body contact region 56. After the formation of the opening 76, a P-type impurity is implanted into the epitaxial layer 51 from the surface 52 thereof. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 30 to 400 keV, for example. After the implantation of the P-type impurity, the mask 75 is removed.

Then, an N-type impurity is implanted into the epitaxial layer 51 from the surface 52 thereof, as shown in FIG. 5D. While the implantation conditions vary with the type of the N-type impurity, acceleration energy is 30 to 400 keV, for example.

Then, a mask 77 made of SiO₂ is formed on the overall region of the surface 52 of the epitaxial layer 51 by CVD or thermal oxidation, as shown in FIG. 5E. The mask 77 may alternatively be made of SiN or the like through CVD. Then, the mask 77 is etched through a photoresist film (not shown) into a pattern having openings 78 in regions for forming the gate trench 43 and the source trench 45. After the formation of the openings 78, mixed gas (SF₆/O₂ gas) containing SF₆ (sulfur hexafluoride) and O₂ (oxygen) or mixed gas (SF₆/O₂/HBr gas) containing SF₆, O₂ and HBr (hydrogen bromide), for example, is introduced into the surface 52 of the epitaxial layer 51 through the openings 78. Thus, the epitaxial layer 51 is dry-etched from the surface 52 (the Si surface), and the gate trench 43 and the source trench 45 are formed at the same time. Further, the large number of unit cells 44 are formed on the epitaxial layer 51.

Then, the mask 77 is removed by wet etching, as shown in FIG. 5F.

Thereafter an organic material film 81 is formed on the overall region of the surface 52 of the epitaxial layer 51, as shown in FIG. 5G. The organic material film 81 is made of a material containing carbon, to which an organic material (polyimide or the like, for example) employed as a photoresist material or the like can be applied, for example. The organic material film 81 is formed with a spin coater or the like, for example.

After the formation of the organic material film 81, the SiC substrate 42 is charged into a resistance heating furnace 82. The resistance heating furnace 82 is not particularly restricted, so far as airtightness in the resistance heating furnace 82 in which a heated object is set can be ensured and gas can be introduced thereinto. Further, the heating system of the resistance heating furnace 82 may be either direct heating or indirect heating.

When the SiC substrate 42 is set in the resistance heating furnace 82, inert gas (N₂, Ar or the like, for example) is introduced into the resistance heating furnace 82, which in turn is subjected to temperature-rise control (first temperature-rise control).

In the first temperature-rise control, the heating temperature is controlled to rise from 100° C. to 1000° C. over 35 to 45 minutes, for example, and thereafter held at 1000° C. (first temperature holding) for 5 to 10 minutes, for example, as shown in FIG. 6. Due to the temperature rise and the temperature holding, elements other than carbon evaporate from the organic material film 81, which in turn is altered into a carbon film 83, as shown in FIG. 5H. Therefore, the overall region of the surface 52 of the epitaxial layer 51 is covered with the carbon film 83.

Then, the resistance heating furnace 82 is subjected to further temperature-rise control (second temperature-rise control) while the inner portion thereof is kept in the inert atmosphere.

In the second temperature-rise control, the heating temperature is controlled to rise from 1000° C. to 1600° C. over 30 to 60 minutes, for example, as shown in FIG. 6. After the temperature rise, the heating temperature is held at 1600° C. (second temperature holding) for 5 to 10 minutes, for example. Due to the temperature rise and the temperature holding, ions of the individual N- and P-type impurities implanted into a surface layer portion of the epitaxial layer 51 are activated, and the body region 53, the source region 55 and the body contact region 56 are formed in response to the implanted portions respectively, as shown in FIG. 5I. Further, the drain region 54 maintaining the state after the epitaxy is formed on a base layer portion of the epitaxial layer 51.

Then, the resistance heating furnace 82 is subjected to temperature-drop control while the inner portion thereof is kept in the inert atmosphere.

In the temperature-drop control, the heating temperature is controlled (temperature-drop-controlled) to drop from 1600° C. to 1300° C. over 15 to 30 minutes, for example, as shown in FIG. 6. After the temperature drop, nitrogen/oxygen-containing gas is introduced into the resistance heating furnace 82 for 5 to 10 minutes, for example, while the heating temperature is held at 1300° C. (third temperature holding). Due to the introduction of the nitrogen/oxygen-containing gas, the carbon film 83 is oxidized and removed by reacting with oxygen contained in the gas, as shown in FIG. 5J. The introduced nitrogen/oxygen-containing gas can be prepared from gas containing at least N₂O (dinitrogen oxide), and may contain NO (nitrogen monoxide). The N₂O gas is fed at a flow rate of not more than 30%, preferably 1 to 30% with respect to the total flow rate of the introduced gas.

Thereafter the heating temperature is further held at 1300° C. (fourth temperature holding) for 200 to 240 minutes, for example, while the nitrogen/oxygen-containing gas is introduced into the resistance heating furnace 82 at the same flow rate. Thus, the surface 52 of the epitaxial layer 51 is oxidized, and a silicon oxynitride film (the gate insulating film 63) covering the overall region of the surface 52 is formed, as shown in FIG. 5K.

After the formation of the gate insulating film 63, the inert gas (N₂, Ar or the like, for example) is reintroduced into the resistance heating furnace 82, while the heating temperature is controlled to drop from 1300° C. to 300° C. After the temperature drop, the SiC substrate 42 is taken out from the resistance heating furnace 82.

Then, a doped polysilicon material 84 is deposited from above the epitaxial layer 51 by CVD, as shown in FIG. 5L. The polysilicon material 84 is continuously deposited until at least the gate trench 43 and the source trench 45 are filled up therewith.

Thereafter the deposited polysilicon material 84 is etched back until the etched-back surface is flush with the surface 52 of the epitaxial layer 51, as shown in FIG. 5M.

Then, only the portion of the polysilicon material 84 remaining in the source trench 45 is removed by dry etching, as shown in FIG. 5N. Thus, the gate electrode 66 is formed by the polysilicon material 84 remaining in the gate trench 43.

Then, the interlayer dielectric film 67 made of SiO₂ is laminated on the epitaxial layer 51 by CVD, as shown in FIG. 5O.

Then, the interlayer dielectric film 67 and the gate insulating film 63 are continuously patterned, whereby the contact hole 68 is formed in the interlayer dielectric film 67 and the gate insulating film 63, as shown in FIG. 5P.

Then, a polysilicon material is deposited by CVD to fill up the contact hole 68, as shown in FIG. 5Q. Thereafter an N- or P-type impurity is implanted into the deposited polysilicon material. While the implantation conditions vary with the type of the N- or P-type impurity, acceleration energy is 10 to 100 keV, for example. Thereafter the impurity is diffused at a temperature of 900° C. for 20 minutes, for example. Thus, the polysilicon layer 70 doped with the impurity in a high concentration is formed. Then, Ti and TiN are deposited in this order on the surface of the polysilicon layer 70 by a method such as sputtering or vapor deposition, and the intermediate layer 71 is formed. Then, a metal such as Al is deposited on the surface of the intermediate layer 71 by a method such as sputtering or vapor deposition, and the metal layer 72 is formed. Thus, the source wire 69 is formed. Then, the drain electrode 74 is formed on the rear surface 50 of the SiC substrate 42.

Thereafter the semiconductor device 41 shown in FIG. 4 is obtained by forming the interlayer dielectric film (not shown), the source pad 46 and the gate pad 48.

In the semiconductor device 41, as hereinabove described, the source wire 69 has the polysilicon layer 70 in the portion in contact with the source region 55 and the body contact region 56 similarly to the semiconductor device 1 according to the first embodiment, whereby the source wire 69 can be brought into ohmic contact with both of the body contact region 56 and the source region 55, which are high-concentration impurity regions.

When the semiconductor device 41 is manufactured, therefore, a step of forming an Ni layer on the surface 52 of the epitaxial layer 51 can be omitted dissimilarly to a case where a layer made of only a metal such as Al is directly brought into contact with the impurity regions, and a step of silicifying such an Ni layer can also be omitted. Thus, the surface 52 of the epitaxial layer 51 can be prevented from formation of a carbon layer.

Consequently, layer peeling can be suppressed between the source wire 69 and the epitaxial layer 51. Thus, connection reliability of the source wire 69 can be improved.

Further, the layer (the polysilicon layer 70) entering the source trench 45 to come into contact with the drain region 54, the body contact region 56 and the source region 55 is made of polysilicon excellent in coverage, whereby coverage of the source wire 69 can be improved. Consequently, the connection reliability of the source wire 69 can be further improved.

In addition, the polysilicon layer 70 is the high-concentration doped layer doped with the impurity in the high concentration of 10¹⁹ to 10²¹ cm⁻³, whereby the resistance of the source wire 69 can be reduced.

Further, the intermediate layer 71 having the multilayer structure of the Ti layer and the TiN layer is interposed between the polysilicon layer 70 and the metal layer 72. A material containing Ti has excellent adhesiveness with respect to both of a polysilicon material and a metal material. Therefore, adhesiveness between the polysilicon layer 70 and the metal layer 72 can be improved. Consequently, the connection reliability of the source wire 69 can be further improved.

In the semiconductor device 41, the source trench 45 is formed at the center of each unit cell 44 surrounded by the gate trench 43, whereby congestion of equipotential lines can be suppressed in the vicinity of both end corner portions 61 of the gate trench 43. Consequently, the electric field applied to both end corner portions 61 on the bottom portion of the gate trench 43 can be relaxed, whereby the portion of the gate insulating film 63 located on the bottom surface 58 can be prevented from dielectric breakdown.

The source trench 45 may be deeper than the gate trench 43, as in a semiconductor device 85 shown in FIG. 7. Thus, the electric field applied to both end corner portions 61 on the bottom portion of the gate trench 43 can be further relaxed.

FIGS. 8(a) and 8(b) are schematic plan views of a semiconductor device according to a third embodiment of the present invention, with FIG. 8(a) showing the overall semiconductor device and FIG. 8(b) showing an inner portion thereof in an enlarged manner. Referring to FIGS. 8(a) and 8(b), portions corresponding to those shown in FIGS. 3(a) and 3(b) are denoted by the same reference numerals. In the following, redundant description on the portions denoted by the same reference numerals is omitted.

A semiconductor device 86 according to the third embodiment of the present invention is a planar gate power VDMOSFET (an individual device) employing SiC in the form of a chip square in plan view, for example. The chip-like semiconductor device 86 has a length of about several mm in the right-and-left (vertical) direction in the plane of FIG. 8(a).

The semiconductor device 86 has an SiC substrate 42 and a large number of unit cells 88 formed on the SiC substrate 42 and partitioned by a gate electrode 87 latticed in plan view. In other words, the unit cells 88 in the form of squares in plan view arranged in window portions of the latticed gate electrode 87 respectively are aligned on the SiC substrate 42 in the form of a matrix. Each unit cell 88 has a length of not more than 10 μm the right-and-left (vertical) direction in the plane of FIG. 8(b), for example, and a source wire 89 is connected to the center thereof from the surface side.

FIG. 9 is a schematic sectional view of the semiconductor device 86 according to the third embodiment of the present invention, taken along a line IX-IX in FIG. 8(b). Referring to FIG. 9, portions corresponding to those shown in FIG. 4 are denoted by the same reference numerals. In the following, redundant description on the portions denoted by the same reference numerals is omitted.

The sectional structure of the semiconductor device 86 is described with reference to FIG. 9. The semiconductor device 86 includes the SiC substrate 41 of an N⁺-type (having a concentration of 10¹⁸ to 10²¹ cm⁻³, for example) and an epitaxial layer 51 laminated on the SiC substrate 42.

A large number of well-shaped P-type body regions 90 are formed on the side of the epitaxial layer 51 closer to a surface 52 (an Si surface), with a concentration of 10¹⁶ to 10¹⁹ cm⁻³, for example. A region of the epitaxial layer 51 closer to the side of the SiC substrate 42 (the side of a C surface) than each body region 90 is an N⁻-type drain region 91 (a drift region) maintaining a state after epitaxy.

An N⁺-type source region 92 (having a concentration of 10¹⁸ to 10²¹ cm⁻³, for example) and a P⁺-type body contact region 93 (having a concentration of 10¹⁸ to 10²¹ cm⁻³, for example) surrounded by the source region 92 are formed in each body region 90.

The latticed gate electrode 87 is formed over the adjacent body regions 90, and a gate insulating film 94 is interposed between the gate electrode 87 and the epitaxial layer 51. The gate electrode 87 extends over the source region 92 and the drain region 91, to control formation of an inversion layer (a channel) on the surface of the body region 90. The gate insulating film 94 consists of an oxide film containing nitrogen, such as a silicon oxynitride film formed by thermal oxidation with gas containing nitride and oxygen, for example. The nitrogen content (the nitrogen concentration) in the gate insulating film 94 is 0.1 to 10%, for example.

An interlayer dielectric film 95 made of SiO₂ is laminated on the epitaxial layer 51, to cover the gate electrode 87. In the interlayer dielectric film 95 and the gate insulating film 63, a contact hole 96 is formed in a central region of the body region 90.

A source wire 89 is formed on the interlayer dielectric film 95. The source wire 89 collectively enters every contact hole 96, and is in contact with the drain region 91, the body contact region 93 and the source region 92 in each unit cell 88. In other words, the source wire 89 is common to all unit cells 88. An interlayer dielectric film (not shown) is formed on the source wire 89, which in turn is electrically connected to a source pad 46 (see FIG. 8(a)) through the interlayer dielectric film (not shown). On the other hand, a gate pad 48 (see FIG. 8(a)) is electrically connected to the gate electrode 87 through a gate wire (not shown) drawn onto the interlayer dielectric film (not shown).

The source wire 89 has a polysilicon layer 97, an intermediate layer 98 and a metal layer 99 successively from the side in contact with the epitaxial layer 51.

The polysilicon layer 97 is a doped layer made of doped polysilicon doped with an impurity, such as a high-concentration doped layer doped with the impurity in a high concentration of 10¹⁹ to 10²¹ cm⁻³, for example. The impurity for forming the polysilicon layer 97 as the doped layer (including the high-concentration doped layer) can be prepared from an N-type impurity such as N (nitrogen), P (phosphorus) or As (arsenic) or a P-type impurity such as Al (aluminum) or B (boron). The thickness of the polysilicon layer 97 is 5000 to 10000 Å, for example.

According to the third embodiment, the polysilicon layer 97 is formed to cover the overall region of the surface of each unit cell 88 exposed in the contact hole 96, and in contact with the body contact region 93 and the source region 92.

The layer of the source wire 89 in contact with the body contact region 93 and the source region 92 is so made of polysilicon that the source wire 89 can be brought into ohmic contact with both of the body contact region 93 and the source region 92, which are high-concentration impurity regions.

The intermediate layer 98, laminated on the polysilicon layer 97, is formed by a single layer containing Ti (titanium) or a plurality of layers including the layer. The layer containing Ti can be prepared from Ti, TiN (titanium nitride) or the like. The thickness of the intermediate layer 98 is 200 to 500 nm, for example.

The metal layer 99, laminated on the intermediate layer 98, is made of Al (aluminum), Au (gold), Ag (silver), Cu (copper) or Mo (molybdenum), an alloy thereof, or a metal material containing the same, for example. The metal layer 99 forms the outermost layer of the source wire 98. The thickness of the metal layer 99 is 1 to 5 μm, for example.

More specifically, the polysilicon layer 97, the intermediate layer 98 and the metal layer 99 may be combined in a multilayer structure (Poly-Si/Ti/TiN/Al) obtained by successively laminating Poly-Si (the polysilicon layer 97), Ti (the intermediate layer 98), TiN (the intermediate layer 98) and Al (the metal layer 99).

A drain electrode 74 is formed on a rear surface 50 of the SiC substrate 42, to cover the overall region thereof.

A prescribed voltage (a voltage of not less than a gate threshold voltage) is applied to the gate pad 48 while a prescribed potential difference is caused between the source pad 46 (the source wire 89) and the drain electrode 74 (between a source and a drain), whereby a channel is formed in the vicinity of the interface between the body region 90 and the gate insulating film 63 due to an electric field from the gate electrode 87. Thus, a current flows between the source wire 89 and the drain electrode 74, and the VDMOSFET is turned on.

FIGS. 10A to 10N are schematic sectional views for illustrating a method of manufacturing the semiconductor device 86 shown in FIG. 9 in step order. Referring to FIGS. 10A to 10N, portions corresponding to those shown in FIGS. 5A to 5Q are denoted by the same reference numerals. In the following, redundant description on the portions denoted by the same reference numerals is omitted.

First, an SiC crystal is grown on a surface 49 (an Si surface) of the SiC substrate 42 by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping the same with an impurity, as shown in FIG. 10A. Thus, the N⁻-type epitaxial layer 51 is formed on the SiC substrate 42.

Then, a mask 39 made of SiO₂ is formed on the epitaxial layer 51 by CVD, as shown in FIG. 10B. Then, the mask 39 is etched through a photoresist film (not shown) into a pattern having an opening in a region for forming the body region 90. After the formation of the opening, a P-type impurity is implanted into the epitaxial layer 51 from the surface 52 thereof. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 200 to 3000 keV, for example. After the implantation of the P-type impurity, the mask 39 is removed.

Then, a mask 40 made of SiO₂ is formed on the epitaxial layer 51 by CVD, as shown in FIG. 10C. Then, the mask 40 is etched through a photoresist film (not shown) into a pattern having an opening in a region for forming the source region 92. After the formation of the opening, an N-type impurity is implanted into the epitaxial layer 51 from the surface 52 thereof. While the implantation conditions vary with the type of the N-type impurity, acceleration energy is 30 to 400 keV, for example. After the implantation of the N-type impurity, the mask 40 is removed.

Then, a mask 62 made of SiO₂ is formed on the epitaxial layer 51 by CVD, as shown in FIG. 10D. Then, the mask 62 is etched through a photoresist film (not shown) into a pattern having an opening in a region for forming the body contact region 93. After the formation of the opening, a P-type impurity is implanted into the epitaxial layer 51 from the surface 52 thereof. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 30 to 400 keV, for example. After the implantation of the P-type impurity, the mask 62 is removed.

Thereafter an organic material film 81 is formed on the overall region of the surface 52 of the epitaxial layer 51, as shown in FIG. 10E.

After the formation of the organic material film 81, the SiC substrate 42 is charged into a resistance heating furnace 82. When the SiC substrate 42 is set in the resistance heating furnace 82, inert gas (N₂, Ar or the like, for example) is introduced into the resistance heating furnace 82, which in turn is subjected to temperature-rise control (first temperature-rise control), similarly to the step shown in FIG. 5H (see FIG. 6). Due to the temperature rise and temperature holding, elements other than carbon evaporate from the organic material film 81, which in turn is altered into a carbon film 83, as shown in FIG. 10F.

Then, the resistance heating furnace 82 is subjected to further temperature-rise control (second temperature-rise control) while the inner portion thereof is kept in the inert atmosphere, similarly to the step shown in FIG. 5I (see FIG. 6). Due to the temperature rise and temperature holding, ions of the individual N- and P-type impurities implanted into a surface layer portion of the epitaxial layer 51 are activated, and the body region 90, the source region 92 and the body contact region 93 are formed in response to the implanted portions respectively, as shown in FIG. 10G. Further, the drain region 91 maintaining the state after the epitaxy is formed on a base layer portion of the epitaxial layer 51.

Then, the resistance heating furnace 82 is subjected to temperature-drop control while the inner portion thereof is kept in the inert atmosphere, similarly to the step shown in FIG. 5J (see FIG. 6). Due to the temperature-drop control introducing nitrogen/oxygen-containing gas, the carbon film 83 is oxidized and removed by reacting with oxygen contained in the gas, as shown in FIG. 10H.

Thereafter the heating temperature is further held at 1300° C. (fourth temperature holding) for 200 to 240 minutes, for example, while the nitrogen/oxygen-containing gas is introduced into the resistance heating furnace 82 at the same flow rate (see FIG. 6). Thus, the surface 52 of the epitaxial layer 51 is oxidized, and a silicon oxynitride film (the gate insulating film 94) covering the overall region of the surface 52 is formed, as shown in FIG. 10I.

After the formation of the gate insulating film 94, the inert gas (N₂, Ar or the like, for example) is reintroduced into the resistance heating furnace 82, while the heating temperature is controlled to drop from 1300° C. to 300° C. After the temperature drop, the SiC substrate 42 is taken out from the resistance heating furnace 82.

Then, a doped polysilicon material 84 is deposited from above the epitaxial layer 51 by CVD, as shown in FIG. 10J.

Thereafter the deposited polysilicon material 84 is removed by dry etching, as shown in FIG. 10K. Thus, the gate electrode 87 is formed.

Then, the interlayer dielectric film 95 made of SiO₂ is laminated on the epitaxial layer 51 by CVD, as shown in FIG. 10L.

Then, the interlayer dielectric film 95 and the gate insulating film 94 are continuously patterned so that the contact hole 96 is formed in the interlayer dielectric film 95 and the gate insulating film 94, as shown in FIG. 10M.

Then, a polysilicon material is deposited by CVD to fill up the contact hole 96, as shown in FIG. 10N. Thereafter an N- or P-type impurity is implanted into the deposited polysilicon material. While the implantation conditions vary with the type of the N- or P-type impurity, acceleration energy is 10 to 100 keV, for example. Thus, the polysilicon layer 97 doped with the impurity in a high concentration is formed. Then, Ti and TiN are deposited in this order on the surface of the polysilicon layer 97 by a method such as sputtering or vapor deposition, and the intermediate layer 98 is formed. Then, a metal such as Al is deposited on the surface of the intermediate layer 98 by a method such as sputtering or vapor deposition, and the metal layer 99 is formed. Thus, the source wire 89 is formed. Then, the drain electrode 74 is formed on the rear surface 50 of the SiC substrate 42.

Thereafter the semiconductor device 86 shown in FIG. 9 is obtained by forming the interlayer dielectric film (not shown), the source pad 46 and the gate pad 48.

In the semiconductor device 86, as hereinabove described, the source wire 89 has the polysilicon layer 97 in the portion in contact with the source region 92 and the body contact region 93, whereby the source wire 89 can be brought into ohmic contact with both of the body contact region 93 and the source region 92, which are high-concentration impurity regions, similarly to the semiconductor device 1 according to the first embodiment.

When the semiconductor device 86 is manufactured, therefore, a step of forming an Ni layer on the surface 52 of the epitaxial layer 51 can be omitted dissimilarly to a case where a layer made of only a metal such as Al is directly brought into contact with the impurity regions, and a step of silicifying such an Ni layer can also be omitted. Thus, the surface 52 of the epitaxial layer 51 can be prevented from formation of a carbon layer.

Consequently, layer peeling can be suppressed between the source wire 89 and the epitaxial layer 51. Thus, connection reliability of the source wire 89 can be improved.

Further, the layer (the polysilicon layer 97) entering the contact hole 96 to come into contact with the drain region 91, the body contact region 93 and the source region 92 is made of polysilicon excellent in coverage, whereby coverage of the source wire 89 can be improved. Consequently, the connection reliability of the source wire 89 can be further improved.

In addition, the polysilicon layer 97 is the high-concentration doped layer doped with the impurity in the high concentration of 10¹⁹ to 10²¹ cm⁻³, whereby the resistance of the source wire 89 can be reduced.

Further, the intermediate layer 98 having the multilayer structure of the Ti layer and the TiN layer is interposed between the polysilicon layer 97 and the metal layer 99. A material containing Ti has excellent adhesiveness with respect to both of a polysilicon material and a metal material. Therefore, adhesiveness between the polysilicon layer 97 and the metal layer 99 can be improved. Consequently, the connection reliability of the source wire 89 can be further improved.

When the body contact region 93 is formed on a side (a lower portion) closer to the SiC substrate 42 than the source region 92 and a source trench 79 is formed to pass through each body contact region 56 as shown in FIG. 11 similarly to the second embodiment, the polysilicon layer 97 can be brought into contact with the drain region 91, the body contact region 93 and the source region 92 in the source trench 79. In other words, a current can be fed to the side of a hetero junction in preference to the side of a body diode 80 (a PN diode formed by junction between the body region 90 and the drain region 91), even if a reverse voltage is applied between the source and the drain and the current flows to the body diode 80.

An embodiment related to the invention of a method of manufacturing an SiC semiconductor device through a resistance heating furnace is now described.

FIG. 12 is a schematic sectional view of a planar gate semiconductor device.

A semiconductor device 101 has a structure obtained by arranging a plurality of unit cells of a planar gate VDMOSFET in the form of a matrix. FIG. 12 shows only part of the plurality of unit cells.

The semiconductor device 101 includes an N⁺-type SiC substrate 102 forming the base of the semiconductor device 101. An N⁻-type epitaxial layer 103 made of SiC (silicon carbide) doped with an N-type impurity in a lower concentration than the SiC substrate 102 is laminated on a surface 121 of the SiC substrate 102. A surface 131 of the epitaxial layer 103 is constituted of a (0001) plane of SiC, for example.

An N⁻-type drain region 104 maintaining a state after epitaxy is formed on the epitaxial layer 103.

A P-type body region 105 is formed on a surface layer portion of the epitaxial layer 103. A plurality of such body regions 105 (not shown in FIG. 12) are formed at regular intervals to parallelly extend in the same direction (a direction perpendicular to the plane of FIG. 12), and arranged in a striped manner or in the form of a matrix, for example. The drain region 104 is exposed between two body regions 105 adjacent to each other.

On a surface layer portion of the body region 105, an N⁺-type source region 106 is formed at an interval from the peripheral edge thereof.

A gate insulating film 107 extending over the drain region 104, the body region 105 and the source region 106 is formed on the surface 131 of the epitaxial layer 103. The gate insulating film 107 is made of SiO₂.

A gate electrode 108 made of polysilicon doped with an N-type impurity in a high concentration is formed on the gate insulating film 107. The gate electrode 108 is opposed to the drain region 104, the body region 105 and the source region 106 through the gate insulating film 107.

An interlayer dielectric film 109 made of SiO₂ is laminated on the epitaxial layer 103. A source wire 111 is formed on the interlayer dielectric film 109. The source wire 111 is electrically connected to the body region 105 and the source region 106 through a contact hole 110 formed in the interlayer dielectric film 109.

A gate wire 112 is electrically connected to the gate electrode 108 through a contact hole (not shown) formed in the interlayer dielectric film 109.

A drain electrode 113 is formed on the rear surface of the SiC substrate 102.

When the source wire 111 is grounded and the potential of the gate electrode 108 is controlled while applying a positive voltage of a proper level to the drain electrode 113, a channel can be formed in the vicinity of the interface between the body region 105 and the gate insulating film 107 due to an electric field from the gate electrode 108. Thus, a current can be fed between the source wire 111 and the drain electrode 113.

FIGS. 13A to 13L are schematic sectional views for illustrating a method of manufacturing the semiconductor device 101 shown in FIG. 12 in step order.

First, the epitaxial layer 103 is formed on the surface 121 of the SiC substrate 102 by epitaxy, as shown in FIG. 13A. At this time, a major growth surface (the surface 121) of the SiC substrate 102 is defined by a (0001) plane. Due to the surface 121 of the SiC substrate 102 defined by the (0001) plane, the epitaxial layer 103 formed on the SiC substrate 102 by epitaxy is grown also with a major surface defined by a (0001) plane. Therefore, the surface 131 of the epitaxial layer 103 parallel to the surface 121 of the SiC substrate 102 is defined by the (0001) plane.

Then, a photoresist film 114 having an opening 115 in a portion opposed to a region for forming the body region 105 is formed on the surface 131 of the epitaxial layer 103 by well-known photolithography. Then, ions (boron ions, for example) of a P-type impurity are introduced into the surface 131 of the epitaxial layer 103 from above the photoresist film 114. Thus, the P-type impurity is implanted into surface layer portions of portions of the epitaxial layer 103 exposed from the opening 115, as shown in FIG. 13B.

Then, a photoresist film 116 having an opening 117 in a portion opposed to a region for forming the source region 106 is formed on the surface 131 of the epitaxial layer 103 by well-known photolithography. Then, ions (arsenic ions, for example) of an N-type impurity are introduced into the surface 131 of the epitaxial layer 103 from above the photoresist film 116. Thus, the N-type impurity is implanted into a surface layer portion (closer to the surface 131 than the portions into which the P-type impurity has been implanted) of a portion of the epitaxial layer 103 exposed from the opening 117, as shown in FIG. 13C.

After the implantation of the impurity ions into the surface layer portion of the epitaxial layer 103, an organic material film 118 is formed on the overall region of the surface 131 of the epitaxial layer 103, as shown in FIG. 13D. The organic material film 118 is made of a material containing carbon, to which an organic material (polyimide or the like, for example) employed as a photoresist material or the like can be applied, for example. The organic material film 118 is formed with a spin coater or the like, for example.

After the formation of the organic material film 118, the SiC substrate 102 is charged into a resistance heating furnace 122. The resistance heating furnace 122 is not particularly restricted, so far as airtightness in the resistance heating furnace 122 in which a heated object is set can be ensured and gas can be introduced thereinto. Further, the heating system of the resistance heating furnace 122 may be either direct heating or indirect heating.

When the SiC substrate 102 is set in the resistance heating furnace 122, inert gas (N₂, Ar or the like, for example) is introduced into the resistance heating furnace 122, which in turn is subjected to temperature-rise control (first temperature-rise control).

In the first temperature-rise control, the heating temperature is controlled to rise from 100° C. to 1000° C. over 35 to 45 minutes, for example, and thereafter held at 1000° C. (first temperature holding) for 5 to 10 minutes, for example, as shown in FIG. 6. Due to the temperature rise and the temperature holding, elements other than carbon evaporate from the organic material film 118, which in turn is altered into a carbon film 119, as shown in FIG. 13E. Therefore, the overall region of the surface 131 of the epitaxial layer 103 is covered with the carbon film 119.

Then, the resistance heating furnace 122 is subjected to further temperature-rise control (second temperature-rise control) while the inner portion thereof is kept in the inert atmosphere.

In the second temperature-rise control, the heating temperature is controlled to rise from 1000° C. to 1600° C. over 30 to 60 minutes, for example, as shown in FIG. 6. After the temperature rise, the heating temperature is held at 1600° C. (second temperature holding) for 5 to 10 minutes, for example. Due to the temperature rise and the temperature holding, ions of the N- and P-type impurities implanted into the surface layer portion of the epitaxial layer 103 are activated, and the body region 105 and the source region 106 are formed on the surface layer portion of the epitaxial layer 103, as shown in FIG. 13F. Further, the drain region 104 isolated from the body region 105 while maintaining the state after the epitaxy is formed on a base layer portion of the epitaxial layer 103.

Then, the resistance heating furnace 122 is subjected to temperature-drop control while the inner portion thereof is kept in the inert atmosphere.

In the temperature-drop control, the heating temperature is controlled (temperature-drop-controlled) to drop from 1600° C. to 1300° C. over 15 to 30 minutes, for example, as shown in FIG. 6. After the temperature drop, oxygen-containing gas is introduced into the resistance heating furnace 122 for 5 to 10 minutes, for example, while holding the heating temperature at 1300° C. (third temperature holding). Due to the introduction of the oxygen-containing gas, the carbon film 119 is oxidized and removed by reacting with oxygen contained in the oxygen-containing gas, as shown in FIG. 13G. The oxygen-containing gas introduced into the resistance heating furnace 122 is preferably prepared from gas containing oxygen and nitrogen. More specifically, gas containing NO (nitrogen monoxide) or N₂O (dinitrogen oxide) can be employed.

Thereafter the heating temperature is further held at 1300° C. (fourth temperature holding) for 200 to 240 minutes, for example, while the oxygen-containing gas is introduced into the resistance heating furnace 122. Thus, the surface 131 of the epitaxial layer 103 is oxidized, and an oxide film 120 covering the overall region of the surface 131 is formed, as shown in FIG. 13H.

After the formation of the oxide film 120, the inert gas (N₂, Ar or the like, for example) is reintroduced into the resistance heating furnace 122, while the heating temperature is controlled to drop from 1300° C. to 300° C. After the temperature drop, the SiC substrate 102 is taken out from the resistance heating furnace 122.

Then, a conductive material film is formed by sputtering. Then, the conductive material film is patterned by well-known photolithography and etching, and the gate electrode 108 is formed on the oxide film 120, as shown in FIG. 13I.

Thereafter the interlayer dielectric film 109 is laminated on the epitaxial layer 103 by CVD (Chemical Vapor Deposition), as shown in FIG. 13J.

Then, the contact hole 110 is formed in the interlayer dielectric film 109 and the oxide film 120 by well-known photolithography and etching, as shown in FIG. 13K. The remaining portion of the oxide film 120 forms the gate insulating film 107.

Then, a film of a conductive material is formed on the epitaxial layer 103 by sputtering. The conductive material is bonded (deposited) to fill up the contact hole 110 and form a thin film on the interlayer dielectric film 109. Then, the conductive material film formed on the interlayer dielectric film 109 is patterned by well-known photolithography and etching. Thus, the source wire 111 is formed, as shown in FIG. 13L. Further, the gate wire 112 electrically connected with the gate electrode 108 is formed. In addition, the drain electrode 113 is formed on the rear surface of the SiC substrate 102.

The semiconductor device 101 shown in FIG. 12 is obtained through the aforementioned steps.

According to the aforementioned method, the organic material film 118 is heated in the resistance heating furnace 122 by the first temperature-rise control after the formation of the organic material film 118 to be altered into the carbon film 119, which is formed on the surface 131 of the epitaxial layer 103.

After the formation of the carbon film 119, the epitaxial layer 103 is heated due to the second temperature-rise control in the resistance heating furnace 122 while the inner portion thereof is kept in the inert atmosphere, thereby activating the ions of the N- and P-type impurities in the epitaxial layer 103.

Then, the temperature-drop control (temperature drop from 1600° C. to 1300° C., for example) is executed while maintaining the resistance heating furnace 122 in the inert state. Thereafter the oxygen-containing gas is introduced for 5 to 10 minutes, for example, while the heating temperature is held at 1300° C. (the third temperature holding). Thus, the carbon film 119 is oxidized and removed, and the surface 131 of the epitaxial layer 103 is exposed.

After the removal of the carbon film 119, the resistance heating furnace 122 is subjected to the temperature holding (the fourth temperature holding) while the oxygen-containing gas is continuously introduced thereinto, whereby the exposed surface 131 is oxidized and the oxide film 120 is formed.

The carbon film 119 is formed on the surface 131 of the epitaxial layer 103 in advance of the heating (the second temperature-rise control) for activating the ions, whereby Si escape from the surface 131 can be prevented when the epitaxial layer 103 is heated. Therefore, roughening of the surface 131 of the epitaxial layer 103 can be suppressed, and planarity of the surface 131 can be maintained. Consequently, the interface between the epitaxial layer 103 and the gate insulating film 107 can be smoothed, whereby channel mobility of the semiconductor device 101 can be improved.

Further, the four steps of altering the organic material film 118 into the carbon film 119 by heating the same (the first temperature-rise control), activating the ions by heating the epitaxial layer 103 (the second temperature-rise control), oxidizing and removing the carbon film 119 with the oxygen-containing gas (the temperature-drop control and the third temperature holding) and forming the oxide film 120 by oxidizing the surface 131 of the epitaxial layer 103 (the fourth temperature holding) can be continuously carried out in the single resistance heating furnace 122. No apparatus for removing the carbon film 119 or the like is additionally required, whereby increase in the device cost can also be suppressed. Further, the resistance heating furnace 122 is so employed that the first temperature-rise control, the second temperature-rise control, the temperature-drop control as well as the third temperature holding, and the fourth temperature holding can be precisely and simply executed.

In addition, the surface 131 of the epitaxial layer 103 on which the oxide film 120 is formed is defined by the (0001) plane, and the oxygen-containing gas introduced into the resistance heating furnace 122 is prepared from the gas containing oxygen and nitrogen.

When oxide films are formed by oxidizing (0001) planes of SiC layers with O₂ gas, H₂O gas (water vapor) and N₂O gas respectively, for example, MOSFETS including the SiC layers exhibit channel mobility values of 1 to 5 cm²/V·s, 5 to 15 cm²/V·s and 15 to 25 cm²/V·s respectively, for example. In other words, the MOSFET including the SiC layer having the oxide film formed with the N₂O gas is most excellent in channel mobility.

In the semiconductor device 101 according to the embodiment, the oxide film 120 is formed by oxidizing the (0001) plane (the surface 131) of the epitaxial layer 103 with NO gas or N₂O gas, whereby the channel mobility of the semiconductor device 101 can be further improved.

EXAMPLES

While the present invention is now described with reference to Example and comparative example, the present invention is not restricted by the following Examples.

Example 1

First, an epitaxial layer made of SiC was formed by growing an SiC crystal on an Si surface of a wafer-shaped SiC substrate (by Cree Inc.). Then, an N-type impurity was multistage-implanted from the surface (the Si surface) of the epitaxial layer with acceleration energy of 30 to 200 keV. Thus, an N-type impurity region (having a concentration of 10²⁰ cm⁻³) was formed on a surface layer portion of the epitaxial layer.

Then, an insulating film made of SiO₂ was formed on the surface of the epitaxial layer by CVD. Then, a contact hole was formed in the insulating film, to expose the aforementioned impurity region.

Then, a contact wire was obtained by forming a polysilicon layer by depositing a polysilicon material in the contact hole by CVD.

Comparative Example 1

Steps similar to those in Example 1 were carried out up to a step of forming a contact hole. After the formation of the contact hole, nickel was deposited in the contact hole by sputtering. Then, a nickel silicide layer was obtained by silicifying nickel through a heat treatment at a temperature of 1000° C. Finally, a contact wire was obtained by forming an aluminum layer by depositing aluminum on the nickel silicide layer by sputtering.

1) Photography with Scanning Electron Microscope (SEM)

The contact wires formed according to Example 1 and comparative example 1 were scanned with electron beams through a scanning electron microscope. SEM images were obtained by image-processing information detected by the scanning with the electron beams. FIGS. 14(a) and 14(b) show the SEM images obtained according to Example 1 and comparative example 1 respectively.

2) Presence or Absence of Layer Peeling

The presence or absence of layer peeling in the contact wires was confirmed by visually recognizing the SEM images shown in FIGS. 14(a) and 14(b).

Referring to FIG. 14(a), the polysilicon layer was in close contact with the impurity region, and it was confirmable that the polysilicon layer was excellently in contact with the impurity region. Thus, it has been confirmed that connection reliability of the contact wire can be improved while forming ohmic contact between the contact wire and the impurity region according to Example 1.

Referring to FIG. 14(b), on the other hand, a void was formed between the nickel silicide layer and the impurity region, and layer peeling was clearly confirmed therebetween. In other words, a contact failure was confirmed between the contact wire and the impurity region.

While the embodiments of the present invention have been described, the present invention may be embodied in other ways.

For example, the conductivity types of the semiconductor portions of the semiconductor device 1, 41, 85 or 86 may be reversed. In other words, the P-type portions may be replaced with N-type portions and vice versa in the semiconductor device 1, 41, 85 or 86.

In the semiconductor device 1, only either the source wire 17 or the drain wire 23 may be employed as the contact wire having the polysilicon layer.

In the semiconductor device 41, 85 or 86, the contact wire having the polysilicon layer may be applied to the drain electrode 74.

The crystal planes of the surface 21 or 49 and the rear surface 22 or 50 of the SiC substrate 2 or 42 may be reversed. In other words, the surface 21 or 49 may be a C surface and the rear surface 22 or 50 may be an Si surface in the SiC substrate 2 or 42.

While the contact wire according to the present invention has been shown as the source wire 17 or 69 and the drain wire 23 of the trench gate MOSFET or the source wire 89 of the planar gate VDMOSFET in each of the aforementioned embodiments, the present invention is also applicable to a wire brought into contact with an impurity region of a diode, a thyristor or a bipolar transistor, for example.

While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.

Claims

1. A semiconductor device, comprising:

a semiconductor layer made of sic;

a source region of a first conductivity type formed in the semiconductor layer, the source region forming a surface of the semiconductor layer;

a body region of a second conductivity type formed in the semiconductor layer, the body region being in contact with the source region from a side of a back surface of the semiconductor layer;

a drain region of a first conductivity type formed in the semiconductor layer, the drain region being in contact with the body region from the side of the back surface of the semiconductor layer;

a gate trench dug down in the semiconductor layer from the surface thereof, the gate trench passing through the source region and the body region and the deepest portion thereof reaching the drain region;

a gate insulating film formed on an inner surface of the gate trench;

a gate electrode embedded in the gate trench on the gate insulating film;

a source trench dug down in the semiconductor layer from the surface thereof, the source trench passing through the source region and the body region, and the deepest portion thereof reaching a first conductivity type part of the drain region; and

a conductive material embedded in the source trench, the conductive material having a first layer conforming to a side surface and a bottom surface of the source trench and a second layer formed on the first layer;

wherein the second layer includes at least a lower layer conforming to the first layer to define a space inside the source trench, and an upper layer embedded in the space.

2. The semiconductor device according to claim 1, wherein the source trench passes through the source region and the body region and the deepest portion thereof reaches the drain region.

3. The semiconductor device according to claim 1, wherein an ohmic contact is selectively formed between the first layer and the semiconductor layer.

4. The semiconductor device according to claim 1, wherein an non-ohmic contact is selectively formed between the first layer and the semiconductor layer.

5. The semiconductor device according to claim 1, wherein the upper layer includes a surface layer made of Al.

6. The semiconductor device according to claim 5, wherein the lower layer includes an intermediate layer between the first and surface layers.

7. The semiconductor device according to claim 6, wherein the intermediate layer contains Ti.

8. The semiconductor device according to claim 6, wherein the intermediate layer contains TiN.

9. The semiconductor device according to claim 6, wherein the intermediate layer has a laminating structure of Ti and TiN.

10. The semiconductor device according to claim 1, the gate trench and the source trench have the same depth.

11. The semiconductor device according to claim 1, wherein the source trench is deeper than the gate trench.

12. The semiconductor device according to claim 1, wherein

the source region is an n⁺-type source region,

the drain region is an n-type drain region, and

the body region has a p-type region forming a side surface of the gate trench, and a p⁺-type region forming the side surface of the source trench and having an impurity concentration larger than that of the p-type region.

13. The semiconductor device according to claim 12, wherein an ohmic contact is selectively formed between the first layer and the n⁺-type source region.

14. The semiconductor device according to claim 1, wherein the first layer is made of polysilicon.

15. The semiconductor device according to claim 1, wherein the gate trench is formed to surround the source trench in plan view.

16. A semiconductor device, comprising:

a semiconductor layer made of sic;

a source region formed in the semiconductor layer, the source region forming a surface of the semiconductor layer;

a body region formed in the semiconductor layer, the body region being in contact with the source region from a side of a back surface of the semiconductor layer;

a drain region formed in the semiconductor layer, the drain region being in contact with the body region from the side of the back surface of the semiconductor layer;

a gate trench dug down in the semiconductor layer from the surface thereof, the gate trench passing through the source region and the body region and the deepest portion thereof the drain region;

a gate insulating film formed on an inner surface of the gate trench;

a gate electrode embedded in the gate trench on the gate insulating film;

a source trench dug down in the semiconductor layer from the surface thereof; and

a conductive material embedded in the source trench, the conductive material having a first layer conforming to a side surface and a bottom surface of the source trench and a second layer formed on the first layer;

wherein the first layer selectively forms an ohmic contact and a first junction with respect to the semiconductor layer, the first junction having a smaller junction barrier than the diffusion potential of a body diode intrinsic in the semiconductor device, and

wherein the second layer includes at least a lower layer conforming to the first layer to define a space inside the source trench, and an upper layer embedded in the space.

17. The semiconductor device according to claim 16, wherein the source trench passes through the source region and the body region and the deepest portion thereof reaches the drain region.

18. The semiconductor device according to claim 16, wherein a non-ohmic contact is selectively formed between the conductive material and the semiconductor layer.

19. The semiconductor device according to claim 16, the gate trench and the source trench have the same depth.

20. The semiconductor device according to claim 16, wherein the source trench is deeper than the gate trench.

21. The semiconductor device according to claim 16, wherein

the source region is an n⁺-type source region,

the drain region is an n-type drain region, and

the body region has a p-type region forming a side surface of the gate trench, and a p⁺-type region forming the side surface of the source trench and having an impurity concentration larger than that of the p-type region.

22. The semiconductor device according to claim 21, wherein an ohmic contact is selectively formed between the conductive material and the n⁺-type source region.

23. The semiconductor device according to claim 16, wherein the gate trench is formed to surround the source trench in plan view.

24. A semiconductor device, comprising:

a semiconductor layer made of sic;

a source region of a first conductivity type in a surface of the semiconductor layer;

a body region of a second conductivity type formed in the semiconductor layer, the body region being in contact with the source region from a side of a back surface of the semiconductor layer;

a drain region of a first conductivity type formed in the semiconductor layer, the drain region being in contact with the body region from the side of the back surface of the semiconductor layer;

a gate trench in the semiconductor layer, the gate trench passing through the source region and the body region and the deepest portion thereof reaching the drain region;

a gate insulating film formed on an inner surface of the gate trench;

a gate electrode embedded in the gate trench on the gate insulating film;

a source trench in the semiconductor layer, the source trench being deeper than the gate trench;

and a conductive material in the source trench;

the conductive material having a first layer and a second layer formed on the first layer,

wherein the second layer includes at least a lower layer conforming to the first layer to define a space inside the source trench, and an upper layer embedded in the space, where the lower layer and the upper layer are different materials from each other,

the conductive material comprises a polysilicon layer,

a non-ohmic contact is selectively formed between the polysilicon layer and a portion of the drain region in the semiconductor layer made of sic; and

the non-ohmic contact is a heterojunction between the polysilicon layer and the drain region.

25. The semiconductor device according to claim 24, wherein the portion of the drain region is located at least at a side of the source trench.

26. The semiconductor device according to claim 24, wherein the portion of the drain region is located below the source region.

27. The semiconductor device according to claim 24, wherein the portion of the drain region is located below the body region.

28. The semiconductor device according to claim 24, wherein the conductive material comprises a metal layer.

29. The semiconductor device according to claim 28, wherein the conductive material further comprises an intermediate layer at least at a portion between the semiconductor layer and the metal layer.

30. The semiconductor device according to claim 29, wherein the intermediate layer comprises titanium.

31. The semiconductor device according to claim 30, wherein the metal layer comprises an aluminum layer.

32. The semiconductor device according to claim 31, wherein the first layer is a polysilicon layer.

33. The semiconductor device according to claim 24, wherein the conductive material comprises an aluminum layer.

34. The semiconductor device according to claim 24, wherein the conductive material comprises a polysilicon layer.

35. The semiconductor device according to claim 24, wherein a part of the second layer is connected to outside of the source trench and is arranged over the gate trench.

36. A semiconductor device, comprising:

a semiconductor layer made of sic;

a source region of a first conductivity type in a surface of the semiconductor layer;

a body region of a second conductivity type formed in the semiconductor layer, the body region being in contact with the source region from a side of a back surface of the semiconductor layer;

a drain region of a first conductivity type formed in the semiconductor layer, the drain region being in contact with the body region from the side of the back surface of the semiconductor layer;

a gate trench in the semiconductor layer, the gate trench passing through the source region and the body region and the deepest portion thereof reaching the drain region;

a gate insulating film formed on an inner surface of the gate trench;

a gate electrode embedded in the gate trench on the gate insulating film;

a source trench in the semiconductor layer, the source trench passing through the source region and the body region to reach the drain region; and

a conductive material in the source trench;

the conductive material having a first layer and a second layer formed on the first layer,

wherein the second layer includes at least a lower layer conforming to the first layer to define a space inside the source trench, and an upper layer embedded in the space, where the lower layer and the upper layer are different materials from each other;

the conductive material contacts with the source region at the surface of the semiconductor layer,

the conductive material comprises a polysilicon layer,

a non-ohmic contact is selectively formed between the polysilicon layer and a portion of the drain region in the semiconductor layer made of sic; and

the non-ohmic contact is a heterojunction between the polysilicon layer and the drain region.

37. The semiconductor device according to claim 36, wherein a non-ohmic contact is selectively formed between the conductive material and a portion of the drain region in the semiconductor layer, and the portion of the drain region is located at least at a side of the source trench.

38. The semiconductor device according to claim 36, wherein a non-ohmic contact is selectively formed between the conductive material and a portion of the drain region in the semiconductor layer, and the portion of the drain region is located below the source region.

39. The semiconductor device according to claim 36, wherein a non-ohmic contact is selectively formed between the conductive material and a portion of the drain region in the semiconductor layer, and the portion of the drain region is located below the body region.

40. The semiconductor device according to claim 36, wherein the conductive material comprises a metal layer.

41. The semiconductor device according to claim 40, wherein the conductive material further comprises an intermediate layer at least at a portion between the semiconductor layer and the metal layer.

42. The semiconductor device according to claim 41, wherein the intermediate layer comprises titanium.

43. The semiconductor device according to claim 36, wherein the conductive material comprises an aluminum layer.

44. The semiconductor device according to claim 36, wherein the conductive material comprises a polysilicon layer.

45. The semiconductor device according to claim 36, wherein the conductive material comprises an aluminum layer.

46. The semiconductor device according to claim 45, wherein the first layer is a polysilicon layer.

47. The semiconductor device according to claim 36, wherein a part of the second layer is connected to outside of the source trench and is arranged over the gate trench.

48. The semiconductor device according to claim 36, wherein the source trench is deeper than the gate trench.