A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
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0. 25. An assembly comprising:
a semiconductor chip having metallization traces, a protective overcoat layer formed above the metallization traces, first windows formed in the protective overcoat exposing portions of the metallization traces, conductive lines formed over the overcoat layer and in electrical contact with the metallization traces through the first windows, an insulating layer formed over and between the conductive lines, the insulating layer having a first thickness between the conductive lines and a second thickness over the conductive lines, second windows in the insulating layer exposing portions of the conductive lines, and one or more metal bumps contacting each conductive line through the second windows in the insulating layer;
a substrate having conductive leads with first and second surfaces, each conductive lead having a first surface connected to a metal bump on at least one of said conductive lines using conductive elements and a second surface facing away from said connected metal bump;
and a molding compound at least partially encapsulating the assembly so that the second lead surfaces of the conductive leads remain un-encapsulated by the molding compound and available for further electrical attachment.
0. 15. A method comprising the steps of:
providing a structure comprising a semiconductor chip having metallization traces, a protective overcoat layer formed above the metallization traces, first windows formed in the protective overcoat exposing portions of the metallization traces, conductive lines formed over the overcoat layer and in electrical contact with the metallization traces through the first windows, an insulating layer formed over and between the conductive lines, the insulating layer having a first thickness between the conductive lines and a second thickness over the conductive lines, second windows in the insulating layer exposing portions of the conductive lines, and one or more metal bumps contacting each conductive line through the second windows in the insulating layer;
providing a substrate having conductive leads with first and second surfaces;
connecting the first surface of each conductive lead to a metal bump on at least one of said conductive lines using conductive elements such that the second surface of each conductive lead is facing away from said connected metal bump;
and at least partially encapsulating the assembly in molding compound so that the second lead surfaces of the conductive leads remain un-encapsulated by the molding compound and available for further electrical attachment.
0. 1. A method for fabricating a low resistance, low inductance interconnection structure for high current semiconductor flip-chip products, comprising the steps of:
providing a semiconductor wafer having metallization traces, the wafer surface protected by an overcoat, and windows in the overcoat to expose portions of the metallization traces;
forming copper lines on the overcoat, contacting the traces by filling the windows with metal;
depositing a layer of photo-imageable insulation material over the lines and the remaining wafer surface;
opening windows in the insulation material to expose portions of the lines, the locations of the windows selected in an orderly and repetitive arrangement on each line so that the windows of one line are positioned about midway between the corresponding windows of the neighboring lines; and
forming copper bumps in the windows, in contact with the lines.
0. 2. The method according to
0. 3. The method according to
0. 4. The method according to
0. 5. The method according to
0. 6. The method according to
depositing a barrier metal layer over the wafer surface;
depositing a seed metal layer over the barrier metal layer;
depositing a first photoresist layer over the seed metal layer in a height commensurate with the height of intended copper lines;
opening windows in the photoresist layer so that the windows are shaped as the intended lines;
depositing copper to fill the photoresist windows and form copper lines;
removing the first photoresist layer; and
removing the portions of the adhesion and barrier layers, which are exposed after removing the first photoresist layer.
0. 7. The method according to
0. 8. The method according to
depositing a barrier metal layer over the wafer surface;
depositing a seed metal layer over the barrier metal layer;
depositing a second photoresist layer over the seed metal layer in a height commensurate with the height of the intended copper bumps;
opening windows in the photoresist layer in locations intended for copper bumps, and of a width commensurate with the width of the intended copper bumps;
filling the photoresist windows by depositing copper to form copper bumps;
removing the second photoresist layer; and
removing the portions of the adhesion and barrier layers, which are exposed after removing the second photoresist layer.
0. 9. The method according the step 8, wherein the step of depositing copper comprises an electroplating technique.
0. 10. The method according to
depositing one or more solderable metal layers on the surface of the copper bump, before removing the second photoresist layer.
0. 11. The method according to
0. 12. A method for fabricating a low resistance, low inductance interconnection device for high current semiconductor flip-chip products, comprising the steps of:
providing a structure comprising a semiconductor chip having metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines;
providing a substrate having elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines;
connecting the first surface of each lead to the corresponding bumps of alternating lines using solder elements; and
encapsulating the assembly in molding compound so that the second lead surfaces remain un-encapsulated.
0. 13. The method according to
0. 14. A method for fabricating a low resistance, low inductance interconnection system for high current semiconductor flip-chip devices, comprising the steps of:
providing a low resistance, low inductance interconnection device comprising:
a semiconductor chip structure including copper lines in contact with chip metallization traces, and copper bumps located in an orderly and repetitive arrangement on each line, the bumps of one line positioned about midway between the corresponding bumps of the neighboring lines;
a substrate having elongated copper leads with first and second surfaces, the leads at right angles to the lines, the first lead surfaces connected to the corresponding bumps of alternating lines by solder elements; and
the chip structure and substrate encapsulated so that the second lead surfaces remain un-encapsulated;
providing a circuit board having copper contact pads parallel to the leads; and
attaching the second surface of the device leads to the board pads using solder layers.
0. 16. The method according to claim 15 wherein the protective overcoat layer is 0.7 to 1.5 μm thick.
0. 17. The method according to claim 15 wherein the second thickness of the insulating layer is less than the first thickness.
0. 18. The method according to claim 17 wherein the step of at least partially encapsulating the assembly comprises submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the encapsulated assembly are straight.
0. 19. The method according to claim 15 wherein the first thickness of the insulating layer is 10 to 20 μm.
0. 20. The method according to claim 15 wherein the substrate is a metallic leadframe.
0. 21. The method according to claim 15 wherein the step of at least partially encapsulating the assembly comprises submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the encapsulated assembly are straight.
0. 22. The method according to claim 15 wherein the conductive lines comprise electroplated copper or copper alloys.
0. 23. The method according to claim 15 wherein the conductive lines comprise silver or silver alloys.
0. 24. The method according to claim 15 wherein the conductive lines comprise carbon nano-tubes.
0. 26. The assembly of claim 25 wherein the protective overcoat layer is 0.7 to 1.5 μm thick.
0. 27. The assembly of claim 25 wherein the second thickness of the insulating layer is less than the first thickness.
0. 28. The assembly of claim 27 wherein the molding compound at least partially encapsulating the assembly is formed by submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the mold compound encapsulating the assembly are straight.
0. 29. The assembly of claim 25 wherein the first thickness of the insulating layer is 10 to 20 μm.
0. 30. The assembly of claim 25 wherein the substrate is a metallic leadframe.
0. 31. The assembly of claim 25 wherein the molding compound at least partially encapsulating the assembly is formed by submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the mold compound encapsulating the assembly are straight.
0. 32. The assembly of claim 25 wherein the conductive lines comprise electroplated copper or copper alloys.
0. 33. The assembly of claim 25 wherein the conductive lines comprise silver or silver alloys.
0. 34. The assembly of claim 25 wherein the conductive lines comprise carbon nanotubes.
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This Application is a Continuation Reissue Application for broadening reissue of U.S. Pat. No. 7,335,536, Ser. No. 11/218,408, filed Sep. 1, 2005, and is a continuation of Reissue application Ser. No. 12/712,934, filed Feb. 25, 2010, now U.S. Pat. No. RE46,466; moreover, more than one reissue patent application has been filed for the reissue of U.S. Pat. No. 7,335,536, which includes Reissue application Ser. No. 13/870,579, filed on Aug. 20, 2013, now U.S. Pat. No. RE46,618, which is a divisional of Reissue application Ser. No. 12/712,934, and also Reissue application Ser. No. 12/712,934, now U.S. Pat. No. RE46,466, through which the present reissue Application claims priority to U.S. Pat. No. 7,335,536.
The present invention is related in general to the field of semiconductor devices and processes and more specifically to a fabrication method of high performance flip-chip semiconductor devices, which have low electrical resistance and can provide high power, low noise, and high speed.
Among the ongoing trends in integrated circuit (IC) technology are the drives towards higher integration, shrinking component feature sizes, and higher speed. In addition, there is the relentless pressure to keep the cost/performance ratio under control, which translates often into the drive for lower cost solutions. Higher levels of integration include the need for higher numbers of signal lines and power lines, yet smaller feature sizes make it more and more difficult to preserve clean signals without mutual interference.
These trends and requirements do not only dominate the semiconductor chips, which incorporate the ICs, but also the packages, which house and protect the IC chips.
Compared to the traditional wire bonding assembly, the growing popularity of flip-chip assembly in the fabrication process flow of silicon integrated circuit (IC) devices is driven by several facts. First, the electrical performance of the semiconductor devices can commonly be improved when the parasitic inductances correlated with conventional wire bonding interconnection techniques are reduced. Second, flip-chip assembly often provides higher interconnection densities between chip and package than wire bonding. Third, in many designs flip-chip assembly consumes less silicon “real estate” than wire bonding, and thus helps to conserve silicon area and reduce device cost. And fourth, the fabrication cost can often be reduced, when concurrent gang-bonding techniques are employed rather than consecutive individual bonding steps.
The standard method of ball bonding in the fabrication process uses solder balls and their reflow technique. These interconnection approaches are more expensive than wire bonding. In addition, there are severe reliability problems in some stress and life tests of solder ball attached devices. Product managers demand the higher performance of flip-chip assembled products, but they also demand the lower cost and higher reliability of wire bonded devices. Furthermore, the higher performance of flip-chip assembled products should be continued even in miniaturized devices, which at present run into severe technical difficulties by using conventional solder ball technologies.
Applicants recognize a need to develop a technical approach which considers the complete system consisting of semiconductor chip—device package—external board, in order to provide superior product characteristics, including low electrical resistance and inductance, high reliability, and low cost. Minimum inductance and noise is the prerequisite of high speed, and reduced resistance is the prerequisite of high power. The system-wide method of assembling should also provide mechanical stability and high product reliability, especially in accelerated stress tests (temperature cycling, drop test, etc.). The fabrication method should be flexible enough to be applied for semiconductor product families with shrinking geometries, including substrates and boards, and a wide spectrum of design and process variations.
One embodiment of the invention is a method for fabricating a low resistance, low inductance interconnection structure for high current semiconductor flip-chip products. A semiconductor wafer is provided, which has metallization traces, the wafer surface protected by an overcoat, and windows in the overcoat to expose portions of the metallization traces. Copper lines are formed on the overcoat, preferably by electroplating; the lines are in contact with the traces by filling the windows with metal. Next a layer of photo-imageable insulation material is deposited over the lines and the remaining wafer surface. Windows are opened in the insulation material to expose portions of the lines, the locations of the windows selected in an orderly and repetitive arrangement on each line so that the windows of one line are positioned about midway between the corresponding windows of the neighboring lines. Copper bumps are formed, preferably by electroplating, in the windows, and are in contact with the lines.
Certain device features serve multiple purposes in the process flow. The photo-imageable insulation layer doubles as protection against running solder in the assembly process. The photoresist layers needed to enable the electroplating steps double as thickness controls for the copper elements being electroplated.
Another embodiment of the invention is a method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is provided, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. Further, a substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
Another embodiment of the invention is a method for fabricating a low resistance, low inductance interconnection system for high current semiconductor flip-chip devices. An encapsulated device as described above is provided, with lead surfaces un-encapsulated. Further a circuit board is provided, which has copper contact pads parallel to the leads. The device lead surfaces are attached to the board pads using solder layers.
The technical advantages represented by certain embodiments of the invention will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
The present invention is related to U.S. patent application Ser. No. 11/210,066, filed on Aug. 22, 2005. (Coyle et al., “High Current Semiconductor Device System having Low Resistance and Inductance”; TI-60885).
A window of width 104 is opened in overcoat 103 to expose a portion of metallization trace 102. The top view of
As
In
In the next process steps shown in
In
The locations of the windows 702a are selected in an orderly and repetitive arrangement on each line 501 so that the windows 702a of one line 501 are positioned about midway between the corresponding windows of the neighboring lines.
As
In
In the next process steps shown in
The next process step is a singulation step, preferably involving a rotating diamond saw, by which the wafer is separated into individual chips. Each chip can then be further processed by assembling the chip onto a substrate or a leadframe.
In the next process step, a substrate is provided, which has elongated copper leads with first and second surfaces. A preferred example is a metallic leadframe with individual leads; preferred leadframe metals are copper or copper alloys, but in specific devices, iron/nickel alloys or aluminum may be used. Other examples include insulating substrates with elongated copper leads. The leads are oriented at right angles to the copper lines 501 shown in
In
Flipping the assembly of
The assembly of
From lead surface 1410b to the chip circuitry, there is a continuous electrical path through copper connectors (with the exception of solder element 1420). Consequently, the electrical resistance and the electrical inductance of the device displayed in
While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, the substrate may be an insulating tape with copper leads of first and second surfaces. As another example, the copper bumps may be considerably shorter than illustrated in the figures; there still will be no risk of electrical shorts by creeping solder elements. It is therefore intended that the appended claims encompass any such modifications.
Coyle, Anthony L., Lange, Bernhard P., Mai, Quang X.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4969029, | Nov 01 1977 | Fujitsu Limited | Cellular integrated circuit and hierarchial method |
5083187, | May 16 1990 | Texas Instruments Incorporated | Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof |
5087590, | Jun 28 1989 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor devices |
5410107, | Mar 01 1993 | The Board of Trustees of the University of Arkansas | Multichip module |
5945730, | Feb 12 1997 | Infineon Technologies AG | Semiconductor power device |
6049130, | Feb 01 1995 | Kabushiki Kaisha Toshiba | Semiconductor device using gold bumps and copper leads as bonding elements |
6169329, | Apr 02 1996 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor devices having interconnections using standardized bonding locations and methods of designing |
6218281, | Dec 26 1997 | SOCIONEXT INC | Semiconductor device with flip chip bonding pads and manufacture thereof |
6297460, | Mar 01 1993 | The Board of Trustees of the University of Arkansas | Multichip module and method of forming same |
6388200, | Mar 01 1993 | The Board of Trustees of the University of Arkansas | Electronic interconnection medium having offset electrical mesh plane |
6407462, | Dec 30 2000 | Bell Semiconductor, LLC | Irregular grid bond pad layout arrangement for a flip chip package |
6489688, | May 02 2001 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Area efficient bond pad placement |
6510976, | May 18 2001 | QUESTECH SOLUTIONS PTE LTD | Method for forming a flip chip semiconductor package |
6518089, | Feb 02 2001 | Texas Instruments Incorporated | Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly |
6550666, | Aug 21 2001 | QUESTECH SOLUTIONS PTE LTD | Method for forming a flip chip on leadframe semiconductor package |
6556454, | Oct 31 2000 | III Holdings 1, LLC | High density contact arrangement |
6630372, | Feb 14 1997 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method for routing die interconnections using intermediate connection elements secured to the die face |
6686666, | May 16 2002 | Intel Corporation | Breaking out signals from an integrated circuit footprint |
6753616, | Feb 02 2001 | Texas Instruments Incorporated | Flip chip semiconductor device in a molded chip scale package |
6759738, | Aug 02 1995 | ULTRATECH, INC | Systems interconnected by bumps of joining material |
6762507, | Dec 13 2001 | ALI CORPORATION | Internal circuit structure of semiconductor chip with array-type bonding pads and method of fabricating the same |
6768210, | Nov 01 2001 | Texas Instruments Incorporated | Bumpless wafer scale device and board assembly |
6790758, | Nov 25 2002 | Silicon Integrated Systems Corp. | Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging |
6798075, | Jul 20 2001 | VIA Technologies Inc. | Grid array packaged integrated circuit |
6977435, | Sep 09 2003 | TAHOE RESEARCH, LTD | Thick metal layer integrated process flow to improve power delivery and mechanical buffering |
7049642, | Sep 16 2003 | NEC Electronics Corporation | Semiconductor device, and wiring-layout design system for automatically designing wiring-layout in such semiconductor device |
7101781, | May 27 2002 | VIA Technologies, Inc. | Integrated circuit packages without solder mask and method for the same |
7122897, | May 12 2004 | SOCIONEXT INC | Semiconductor device and method of manufacturing the semiconductor device |
7127807, | Sep 07 2001 | NYTELL SOFTWARE LLC | Process of manufacturing multilayer modules |
7335536, | Sep 01 2005 | Texas Instruments Incorporated | Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices |
7385286, | Jun 05 2001 | III Holdings 12, LLC | Semiconductor module |
7465654, | Jul 09 2004 | Qualcomm Incorporated | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures |
7763977, | Nov 24 2006 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method therefor |
8039956, | Aug 22 2005 | Texas Instruments Incorporated | High current semiconductor device system having low resistance and inductance |
8067837, | Sep 20 2004 | Qualcomm Incorporated | Metallization structure over passivation layer for IC chip |
8492282, | Nov 24 2008 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods of forming a masking pattern for integrated circuits |
20020084534, | |||
20040007779, | |||
20040089946, | |||
20040201101, | |||
20050056932, | |||
20050073059, | |||
20050167826, | |||
20060151614, | |||
20070040237, | |||
20070080360, | |||
20070130554, | |||
20080023819, | |||
20110057304, | |||
EP61863, | |||
EP859414, | |||
EP1189279, | |||
JP2000183089, | |||
WO3048981, | |||
WO2007024587, | |||
WO2007027994, | |||
WO99034415, |
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