Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.
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1. A semiconductor device, comprising:
a shallow trench isolation (STI) layer on and in contact with a substrate;
an interlayer dielectric (ILD) layer on and in contact with the STI layer, the ILD layer corresponding to a gate cut region; and
a filling on and in contact with the STI layer on both sides of the ILD layer including both sides of the ILD layer corresponding to an isolation cut region,
wherein the gate cut region and the isolation cut region intersect each other at a junction, and
wherein the ILD layer is continuous through the junction.
2. The semiconductor device of
wherein the ILD layer comprises a single layer, and
wherein the filling comprises two or more layers.
3. The semiconductor device of
4. The semiconductor device of
wherein the ILD layer comprises SiO2, and
wherein the filling comprises SiN and/or SiO.
5. The semiconductor device of
6. The semiconductor device of
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The present Application for Patent is a divisional of U.S. patent application Ser. No. 15/271,867, entitled “LAYOUT EFFECT MITIGATION IN FINFET,” filed Sep. 21, 2016, pending, assigned to the assignee hereof, and expressly incorporated herein by reference in its entirety.
The field of the disclosed subject matter generally relates to fabrication of semiconductor devices. In particular, the field of the disclosed subject matter relates to fabrication of multigate transistor devices such as fin-shaped field effect transistor (FinFET) devices to mitigate layout effects.
Multigate transistors have been implemented in integrated circuit chips for area efficiency. Examples of multigate transistors include fin-shaped field effect transistors (FinFETs) having multiple fins disposed on two sides of a gate stripe, with fins on one side of the gate stripe serving as sources and fins on the other side of the gate stripe serving as drains. Examples of typical FinFET devices include devices in which transistor arrays are formed by multiple gate stripes in parallel with one another, which are positioned perpendicular to multiple oxide diffusion stripes in parallel with one another. The oxide diffusion stripes are positioned like fins on two sides of each gate stripe. Each pair of source and drain and a portion of the gate stripe between such pair of source and drain may be implemented as an individual transistor.
As illustrated in
When the long isolation cut mask 125 is used, the interlayer dielectric layer corresponding to the junction between the gate cut mask 115 and the isolation cut mask 125 is etched. This unfortunately has the effect of introducing stresses in later processing. The break of the active region and the surrounding inter-layer-dielectric (ILD) causes strain accumulation at the region. For example the PFET adjacent to the isolation cut is usually impacted by compressive strain, and causes threshold voltage Vt of the PFET to be lowered from a target Vt. Also, as the isolation cut length is increased, this has the effect of lowering the threshold voltage from the target even further. In other words, ΔVt, which is the deviation from the target, may increase as the isolation cut length increases. Such layout effects are generally undesirable.
This summary identifies features of some example aspects, and is not an exclusive or exhaustive description of the disclosed subject matter. Whether features or aspects are included in, or omitted from this Summary is not intended as indicative of relative importance of such features. Additional features and aspects are described, and will become apparent to persons skilled in the art upon reading the following detailed description and viewing the drawings that form a part thereof.
An exemplary method for forming a semiconductor device is disclosed. The method may comprise forming a shallow trench isolation (STI) layer on a substrate, forming first and second dummy gates on the STI layer, and forming an interlayer dielectric (ILD) layer on the STI layer. The ILD layer may correspond to a gate cut region and may separate the first and second dummy gates. The method may also comprise forming a first mask on the first and second dummy gates and on the ILD layer. The first mask may have a trench corresponding to an isolation cut region. The trench may expose the first and second dummy gates and the ILD layer. The gate cut and isolation cut regions may intersect. The method may further comprise forming a second mask on the first mask and on the ILD layer exposed by the trench, removing the first and second dummy gates, and removing the first and second masks. The first and second masks may be removed such that the ILD layer remains on the STI layer. The method may yet further comprise filling regions left by the removed first and second dummy gates.
Another exemplary method for forming a semiconductor device is disclosed. The method may comprise forming a shallow trench isolation (STI) layer on a substrate, forming first and second dummy gates on the STI layer, and forming an interlayer dielectric (ILD) layer on the STI layer. The ILD layer may correspond to a gate cut region and may separate the first and second dummy gates. The method may also comprise forming a first mask on the first and second dummy gates and on the ILD layer, and forming a second mask on the first mask. The second mask may correspond to the gate cut region such that a portion of the first mask outside of the gate cut region is exposed. The method may further comprise removing the exposed portion of the first mask and the second mask. In doing so, a portion of the first mask corresponding to the gate cut region may remain on the ILD layer. The method may yet further comprise removing the first and second dummy gates, removing the first mask such that the ILD layer remains on the STI layer, and filling regions left by the removed first and second dummy gates.
An exemplary semiconductor device is disclosed. The semiconductor device may comprise a shallow trench isolation (STI) layer on a substrate and an interlayer dielectric (ILD) layer on the STI layer. The ILD layer may correspond to a gate cut region. The semiconductor device may also comprise a filling on the STI layer on both sides of the ILD layer including both sides of the ILD layer corresponding to an isolation cut region. The gate cut region and the isolation cut region may intersect each other at a junction, and the ILD layer may be continuous through the junction.
The accompanying drawings are presented to aid in the description of examples of one or more aspects of the disclosed subject matter and are provided solely for illustration of the examples and not limitation thereof.
Aspects of the subject matter are provided in the following description and related drawings directed to specific examples of the disclosed subject matter. Alternates may be devised without departing from the scope of the disclosed subject matter. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments” does not require that all embodiments of the disclosed subject matter include the discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, processes, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, processes, operations, elements, components, and/or groups thereof.
Further, many examples are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the examples described herein, the corresponding form of any such examples may be described herein as, for example, “logic configured to” perform the described action.
As indicated above, conventional FinFET fabrication processes typically include using the long isolation cut mask 125 illustrated in
However, in a non-limiting aspect, it is proposed to change the fabrication process to keep the ILD layer at the gate cut location intact during the fabrication process. Referring to
In the non-limiting aspect, it is proposed to maintain at least the ILD layer intact in an area corresponding to the junction between the gate cut and isolation cut masks 115, 125 during the fabrication process. In other words, the ILD layer may remain continuous through the junction. By maintaining the ILD layer intact, the undesirable layout effects may be mitigated or even eliminated.
While not specifically indicated, the gate cut direction may correspond to the left/right direction and the isolation cut direction may correspond to the up/down direction of the viewing surface. Moreover, the gate cut region (region occupied by the gate cut mask 115) may be viewed as corresponding to a center horizontal portion and the isolation cut region (region occupied by the isolation cut mask 115) may be viewed as corresponding to a center vertical portion in these figures.
As seen, the filling 1190 may be on both sides of the ILD layer 230 including on both sides of the ILD layer 230 corresponding to the isolation cut region. Note that the ILD layer 230 may be continuous through the junction where the gate cut and isolation cut regions intersect. In an aspect, the ILD layer 230 may comprise a single layer (e.g., an SiO2 layer) and the filling 1190 may comprise multiple layers (e.g., SiN and SiO layers). In another aspect, the material of the ILD layer 230 may be different from the material(s) of the filling 1190.
While not shown, conventional replacement metal gate (RMG) process may follow the stage illustrated in
The filling 2290 may be on both sides of the ILD layer 230 including on both sides of the ILD layer 230 corresponding to the isolation cut region. The ILD layer 230 may be continuous through the junction where the gate cut and isolation cut regions intersect. In an aspect, the ILD layer 230 may comprise a single layer (e.g., an SiO2 layer) and the filling 2290 may comprise multiple layers (e.g., SiN and SiO layers). In another aspect, the material of the ILD layer 230 may be different from the material(s) of the filling 2290.
While not shown, conventional replacement metal gate (RMG) process may follow the stage illustrated in
In block 2310, the STI layer 220 may be formed on the substrate 210. In block 2320, the first and dummy gates 240 may be formed on the STI layer 220. In block 2330, the ILD layer 230 may also be formed on the STI layer. The blocks 2310, 2320 and 2330 may correspond to the stage illustrated in
In block 2340, the first mask 350 may be formed on the first and second dummy gates 240 and on the ILD layer 230. The trench 555 corresponding to the isolation cut region may be formed in the first mask 350. Recall that the isolation cut region may be a region or an area of the isolation cut mask 125. As noted, the gate cut and isolation cut regions may intersect. In an aspect, the two regions may be substantially perpendicular.
In block 2420, the first photoresist 460 may be deposited on the first mask 350. The first photoresist 460 may be patterned to have an opening 465 that corresponds to the isolation cut region. The opening 465 may expose a portion of the first mask 350. The block 2420 may correspond to the stage illustrated in
In block 2430, the exposed portion of the first mask 350 may be etched to form the trench 555. The portion of the first mask 350 outside the isolation cut region, i.e., the portion of the first mask 350 covered by the first photoresist 460 may be protected from being etched. Then in block 2440, the first photoresist 460 may be removed. The blocks 2430 and 2440 may correspond to the stage illustrated in
Referring back to
In block 2360, the first and second dummy gates 240 may be removed.
In block 2520, the exposed portion of the second mask 670 may be removed, e.g., through etching. The first and second dummy gates 240, which are outside of the gate cut region, may be exposed after the second mask 670 is removed. In block 2530, the second photoresist 670 may be removed. The remaining second mask 670, i.e., the portion that corresponds to the gate cut region, may protect the ILD layer 230. The blocks 2520 and 2530 may correspond to the stage illustrated in
In block 2540, the first and second dummy gates 240 may be removed. For example, etching may be performed which pulls out the dummy gates 240. The gate cut region may be protected by the remaining second mask 670. Thus, the ILD layer 230 may remain intact through the etching process. The block 2540 may correspond to the stage illustrated in
Referring back to
In block 2380, the regions left by the removed dummy gates 240 may be filled with filling 1190. That is, the filling 1190 may be filled in the area outside of the gate cut region. Materials including SiN and SiO may be used for the filling 1190. The filling 1190 and/or the ILD layer 230 may be polished, e.g., through chemical-mechanical polishing (CMP). The polishing may stop just above the gate. The block 2380 may correspond to the stage illustrated in
While not shown, conventional replacement metal gate (RMG) process may follow the method illustrated in
In block 2610, the STI layer 220 may be formed on the substrate 210. In block 2620, the first and dummy gates 240 may be formed on the STI layer 220. In block 2630, the ILD layer 230 may also be formed on the STI layer. The blocks 2610, 2620 and 2630 may correspond to the stage illustrated in
In block 2640, the first mask 350 may be formed on the first and second dummy gates 240 and on the ILD layer 230. The first mask 350 may be a hardmask formed from materials such as SiN and/or SiO2. The block 2640 may correspond to the stage illustrated in
In block 2650, the second mask 1470 may be formed on the first mask 1350. The second mask 1470 may correspond to the gate cut region such that a portion of the first mask 1350 outside of the gate cut region is exposed.
In block 2720, the first photoresist 1560 may be deposited on the second mask 1470. The first photoresist 1560 may be patterned to correspond to the gate cut region, e.g., in accordance with the gate cut mask 115. The portion of the second mask 1470 outside the gate cut region may be exposed after the first photoresist 1560 is formed. The block 2720 may correspond to the stage illustrated in
In block 2730, the exposed portion of the second mask 1470 may be removed. In this way, the portion of the first mask 1350 outside of the gate cut region may be exposed. Thereafter in block 2740, the first photoresist 1560 may be removed. The blocks 2730 and 2740 may correspond to the stage illustrated in
Referring back to
In block 2820, the exposed portion of the first mask 1350 may be selectively removed, e.g., through selective etching. When the selective etching is performed, the portion of the first mask 1350 corresponding to the gate cut region below the second mask 1470 may remain since it may be protected by the second mask 1470. This means that the ILD layer 230 below the first mask 1350 may also remain. In block 2830, the exposed second photoresist 1780 may be removed. The blocks 2820 and 2830 may correspond to the stage illustrated in
In block 2840, the second mask 1470 may be removed. In doing so, the first mask 1350 corresponding to the gate cut region may be exposed. The block 2840 may correspond to the stage illustrated in
Referring back to
In block 2680, the first mask 1350 may be removed, e.g., through etching. Note that the ILD layer 230 may still remain. The block 2680 may correspond to the stage illustrated in
In block 2690, the regions left by the removed dummy gates 240 may be filled with filling 2290. That is, the filling 2290 may be filled in the area outside of the gate cut region. Materials including SiN and SiO may be used for the filling 2290. The filling 2290 and/or the ILD layer 230 may be polished, e.g., through chemical-mechanical polishing (CMP). The polishing may stop just above the gate. The block 2690 may correspond to the stage illustrated in
While not shown, conventional replacement metal gate (RMG) process may follow the method illustrated in
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and methods have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The methods, sequences and/or algorithms described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an aspect can include a computer readable media embodying a method of forming a semiconductor device. Accordingly, the scope of the disclosed subject matter is not limited to illustrated examples and any means for performing the functionality described herein are included.
While the foregoing disclosure shows illustrative examples, it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosed subject matter as defined by the appended claims. The functions, processes and/or actions of the method claims in accordance with the examples described herein need not be performed in any particular order. Furthermore, although elements of the disclosed subject matter may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Liu, Yanxiang, Yuan, Jun, Rim, Kern, Yang, Da
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